6670: Don't init DDR PLL twice
authorSandeep Paulraj <s-paulraj@ti.com>
Fri, 7 Oct 2011 14:44:03 +0000 (10:44 -0400)
committerSandeep Paulraj <s-paulraj@ti.com>
Fri, 7 Oct 2011 14:44:03 +0000 (10:44 -0400)
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
src/util/i2cConfig/i2cConfig.gel
src/util/iblConfig/src/device.c

index 7f617d956fe4b8cb10c5c55f829575de94a0941a..392dd31bfca533b5ade1fc97931954a6bace35b8 100755 (executable)
@@ -996,7 +996,7 @@ hotmenu setConfig_c6670_main()
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
 
        /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1; 
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0;
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
index 5b43985856216c665d5460ee9b05e42957c7dc3a..c02df1000d8becf5a80a6ed2c4dd25c1ca613466 100644 (file)
@@ -940,7 +940,7 @@ ibl_t c6670_ibl_config(void)
        ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
 
        /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0
        ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
        ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
        ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;