Changes for C6670 support from Hao

diff --git a/doc/evmc6670-instructions.txt b/doc/evmc6670-instructions.txt
new file mode 100644 (file)
index 0000000..0b788af
--- /dev/null
+++ b/doc/evmc6670-instructions.txt
@@ -0,0 +1,38 @@
+Steps to use IBL on the c6670 EVM
+
+1. Programing "IBL" on the EVM's EEPROM
+   (a) Use the I2C EEPROM writer for c6670 EVM from the MCSDK distribution.
+   (b) Program i2crom_0x51_c6670_le.dat (IBL image) to the EEPROM at I2C BUS 
+       address 0x51 following the EEPROM writer's procedure.
+
+2. Programing "IBL Configuration"
+   NOTE: For an understanding of the IBL configuration parameters used in this step, 
+         please refer to the IBL-Configuration documentation. The configuration 
+         data structure is ibl_s.               
+   (a) Make sure that the boot mode dip switch is set to no boot/EMIF16 
+       boot mode on the EVM (please refer to the EVM technical reference manual
+          on how to set the boot mode dip switches.
+   (b) Open CCSv5 and launch the evmc66xx emulator target configuration and connect to core 0.
+   (c) Load the program i2cparam_c6670_le.out to CCS.
+   (d) Run the program and a message "Run the GEL for the device to be configured, 
+       press return to program the I2C" will be printed on the CCS console.
+   (e) Load i2cConfig.gel (in CCSv5 Tools->GEL Files, right click mouse in GEL Files
+       window and select "Load GEL"
+   (f) Run the GEL script "EVM c6670 IBL"->setConfig_c6670_main, this will set the 
+       default boot parameters for booting application images from NOR, NAND and 
+       Ethernet.
+   (g) Now press "Enter" in the CCS console window, and the program will write the 
+       boot parameter table to the EEPROM. On success the message "I2c table write complete" 
+          will be printed on the CCS console.
+
+3. Programming the application on NAND or NOR flash
+   NOTE: This step is not needed if the application is booted from Ethernet.
+   (a) Use the NAND or NOR writer c6670 EVM from the tools directory.
+   (a) Flash the Application to NAND or NOR. For instructions please follow 
+       the instructions given along with the NAND/NOR writer.
+
+4. Booting the Application using IBL
+   (a) Set the boot mode dip switch to I2C address (0x51) boot mode on the EVM
+       (please refer to the EVM technical reference manual on how to set the 
+          boot mode dip switches) and power cycle the EVM.
+

diff --git a/doc/evmc6678-instructions.txt b/doc/evmc6678-instructions.txt
index 2fae589539aa8639161c476c44284cc7378ad9cd..14fe4e67cced669638fbea7584de3229e3dc4137 100644 (file)
--- a/doc/evmc6678-instructions.txt
+++ b/doc/evmc6678-instructions.txt
@@ -1,11 +1,11 @@
 Steps to use IBL on the c6678 EVM
 
 1. Programing "IBL" on the EVM's EEPROM
-   (a) Use the I2C EEPROM writer for c6678 EVM from the tools directory.
+   (a) Use the I2C EEPROM writer for c6678 EVM from the MCSDK distribution.
    (b) Program i2crom_0x51_c6678_le.dat (IBL image) to the EEPROM at I2C BUS 
        address 0x51 following the EEPROM writer's procedure.
 
-2. Programing "IBL COnfiguration"
+2. Programing "IBL Configuration"
    NOTE: For an understanding of the IBL configuration parameters used in this step, 
          please refer to the IBL-Configuration documentation. The configuration 
          data structure is ibl_s.               

diff --git a/doc/release_info.txt b/doc/release_info.txt
index 8ce67229bfd9603d70d0de7c54a6d4fd777f521d..54c726e8697687a0e51054341aefe1c383ef2865 100644 (file)
--- a/doc/release_info.txt
+++ b/doc/release_info.txt
@@ -1,7 +1,7 @@
 =====================================================
 C6x Bootloader Release Note
-Version: 1.0.0.3
-April 2011
+Version: 1.0.0.4
+May 2011
 =====================================================
 
 1) Supported TARGETS:
@@ -29,8 +29,9 @@ ENDIAN mode "both".
         For building in Linux Bash shell modify setupenvLnx.sh 
     - Set the environment by running "setupenv.bat" or "source setupenvLnx.sh"
       or "source setupenvMsys.sh"
-    - For building run:
-        make evm_c6678_i2c ENDIAN=little I2C_BUS_ADDR=0x51
+    - For building run the following make command:
+    C6678/C6670 EVM:
+        make evm_c667x_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
       or:
         make <TARGET>  ENDIAN=[little|big]
         make c6455 ENDIAN=liitle

diff --git a/release.sh b/release.sh
index cd1c89cc8089e891ac67dc019934c50458cb3339..7c7fef611c4a14ff145fbe6c157530e1ccc524ce 100755 (executable)
--- a/release.sh
+++ b/release.sh
@@ -118,7 +118,7 @@ cp -f src/make/ibl_c6457/i2crom_0x50_c6457_be.bin ibl_bin_$IBL_VERSION/c6457/be/
 cp -f src/util/i2cConfig/i2cparam_c6457_le.out   ibl_bin_$IBL_VERSION/c6457/le/
 cp -f src/util/i2cConfig/i2cparam_c6457_be.out   ibl_bin_$IBL_VERSION/c6457/be/
 
-# Build c6678 EVM 
+# Build c6678/c6670 EVM 
 pushd src/make
 make clean
 make evm_c667x_i2c ENDIAN=little I2C_BUS_ADDR=0x51 

diff --git a/src/driver/nand/nand.c b/src/driver/nand/nand.c
index 1261694f9eb4eb007bdb647305f834b5a061c16f..19a2399f3efc785ab800bc45834c2c0764e019da 100644 (file)
--- a/src/driver/nand/nand.c
+++ b/src/driver/nand/nand.c
@@ -180,7 +180,7 @@ Int32 nand_open (void *ptr_driver, void (*asyncComplete)(void *))
     
     Int32 size;
     Int32 ret;
-    Int32 i, j;
+    Int32 i, j, startBlock;
     Bool  badBlock;
 
     /* Initialize the control info */
@@ -251,7 +251,8 @@ Int32 nand_open (void *ptr_driver, void (*asyncComplete)(void *))
         return (-1);
 
     nandmcb.numBadBlocks = 0;
-    for (i = 0; i < nandmcb.devInfo.totalBlocks; i++)  {
+    startBlock = ibln->bootAddress[iblEndianIdx][iblImageIdx]/(nandmcb.devInfo.pageSizeBytes*nandmcb.devInfo.pagesPerBlock);
+    for (i = startBlock; i < nandmcb.devInfo.totalBlocks; i++)  {
 
         badBlock = FALSE;
         for (j = 0; j < ibl_N_BAD_BLOCK_PAGE; j++)
@@ -287,13 +288,13 @@ Int32 nand_open (void *ptr_driver, void (*asyncComplete)(void *))
     
 
     /* Construct the logical to physical block array */  
-    for (i = j = 0; i < nandmcb.devInfo.totalBlocks; i++)  {
+    for (i = j = startBlock; i < nandmcb.devInfo.totalBlocks; i++)  {
         if (nandmcb.blocks[i] != 0xff)
             nandmcb.logicalToPhysMap[j++] = i;
     }
 
     /* Construct the physical to logical block array */
-    for (i = j = 0; i < nandmcb.devInfo.totalBlocks; i++)  {
+    for (i = j = startBlock; i < nandmcb.devInfo.totalBlocks; i++)  {
         if (nandmcb.blocks[i] == 0xff)
             nandmcb.physToLogicalMap[i] = 0xff;
         else

diff --git a/src/make/Makefile b/src/make/Makefile
index 2cd2d6bea2297b716b386fcb9b30b6825d572e62..d9e5a8744533b6111cbc5243cd746d52211927d6 100644 (file)
--- a/src/make/Makefile
+++ b/src/make/Makefile
@@ -276,7 +276,7 @@ evm_c6455:
 # The c6472 EVM has a 128k eeprom (64k at 0x50, 64k at 0x51), so both endians are built with full functionality
 evm_c6472:
        make -f makestg1 ARCH=c64x TARGET=c6472 I2C_BUS_ADDR=0x50 \
-    I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no ENDIAN_MODE=both CEXCLUDES='ELF BIS MULTI_BOOT' c6472
+    I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no ENDIAN_MODE=both CEXCLUDES='ELF BIS MULTI_BOOT NAND_GPIO' c6472
 
 # The 6474 EVM has a 32k eeprom. A stripped down version is build with only one endian.
 evm_c6474:
@@ -403,11 +403,3 @@ clean:
        find ../ -name cdefdep | xargs rm -f
 
 
-
-
-
-
-
-
-
-

diff --git a/src/make/makestg1 b/src/make/makestg1
index 622ff112bbf34b4dc8a458c35744771171cc675f..c77490f87bb202bf349ef0c528f55e80ead1a239 100644 (file)
--- a/src/make/makestg1
+++ b/src/make/makestg1
@@ -109,11 +109,11 @@ all:
 
 be_target:
        @echo EXCLUDES= $(EXCLUDES)
-       make -f makestg2 ARCH=c64x TARGET=$(TARGET) ENDIAN=big    I2C_SIZE_BYTES=$(I2C_SIZE_BYTES) I2C_BUS_ADDR=$(I2C_BUS_ADDR) SPI_DEFS='$(SPI_DEFS)' utils
+       make -f makestg2 ARCH=c64x TARGET=$(TARGET) ENDIAN=big    I2C_SIZE_BYTES=$(I2C_SIZE_BYTES) I2C_BUS_ADDR=$(I2C_BUS_ADDR) INTERNAL_UTILS=$(INTERNAL_UTILS) SPI_DEFS='$(SPI_DEFS)' utils
        make -f makestg2 ARCH=c64x TARGET=$(TARGET) ENDIAN=big    I2C_SIZE_BYTES=$(I2C_SIZE_BYTES) I2C_BUS_ADDR=$(I2C_BUS_ADDR) SPI_DEFS='$(SPI_DEFS)' $(TARGET)
 
 le_target:
-       make -f makestg2 ARCH=c64x TARGET=$(TARGET) ENDIAN=little I2C_SIZE_BYTES=$(I2C_SIZE_BYTES) I2C_BUS_ADDR=$(I2C_BUS_ADDR) SPI_DEFS='$(SPI_DEFS)' utils
+       make -f makestg2 ARCH=c64x TARGET=$(TARGET) ENDIAN=little I2C_SIZE_BYTES=$(I2C_SIZE_BYTES) I2C_BUS_ADDR=$(I2C_BUS_ADDR) INTERNAL_UTILS=$(INTERNAL_UTILS) SPI_DEFS='$(SPI_DEFS)' utils
        make -f makestg2 ARCH=c64x TARGET=$(TARGET) ENDIAN=little I2C_SIZE_BYTES=$(I2C_SIZE_BYTES) I2C_BUS_ADDR=$(I2C_BUS_ADDR) SPI_DEFS='$(SPI_DEFS)' $(TARGET)
 
 compare:

diff --git a/src/make/setupenvMsys.sh b/src/make/setupenvMsys.sh
index ce0fe89877691490daf9656735a700a67b3d20a5..66855aafbfb571c252f5bab4e854a39db6561353 100755 (executable)
--- a/src/make/setupenvMsys.sh
+++ b/src/make/setupenvMsys.sh
@@ -1,15 +1,15 @@
-#!/bin/bash\r
-\r
-# Environment setup to be done if using MSYS Bash shell for build\r
-\r
-# Specify the base directory of the c6000 compiler with UNIX style path separator\r
-export C6X_BASE_DIR='"G:/Program Files/Texas Instruments/ccsv5/tools/compiler/c6000"'\r
-\r
-# Specify the base directory of the c6000 compiler in format understandable by the MSYS Bash shell \r
-export C6X_BASE_DIR_MSYS=/g/Program\ Files/Texas\ Instruments/ccsv5/tools/compiler/c6000\r
-\r
-# Don't modify the below variables. They are derived from the above definitions \r
-export PATH=$PATH:$C6X_BASE_DIR_MSYS/bin\r
-export TOOLSC6X=$C6X_BASE_DIR\r
-export TOOLSC6XDOS=$C6X_BASE_DIR\r
-\r
+#!/bin/bash
+
+# Environment setup to be done if using MSYS Bash shell for build
+
+# Specify the base directory of the c6000 compiler with UNIX style path separator
+export C6X_BASE_DIR='"C:/Program Files/Texas Instruments/ccsv5/tools/compiler/c6000"'
+
+# Specify the base directory of the c6000 compiler in format understandable by the MSYS Bash shell 
+export C6X_BASE_DIR_MSYS=/c/Program\ Files/Texas\ Instruments/ccsv5/tools/compiler/c6000
+
+# Don't modify the below variables. They are derived from the above definitions 
+export PATH=$PATH:$C6X_BASE_DIR_MSYS/bin
+export TOOLSC6X=$C6X_BASE_DIR
+export TOOLSC6XDOS=$C6X_BASE_DIR
+

diff --git a/src/util/i2cConfig/i2cConfig.gel b/src/util/i2cConfig/i2cConfig.gel
index fee3f6021ed393b05f9096e1ae8e55ef1ed87e6d..0647a152f0ba7c0b6452c9c6aa041573ac9e7cac 100755 (executable)
--- a/src/util/i2cConfig/i2cConfig.gel
+++ b/src/util/i2cConfig/i2cConfig.gel
@@ -690,31 +690,48 @@ hotmenu setConfig_c6678_main()
        ibl.bootModes[0].port     = 0;
 
        ibl.bootModes[0].u.norBoot.bootFormat   = ibl_BOOT_FORMAT_ELF;
-       ibl.bootModes[0].u.norBoot.bootAddress[0][0]    = 0;
-       ibl.bootModes[0].u.norBoot.bootAddress[1][0]    = 0;
+       ibl.bootModes[0].u.norBoot.bootAddress[0][0]    = 0;            /* Image 0 NOR offset byte address in LE mode */ 
+       ibl.bootModes[0].u.norBoot.bootAddress[0][1]    = 0xA00000;     /* Image 1 NOR offset byte address in LE mode  */
+       ibl.bootModes[0].u.norBoot.bootAddress[1][0]    = 0;            /* Image 0 NOR offset byte address in BE mode */ 
+       ibl.bootModes[0].u.norBoot.bootAddress[1][1]    = 0xA00000;     /* Image 1 NOR offset byte address in BE mode  */
        ibl.bootModes[0].u.norBoot.interface    = ibl_PMEM_IF_SPI;
-    ibl.bootModes[0].u.norBoot.blob[0][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes     = 0xA00000;         /* 10 MB */
-    ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[0].u.norBoot.blob[1][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes     = 0xA00000;         /* 10 MB */
-    ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[0].u.norBoot.blob[0][0].startAddress  = 0x80000000;       /* Image 0 load start address in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes     = 0xA00000;         /* Image 0 size (10 MB) in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000;       /* Image 0 branch address after loading in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[0][1].startAddress  = 0x90000000;       /* Image 1 load start address in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes     = 0xA00000;         /* Image 1 size (10 MB) in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x90000000;       /* Image 1 branch address after loading in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][0].startAddress  = 0x80000000;       /* Image 0 load start address in BE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes     = 0xA00000;         /* Image 0 size (10 MB) in BE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000;       /* Image 0 branch address after loading in BE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][1].startAddress  = 0x90000000;       /* Image 1 load start address in BE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes     = 0xA00000;         /* Image 1 size (10 MB) in BE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x90000000;       /* Image 1 branch address after loading in BE mode */
 
     ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
     ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
     ibl.bootModes[1].port     = 0;
 
     ibl.bootModes[1].u.nandBoot.bootFormat        = ibl_BOOT_FORMAT_BBLOB;
-    ibl.bootModes[1].u.nandBoot.bootAddress[0][0]        = 0x4000;
-    ibl.bootModes[1].u.nandBoot.bootAddress[1][0]        = 0x4000;
+    ibl.bootModes[1].u.nandBoot.bootAddress[0][0]        = 0x4000;         /* Image 0 NAND offset address (block 1) in LE mode */
+    ibl.bootModes[1].u.nandBoot.bootAddress[0][1]        = 0x2000000;      /* Image 1 NAND offset address (block 2048) in LE mode */
+    ibl.bootModes[1].u.nandBoot.bootAddress[1][0]        = 0x4000;         /* Image 0 NAND offset address (block 1) in BE mode */
+    ibl.bootModes[1].u.nandBoot.bootAddress[1][1]        = 0x2000000;      /* Image 1 NAND offset address (block 2048) in BE mode */
     ibl.bootModes[1].u.nandBoot.interface         = ibl_PMEM_IF_CHIPSEL_2;
 
-    ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes     = 0xA00000;         /* 10 MB */
-    ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes     = 0xA00000;         /* 10 MB */
-    ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress  = 0x80000000;       /* Image 0 load start address in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes     = 0xA00000;         /* Image 0 size (10 MB) in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000;       /* Image 0 branch address after loading in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress  = 0x90000000;       /* Image 1 load start address in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes     = 0xA00000;         /* Image 1 size (10 MB) in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x90000000;       /* Image 1 branch address after loading in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress  = 0x80000000;       /* Image 0 load start address in BE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes     = 0xA00000;         /* Image 0 size (10 MB) in BE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000;       /* Image 0 branch address after loading in BE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress  = 0x90000000;       /* Image 1 load start address in BE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes     = 0xA00000;         /* Image 1 size (10 MB) in BE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x90000000;       /* Image 1 branch address after loading in BE mode */
+
 
     ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits  = 8;
     ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
@@ -787,9 +804,9 @@ hotmenu setConfig_c6678_main()
     ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
     ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
 
-    ibl.bootModes[2].u.ethBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[2].u.ethBoot.blob.sizeBytes     = 0xA00000;         /* 10 MB */
-    ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
+    ibl.bootModes[2].u.ethBoot.blob.startAddress  = 0x80000000;       /* Load start address */
+    ibl.bootModes[2].u.ethBoot.blob.sizeBytes     = 0xA00000;         /* Image size (10 MB) */
+    ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000;       /* Branch address after loading */
 
     ibl.chkSum = 0;
 }
@@ -888,31 +905,48 @@ hotmenu setConfig_c6670_main()
        ibl.bootModes[0].port     = 0;
 
        ibl.bootModes[0].u.norBoot.bootFormat   = ibl_BOOT_FORMAT_ELF;
-       ibl.bootModes[0].u.norBoot.bootAddress[0][0]    = 0;
-       ibl.bootModes[0].u.norBoot.bootAddress[1][0]    = 0;
+       ibl.bootModes[0].u.norBoot.bootAddress[0][0]    = 0;            /* Image 0 NOR offset byte address in LE mode */ 
+       ibl.bootModes[0].u.norBoot.bootAddress[0][1]    = 0xA00000;     /* Image 1 NOR offset byte address in LE mode  */
+       ibl.bootModes[0].u.norBoot.bootAddress[1][0]    = 0;            /* Image 0 NOR offset byte address in BE mode */ 
+       ibl.bootModes[0].u.norBoot.bootAddress[1][1]    = 0xA00000;     /* Image 1 NOR offset byte address in BE mode  */
        ibl.bootModes[0].u.norBoot.interface    = ibl_PMEM_IF_SPI;
-    ibl.bootModes[0].u.norBoot.blob[0][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes     = 0xA00000;         /* 10 MB */
-    ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[0].u.norBoot.blob[1][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes     = 0xA00000;         /* 10 MB */
-    ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[0].u.norBoot.blob[0][0].startAddress  = 0x80000000;       /* Image 0 load start address in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes     = 0xA00000;         /* Image 0 size (10 MB) in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000;       /* Image 0 branch address after loading in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[0][1].startAddress  = 0x90000000;       /* Image 1 load start address in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes     = 0xA00000;         /* Image 1 size (10 MB) in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x90000000;       /* Image 1 branch address after loading in LE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][0].startAddress  = 0x80000000;       /* Image 0 load start address in BE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes     = 0xA00000;         /* Image 0 size (10 MB) in BE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000;       /* Image 0 branch address after loading in BE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][1].startAddress  = 0x90000000;       /* Image 1 load start address in BE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes     = 0xA00000;         /* Image 1 size (10 MB) in BE mode */
+    ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x90000000;       /* Image 1 branch address after loading in BE mode */
 
     ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
     ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
     ibl.bootModes[1].port     = 0;
 
     ibl.bootModes[1].u.nandBoot.bootFormat        = ibl_BOOT_FORMAT_BBLOB;
-    ibl.bootModes[1].u.nandBoot.bootAddress[0][0]        = 0x4000;
-    ibl.bootModes[1].u.nandBoot.bootAddress[1][0]        = 0x4000;
+    ibl.bootModes[1].u.nandBoot.bootAddress[0][0]        = 0x4000;         /* Image 0 NAND offset address (block 1) in LE mode */
+    ibl.bootModes[1].u.nandBoot.bootAddress[0][1]        = 0x2000000;      /* Image 1 NAND offset address (block 2048) in LE mode */
+    ibl.bootModes[1].u.nandBoot.bootAddress[1][0]        = 0x4000;         /* Image 0 NAND offset address (block 1) in BE mode */
+    ibl.bootModes[1].u.nandBoot.bootAddress[1][1]        = 0x2000000;      /* Image 1 NAND offset address (block 2048) in BE mode */
     ibl.bootModes[1].u.nandBoot.interface         = ibl_PMEM_IF_GPIO;
 
-    ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes     = 0xA00000;         /* 10 MB */
-    ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes     = 0xA00000;         /* 10 MB */
-    ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress  = 0x80000000;       /* Image 0 load start address in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes     = 0xA00000;         /* Image 0 size (10 MB) in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000;       /* Image 0 branch address after loading in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress  = 0x90000000;       /* Image 1 load start address in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes     = 0xA00000;         /* Image 1 size (10 MB) in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x90000000;       /* Image 1 branch address after loading in LE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress  = 0x80000000;       /* Image 0 load start address in BE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes     = 0xA00000;         /* Image 0 size (10 MB) in BE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000;       /* Image 0 branch address after loading in BE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress  = 0x90000000;       /* Image 1 load start address in BE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes     = 0xA00000;         /* Image 1 size (10 MB) in BE mode */
+    ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x90000000;       /* Image 1 branch address after loading in BE mode */
+
 
     ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits  = 8;
     ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 512;
@@ -985,9 +1019,9 @@ hotmenu setConfig_c6670_main()
     ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
     ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
 
-    ibl.bootModes[2].u.ethBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
-    ibl.bootModes[2].u.ethBoot.blob.sizeBytes     = 0xA00000;         /* 10 MB */
-    ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
+    ibl.bootModes[2].u.ethBoot.blob.startAddress  = 0x80000000;       /* Load start address */
+    ibl.bootModes[2].u.ethBoot.blob.sizeBytes     = 0xA00000;         /* Image size (10 MB) */
+    ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000;       /* Branch address after loading */
 
     ibl.chkSum = 0;
 }

diff --git a/src/util/i2cConfig/i2cparam.c b/src/util/i2cConfig/i2cparam.c
index 3228f71417c86fff39c44955ddd83c105ebce19f..c64debb0454b714257766bbbd557d0f78d6066c1 100644 (file)
--- a/src/util/i2cConfig/i2cparam.c
+++ b/src/util/i2cConfig/i2cparam.c
@@ -189,6 +189,8 @@ void main (void)
       return;
     }
 
+    memset(&ibl, 0, sizeof(ibl_t));
+
     printf ("Run the GEL for for the device to be configured, press return to program the I2C\n");
     getchar ();
 
@@ -247,13 +249,3 @@ void main (void)
 
 }
 
-
-
-        
-
-
-
-
-
-
-