c6x-IBL: C6457: Adding device specific file

This commit adds device specific file

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

diff --git a/src/device/c6457/c6457.c b/src/device/c6457/c6457.c
new file mode 100644 (file)
index 0000000..225ab7c
--- /dev/null
+++ b/src/device/c6457/c6457.c
@@ -0,0 +1,163 @@
+/************************************************************************************
+ * FILE PURPOSE: C6457 Device Specific functions
+ ************************************************************************************
+ * FILE NAME: c6457.c
+ *
+ * DESCRIPTION: Implements the device specific functions for the IBL
+ *
+ * @file c6457.c
+ *
+ * @brief
+ *  This file implements the device specific functions for the IBL
+ *
+ ************************************************************************************/
+#include "ibl.h"
+#include "device.h"
+#include "pllapi.h"
+#include "emif31api.h"
+#include "pscapi.h"
+#include "gpio.h"
+#include <string.h>
+
+extern cregister unsigned int DNUM;
+
+
+/**
+ *  @brief Determine if an address is local
+ *
+ *  @details
+ *    Examines an input address to determine if it is a local address
+ */
+bool address_is_local (Uint32 addr)
+{
+    /* L2 */
+    if ((addr >= 0x00800000) && (addr < 0x00898000))
+        return (TRUE);
+
+    /* L1P */
+    if ((addr >= 0x00e00000) && (addr < 0x00e08000))
+        return (TRUE);
+
+    /* L2D */
+    if ((addr >= 0x00f00000) && (addr < 0x00f08000))
+        return (TRUE);
+
+    return (FALSE);
+
+}
+
+
+/**
+ * @brief  Convert a local l1d, l1p or l2 address to a global address
+ *
+ * @details
+ *  The global address is formed. If the address is not local then
+ *  the input address is returned
+ */
+Uint32 deviceLocalAddrToGlobal (Uint32 addr)
+{
+
+    if (address_is_local (addr))
+        addr = (1 << 28) | (DNUM << 24) | addr;
+
+    return (addr);
+
+}
+        
+        
+/**
+ * @brief Configure the PLLs
+ *
+ * @details
+ *   Only the main PLL can be configured here. The DDR pll is enabled by default,
+ *   and the network PLL is enabled through serdes configuration.
+ *   the multiplier and dividers.
+ */
+void devicePllConfig (void)
+{
+    if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
+        hwPllSetPll (MAIN_PLL, 
+                     ibl.pllConfig[ibl_MAIN_PLL].prediv,
+                     ibl.pllConfig[ibl_MAIN_PLL].mult,
+                     ibl.pllConfig[ibl_MAIN_PLL].postdiv);
+
+}
+
+/**
+ * @brief
+ *   Enable the DDR
+ *
+ * @details
+ *   The DDR controller on the c6457 is an emif 3.1. The controller is
+ *   initialized directly with the supplied values
+ */
+void deviceDdrConfig (void)
+{
+    if (ibl.ddrConfig.configDdr != 0)
+        hwEmif3p1Enable (&ibl.ddrConfig.uEmif.emif3p1);
+
+}
+        
+
+/**
+ *  @brief Power up a peripheral
+ *
+ *  @details
+ *    Boot peripherals are powered up
+ */
+int32 devicePowerPeriph (int32 modNum)
+{
+    /* If the input value is < 0 there is nothing to power up */
+    if (modNum < 0)
+        return (0);
+
+
+    if (modNum >= TARGET_PWR_MAX_MOD)
+        return (-1);
+
+    return ((int32)pscEnableModule(modNum));
+        
+}
+
+
+/**
+ *  @brief  Enable the pass through version of the nand controller
+ *
+ *  @details  On the evm the nand controller is enabled by setting 
+ *            gpio 14 high
+ */
+#if 0
+int32 deviceConfigureForNand(void)
+{
+       hwGpioSetDirection(NAND_MODE_GPIO, GPIO_OUT);
+       hwGpioSetOutput(NAND_MODE_GPIO);
+    return (0);
+
+}
+#endif
+
+
+/**
+ *  @brief
+ *    The e-fuse mac address is loaded
+ */
+void deviceLoadDefaultEthAddress (uint8 *maddr)
+{
+    uint32 macA, macB;
+
+    /* Read the e-fuse mac address */
+    macA = *((uint32 *)0x02880914);
+    macB = *((uint32 *)0x02880918);
+
+    maddr[0] = (macB >>  8) & 0xff;
+    maddr[1] = (macB >>  0) & 0xff;
+    maddr[2] = (macA >> 24) & 0xff;
+    maddr[3] = (macA >> 16) & 0xff;
+    maddr[4] = (macA >>  8) & 0xff;
+    maddr[5] = (macA >>  0) & 0xff;
+}
+
+
+
+
+

diff --git a/src/device/c6457/target.h b/src/device/c6457/target.h
new file mode 100644 (file)
index 0000000..767885b
--- /dev/null
+++ b/src/device/c6457/target.h
@@ -0,0 +1,166 @@
+/**************************************************************************
+ * FILE PURPOSE: Target specific definitions
+ **************************************************************************
+ * FILE NAME: target.h
+ *
+ * DESCRIPTION: This file defines target specific values used by low level
+ *                             drivers.
+ *
+ * @file target.h
+ *
+ * @brief
+ *  Low level target specific values are defined
+ *
+ ***************************************************************************/
+ 
+ 
+/** 
+ *  @brief
+ *   Device EMAC definitions
+ */
+#define TARGET_DEVICE_CPMAC
+ 
+#define TARGET_EMAC_N_PORTS            1
+
+#define TARGET_EMAC_BASE_ADDRESSES     { 0x02c80000u }
+#define TARGET_EMAC_DSC_BASE_ADDR      { 0x02c82000u }
+
+#define TARGET_SGMII_BASE_ADDRESSES    { 0x02c40000u }
+
+/* SGMII offsets (at least the serdes configs, vary between devices, so
+ * they are defined here. */
+#define TARGET_SGMII_IDVER             0x000
+#define TARGET_SGMII_SOFT_RESET        0x004
+#define TARGET_SGMII_CONTROL           0x010
+#define TARGET_SGMII_STATUS            0x014
+#define TARGET_SGMII_MR_ADV_ABILITY    0x018
+#define TARGET_SGMII_MR_LP_ADV_ABILITY 0x020
+#define TARGET_SGMII_TX_CFG            0x030
+#define TARGET_SGMII_RX_CFG            0x034
+#define TARGET_SGMII_AUX_CFG           0x038
+
+/* Leave mdio disabled */
+#define dev_mdio_open()     1
+
+/* No chip level reset required for ethernet, the function call is made a void statment */
+#define deviceSetEthResetState(x,y)
+
+/* The mac control register values */
+#define TARGET_MAC_CONTROL       ( 1 << 18)            /* EXT_EN              */     \
+                            | ( 0 << 9 )            /* Round robin         */     \
+                               | ( 1 << 7 )            /* GIG                 */     \
+                            | ( 0 << 6 )            /* TX pacing disabled  */     \
+                            | ( 1 << 5 )            /* GMII RX & TX        */     \
+                            | ( 0 << 4 )            /* TX flow disabled    */     \
+                            | ( 0 << 3 )            /* RX flow disabled    */     \
+                            | ( 0 << 1 )            /* Loopback enabled    */     \
+                            | ( 1 << 0 )            /* full duplex         */
+
+
+/**
+ *  @brief
+ *    Device Timer definitions
+ */
+#define TIMER0_BASE             0x02940000u
+
+#define TIMER_INPUT_DIVIDER     6           /* Timer driven from cpu clock / 6 */
+
+
+/**
+ *  @def MAIN_PLL
+ */
+#define MAIN_PLL        0   /**< The index to the main PLL */
+
+
+/**
+ *  @brief
+ *    Device PLL definitions
+ */
+#define DEVICE_PLL_BASE(x)  ((x) == MAIN_PLL ? 0x29a0000 : 0)
+
+
+/**
+ * @brief 
+ *  Device PSC definitions
+ */
+#define DEVICE_PSC_BASE     0x02ac0000u
+
+/**
+ * @brief
+ *  The ethernet is in the always on domain */
+#define TARGET_PWR_ETH(x)   -1
+
+/**
+ *  @brief
+ *    The nand is done through gpio, which is always powered up.
+ *    A value < 0 tells the low level psc driver to simply return success
+ */
+#define TARGET_PWR_NAND     -1
+
+/**
+ * @brief
+ *  Flag to indicate timer 0 power up requested. The time is always on in the 6474
+ */
+#define TARGET_PWR_TIMER_0  -1
+
+
+/**
+ *  @brief
+ *    Device DDR controller definitions
+ */
+#define DEVICE_DDR_BASE  0x80000000
+
+/**
+ * @brief
+ *  The highest module number
+ */
+#define TARGET_PWR_MAX_MOD  5
+ 
+
+/**
+ * @brief
+ *   The base address of MDIO 
+ */
+#define TARGET_MDIO_BASE    0x2c81800
+
+/**
+ *  @brief
+ *    GPIO address
+ */
+#define GPIO_GPIOPID_REG               0x02B00000
+#define GPIO_GPIOEMU_REG               0x02B00004
+#define GPIO_BINTEN_REG                        0x02B00008
+#define GPIO_DIR_REG                   0x02B00010
+#define GPIO_OUT_DATA_REG              0x02B00014
+#define GPIO_SET_DATA_REG              0x02B00018
+#define GPIO_CLEAR_DATA_REG            0x02B0001C
+#define GPIO_IN_DATA_REG               0x02B00020
+#define GPIO_SET_RIS_TRIG_REG  0x02B00024
+#define GPIO_CLR_RIS_TRIG_REG  0x02B00028
+#define GPIO_SET_FAL_TRIG_REG  0x02B0002C
+#define GPIO_CLR_FAL_TRIG_REG  0x02B00030
+
+/**
+ *  @brief
+ *    GPIO pin mapping 
+ */
+#define NAND_CLE_GPIO_PIN      GPIO_8     // High: Command Cycle occuring
+#define NAND_ALE_GPIO_PIN      GPIO_9     // High: Address input cycle oddcuring
+#define NAND_NWE_GPIO_PIN      GPIO_10
+#define NAND_NRE_GPIO_PIN      GPIO_12
+#define NAND_NCE_GPIO_PIN      GPIO_13
+#define NAND_MODE_GPIO         GPIO_14
+
+/**
+ *  @brief
+ *      The standard NAND delay must be big enough to handle the highest possible
+ *      operating frequency of the device */
+#define TARGET_NAND_STD_DELAY                          25 // In cpu cycles
+
+/**
+ *  @brief
+ *      The base address of the I2C peripheral, and the module divisor of the cpu clock
+ */
+#define DEVICE_I2C_BASE                 0x02b04000
+#define DEVICE_I2C_MODULE_DIVISOR       6
+