summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 08f2c57)
raw | patch | inline | side by side (parent: 08f2c57)
author | Prabhu Kuttiyam <pkuttiyam@ti.com> | |
Tue, 22 Nov 2011 03:33:35 +0000 (22:33 -0500) | ||
committer | Prabhu Kuttiyam <pkuttiyam@ti.com> | |
Tue, 22 Nov 2011 03:33:35 +0000 (22:33 -0500) |
diff --git a/src/device/c66x/c66x.c b/src/device/c66x/c66x.c
index 22f0e088fd0ea47ecfe322385654f00240b15277..51e83cdd1657c208625ad1ead0d23b91bc8a33cb 100755 (executable)
--- a/src/device/c66x/c66x.c
+++ b/src/device/c66x/c66x.c
#include "evmc66x_uart.h"
#define PLL_DDR_INIT_LOOPMAX 10
-#define IBL_STR_LEN 20
+#define IBL_RESULT_CODE_STR_LEN 20
+#define IBL_RESULT_CODE_LOC 17
extern cregister unsigned int DNUM;
#define DDR3_TEST_ENABLE
void deviceDdrConfig (void)
{
uint32 loopcount=0;
- int8 ddr_pass_str[IBL_STR_LEN] = "IBL: DDR TEST PASS\n";
- int8 ddr_fail_str[IBL_STR_LEN] = "IBL: DDR TEST FAIL\n";
- int8 ibl_msg_str1[IBL_STR_LEN] = "IBL: PLL SEQ DONE \n";
-
-
+ int8 ddr_result_code_str[IBL_RESULT_CODE_STR_LEN] = "IBL Result code 0";
/* The emif registers must be made visible. MPAX mapping 2 is used */
DEVICE_REG_XMPAX_L(2) = 0x10000000 | 0xff; /* replacement addr + perm*/
DEVICE_REG_XMPAX_H(2) = 0x2100000B; /* base addr + seg size (64KB)*/
- for (loopcount = 0; loopcount < PLL_DDR_INIT_LOOPMAX ; loopcount++)
+ for (loopcount = 0; loopcount < PLL_DDR_INIT_LOOPMAX; loopcount++)
{
if(loopcount !=0) /*Do not call PLL sequence for the first time */
{
hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
/* Init UART */
uart_init();
- /* Write something to UART */
- uart_write_string(ibl_msg_str1,IBL_STR_LEN);
#ifdef DDR3_TEST_ENABLE
if (ddr3_memory_test() == 0)
{
- uart_write_string(ddr_pass_str,IBL_STR_LEN);
break;
}
#endif
- uart_write_string(ddr_fail_str,IBL_STR_LEN);
}
+ if (loopcount < 10)
+ {
+ ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + '0';
+ }
+ else if ((loopcount >= 10) && (loopcount < 35))
+ {
+ ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + 'A';
+ }
+ else
+ {
+ ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + 'Z';
+ }
+
+ if (loopcount == PLL_DDR_INIT_LOOPMAX)
+ {
+ uart_write_string("IBL: DDR INITIALIZATION FAILED",0);
+ }
+ else
+ {
+ uart_write_string("IBL: PLL and DDR Initialization Complete",0);
+ }
+ uart_write_string(ddr_result_code_str,0);
}
index 639e130db3c32d4d31ce347365a48ba95394de93..1f0472efb86f39772c961730495501d9a89aeed5 100755 (executable)
static void uart_delay_cycles(uint32_t cycles)
{
- while (cycles--) {
- asm ("NOP");
- }
+ while (cycles--) {
+ asm ("NOP");
+ }
}
+/******************************************************************************
+ *
+ * Function: uart_init
+ *
+ * Description: This function initializes UART peripheral for C66x
+ *
+ * Parameters: str - string to print
+ * length - length of the string to print
+ *
+ * Return Value: none
+ ******************************************************************************/
void uart_init(void)
{
- uint16_t uiBaudRate;
- uint8_t uiDLLVal = 0;
- uint8_t uiDLHVal = 0;
+ uint8_t DLL_val = 0;
+ uint8_t DLH_val = 0;
- // Allows access to the divisor latches of the baud generator during a
- // read or write operation (DLL and DLH)
+ /* Setting baud rate to 115200 */
+ DLL_val = (uint8_t )(0x00FF & BAUD_RATE_115200);
+ DLH_val = (uint8_t )(0x00FF & (BAUD_RATE_115200 >> 8));
- hUartRegs->LCR = 0x80;
+ /* Allows access to the divisor latches of the baud generator during a
+ read or write operation (DLL and DLH) */
- // Set the baudrate,for accessing LCR[7] should be enable
- hUartRegs->DLL = DLL_VAL;
- hUartRegs->DLH = DLM_VAL;
+ uart_registers->LCR = 0x80;
- // Allows access to the receiver buffer register (RBR),
- // the transmitter holding register (THR), and the
- // interrupt enable register (IER) selected.
- hUartRegs->LCR = 0x18;
+ /* Set the baudrate,for accessing LCR[7] should be enable */
+ uart_registers->DLL = DLL_val;
+ uart_registers->DLH = DLH_val;
- // Disable THR, RHR, Receiver line status interrupts
- hUartRegs->IER = 0;
+ /* Allows access to the receiver buffer register (RBR),
+ the transmitter holding register (THR), and the
+ interrupt enable register (IER) selected. */
+ uart_registers->LCR = 0x18;
+
+ /* Disable THR, RHR, Receiver line status interrupts */
+ uart_registers->IER = 0;
/* If autoflow control is desired,
- * write appropriate values to the modem
- * control register (MCR). Note that all UARTs
- * do not support autoflow control, see
- * the device-specific data manual for supported features.
- *
- * MCR
- * ====================================================
- * Bit Field Value Description
- * 5 AFE 0 Autoflow control is disabled
- * 4 LOOP 0 Loop back mode is disabled.
- * 1 RTS 0 RTS control (UARTn_RTS is disabled,
- * UARTn_CTS is only enabled.)
- * =====================================================
- *
- *
- */
-
- hUartRegs->MCR = 0;
+ * write appropriate values to the modem
+ * control register (MCR). Note that all UARTs
+ * do not support autoflow control, see
+ * the device-specific data manual for supported features.
+ *
+ * MCR
+ * ====================================================
+ * Bit Field Value Description
+ * 5 AFE 0 Autoflow control is disabled
+ * 4 LOOP 0 Loop back mode is disabled.
+ * 1 RTS 0 RTS control (UARTn_RTS is disabled,
+ * UARTn_CTS is only enabled.)
+ * =====================================================
+ *
+ *
+ */
+
+ uart_registers->MCR = 0;
/* Choose the desired response to
- * emulation suspend events by configuring
- * the FREE bit and enable the UART by setting
- * the UTRST and URRST bits in the power and
- * emulation management register (PWREMU_MGMT).
- *
- *
- * PWREMU_MGMT
- * =================================================
- * Bit Field Value Description
- * 14 UTRST 1 Transmitter is enabled
- * 13 URRST 1 Receiver is enabled
- * 0 FREE 1 Free-running mode is enabled
- * ===================================================
- *
- */
- hUartRegs->PWREMU_MGMT = 0x6001;
+ * emulation suspend events by configuring
+ * the FREE bit and enable the UART by setting
+ * the UTRST and URRST bits in the power and
+ * emulation management register (PWREMU_MGMT).
+ *
+ *
+ * PWREMU_MGMT
+ * =================================================
+ * Bit Field Value Description
+ * 14 UTRST 1 Transmitter is enabled
+ * 13 URRST 1 Receiver is enabled
+ * 0 FREE 1 Free-running mode is enabled
+ * ===================================================
+ *
+ */
+ uart_registers->PWREMU_MGMT = 0x6001;
/* Cleanup previous data (rx trigger is also set to 0)*/
- /* Set FCR = 0x07; */
- hUartRegs->FCR = 0xC1;
-
- /* Setting baud rate to 115200 */
- uiBaudRate = 88;
+ uart_registers->FCR = 0xC1;
/* Setting the baud rate */
- hUartRegs->LCR = 0x80;
- uiDLLVal = (uint8_t )(0x00FF & uiBaudRate);
- uiDLHVal = (uint8_t )(0x00FF & (uiBaudRate >> 8));
-
- // Set the baudrate,for accessing LCR[7] should be enable
- hUartRegs->DLL = uiDLLVal;
- hUartRegs->DLH = uiDLHVal;
- hUartRegs->LCR = 0x03;
-
- hUartRegs->LCR = 0x80;
- uiDLLVal = (uint8_t )(0x00FF & uiBaudRate);
- uiDLHVal = (uint8_t )(0x00FF & (uiBaudRate >> 8));
- // Set the baudrate,for accessing LCR[7] should be enable
- hUartRegs->DLL = uiDLLVal;
- hUartRegs->DLH = uiDLHVal;
- hUartRegs->LCR = 0x03;
+ uart_registers->LCR = 0x80;
+
+ /* Set the baudrate,for accessing LCR[7] should be enable */
+ uart_registers->DLL = DLL_val;
+ uart_registers->DLH = DLH_val;
+ uart_registers->LCR = 0x03;
return;
}
/******************************************************************************
*
- * Function: uart_write_byte
+ * Function: uart_write_byte
*
- * Description: This function writes a byte of data to UART device
+ * Description: This function writes a byte of data to UART device
*
- * Parameters: uint8_t uchAddress - Address of 8-bit register
- * uint8_t uchByte - 8-bit data to write to THR
+ * Parameters: byte - 8-bit data to write to THR
*
* Return Value: none
******************************************************************************/
-static void uart_write_byte(uint8_t uchByte)
+static inline void uart_write_byte(uint8_t byte)
{
- while (!(hUartRegs->LSR & UART_LSR_THRE_MASK)) {
- uart_delay_cycles(10000);
+ while (!(uart_registers->LSR & UART_LSR_THRE_MASK)) {
+ uart_delay_cycles(10000);
}
- hUartRegs->THR = (UART_THR_DATA_MASK & uchByte);
+ uart_registers->THR = (UART_THR_DATA_MASK & byte);
return;
}
-void uart_write_string(uint8_t * str, uint32_t length)
+/******************************************************************************
+ *
+ * Function: uart_write_string
+ *
+ * Description: This function writes a string of data to UART device
+ *
+ * Parameters: str - string to print
+ * length - length of the string to print, maximum is 80
+ *
+ * Return Value: none
+ ******************************************************************************/
+void uart_write_string(char * str, uint32_t length)
{
- uint32_t i;
- uart_write_byte((uint8_t)0x0D);
- uart_write_byte((uint8_t)0x0A);
- for(i = 0; i < length; i++)
- {
- uart_write_byte(str[i]);
- }
+ uint32_t i;
+ if (length==0)
+ {
+ /*Maximum length is 80 */
+ length=80;
+ }
+ for(i = 0; i < length; i++) {
+ if(str[i]=='\0') break;
+ uart_write_byte((uint8_t)str[i]);
+ }
+ uart_write_byte((uint8_t)0x0D);
+ uart_write_byte((uint8_t)0x0A);
}
index a638eaf71508d1425e97706977d4f8960d7c64ac..5dad2766d258c9f73d54b2ce19a8553d468b8554 100755 (executable)
/******************************************************************************
*
- * File Name: evmc66x_i2c_uart.h
+ * File Name: evmc66x_uart.h
*
- * Description: This contains UART specific structure, typedefs, function
- * prototypes.
+ * Description: This contains UART specific structure, typedefs, function
+ * prototypes.
*
******************************************************************************/
-#ifndef _EVM66X_I2C_UART_H_
-#define _EVM66X_I2C_UART_H_
+#ifndef _EVM66X_I2C_UART_H_
+#define _EVM66X_I2C_UART_H_
+
#include <stdint.h>
#define UART_REGS_BASE (0x02540000)
-/**************************************************************************\
-* Register Overlay Structure
-\**************************************************************************/
+/**************************************************************************
+ * Register Overlay Structure
+ **************************************************************************/
typedef struct {
volatile uint32_t RBR;
volatile uint32_t IER;
volatile uint32_t REVID2;
volatile uint32_t PWREMU_MGMT;
volatile uint32_t MDR;
-} UartRegs;
-
-/************************
- * Defines and Macros
- ************************/
-/* Mask to enable DLL and DLM */
-#define DLAB (0x80) // Way to swap mem banks
+} uart_registers_t;
-/* for 19200 baudrate for crystal clock 14.7456 MHz*/
-#define DLL_VAL (0x30)
-#define DLM_VAL (0x00)
+/* Mask to enable DLL and DLM */
+#define DLAB (0x80) /* Way to swap mem banks */
-/* Macros to be used for setting baudrate */
-#define BAUD_RATE_9600 (0x0060)
-#define BAUD_RATE_19200 (0x0030)
-#define BAUD_RATE_56000 (0x0010)
-#define BAUD_RATE_115200 (0x0008)
+/* Baudrate table for crystal clock 14.7456 MHz*/
+#define BAUD_RATE_9600 (0x0060)
+#define BAUD_RATE_19200 (0x0030)
+#define BAUD_RATE_115200 (0x0058)
-#define hUartRegs ((UartRegs*) UART_REGS_BASE)
+#define uart_registers ((uart_registers_t*) UART_REGS_BASE)
/* Following 2 lines are added due to CSL3.x tools limitations */
#define THR RBR /* RBR & THR have same offset */
/************************
* Function declarations
-************************/
+ ************************/
void uart_init(void);
-void uart_write_string(uint8_t * str, uint32_t length);
+void uart_write_string(char * str, uint32_t length);
+
#endif /* _EVM66X_I2C_UART_H_ */
diff --git a/src/main/iblmain.c b/src/main/iblmain.c
index cbbcad73c610b897bd8a96300a056200107fefd8..20955acb23ce220aea3da09d6b2afe6c2c6d7dbc 100755 (executable)
--- a/src/main/iblmain.c
+++ b/src/main/iblmain.c
#include "spi_api.h"
#include "ibl_elf.h"
#include <string.h>
+#include "evmc66x_uart.h"
extern cregister unsigned int IER;
#ifndef EXCLUDE_ETH
case ibl_BOOT_MODE_TFTP:
iblStatus.activeDevice = ibl_ACTIVE_DEVICE_ETH;
+ /*Print something to UART, max len=80, if len is pased as 0 UART prints entire string upto '\n' or max len */
+ uart_write_string("IBL: Booting from ethernet",0);
iblMemcpy (&iblStatus.ethParams, &ibl.bootModes[boot_mode_idx].u.ethBoot.ethInfo, sizeof(iblEthBootInfo_t));
iblEthBoot (boot_mode_idx);
break;
case ibl_BOOT_MODE_NAND:
iblPmemCfg (ibl.bootModes[boot_mode_idx].u.nandBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
memset ((void *)0x80000000, 0, 0x20000000);
+ /*Print something to UART, max len=80, if len is pased as 0 UART prints entire string upto '\n' or max len */
+ uart_write_string("IBL: Booting from NAND",0);
iblNandBoot (boot_mode_idx);
break;
#endif
#if (!defined(EXCLUDE_NOR_EMIF) && !defined(EXCLUDE_NOR_SPI))
case ibl_BOOT_MODE_NOR:
iblPmemCfg (ibl.bootModes[boot_mode_idx].u.norBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
+ /*Print something to UART, max len=80, if len is pased as 0 UART prints entire string upto '\n' or max len */
+ uart_write_string("IBL: Booting from NOR",0);
iblNorBoot (boot_mode_idx);
break;
#endif
case ibl_BOOT_MODE_TFTP:
iblStatus.activeDevice = ibl_ACTIVE_DEVICE_ETH;
iblMemcpy (&iblStatus.ethParams, &ibl.bootModes[boot_mode_idx].u.ethBoot.ethInfo, sizeof(iblEthBootInfo_t));
+ /*Print something to UART, max len=80, if len is pased as 0 UART prints entire string upto '\n' or max len */
+ uart_write_string("IBL: Booting from Ethernet",0);
iblEthBoot (boot_mode_idx);
break;
#endif
#if ((!defined(EXCLUDE_NAND_EMIF)) || (!defined(EXCLUDE_NAND_GPIO)))
case ibl_BOOT_MODE_NAND:
iblPmemCfg (ibl.bootModes[boot_mode_idx].u.nandBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
+ /*Print something to UART, max len=80, if len is pased as 0 UART prints entire string upto '\n' or max len */
+ uart_write_string("IBL: Booting from NAND",0);
iblNandBoot (boot_mode_idx);
break;
#endif