6670 LC: NAND specific definitions
authorSandeep Paulraj <s-paulraj@ti.com>
Wed, 18 May 2011 15:40:31 +0000 (11:40 -0400)
committerSandeep Paulraj <s-paulraj@ti.com>
Wed, 18 May 2011 15:40:31 +0000 (11:40 -0400)
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
src/cfg/c661x/iblcfg.h

index c509fb7b5d313826a8281a843c37b13a064dbb39..d4478c56b77a3b4e610a691dd3c70882682b5744 100644 (file)
  #define IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW     0
 #endif
 
+#define NAND_CLE_GPIO_PIN GPIO_8     /*High: Command Cycle occuring */
+#define NAND_ALE_GPIO_PIN GPIO_9     /* High: Address input cycle oddcuring */
+#define NAND_NWE_GPIO_PIN GPIO_10
+#define NAND_BSY_GPIO_PIN GPIO_11     /* NAND Ready/Busy pin */
+#define NAND_NRE_GPIO_PIN GPIO_12
+#define NAND_NCE_GPIO_PIN GPIO_13
+
+/**
+ *  @brief
+ *      The standard NAND delay must be big enough to handle the highest possible
+ *      operating frequency of the device */
+#define TARGET_NAND_STD_DELAY          50 // In cpu cycles
+#define NAND_WAIT_PIN_POLL_ST_DLY      (10000)
+
 
 #endif