Renamed ifdef flag, init uart from iblmain

diff --git a/src/device/c66x/c66x.c b/src/device/c66x/c66x.c
index 7fe8c3e50d9f0bff891fe2dcec5d631300d416e8..a285ca503f9f97f596e4649cfa93a1220a4b4d71 100755 (executable)
--- a/src/device/c66x/c66x.c
+++ b/src/device/c66x/c66x.c
@@ -138,7 +138,7 @@ void deviceDdrConfig (void)
     if (ibl.ddrConfig.configDdr != 0)
         hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
 
-#ifdef DDR3_TEST_ENABLE
+#ifdef PLL_REINIT_WORKAROUND
     for (loopcount = 0; loopcount < PLL_DDR_INIT_LOOPMAX; loopcount++)
     {
        if (ddr3_memory_test() == 0) 
@@ -170,9 +170,9 @@ void deviceDdrConfig (void)
          
         if (ibl.ddrConfig.configDdr != 0)
             hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
-        /* Init UART 
-        uart_init();*/
     }
+    /* Init UART again because we are re-initializing the PLL's */ 
+    uart_init();
 
     if (loopcount < 10) 
     {

diff --git a/src/device/c66x/c66xutil.c b/src/device/c66x/c66xutil.c
index c895bcfdf72711dc0a8bcd6bb85445edea8a755d..1edf768a0a0a3d7a0834c64e1ceb44d8dd58d981 100644 (file)
--- a/src/device/c66x/c66xutil.c
+++ b/src/device/c66x/c66xutil.c
@@ -6,6 +6,7 @@
  */
 
 #include "device.h"
+#include "target.h"
 #include "pllapi.h"
 #include <string.h>
 #include <stdint.h>
@@ -131,7 +132,7 @@ int32 devicePowerPeriph (int32 modNum)
         
 }
 
-#ifdef DDR3_TEST_ENABLE
+#ifdef PLL_REINIT_WORKAROUND
 /**
  *  @brief Simple DDR3 test
  *

diff --git a/src/device/c66x/target.h b/src/device/c66x/target.h
index bd4065143b0a301ebf329d5dfc7720e0001e5f43..763207ff7dc019f01b63a66cc3d0fb9e2f3d5bdf 100644 (file)
--- a/src/device/c66x/target.h
+++ b/src/device/c66x/target.h
@@ -56,7 +56,7 @@
 #include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
- 
+
  
 /** 
  *  @brief
@@ -416,7 +416,7 @@ Int32 targetMacRcv (void *ptr_device, UINT8 *buffer);
  *  @brief
  *     Software workaround for DDR3 memory corruption is to re-init the PLL's and DDR controller. This flag enables the workaround
  */
-#define DDR3_TEST_ENABLE
+#define PLL_REINIT_WORKAROUND
 
 extern int32_t ddr3_memory_test();
 

diff --git a/src/main/iblmain.c b/src/main/iblmain.c
index 52f6c107452ef54cec8909a13585cbdc0f500725..49c637a48b10db511ea595a4b456d7879ff801f7 100755 (executable)
--- a/src/main/iblmain.c
+++ b/src/main/iblmain.c
@@ -245,6 +245,8 @@ void main (void)
     iblStatus.iblMagic   = ibl_MAGIC_VALUE;
     iblStatus.iblVersion = ibl_VERSION;
 
+    /* Init UART */
+     uart_init();
 
     /* Power up the timer */
     devicePowerPeriph (TARGET_PWR_TIMER_0);