Added NOR over I2C and POST I2C boot
authorHao Zhang <hzhang@ti.com>
Tue, 15 Feb 2011 20:01:16 +0000 (15:01 -0500)
committerHao Zhang <hzhang@ti.com>
Tue, 15 Feb 2011 20:01:16 +0000 (15:01 -0500)
24 files changed:
src/device/c6455/target.h
src/device/c6457/target.h
src/device/c6472/target.h
src/device/c6474/target.h
src/device/c661x/c661xinit.c
src/device/c661x/target.h
src/device/c661x/tiboot_c661x.h
src/hw/spi/spi_loc.h
src/interp/elf/dload.c
src/main/iblinit.c
src/main/ibliniti2c.c
src/make/Makefile
src/make/ibl_c661x/spiRom.map.pre [new file with mode: 0644]
src/make/makestg1
src/make/setupenv.bat
src/util/i2cConfig/i2cConfig.gel
src/util/i2cConfig/i2cparam.c
src/util/i2cConfig/makestg2
src/util/i2cRead/i2cRead.c
src/util/i2cRead/makestg2
src/util/i2cWrite/i2cWrite.c
src/util/i2cWrite/makestg2
src/util/romparse/Makefile
src/util/romparse/romparse.c

index 2551d31aa0076b901c9fdfe167b5fd8621fc01c7..0eaa973680dcfd2287f92afc44a8230596aa1169 100644 (file)
  */
 #define deviceReadBootDevice()  BOOT_DEVICE_I2C
 
+#define IBL_REENTER_ROM         0
+#define iblReEnterRom()     
 
  
 
index 81ead8494ca9d57c8e1a68a2459a80c3b2ab34f0..9853337a7045f298627347099d43400a548e5c57 100644 (file)
  */
 #define deviceReadBootDevice()  BOOT_DEVICE_I2C
 
+#define IBL_REENTER_ROM         0
+#define iblReEnterRom()     
index 7cdfc6cce296ac51e88b7dfa0c7e682078d677b8..135f12e8cc6894c2c6908876fc19579a061c979f 100644 (file)
  */
 #define deviceReadBootDevice()  BOOT_DEVICE_I2C
 
+#define IBL_REENTER_ROM         0
+#define iblReEnterRom()     
index 88b6f9d9474ac42e5d311fca21b7f2efc8608de8..ef82b36afd48ae1e79c3cc479157fb489a1b25fd 100644 (file)
  */
 #define deviceReadBootDevice()  BOOT_DEVICE_I2C
 
+#define IBL_REENTER_ROM         0
+#define iblReEnterRom()     
+
index be07171b26362c50a007fe94a9ed1456d036fc4a..58c144d788c99d039b72be0bb5953a1210f963d0 100644 (file)
@@ -10,6 +10,7 @@
 #include "device.h"
 #include "pllapi.h"
 #include "spi_api.h"
+#include "spi_loc.h"
 #include "tiboot_c661x.h"       
 
 
@@ -126,6 +127,63 @@ int32 deviceReadBootDevice (void)
     return (w);
 }
 
+#define FPGA_BOOT_MODE_REG              0
+#define FPGA_READ_BOOT_MODE_REG_CMD     ((FPGA_BOOT_MODE_REG | 0x80) << 8)
+/**
+ *  @brief
+ *      Re-enter the ROM boot loader if the FPGA boot register
+ *      indicates it was not I2C or SPI boot, this is necessary
+ *      to apply the PLL workaround for ROM boot modes
+ */
+void iblReEnterRom ()
+{
+    uint32      reg =  DEVICE_REG32_R (DEVICE_REG_DEVSTAT);
+    uint32      v;
+    void        (*exit)();
+
+    /* Reset */
+    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
+
+    /* Release Reset */
+    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_ENABLE);
+
+    /* CS1, CLK, in and out are functional pins, FPGA uses SPI CS1 */
+    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIPC0, 0xe02);
+
+    /* prescale=7, char len=16 */
+    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIFMT(0), 0x710);
+
+    /* C2TDELAY=0x6, T2CDELAY=0x3 */
+    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIDELAY, 0x6030000);
+
+    /* Clear the SPIDAT0 */
+    //DEVICE_REG32_R (DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0);
+
+    /* Master mode, enable SPI */
+    DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR1, 0x01000003);
+
+    /* Send the read register address to FPGA */
+       DEVICE_REG32_W(DEVICE_SPI_BASE(0) + 0x38, FPGA_READ_BOOT_MODE_REG_CMD);
+
+    chipDelay32(10000);
+
+    /* Check if received the data */
+    v = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIFLG);
+    if ( v & 0x100)
+    {
+        v = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIBUF) & 0xff;
+
+        /* Add code to check the boot mode in FPGA register, if not I2C, configure the 
+           devstat with the actual boot mode and re-enter ROM boot loader */
+#if 0
+        exit = (void (*)())BOOT_ROM_REENTER_ADDRESS;
+        (*exit)();
+#endif
+    }
+
+}
+
+
 
 #if (!defined(EXCLUDE_NOR_SPI) || !defined(EXCLUDE_NAND_SPI))
 /**
index 968a8ec5085912adbd8c4331aea380a23e0925ef..e8093b3656d8f0db439327b760c5b7478f9a23ca 100644 (file)
  *   The PSC numbers for EMIF16 and SPI vary between devices. The devices are run time
  *   identified by reading the JTAG ID register 
  */
-#define DEVICE_C6616_JTAG_ID_VAL    0x9d02f
-#define DEVICE_C6618_JTAG_ID_VAL    0x9e02f
+#define DEVICE_C6616_JTAG_ID_VAL    0x9d02f     /* C6670 */
+#define DEVICE_C6618_JTAG_ID_VAL    0x9e02f     /* C6678 */     
 #define DEVICE_JTAG_ID_REG          0x2620018
 
 
@@ -212,6 +212,12 @@ uint32 deviceNandMemBase (int32 cs);
 #define DEVICE_I2C_BASE                 0x02530000
 #define DEVICE_I2C_MODULE_DIVISOR       6
  
+/**
+ * @brief
+ *      The address of the DEVSTAT register
+ */
+#define DEVICE_REG_DEVSTAT              0x02620020
+
 /**
  * @brief
  *     Prototypes for the PLL functions handled outside the main PLL registers
@@ -341,4 +347,10 @@ Int32 targetMacRcv (void *ptr_device, UINT8 *buffer);
 #define deviceConfigureForNor()    0
 
 
+/**
+ *  @brief
+ *      Support for PLL workaround to re-enter ROM boot loader.
+ */
+#define IBL_REENTER_ROM            1
+
 #endif /* _TARGET_H */
index bdf6e8534537b832b332078a0ded2006783b4add..f481ab8b60f6564d5be8a30597a56070d300f2da 100644 (file)
@@ -919,7 +919,8 @@ typedef struct bootEmif4Tbl_s  {
 #define BOOT_MODE_I2C               40
 #define BOOT_MODE_SPI               50
 
-
+/* ROM boot loader re-enter address */
+#define BOOT_ROM_REENTER_ADDRESS    0x20b00008
 
 #endif  /* __TIBOOT_H__ */
 
index 00c3f43d69c10e12fe1158d212a33d90ca8b2fd8..679dd21cfd71dabc88e5fa50d1d28ab1bb25e1a0 100644 (file)
@@ -14,6 +14,7 @@
 #define SPI_REG_SPIGCR1         0x04
 #define SPI_REG_SPIFLG          0x10
 #define SPI_REG_SPIPC0          0x14
+#define SPI_REG_SPIDAT0         0x38
 #define SPI_REG_SPIDAT1         0x3c
 #define SPI_REG_SPIBUF          0x40
 #define SPI_REG_SPIDELAY        0x48
index ce548b869ed48e380ebb69e4223d578f731a32b2..5f69ce41d7c45e64fda6bce20d7d5a0ca9162a4c 100644 (file)
@@ -2411,9 +2411,8 @@ int32_t DLOAD_load(LOADER_FILE_DESC *fd, int argc, char** argv, int32_t *entry)
    /*------------------------------------------------------------------------*/
    *entry = 0;
    if (!dyn_module->relocatable)  {
-      return (dload_static_executable(fd, dyn_module));
       *entry = dyn_module->fhdr.e_entry;
-      return (0); 
+      return (dload_static_executable(fd, dyn_module));
    }
 
 #if 0
index 46b48fe67bbb7cb543bf7689815d70bc87bd0b49..aa177ae11a2f3ae79aaa0a0ab5318ae13eca1f1d 100644 (file)
@@ -460,6 +460,11 @@ void main (void)
     /* Pll configuration is device specific */
     devicePllConfig ();
 
+    /* iblReEnterRom () */
+    if (IBL_REENTER_ROM)
+    {
+        iblReEnterRom ();
+    }
 
     /* Pass control to the boot table processor */
     iblBootBtbl (bFxnTbl, &entry);
index b17d5cd0170ee0a922d8d9a3ff32164eca4bd458..ab299b6902f64383f4c2e515f39f160cbfcf9a13 100644 (file)
@@ -48,7 +48,7 @@
  *      A global value is used to track the read through the i2c during
  *      the program load.
  */
-uint32 i2cReadAddress;
+uint32 i2cReadAddress, i2cBusAddress;
 
 /**
  *  @brief
@@ -64,7 +64,7 @@ void i2cReadBlock (void)
         while (hwI2cMasterRead (i2cReadAddress & 0xffff,    /* The address on the eeprom of the table */
                                 4,                          /* The number of bytes to read */
                                 iData,                      /* Where to store the bytes */
-                                i2cReadAddress >> 16,       /* The bus address of the eeprom */
+                                i2cBusAddress,              /* The bus address of the eeprom */
                                 IBL_CFG_I2C_ADDR_DELAY)     /* The delay between sending the address and reading data */
     
              != I2C_RET_OK)  {
@@ -83,7 +83,7 @@ void i2cReadBlock (void)
         while (hwI2cMasterRead (i2cReadAddress & 0xffff,    /* The address on the eeprom of the table */
                                 len,                        /* The number of bytes to read */
                                 iData,                      /* Where to store the bytes */
-                                i2cReadAddress >> 16,       /* The bus address of the eeprom */
+                                i2cBusAddress,              /* The bus address of the eeprom */
                                 IBL_CFG_I2C_ADDR_DELAY)     /* The delay between sending the address and reading data */
     
              != I2C_RET_OK)  {
@@ -210,6 +210,7 @@ BOOT_MODULE_FXN_TABLE *iblInitI2c (void)
 
                 }
 
+                i2cBusAddress = i2cReadAddress >>16;
 
                 if (map.length != sizeof(iblBootMap_t))  {
                     iblStatus.mapSizeFail += 1;
index c106746c7b64b2b064b165c50f9bcff36ff9ee1d..4e1f0574e8632e098ef9ac6469767bd25da3a028 100644 (file)
@@ -287,6 +287,15 @@ EVM_6608_SPI_DEFS= SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL
 evm_c6608:
        make -f makestg1 ARCH=c64x TARGET=c661x I2C=no I2C_BUS_ADDR=0x50 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
 
+# The 6678 EVM SPI/NOR Boot
+EVM_6678_SPI_DEFS= SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=1 SPI_CLKDIV=8 SPI_ROM=1
+
+evm_c6678_spi:
+       make -f makestg1 ARCH=c64x TARGET=c661x I2C=no I2C_BUS_ADDR=0x51 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
+
+evm_c6678_i2c:
+       make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
+
 test_c661x:
        make -f makestg1 ARCH=c64x TARGET=c661x ENDIAN_MODE=both CEXCLUDES='NOR_SPI' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 COMPACT_I2C=no c661x
        make -f makestg1 ARCH=c64x TARGET=c661x ENDIAN_MODE=both CEXCLUDES='NAND_SPI' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 COMPACT_I2C=no c661x
diff --git a/src/make/ibl_c661x/spiRom.map.pre b/src/make/ibl_c661x/spiRom.map.pre
new file mode 100644 (file)
index 0000000..2568761
--- /dev/null
@@ -0,0 +1,80 @@
+#include "iblcfg.h"
+;  This file is run through the C preprocessor to get the build time layout information
+;  The following values must be defined:
+;     SPI_CSEL       - The SPI chip select of the eeprom holding the ROM boot info and the layout info
+;     SPI_ADDR_WIDTH - Number of bits in the SPI address
+;     SPI_NPINS                 - Number of pins used by the interface (4 or 5)
+;     SPI_MODE       - SPI operation mode (0-3)
+;        INIT_EXE_FILE  - The SPI blocked stage 1 of the ibl
+;     EXE_FILE_1     - The SPI blocked stage 2 of the ibl, must be the little endian version
+;     EXE_FILE_2        - The SPI blocked stage 2 of the ibl, must be the big endian version
+;     PAD_FILE_ID_1  - This pad holds the IBL configuration structure for the little endian version
+;     PAD_FILE_ID_2  - This pad holds the IBL configuration structure for the big endian version
+;
+;  The section statement directs the ROM boot loader to load the initial endian independent 
+;  portion of the IBL
+section 
+{
+  param_index    = 0
+  boot_mode      = 50
+  sw_pll_prediv         = 0
+  sw_pll_mult    = 0
+  sw_pll_postdiv = 0
+  sw_pll_flags   = 0
+
+  options        = 1
+  core_freq_mhz  = 800
+
+  bus_freq_mhz     = 1
+  bus_freq_khz     = 0
+
+  addr_width   = SPI_ADDR_WIDTH
+  n_pins       = SPI_NPIN
+  mode         = SPI_MODE
+  csel         = SPI_CSEL
+
+  exe_file = INIT_EXE_FILE
+}
+
+; The layout statement defines how the resulting SPI image is layed out. The base address
+; of this (given in the dev_addr) statement must be known to the initial IBL program
+; at compile time. The layout block is simple a group of 32 bit i2c addresses, so 
+; the order of the exe_file and pad_file_id statements must be configured so as to
+; match the definition of struct iblI2cMap_t defined in ibl.h.
+layout
+{
+  dev_addr     = IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_LSW           ; Defined in iblcfg.h
+  dev_addr_ext = IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW
+  file_align   = 0x80
+
+  exe_file    = EXE_FILE_1
+  pad_file_id = PAD_FILE_ID_1
+
+
+  exe_file    = EXE_FILE_2
+  pad_file_id = PAD_FILE_ID_2
+}
+
+; The pad statements simply provide space for the IBL configuration structures. It is valid to
+; have a single configuration structure which is used for both endian values.
+pad
+{
+  pad_file_id  = 1
+  dev_addr     = 0x500
+  dev_addr_ext = IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW
+  len          = 0x300
+}
+
+#if (PAD_FILE_ID_1 != PAD_FILE_ID_2)
+pad
+{
+  pad_file_id  = 2
+  dev_addr     = 0x800
+  dev_addr_ext = I2C_BUS_ADDR
+  len          = IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW
+}
+#endif
+
+
+
+
index 93540424ace39c91a6a1a935390d326b1315c994..33bbde74f86e3e6f542fc295294d4116252e3307 100644 (file)
@@ -36,7 +36,7 @@ EXCLUDES= $(CEXCLUDES)
 
 # The default i2c size. This is used only for the i2c writer utility
 ifndef I2C_SIZE_BYTES
- I2C_SIZE_BYTES=0x20000
+ I2C_SIZE_BYTES=0x10000
 endif
 
 # exclusions based on device capability
index f90b425418b52e5e81acf74dda1c634fd4d857cd..7d64a43737c8e8ce07e132396ea07cfa9e5933e8 100644 (file)
@@ -31,7 +31,7 @@ REM  Setup the ibl build environment
 REM Modify following lines based on target environment for the toolset installed 
 REM Dependency is related to path for Cygwin and CGEN installed
 
-set PATH=t:\gen\gnu\99-11-01\cygwin-b20\H-i586-cygwin32\bin;C:\PROGRA~1\TEXASI~1\C6000C~1.12\bin
+set PATH=t:\gen\gnu\99-11-01\cygwin-b20\H-i586-cygwin32\bin;C:\PROGRA~1\TEXASI~1\C6000C~.2.0\bin
 set PATH=%PATH%;%SystemRoot%\system32;%SystemRoot%;
 
 set PERL=//t/gen/perl/activestate/5_6_1_635/bin/perl
@@ -39,11 +39,11 @@ set PERLDOS=t:\gen\perl\activestate\5_6_1_635\bin\perl
 
 set CYGWINPATH=//t/gen/gnu/99-11-01/cygwin-b20/H-i586-cygwin32/bin
 set BISONSKEL=t:\gen\gnu\99-11-01\cygwin-b20\share\bison.simple
-set TOOLSC6X=C:/PROGRA~1/TEXASI~1/C6000C~1.12
-set TOOLSC6XDOS=C:\PROGRA~1\TEXASI~1\C6000C~1.12
+set TOOLSC6X=C:/PROGRA~1/TEXASI~1/C6000C~.2.0
+set TOOLSC6XDOS=C:\PROGRA~1\TEXASI~1\C6000C~.2.0
 
-set TOOLC6XSRC=t:\c6xx\cgen6_1_12\c6000\cgtools
-set TOOLC6XDST=C:\PROGRA~1\TEXASI~1\C6000C~1.12
+set TOOLC6XSRC=t:\c6xx\cgen_7_2_0\c6000\cgtools
+set TOOLC6XDST=C:\PROGRA~1\TEXASI~1\C6000C~.2.0
 
 
 rem ************************* Tools Copy/Validation **************************
index 6ee17d45c01ef048c84c6478881e2902a5ef5073..f15968d6acd3c61d197a293839e3a087e0181a37 100755 (executable)
-#define TRUE  1\r
-#define FALSE 0\r
-\r
-#define ibl_MAGIC_VALUE                 0xCEC11EBB\r
-\r
-#define ibl_HIGHEST_PRIORITY     1  \r
-#define ibl_LOWEST_PRIORITY     10\r
-#define ibl_DEVICE_NOBOOT       20\r
-\r
-#define ibl_PORT_SWITCH_ALL     -2\r
-\r
-#define SETIP(array,i0,i1,i2,i3)      array[0]=(i0);  \\r
-                                      array[1]=(i1);  \\r
-                                      array[2]=(i2);  \\r
-                                      array[3]=(i3)\r
-\r
-#define  ibl_BOOT_MODE_TFTP     10\r
-#define  ibl_BOOT_MODE_NAND     11\r
-#define  ibl_BOOT_MODE_NOR      12\r
-#define  ibl_BOOT_MODE_NONE     13\r
-\r
-\r
-#define ibl_BOOT_FORMAT_AUTO    0\r
-#define ibl_BOOT_FORMAT_NAME    1\r
-#define ibl_BOOT_FORMAT_BIS     2\r
-#define ibl_BOOT_FORMAT_COFF    3\r
-#define ibl_BOOT_FORMAT_ELF     4\r
-#define ibl_BOOT_FORMAT_BBLOB   5\r
-#define ibl_BOOT_FORMAT_BTBL    6\r
-\r
-#define ibl_MAIN_PLL    0\r
-#define ibl_DDR_PLL     1\r
-#define ibl_NET_PLL     2\r
-\r
-#define ibl_EMIF4_ENABLE_sdRamConfig                  (1 <<  0)\r
-#define  ibl_EMIF4_ENABLE_sdRamConfig2                (1 <<  1)\r
-#define  ibl_EMIF4_ENABLE_sdRamRefreshCtl             (1 <<  2)\r
-#define  ibl_EMIF4_ENABLE_sdRamTiming1                (1 <<  3)\r
-#define  ibl_EMIF4_ENABLE_sdRamTiming2                (1 <<  4)\r
-#define  ibl_EMIF4_ENABLE_sdRamTiming3                (1 <<  5)\r
-#define  ibl_EMIF4_ENABLE_lpDdrNvmTiming              (1 <<  6)\r
-#define  ibl_EMIF4_ENABLE_powerManageCtl              (1 <<  7)\r
-#define  ibl_EMIF4_ENABLE_iODFTTestLogic              (1 <<  8)\r
-#define  ibl_EMIF4_ENABLE_performCountCfg             (1 <<  9)\r
-#define  ibl_EMIF4_ENABLE_performCountMstRegSel       (1 << 10)\r
-#define  ibl_EMIF4_ENABLE_readIdleCtl                 (1 << 11)\r
-#define  ibl_EMIF4_ENABLE_sysVbusmIntEnSet            (1 << 12)\r
-#define  ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg        (1 << 13)\r
-#define  ibl_EMIF4_ENABLE_tempAlterCfg                (1 << 14)\r
-#define  ibl_EMIF4_ENABLE_ddrPhyCtl1                  (1 << 15)\r
-#define  ibl_EMIF4_ENABLE_ddrPhyCtl2                  (1 << 16)\r
-#define  ibl_EMIF4_ENABLE_priClassSvceMap             (1 << 17)\r
-#define  ibl_EMIF4_ENABLE_mstId2ClsSvce1Map           (1 << 18)\r
-#define  ibl_EMIF4_ENABLE_mstId2ClsSvce2Map           (1 << 11)\r
-#define  ibl_EMIF4_ENABLE_eccCtl                      (1 << 19)\r
-#define  ibl_EMIF4_ENABLE_eccRange1                   (1 << 20)\r
-#define  ibl_EMIF4_ENABLE_eccRange2                   (1 << 21)\r
-#define  ibl_EMIF4_ENABLE_rdWrtExcThresh              (1 << 22)\r
-#define  ibl_BOOT_EMIF4_ENABLE_ALL                    0x007fffff\r
-    \r
-/* @} */  \r
-\r
-menuitem "EVM c6472 IBL";\r
-\r
-hotmenu setConfig_c6472()\r
-{\r
-    ibl.iblMagic = ibl_MAGIC_VALUE;\r
-\r
-    ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;\r
-    ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;\r
-    ibl.pllConfig[ibl_MAIN_PLL].mult          = 28;\r
-    ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 1;\r
-    ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;\r
-\r
-    /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
-    ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
-\r
-    /* The network PLL. The multipliers/dividers are fixed */\r
-    ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
-\r
-    /* EMIF configuration. The values are for DDR at 533 MHz  */\r
-    ibl.ddrConfig.configDdr = TRUE;\r
-\r
-    ibl.ddrConfig.uEmif.emif3p1.sdcfg  = 0x00538832; /* timing, 32bit wide */\r
-    ibl.ddrConfig.uEmif.emif3p1.sdrfc  = 0x0000073B; /* Refresh 533Mhz */ \r
-    ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */\r
-    ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */\r
-    ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
-\r
-    /* Ethernet configuration for port 0 */\r
-    ibl.ethConfig[0].ethPriority      = ibl_HIGHEST_PRIORITY;\r
-    ibl.ethConfig[0].port             = 0;\r
-\r
-    /* Bootp is disabled. The server and file name are provided here */\r
-    ibl.ethConfig[0].doBootp          = FALSE;\r
-    ibl.ethConfig[0].useBootpServerIp = FALSE;\r
-    ibl.ethConfig[0].useBootpFileName = FALSE;\r
-    ibl.ethConfig[0].bootFormat       = ibl_BOOT_FORMAT_AUTO;\r
-\r
-\r
-    SETIP(ibl.ethConfig[0].ethInfo.ipAddr,    10,218,109,21);\r
-    SETIP(ibl.ethConfig[0].ethInfo.serverIp,  10,218,109,196);\r
-    SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,2);\r
-    SETIP(ibl.ethConfig[0].ethInfo.netmask,   255,255,255,0);\r
-\r
-    /* Leave the hardware address as 0 so the e-fuse value will be used */\r
-\r
-\r
-\r
-\r
-    ibl.ethConfig[0].ethInfo.fileName[0]  = 't';\r
-    ibl.ethConfig[0].ethInfo.fileName[1]  = 'e';\r
-    ibl.ethConfig[0].ethInfo.fileName[2]  = 's';\r
-    ibl.ethConfig[0].ethInfo.fileName[3]  = 't';\r
-    ibl.ethConfig[0].ethInfo.fileName[4]  = '.';\r
-    ibl.ethConfig[0].ethInfo.fileName[5]  = 'o';\r
-    ibl.ethConfig[0].ethInfo.fileName[6]  = 'u';\r
-    ibl.ethConfig[0].ethInfo.fileName[7]  = 't';\r
-    ibl.ethConfig[0].ethInfo.fileName[8]  = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[9]  = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[10] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[11] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
-\r
-    /* Even though the entire range of DDR2 is chosen, the load will\r
-     * stop when the ftp reaches the end of the file */\r
-    ibl.ethConfig[0].blob.startAddress  = 0xe0000000;       /* Base address of DDR2 */\r
-    ibl.ethConfig[0].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */\r
-    ibl.ethConfig[0].blob.branchAddress = 0xe0000000;       /* Base of DDR2 */\r
-\r
-    /* For port 1 use bootp */\r
-    /* Ethernet configuration for port 0 */\r
-    ibl.ethConfig[1].ethPriority      = ibl_HIGHEST_PRIORITY + 1;\r
-    ibl.ethConfig[1].port             = 1;\r
-\r
-    /* Bootp is disabled. The server and file name are provided here */\r
-    ibl.ethConfig[1].doBootp          = TRUE;\r
-    ibl.ethConfig[1].useBootpServerIp = TRUE;\r
-    ibl.ethConfig[1].useBootpFileName = TRUE;\r
-    ibl.ethConfig[1].bootFormat       = ibl_BOOT_FORMAT_AUTO;\r
-\r
-\r
-    /* SGMII not present */\r
-       ibl.sgmiiConfig[0].adviseAbility = 0;\r
-       ibl.sgmiiConfig[0].control       = 0;\r
-       ibl.sgmiiConfig[0].txConfig      = 0;\r
-       ibl.sgmiiConfig[0].rxConfig      = 0;\r
-       ibl.sgmiiConfig[0].auxConfig     = 0;\r
-\r
-       ibl.sgmiiConfig[1].adviseAbility = 0;\r
-       ibl.sgmiiConfig[1].control       = 0;\r
-       ibl.sgmiiConfig[1].txConfig      = 0;\r
-       ibl.sgmiiConfig[1].rxConfig      = 0;\r
-       ibl.sgmiiConfig[1].auxConfig     = 0;\r
-\r
-\r
-    /* Leave the hardware address as 0 so the e-fuse value will be used */\r
-    ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
-\r
-\r
-    /* Leave all remaining fields as 0 since bootp will fill them in */\r
-\r
-\r
-    /* Even though the entire range of DDR2 is chosen, the load will */\r
-    /* stop when the ftp reaches the end of the file */\r
\r
-    ibl.ethConfig[1].blob.startAddress  = 0xe0000000;       /* Base address of DDR2 */\r
-    ibl.ethConfig[1].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */\r
-    ibl.ethConfig[1].blob.branchAddress = 0xe0000000;       /* Base of DDR2 */\r
-    \r
-\r
-\r
-    /* MDIO configuration */\r
-    ibl.mdioConfig.nMdioOps = 8;\r
-    ibl.mdioConfig.mdioClkDiv = 0x20;\r
-    ibl.mdioConfig.interDelay = 1400;   /* ~2ms at 700 MHz */\r
-\r
-    ibl.mdioConfig.mdio[0] =  (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;\r
-    ibl.mdioConfig.mdio[1] =  (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;\r
-    ibl.mdioConfig.mdio[2] =  (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;\r
-    ibl.mdioConfig.mdio[3] =  (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;\r
-\r
-    ibl.mdioConfig.mdio[4] =  (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;\r
-    ibl.mdioConfig.mdio[5] =  (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;\r
-    ibl.mdioConfig.mdio[6] =  (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;\r
-    ibl.mdioConfig.mdio[7] =  (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;\r
-\r
-\r
-    /* Nand boot is disabled */\r
-    ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
-\r
-    ibl.nandConfig.bootFormat   = ibl_BOOT_FORMAT_AUTO;\r
-\r
-    ibl.nandConfig.nandInfo.busWidthBits  = 8;\r
-    ibl.nandConfig.nandInfo.pageSizeBytes = 2048;\r
-    ibl.nandConfig.nandInfo.pageEccBytes  = 64;\r
-    ibl.nandConfig.nandInfo.pagesPerBlock = 64;\r
-    ibl.nandConfig.nandInfo.totalBlocks   = 1024;\r
-\r
-    ibl.nandConfig.nandInfo.addressBytes  = 4;\r
-    ibl.nandConfig.nandInfo.lsbFirst      = TRUE;\r
-    ibl.nandConfig.nandInfo.blockOffset   = 22;\r
-    ibl.nandConfig.nandInfo.pageOffset    = 16;\r
-    ibl.nandConfig.nandInfo.columnOffset  = 0;\r
-\r
-    ibl.nandConfig.nandInfo.resetCommand    = 0xff;\r
-    ibl.nandConfig.nandInfo.readCommandPre  = 0;\r
-    ibl.nandConfig.nandInfo.readCommandPost = 0x30;\r
-    ibl.nandConfig.nandInfo.postCommand     = TRUE;\r
-\r
-}\r
-\r
-\r
-menuitem "EVM c6474 Mez IBL";\r
-\r
-hotmenu setConfig_c6474()\r
-{\r
-    ibl.iblMagic = ibl_MAGIC_VALUE;\r
-\r
-    ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;\r
-    ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;\r
-    ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;\r
-    ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 1;\r
-    ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
-\r
-    /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
-    ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
-\r
-    /* The network PLL. The multipliers/dividers are fixed */\r
-    ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
-\r
-    /* EMIF configuration. The values are for DDR at 533 MHz  */\r
-    ibl.ddrConfig.configDdr = TRUE;\r
-\r
-    ibl.ddrConfig.uEmif.emif3p1.sdcfg  = 0x00d38a32; /* cas5, 8 banks, 10 bit column */\r
-    ibl.ddrConfig.uEmif.emif3p1.sdrfc  = 0x00000a29; /* Refresh 333Mhz */ \r
-    ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */\r
-    ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */\r
-    ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
-\r
-\r
-    /* Ethernet configuration for port 0 */\r
-    ibl.ethConfig[0].ethPriority      = ibl_HIGHEST_PRIORITY;\r
-    ibl.ethConfig[0].port             = 0;\r
-\r
-    /* Bootp is disabled. The server and file name are provided here */\r
-    ibl.ethConfig[0].doBootp          = FALSE;\r
-    ibl.ethConfig[0].useBootpServerIp = FALSE;\r
-    ibl.ethConfig[0].useBootpFileName = FALSE;\r
-    ibl.ethConfig[0].bootFormat       = ibl_BOOT_FORMAT_BBLOB;\r
-\r
-    SETIP(ibl.ethConfig[0].ethInfo.ipAddr,    10,218,109,35);\r
-    SETIP(ibl.ethConfig[0].ethInfo.serverIp,  10,218,109,196);\r
-    SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,1);\r
-    SETIP(ibl.ethConfig[0].ethInfo.netmask,   255,255,255,0);\r
-\r
-    /* Set the hardware address as 0 so the e-fuse value will be used */\r
-    ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
-\r
-\r
-    ibl.ethConfig[0].ethInfo.fileName[0]  = 't';\r
-    ibl.ethConfig[0].ethInfo.fileName[1]  = 'e';\r
-    ibl.ethConfig[0].ethInfo.fileName[2]  = 's';\r
-    ibl.ethConfig[0].ethInfo.fileName[3]  = 't';\r
-    ibl.ethConfig[0].ethInfo.fileName[4]  = '.';\r
-    ibl.ethConfig[0].ethInfo.fileName[5]  = 'b';\r
-    ibl.ethConfig[0].ethInfo.fileName[6]  = 'l';\r
-    ibl.ethConfig[0].ethInfo.fileName[7]  = 'o';\r
-    ibl.ethConfig[0].ethInfo.fileName[8]  = 'b';\r
-    ibl.ethConfig[0].ethInfo.fileName[9]  = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[10] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[11] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
-\r
-\r
-    /* Even though the entire range of DDR2 is chosen, the load will\r
-     * stop when the ftp reaches the end of the file */\r
-    ibl.ethConfig[0].blob.startAddress  = 0x80000000;       /* Base address of DDR2 */\r
-    ibl.ethConfig[0].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */\r
-    ibl.ethConfig[0].blob.branchAddress = 0x80000000;       /* Base of DDR2 */\r
-\r
-    /* There is no port 1 on the 6474 */\r
-    ibl.ethConfig[1].ethPriority      = ibl_DEVICE_NOBOOT;\r
-\r
-    /* SGMII is present */\r
-    ibl.sgmiiConfig[0].adviseAbility = 0x9801;\r
-    ibl.sgmiiConfig[0].control       = 0x20;\r
-    ibl.sgmiiConfig[0].txConfig      = 0x00000ea3;\r
-    ibl.sgmiiConfig[0].rxConfig      = 0x00081023;\r
-    ibl.sgmiiConfig[0].auxConfig     = 0x0000000b;\r
-\r
-    /* MDIO configuration */\r
-    ibl.mdioConfig.nMdioOps = 8;\r
-    ibl.mdioConfig.mdioClkDiv = 0x26;\r
-    ibl.mdioConfig.interDelay = 2000;   /* ~2ms at 1000 MHz */\r
-\r
-    ibl.mdioConfig.mdio[0] =  (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;\r
-    ibl.mdioConfig.mdio[1] =  (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;\r
-    ibl.mdioConfig.mdio[2] =  (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;\r
-    ibl.mdioConfig.mdio[3] =  (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;\r
-\r
-    ibl.mdioConfig.mdio[4] =  (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;\r
-    ibl.mdioConfig.mdio[5] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
-    ibl.mdioConfig.mdio[6] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
-    ibl.mdioConfig.mdio[7] =  (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;\r
-\r
-\r
-    /* Nand boot is disabled */\r
-    ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
-\r
-}\r
-\r
-menuitem "EVM c6474 Lite EVM IBL";\r
-\r
-hotmenu setConfig_c6474lite()\r
-{\r
-    ibl.iblMagic = ibl_MAGIC_VALUE;\r
-\r
-    ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;\r
-    ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;\r
-    ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;\r
-    ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 1;\r
-    ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
-\r
-    /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
-    ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
-\r
-    /* The network PLL. The multipliers/dividers are fixed */\r
-    ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
-\r
-    /* EMIF configuration. The values are for DDR at 533 MHz  */\r
-    ibl.ddrConfig.configDdr = TRUE;\r
-\r
-    ibl.ddrConfig.uEmif.emif3p1.sdcfg  = 0x00d38a32; /* cas5, 8 banks, 10 bit column */\r
-    ibl.ddrConfig.uEmif.emif3p1.sdrfc  = 0x00000a29; /* Refresh 333Mhz */ \r
-    ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */\r
-    ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */\r
-    ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
-\r
-\r
-    /* Ethernet configuration for port 0 */\r
-    ibl.ethConfig[0].ethPriority      = ibl_HIGHEST_PRIORITY;\r
-    ibl.ethConfig[0].port             = 0;\r
-\r
-    /* Bootp is disabled. The server and file name are provided here */\r
-    ibl.ethConfig[0].doBootp          = FALSE;\r
-    ibl.ethConfig[0].useBootpServerIp = FALSE;\r
-    ibl.ethConfig[0].useBootpFileName = FALSE;\r
-    ibl.ethConfig[0].bootFormat       = ibl_BOOT_FORMAT_BBLOB;\r
-\r
-    SETIP(ibl.ethConfig[0].ethInfo.ipAddr,    158,218,100,114);\r
-    SETIP(ibl.ethConfig[0].ethInfo.serverIp,  158,218,100,25);\r
-    SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
-    SETIP(ibl.ethConfig[0].ethInfo.netmask,   255,255,255,0);\r
-\r
-    /* Set the hardware address as 0 so the e-fuse value will be used */\r
-    ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
-\r
-\r
-    ibl.ethConfig[0].ethInfo.fileName[0]  = 'c';\r
-    ibl.ethConfig[0].ethInfo.fileName[1]  = '6';\r
-    ibl.ethConfig[0].ethInfo.fileName[2]  = '4';\r
-    ibl.ethConfig[0].ethInfo.fileName[3]  = '7';\r
-    ibl.ethConfig[0].ethInfo.fileName[4]  = '4';\r
-    ibl.ethConfig[0].ethInfo.fileName[5]  = 'l';\r
-    ibl.ethConfig[0].ethInfo.fileName[6]  = '-';\r
-    ibl.ethConfig[0].ethInfo.fileName[7]  = 'l';\r
-    ibl.ethConfig[0].ethInfo.fileName[8]  = 'e';\r
-    ibl.ethConfig[0].ethInfo.fileName[9]  = '.';\r
-    ibl.ethConfig[0].ethInfo.fileName[10] = 'b';\r
-    ibl.ethConfig[0].ethInfo.fileName[11] = 'i';\r
-    ibl.ethConfig[0].ethInfo.fileName[12] = 'n';\r
-    ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
-\r
-\r
-    /* Even though the entire range of DDR2 is chosen, the load will\r
-     * stop when the ftp reaches the end of the file */\r
-    ibl.ethConfig[0].blob.startAddress  = 0x80000000;       /* Base address of DDR2 */\r
-    ibl.ethConfig[0].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */\r
-    ibl.ethConfig[0].blob.branchAddress = 0x80000000;       /* Base of DDR2 */\r
-\r
-    /* There is no port 1 on the 6474 Lite EVM */\r
-    ibl.ethConfig[1].ethPriority      = ibl_DEVICE_NOBOOT;\r
-\r
-    /* SGMII is present */\r
-    ibl.sgmiiConfig[0].adviseAbility = 0x9801;\r
-    ibl.sgmiiConfig[0].control       = 0x20;\r
-    ibl.sgmiiConfig[0].txConfig      = 0x00000e23;\r
-    ibl.sgmiiConfig[0].rxConfig      = 0x00081023;\r
-    ibl.sgmiiConfig[0].auxConfig     = 0x0000000b;\r
-\r
-    /* MDIO configuration */\r
-    ibl.mdioConfig.nMdioOps = 8;\r
-    ibl.mdioConfig.mdioClkDiv = 0x26;\r
-    ibl.mdioConfig.interDelay = 2000;   /* ~2ms at 1000 MHz */\r
-\r
-    ibl.mdioConfig.mdio[0] =  (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;\r
-    ibl.mdioConfig.mdio[1] =  (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;\r
-    ibl.mdioConfig.mdio[2] =  (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;\r
-    ibl.mdioConfig.mdio[3] =  (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;\r
-\r
-    ibl.mdioConfig.mdio[4] =  (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;\r
-    ibl.mdioConfig.mdio[5] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
-    ibl.mdioConfig.mdio[6] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
-    ibl.mdioConfig.mdio[7] =  (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;\r
-\r
-\r
-    /* This board has NAND. We will enable later */\r
-    ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
-\r
-}\r
-\r
-menuitem "EVM c6457 EVM IBL";\r
-\r
-hotmenu setConfig_c6457()\r
-{\r
-    ibl.iblMagic = ibl_MAGIC_VALUE;\r
-\r
-    ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;\r
-    ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;\r
-    ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;\r
-    ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 1;\r
-    ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
-\r
-    /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
-    ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
-\r
-    /* The network PLL. The multipliers/dividers are fixed */\r
-    ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
-\r
-    /* EMIF configuration */\r
-    ibl.ddrConfig.configDdr = TRUE;\r
-\r
-    ibl.ddrConfig.uEmif.emif3p1.sdcfg  = 0x00d38a32; /* cas5, 8 banks, 10 bit column */\r
-    ibl.ddrConfig.uEmif.emif3p1.sdrfc  = 0x00000a0e; /* Refresh 333Mhz */ \r
-    ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x832474da; /* Timing 1 */\r
-    ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x3d44c742; /* Timing 2 */\r
-    ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
-\r
-\r
-    /* Ethernet configuration for port 0 */\r
-    ibl.ethConfig[0].ethPriority      = ibl_HIGHEST_PRIORITY;\r
-    ibl.ethConfig[0].port             = 0;\r
-\r
-    /* Bootp is disabled. The server and file name are provided here */\r
-    ibl.ethConfig[0].doBootp          = FALSE;\r
-    ibl.ethConfig[0].useBootpServerIp = FALSE;\r
-    ibl.ethConfig[0].useBootpFileName = FALSE;\r
-    ibl.ethConfig[0].bootFormat       = ibl_BOOT_FORMAT_BBLOB;\r
-\r
-    SETIP(ibl.ethConfig[0].ethInfo.ipAddr,    158,218,100,115);\r
-    SETIP(ibl.ethConfig[0].ethInfo.serverIp,  158,218,100,25);\r
-    SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
-    SETIP(ibl.ethConfig[0].ethInfo.netmask,   255,255,255,0);\r
-\r
-    /* Set the hardware address as 0 so the e-fuse value will be used */\r
-    ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
-\r
-\r
-    ibl.ethConfig[0].ethInfo.fileName[0]  = 'c';\r
-    ibl.ethConfig[0].ethInfo.fileName[1]  = '6';\r
-    ibl.ethConfig[0].ethInfo.fileName[2]  = '4';\r
-    ibl.ethConfig[0].ethInfo.fileName[3]  = '5';\r
-    ibl.ethConfig[0].ethInfo.fileName[4]  = '7';\r
-    ibl.ethConfig[0].ethInfo.fileName[5]  = '-';\r
-    ibl.ethConfig[0].ethInfo.fileName[6]  = 'l';\r
-    ibl.ethConfig[0].ethInfo.fileName[7]  = 'e';\r
-    ibl.ethConfig[0].ethInfo.fileName[8]  = '.';\r
-    ibl.ethConfig[0].ethInfo.fileName[9]  = 'b';\r
-    ibl.ethConfig[0].ethInfo.fileName[10] = 'i';\r
-    ibl.ethConfig[0].ethInfo.fileName[11] = 'n';\r
-    ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
-\r
-\r
-    /* Even though the entire range of DDR2 is chosen, the load will\r
-     * stop when the ftp reaches the end of the file */\r
-    ibl.ethConfig[0].blob.startAddress  = 0xe0000000;       /* Base address of DDR2 */\r
-    ibl.ethConfig[0].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */\r
-    ibl.ethConfig[0].blob.branchAddress = 0xe0000000;       /* Base of DDR2 */\r
-\r
-    /* There is no port 1 on the 6457 Lite EVM */\r
-    ibl.ethConfig[1].ethPriority      = ibl_DEVICE_NOBOOT;\r
-\r
-    /* SGMII is present */\r
-    ibl.sgmiiConfig[0].adviseAbility = 0x9801;\r
-    ibl.sgmiiConfig[0].control       = 0x20;\r
-    ibl.sgmiiConfig[0].txConfig      = 0x00000e23;\r
-    ibl.sgmiiConfig[0].rxConfig      = 0x00081023;\r
-    ibl.sgmiiConfig[0].auxConfig     = 0x0000000b;\r
-\r
-    /* MDIO configuration */\r
-    ibl.mdioConfig.nMdioOps = 8;\r
-    ibl.mdioConfig.mdioClkDiv = 0x26;\r
-    ibl.mdioConfig.interDelay = 2000;   /* ~2ms at 1000 MHz */\r
-\r
-    ibl.mdioConfig.mdio[0] =  (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;\r
-    ibl.mdioConfig.mdio[1] =  (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;\r
-    ibl.mdioConfig.mdio[2] =  (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;\r
-    ibl.mdioConfig.mdio[3] =  (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;\r
-\r
-    ibl.mdioConfig.mdio[4] =  (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;\r
-    ibl.mdioConfig.mdio[5] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
-    ibl.mdioConfig.mdio[6] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
-    ibl.mdioConfig.mdio[7] =  (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;\r
-\r
-\r
-    /* This board has NAND. We will enable later */\r
-    ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
-\r
-}\r
-\r
-menuitem "EVM c6455 IBL";\r
-\r
-hotmenu setConfig_c6455()\r
-{\r
-    ibl.iblMagic = ibl_MAGIC_VALUE;\r
-\r
-    ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;\r
-    ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;\r
-    ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;\r
-    ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 1;\r
-    ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
-\r
-    /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
-    ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
-\r
-    /* The network PLL. The multipliers/dividers are fixed */\r
-    ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
-\r
-    /* EMIF configuration. The values are for DDR at 500 MHz  */\r
-    ibl.ddrConfig.configDdr = TRUE;\r
-\r
-    ibl.ddrConfig.uEmif.emif3p1.sdcfg  = 0x00538822; /* timing, 32bit wide */\r
-    ibl.ddrConfig.uEmif.emif3p1.sdrfc  = 0x000007a2; /* Refresh 500Mhz */ \r
-    ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */\r
-    ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */\r
-    ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */\r
-\r
-    /* Ethernet configuration for port 0 */\r
-    ibl.ethConfig[0].ethPriority      = ibl_HIGHEST_PRIORITY;\r
-    ibl.ethConfig[0].port             = 0;\r
-\r
-    /* Bootp is disabled. The server and file name are provided here */\r
-    ibl.ethConfig[0].doBootp          = FALSE;\r
-    ibl.ethConfig[0].useBootpServerIp = FALSE;\r
-    ibl.ethConfig[0].useBootpFileName = FALSE;\r
-    ibl.ethConfig[0].bootFormat       = ibl_BOOT_FORMAT_BBLOB;\r
-\r
-\r
-    SETIP(ibl.ethConfig[0].ethInfo.ipAddr,    158,218,100,118);\r
-    SETIP(ibl.ethConfig[0].ethInfo.serverIp,  158,218,100,25);\r
-    SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
-    SETIP(ibl.ethConfig[0].ethInfo.netmask,   255,255,255,0);\r
-\r
-    /* There is no e-fuse mac address. A value must be assigned */\r
-    ibl.ethConfig[0].ethInfo.hwAddress[0] = 10;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[1] = 224;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[2] = 166;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[3] = 102;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[4] = 87;\r
-    ibl.ethConfig[0].ethInfo.hwAddress[5] = 25;\r
-\r
-\r
-    ibl.ethConfig[0].ethInfo.fileName[0]  = 't';\r
-    ibl.ethConfig[0].ethInfo.fileName[1]  = 'e';\r
-    ibl.ethConfig[0].ethInfo.fileName[2]  = 's';\r
-    ibl.ethConfig[0].ethInfo.fileName[3]  = 't';\r
-    ibl.ethConfig[0].ethInfo.fileName[4]  = '.';\r
-    ibl.ethConfig[0].ethInfo.fileName[5]  = 'b';\r
-    ibl.ethConfig[0].ethInfo.fileName[6]  = 'l';\r
-    ibl.ethConfig[0].ethInfo.fileName[7]  = 'o';\r
-    ibl.ethConfig[0].ethInfo.fileName[8]  = 'b';\r
-    ibl.ethConfig[0].ethInfo.fileName[9]  = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[10] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[11] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
-    ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
-\r
-\r
-    /* Even though the entire range of DDR2 is chosen, the load will\r
-     * stop when the ftp reaches the end of the file */\r
-    ibl.ethConfig[0].blob.startAddress  = 0xe0000000;       /* Base address of DDR2 */\r
-    ibl.ethConfig[0].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */\r
-    ibl.ethConfig[0].blob.branchAddress = 0xe0000000;       /* Base of DDR2 */\r
-\r
-    /* There is no ethernet port 1 */\r
-    ibl.ethConfig[1].ethPriority      = ibl_DEVICE_NOBOOT;\r
-\r
-\r
-    /* SGMII not present */\r
-       ibl.sgmiiConfig[0].adviseAbility = 0;\r
-       ibl.sgmiiConfig[0].control       = 0;\r
-       ibl.sgmiiConfig[0].txConfig      = 0;\r
-       ibl.sgmiiConfig[0].rxConfig      = 0;\r
-       ibl.sgmiiConfig[0].auxConfig     = 0;\r
-\r
-       ibl.sgmiiConfig[1].adviseAbility = 0;\r
-       ibl.sgmiiConfig[1].control       = 0;\r
-       ibl.sgmiiConfig[1].txConfig      = 0;\r
-       ibl.sgmiiConfig[1].rxConfig      = 0;\r
-       ibl.sgmiiConfig[1].auxConfig     = 0;\r
-\r
-\r
-\r
-    /* MDIO configuration */\r
-    ibl.mdioConfig.nMdioOps = 0;\r
-    ibl.mdioConfig.mdioClkDiv = 0x20;\r
-    ibl.mdioConfig.interDelay = 2000;   /* ~2ms at 1000 MHz */\r
-\r
-    ibl.mdioConfig.mdio[0] =  (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;\r
-\r
-\r
-    /* Nand boot is disabled */\r
-    ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
-\r
-}\r
-\r
-\r
-menuitem "EVM c6608 IBL";\r
-\r
-hotmenu setConfig_c6608()\r
-{\r
-       ibl.iblMagic = ibl_MAGIC_VALUE;\r
-\r
-       /* Main PLL: 100 MHz reference, 1GHz output */\r
-       ibl.pllConfig[ibl_MAIN_PLL].doEnable      = 1;\r
-       ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;\r
-       ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;\r
-       ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 2;\r
-       ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
-\r
-       /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */\r
-       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1; \r
-       ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;\r
-       ibl.pllConfig[ibl_DDR_PLL].mult           = 12;\r
-       ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;\r
-       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 400;\r
-\r
-    /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */\r
-       ibl.pllConfig[ibl_NET_PLL].doEnable       = 1;\r
-       ibl.pllConfig[ibl_NET_PLL].prediv         = 1;\r
-       ibl.pllConfig[ibl_NET_PLL].mult                   = 21;\r
-       ibl.pllConfig[ibl_NET_PLL].postdiv        = 2;\r
-       ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz  = 1050;\r
-\r
-\r
-       ibl.ddrConfig.configDdr = 1;\r
-       ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;\r
-\r
-       ibl.ddrConfig.uEmif.emif4p0.sdRamConfig                         = 0x63C452B2;\r
-       ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2                        = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl                     = 0x000030D4;\r
-       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1                        = 0x0AAAE51B;\r
-       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2                        = 0x2A2F7FDA;\r
-       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3                        = 0x057F82B8;\r
-       ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming                      = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.powerManageCtl                      = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic                      = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.performCountCfg                     = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel       = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.readIdleCtl                         = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet            = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg        = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg                        = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1                          = 0x0010010d;\r
-       ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2                          = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap                     = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map           = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map           = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.eccCtl                                      = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.eccRange1                           = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.eccRange2                           = 0;\r
-       ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh                      = 0;\r
-\r
-\r
-       ibl.sgmiiConfig[0].configure     = 1;\r
-       ibl.sgmiiConfig[0].adviseAbility = 1;\r
-       ibl.sgmiiConfig[0].control               = 1;\r
-       ibl.sgmiiConfig[0].txConfig      = 0x108a1;\r
-       ibl.sgmiiConfig[0].rxConfig      = 0x700621;\r
-       ibl.sgmiiConfig[0].auxConfig     = 0x41;\r
-\r
-       ibl.sgmiiConfig[1].configure     = 1;\r
-       ibl.sgmiiConfig[1].adviseAbility = 1;\r
-       ibl.sgmiiConfig[1].control               = 1;\r
-       ibl.sgmiiConfig[1].txConfig      = 0x108a1;\r
-       ibl.sgmiiConfig[1].rxConfig      = 0x700621;\r
-       ibl.sgmiiConfig[1].auxConfig     = 0x41;\r
-\r
-       ibl.mdioConfig.nMdioOps = 0;\r
-\r
-       ibl.spiConfig.addrWidth  = 0;\r
-       ibl.spiConfig.nPins      = 0;\r
-       ibl.spiConfig.mode       = 0;\r
-       ibl.spiConfig.csel       = 0;\r
-       ibl.spiConfig.c2tdelay   = 0;\r
-       ibl.spiConfig.busFreqMHz = 0;\r
-\r
-       ibl.emifConfig[0].csSpace    = 0;\r
-       ibl.emifConfig[0].busWidth   = 0;\r
-       ibl.emifConfig[0].waitEnable = 0;\r
-\r
-       ibl.emifConfig[1].csSpace    = 0;\r
-       ibl.emifConfig[1].busWidth   = 0;\r
-       ibl.emifConfig[1].waitEnable = 0;\r
-\r
-       ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP;\r
-       ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;\r
-       ibl.bootModes[0].port     = ibl_PORT_SWITCH_ALL;\r
-\r
-       ibl.bootModes[0].u.ethBoot.doBootp          = FALSE;\r
-       ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE;\r
-       ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE;\r
-       ibl.bootModes[0].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_BBLOB;\r
-\r
-\r
-    SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr,    158,218,32,118);\r
-    SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp,  158,218,32,252);\r
-    SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,32,2);\r
-    SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask,   255,255,255,0);\r
-\r
-    /* Use the e-fuse value */\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0;\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0;\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0;\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0;\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0;\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0;\r
-\r
-\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0]  = 't';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1]  = 'e';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2]  = 's';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3]  = 't';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4]  = '.';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5]  = 'b';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6]  = 'l';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7]  = 'o';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8]  = 'b';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9]  = '\0';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = '\0';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = '\0';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0';\r
-    ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0';\r
-\r
-    ibl.bootModes[0].u.ethBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */\r
-    ibl.bootModes[0].u.ethBoot.blob.sizeBytes     = 0x20000000;       /* All of DDR2 */\r
-    ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */\r
-\r
-\r
-       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE;\r
-\r
-       ibl.chkSum = 0;\r
-\r
-}\r
+#define TRUE  1
+#define FALSE 0
+
+#define ibl_MAGIC_VALUE                 0xCEC11EBB
+
+#define ibl_HIGHEST_PRIORITY     1  
+#define ibl_LOWEST_PRIORITY     10
+#define ibl_DEVICE_NOBOOT       20
+
+#define ibl_PORT_SWITCH_ALL     -2
+
+#define SETIP(array,i0,i1,i2,i3)      array[0]=(i0);  \
+                                      array[1]=(i1);  \
+                                      array[2]=(i2);  \
+                                      array[3]=(i3)
+
+#define  ibl_BOOT_MODE_TFTP     10
+#define  ibl_BOOT_MODE_NAND     11
+#define  ibl_BOOT_MODE_NOR      12
+#define  ibl_BOOT_MODE_NONE     13
+
+
+#define ibl_BOOT_FORMAT_AUTO    0
+#define ibl_BOOT_FORMAT_NAME    1
+#define ibl_BOOT_FORMAT_BIS     2
+#define ibl_BOOT_FORMAT_COFF    3
+#define ibl_BOOT_FORMAT_ELF     4
+#define ibl_BOOT_FORMAT_BBLOB   5
+#define ibl_BOOT_FORMAT_BTBL    6
+
+#define  ibl_PMEM_IF_SPI        100 
+
+#define ibl_MAIN_PLL    0
+#define ibl_DDR_PLL     1
+#define ibl_NET_PLL     2
+
+#define ibl_EMIF4_ENABLE_sdRamConfig                  (1 <<  0)
+#define  ibl_EMIF4_ENABLE_sdRamConfig2                (1 <<  1)
+#define  ibl_EMIF4_ENABLE_sdRamRefreshCtl             (1 <<  2)
+#define  ibl_EMIF4_ENABLE_sdRamTiming1                (1 <<  3)
+#define  ibl_EMIF4_ENABLE_sdRamTiming2                (1 <<  4)
+#define  ibl_EMIF4_ENABLE_sdRamTiming3                (1 <<  5)
+#define  ibl_EMIF4_ENABLE_lpDdrNvmTiming              (1 <<  6)
+#define  ibl_EMIF4_ENABLE_powerManageCtl              (1 <<  7)
+#define  ibl_EMIF4_ENABLE_iODFTTestLogic              (1 <<  8)
+#define  ibl_EMIF4_ENABLE_performCountCfg             (1 <<  9)
+#define  ibl_EMIF4_ENABLE_performCountMstRegSel       (1 << 10)
+#define  ibl_EMIF4_ENABLE_readIdleCtl                 (1 << 11)
+#define  ibl_EMIF4_ENABLE_sysVbusmIntEnSet            (1 << 12)
+#define  ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg        (1 << 13)
+#define  ibl_EMIF4_ENABLE_tempAlterCfg                (1 << 14)
+#define  ibl_EMIF4_ENABLE_ddrPhyCtl1                  (1 << 15)
+#define  ibl_EMIF4_ENABLE_ddrPhyCtl2                  (1 << 16)
+#define  ibl_EMIF4_ENABLE_priClassSvceMap             (1 << 17)
+#define  ibl_EMIF4_ENABLE_mstId2ClsSvce1Map           (1 << 18)
+#define  ibl_EMIF4_ENABLE_mstId2ClsSvce2Map           (1 << 11)
+#define  ibl_EMIF4_ENABLE_eccCtl                      (1 << 19)
+#define  ibl_EMIF4_ENABLE_eccRange1                   (1 << 20)
+#define  ibl_EMIF4_ENABLE_eccRange2                   (1 << 21)
+#define  ibl_EMIF4_ENABLE_rdWrtExcThresh              (1 << 22)
+#define  ibl_BOOT_EMIF4_ENABLE_ALL                    0x007fffff
+    
+/* @} */  
+
+menuitem "EVM c6472 IBL";
+
+hotmenu setConfig_c6472()
+{
+    ibl.iblMagic = ibl_MAGIC_VALUE;
+
+    ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;
+    ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
+    ibl.pllConfig[ibl_MAIN_PLL].mult          = 28;
+    ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 1;
+    ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;
+
+    /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+    ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+    /* The network PLL. The multipliers/dividers are fixed */
+    ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+    /* EMIF configuration. The values are for DDR at 533 MHz  */
+    ibl.ddrConfig.configDdr = TRUE;
+
+    ibl.ddrConfig.uEmif.emif3p1.sdcfg  = 0x00538832; /* timing, 32bit wide */
+    ibl.ddrConfig.uEmif.emif3p1.sdrfc  = 0x0000073B; /* Refresh 533Mhz */ 
+    ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */
+    ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */
+    ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+    /* Ethernet configuration for port 0 */
+    ibl.ethConfig[0].ethPriority      = ibl_HIGHEST_PRIORITY;
+    ibl.ethConfig[0].port             = 0;
+
+    /* Bootp is disabled. The server and file name are provided here */
+    ibl.ethConfig[0].doBootp          = FALSE;
+    ibl.ethConfig[0].useBootpServerIp = FALSE;
+    ibl.ethConfig[0].useBootpFileName = FALSE;
+    ibl.ethConfig[0].bootFormat       = ibl_BOOT_FORMAT_AUTO;
+
+
+    SETIP(ibl.ethConfig[0].ethInfo.ipAddr,    10,218,109,21);
+    SETIP(ibl.ethConfig[0].ethInfo.serverIp,  10,218,109,196);
+    SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,2);
+    SETIP(ibl.ethConfig[0].ethInfo.netmask,   255,255,255,0);
+
+    /* Leave the hardware address as 0 so the e-fuse value will be used */
+
+
+
+
+    ibl.ethConfig[0].ethInfo.fileName[0]  = 't';
+    ibl.ethConfig[0].ethInfo.fileName[1]  = 'e';
+    ibl.ethConfig[0].ethInfo.fileName[2]  = 's';
+    ibl.ethConfig[0].ethInfo.fileName[3]  = 't';
+    ibl.ethConfig[0].ethInfo.fileName[4]  = '.';
+    ibl.ethConfig[0].ethInfo.fileName[5]  = 'o';
+    ibl.ethConfig[0].ethInfo.fileName[6]  = 'u';
+    ibl.ethConfig[0].ethInfo.fileName[7]  = 't';
+    ibl.ethConfig[0].ethInfo.fileName[8]  = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[9]  = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[10] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[11] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
+
+    /* Even though the entire range of DDR2 is chosen, the load will
+     * stop when the ftp reaches the end of the file */
+    ibl.ethConfig[0].blob.startAddress  = 0xe0000000;       /* Base address of DDR2 */
+    ibl.ethConfig[0].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
+    ibl.ethConfig[0].blob.branchAddress = 0xe0000000;       /* Base of DDR2 */
+
+    /* For port 1 use bootp */
+    /* Ethernet configuration for port 0 */
+    ibl.ethConfig[1].ethPriority      = ibl_HIGHEST_PRIORITY + 1;
+    ibl.ethConfig[1].port             = 1;
+
+    /* Bootp is disabled. The server and file name are provided here */
+    ibl.ethConfig[1].doBootp          = TRUE;
+    ibl.ethConfig[1].useBootpServerIp = TRUE;
+    ibl.ethConfig[1].useBootpFileName = TRUE;
+    ibl.ethConfig[1].bootFormat       = ibl_BOOT_FORMAT_AUTO;
+
+
+    /* SGMII not present */
+       ibl.sgmiiConfig[0].adviseAbility = 0;
+       ibl.sgmiiConfig[0].control       = 0;
+       ibl.sgmiiConfig[0].txConfig      = 0;
+       ibl.sgmiiConfig[0].rxConfig      = 0;
+       ibl.sgmiiConfig[0].auxConfig     = 0;
+
+       ibl.sgmiiConfig[1].adviseAbility = 0;
+       ibl.sgmiiConfig[1].control       = 0;
+       ibl.sgmiiConfig[1].txConfig      = 0;
+       ibl.sgmiiConfig[1].rxConfig      = 0;
+       ibl.sgmiiConfig[1].auxConfig     = 0;
+
+
+    /* Leave the hardware address as 0 so the e-fuse value will be used */
+    ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
+
+
+    /* Leave all remaining fields as 0 since bootp will fill them in */
+
+
+    /* Even though the entire range of DDR2 is chosen, the load will */
+    /* stop when the ftp reaches the end of the file */
+    ibl.ethConfig[1].blob.startAddress  = 0xe0000000;       /* Base address of DDR2 */
+    ibl.ethConfig[1].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
+    ibl.ethConfig[1].blob.branchAddress = 0xe0000000;       /* Base of DDR2 */
+    
+
+
+    /* MDIO configuration */
+    ibl.mdioConfig.nMdioOps = 8;
+    ibl.mdioConfig.mdioClkDiv = 0x20;
+    ibl.mdioConfig.interDelay = 1400;   /* ~2ms at 700 MHz */
+
+    ibl.mdioConfig.mdio[0] =  (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;
+    ibl.mdioConfig.mdio[1] =  (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;
+    ibl.mdioConfig.mdio[2] =  (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;
+    ibl.mdioConfig.mdio[3] =  (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;
+
+    ibl.mdioConfig.mdio[4] =  (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;
+    ibl.mdioConfig.mdio[5] =  (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;
+    ibl.mdioConfig.mdio[6] =  (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;
+    ibl.mdioConfig.mdio[7] =  (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;
+
+
+    /* Nand boot is disabled */
+    ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+
+    ibl.nandConfig.bootFormat   = ibl_BOOT_FORMAT_AUTO;
+
+    ibl.nandConfig.nandInfo.busWidthBits  = 8;
+    ibl.nandConfig.nandInfo.pageSizeBytes = 2048;
+    ibl.nandConfig.nandInfo.pageEccBytes  = 64;
+    ibl.nandConfig.nandInfo.pagesPerBlock = 64;
+    ibl.nandConfig.nandInfo.totalBlocks   = 1024;
+
+    ibl.nandConfig.nandInfo.addressBytes  = 4;
+    ibl.nandConfig.nandInfo.lsbFirst      = TRUE;
+    ibl.nandConfig.nandInfo.blockOffset   = 22;
+    ibl.nandConfig.nandInfo.pageOffset    = 16;
+    ibl.nandConfig.nandInfo.columnOffset  = 0;
+
+    ibl.nandConfig.nandInfo.resetCommand    = 0xff;
+    ibl.nandConfig.nandInfo.readCommandPre  = 0;
+    ibl.nandConfig.nandInfo.readCommandPost = 0x30;
+    ibl.nandConfig.nandInfo.postCommand     = TRUE;
+
+}
+
+
+menuitem "EVM c6474 Mez IBL";
+
+hotmenu setConfig_c6474()
+{
+    ibl.iblMagic = ibl_MAGIC_VALUE;
+
+    ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;
+    ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
+    ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;
+    ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 1;
+    ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+    /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+    ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+    /* The network PLL. The multipliers/dividers are fixed */
+    ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+    /* EMIF configuration. The values are for DDR at 533 MHz  */
+    ibl.ddrConfig.configDdr = TRUE;
+
+    ibl.ddrConfig.uEmif.emif3p1.sdcfg  = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
+    ibl.ddrConfig.uEmif.emif3p1.sdrfc  = 0x00000a29; /* Refresh 333Mhz */ 
+    ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
+    ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
+    ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+
+    /* Ethernet configuration for port 0 */
+    ibl.ethConfig[0].ethPriority      = ibl_HIGHEST_PRIORITY;
+    ibl.ethConfig[0].port             = 0;
+
+    /* Bootp is disabled. The server and file name are provided here */
+    ibl.ethConfig[0].doBootp          = FALSE;
+    ibl.ethConfig[0].useBootpServerIp = FALSE;
+    ibl.ethConfig[0].useBootpFileName = FALSE;
+    ibl.ethConfig[0].bootFormat       = ibl_BOOT_FORMAT_BBLOB;
+
+    SETIP(ibl.ethConfig[0].ethInfo.ipAddr,    10,218,109,35);
+    SETIP(ibl.ethConfig[0].ethInfo.serverIp,  10,218,109,196);
+    SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,1);
+    SETIP(ibl.ethConfig[0].ethInfo.netmask,   255,255,255,0);
+
+    /* Set the hardware address as 0 so the e-fuse value will be used */
+    ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
+
+
+    ibl.ethConfig[0].ethInfo.fileName[0]  = 't';
+    ibl.ethConfig[0].ethInfo.fileName[1]  = 'e';
+    ibl.ethConfig[0].ethInfo.fileName[2]  = 's';
+    ibl.ethConfig[0].ethInfo.fileName[3]  = 't';
+    ibl.ethConfig[0].ethInfo.fileName[4]  = '.';
+    ibl.ethConfig[0].ethInfo.fileName[5]  = 'b';
+    ibl.ethConfig[0].ethInfo.fileName[6]  = 'l';
+    ibl.ethConfig[0].ethInfo.fileName[7]  = 'o';
+    ibl.ethConfig[0].ethInfo.fileName[8]  = 'b';
+    ibl.ethConfig[0].ethInfo.fileName[9]  = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[10] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[11] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
+
+
+    /* Even though the entire range of DDR2 is chosen, the load will
+     * stop when the ftp reaches the end of the file */
+    ibl.ethConfig[0].blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.ethConfig[0].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
+    ibl.ethConfig[0].blob.branchAddress = 0x80000000;       /* Base of DDR2 */
+
+    /* There is no port 1 on the 6474 */
+    ibl.ethConfig[1].ethPriority      = ibl_DEVICE_NOBOOT;
+
+    /* SGMII is present */
+    ibl.sgmiiConfig[0].adviseAbility = 0x9801;
+    ibl.sgmiiConfig[0].control       = 0x20;
+    ibl.sgmiiConfig[0].txConfig      = 0x00000ea3;
+    ibl.sgmiiConfig[0].rxConfig      = 0x00081023;
+    ibl.sgmiiConfig[0].auxConfig     = 0x0000000b;
+
+    /* MDIO configuration */
+    ibl.mdioConfig.nMdioOps = 8;
+    ibl.mdioConfig.mdioClkDiv = 0x26;
+    ibl.mdioConfig.interDelay = 2000;   /* ~2ms at 1000 MHz */
+
+    ibl.mdioConfig.mdio[0] =  (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
+    ibl.mdioConfig.mdio[1] =  (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;
+    ibl.mdioConfig.mdio[2] =  (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
+    ibl.mdioConfig.mdio[3] =  (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;
+
+    ibl.mdioConfig.mdio[4] =  (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
+    ibl.mdioConfig.mdio[5] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+    ibl.mdioConfig.mdio[6] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+    ibl.mdioConfig.mdio[7] =  (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;
+
+
+    /* Nand boot is disabled */
+    ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+
+}
+
+menuitem "EVM c6474 Lite EVM IBL";
+
+hotmenu setConfig_c6474lite()
+{
+    ibl.iblMagic = ibl_MAGIC_VALUE;
+
+    ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;
+    ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
+    ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;
+    ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 1;
+    ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+    /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+    ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+    /* The network PLL. The multipliers/dividers are fixed */
+    ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+    /* EMIF configuration. The values are for DDR at 533 MHz  */
+    ibl.ddrConfig.configDdr = TRUE;
+
+    ibl.ddrConfig.uEmif.emif3p1.sdcfg  = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
+    ibl.ddrConfig.uEmif.emif3p1.sdrfc  = 0x00000a29; /* Refresh 333Mhz */ 
+    ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
+    ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
+    ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+
+    /* Ethernet configuration for port 0 */
+    ibl.ethConfig[0].ethPriority      = ibl_HIGHEST_PRIORITY;
+    ibl.ethConfig[0].port             = 0;
+
+    /* Bootp is disabled. The server and file name are provided here */
+    ibl.ethConfig[0].doBootp          = FALSE;
+    ibl.ethConfig[0].useBootpServerIp = FALSE;
+    ibl.ethConfig[0].useBootpFileName = FALSE;
+    ibl.ethConfig[0].bootFormat       = ibl_BOOT_FORMAT_BBLOB;
+
+    SETIP(ibl.ethConfig[0].ethInfo.ipAddr,    158,218,100,114);
+    SETIP(ibl.ethConfig[0].ethInfo.serverIp,  158,218,100,25);
+    SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
+    SETIP(ibl.ethConfig[0].ethInfo.netmask,   255,255,255,0);
+
+    /* Set the hardware address as 0 so the e-fuse value will be used */
+    ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
+
+
+    ibl.ethConfig[0].ethInfo.fileName[0]  = 'c';
+    ibl.ethConfig[0].ethInfo.fileName[1]  = '6';
+    ibl.ethConfig[0].ethInfo.fileName[2]  = '4';
+    ibl.ethConfig[0].ethInfo.fileName[3]  = '7';
+    ibl.ethConfig[0].ethInfo.fileName[4]  = '4';
+    ibl.ethConfig[0].ethInfo.fileName[5]  = 'l';
+    ibl.ethConfig[0].ethInfo.fileName[6]  = '-';
+    ibl.ethConfig[0].ethInfo.fileName[7]  = 'l';
+    ibl.ethConfig[0].ethInfo.fileName[8]  = 'e';
+    ibl.ethConfig[0].ethInfo.fileName[9]  = '.';
+    ibl.ethConfig[0].ethInfo.fileName[10] = 'b';
+    ibl.ethConfig[0].ethInfo.fileName[11] = 'i';
+    ibl.ethConfig[0].ethInfo.fileName[12] = 'n';
+    ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
+
+
+    /* Even though the entire range of DDR2 is chosen, the load will
+     * stop when the ftp reaches the end of the file */
+    ibl.ethConfig[0].blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.ethConfig[0].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
+    ibl.ethConfig[0].blob.branchAddress = 0x80000000;       /* Base of DDR2 */
+
+    /* There is no port 1 on the 6474 Lite EVM */
+    ibl.ethConfig[1].ethPriority      = ibl_DEVICE_NOBOOT;
+
+    /* SGMII is present */
+    ibl.sgmiiConfig[0].adviseAbility = 0x9801;
+    ibl.sgmiiConfig[0].control       = 0x20;
+    ibl.sgmiiConfig[0].txConfig      = 0x00000e23;
+    ibl.sgmiiConfig[0].rxConfig      = 0x00081023;
+    ibl.sgmiiConfig[0].auxConfig     = 0x0000000b;
+
+    /* MDIO configuration */
+    ibl.mdioConfig.nMdioOps = 8;
+    ibl.mdioConfig.mdioClkDiv = 0x26;
+    ibl.mdioConfig.interDelay = 2000;   /* ~2ms at 1000 MHz */
+
+    ibl.mdioConfig.mdio[0] =  (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
+    ibl.mdioConfig.mdio[1] =  (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;
+    ibl.mdioConfig.mdio[2] =  (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
+    ibl.mdioConfig.mdio[3] =  (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;
+
+    ibl.mdioConfig.mdio[4] =  (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
+    ibl.mdioConfig.mdio[5] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+    ibl.mdioConfig.mdio[6] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+    ibl.mdioConfig.mdio[7] =  (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;
+
+
+    /* This board has NAND. We will enable later */
+    ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+
+}
+
+menuitem "EVM c6457 EVM IBL";
+
+hotmenu setConfig_c6457()
+{
+    ibl.iblMagic = ibl_MAGIC_VALUE;
+
+    ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;
+    ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
+    ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;
+    ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 1;
+    ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+    /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+    ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+    /* The network PLL. The multipliers/dividers are fixed */
+    ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+    /* EMIF configuration */
+    ibl.ddrConfig.configDdr = TRUE;
+
+    ibl.ddrConfig.uEmif.emif3p1.sdcfg  = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
+    ibl.ddrConfig.uEmif.emif3p1.sdrfc  = 0x00000a0e; /* Refresh 333Mhz */ 
+    ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x832474da; /* Timing 1 */
+    ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x3d44c742; /* Timing 2 */
+    ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+
+    /* Ethernet configuration for port 0 */
+    ibl.ethConfig[0].ethPriority      = ibl_HIGHEST_PRIORITY;
+    ibl.ethConfig[0].port             = 0;
+
+    /* Bootp is disabled. The server and file name are provided here */
+    ibl.ethConfig[0].doBootp          = FALSE;
+    ibl.ethConfig[0].useBootpServerIp = FALSE;
+    ibl.ethConfig[0].useBootpFileName = FALSE;
+    ibl.ethConfig[0].bootFormat       = ibl_BOOT_FORMAT_BBLOB;
+
+    SETIP(ibl.ethConfig[0].ethInfo.ipAddr,    158,218,100,115);
+    SETIP(ibl.ethConfig[0].ethInfo.serverIp,  158,218,100,25);
+    SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
+    SETIP(ibl.ethConfig[0].ethInfo.netmask,   255,255,255,0);
+
+    /* Set the hardware address as 0 so the e-fuse value will be used */
+    ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;
+    ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;
+
+
+    ibl.ethConfig[0].ethInfo.fileName[0]  = 'c';
+    ibl.ethConfig[0].ethInfo.fileName[1]  = '6';
+    ibl.ethConfig[0].ethInfo.fileName[2]  = '4';
+    ibl.ethConfig[0].ethInfo.fileName[3]  = '5';
+    ibl.ethConfig[0].ethInfo.fileName[4]  = '7';
+    ibl.ethConfig[0].ethInfo.fileName[5]  = '-';
+    ibl.ethConfig[0].ethInfo.fileName[6]  = 'l';
+    ibl.ethConfig[0].ethInfo.fileName[7]  = 'e';
+    ibl.ethConfig[0].ethInfo.fileName[8]  = '.';
+    ibl.ethConfig[0].ethInfo.fileName[9]  = 'b';
+    ibl.ethConfig[0].ethInfo.fileName[10] = 'i';
+    ibl.ethConfig[0].ethInfo.fileName[11] = 'n';
+    ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
+
+
+    /* Even though the entire range of DDR2 is chosen, the load will
+     * stop when the ftp reaches the end of the file */
+    ibl.ethConfig[0].blob.startAddress  = 0xe0000000;       /* Base address of DDR2 */
+    ibl.ethConfig[0].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
+    ibl.ethConfig[0].blob.branchAddress = 0xe0000000;       /* Base of DDR2 */
+
+    /* There is no port 1 on the 6457 Lite EVM */
+    ibl.ethConfig[1].ethPriority      = ibl_DEVICE_NOBOOT;
+
+    /* SGMII is present */
+    ibl.sgmiiConfig[0].adviseAbility = 0x9801;
+    ibl.sgmiiConfig[0].control       = 0x20;
+    ibl.sgmiiConfig[0].txConfig      = 0x00000e23;
+    ibl.sgmiiConfig[0].rxConfig      = 0x00081023;
+    ibl.sgmiiConfig[0].auxConfig     = 0x0000000b;
+
+    /* MDIO configuration */
+    ibl.mdioConfig.nMdioOps = 8;
+    ibl.mdioConfig.mdioClkDiv = 0x26;
+    ibl.mdioConfig.interDelay = 2000;   /* ~2ms at 1000 MHz */
+
+    ibl.mdioConfig.mdio[0] =  (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
+    ibl.mdioConfig.mdio[1] =  (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;
+    ibl.mdioConfig.mdio[2] =  (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
+    ibl.mdioConfig.mdio[3] =  (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;
+
+    ibl.mdioConfig.mdio[4] =  (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
+    ibl.mdioConfig.mdio[5] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+    ibl.mdioConfig.mdio[6] =  (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
+    ibl.mdioConfig.mdio[7] =  (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;
+
+
+    /* This board has NAND. We will enable later */
+    ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+
+}
+
+menuitem "EVM c6455 IBL";
+
+hotmenu setConfig_c6455()
+{
+    ibl.iblMagic = ibl_MAGIC_VALUE;
+
+    ibl.pllConfig[ibl_MAIN_PLL].doEnable      = TRUE;
+    ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
+    ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;
+    ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 1;
+    ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+    /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+    ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+    /* The network PLL. The multipliers/dividers are fixed */
+    ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+    /* EMIF configuration. The values are for DDR at 500 MHz  */
+    ibl.ddrConfig.configDdr = TRUE;
+
+    ibl.ddrConfig.uEmif.emif3p1.sdcfg  = 0x00538822; /* timing, 32bit wide */
+    ibl.ddrConfig.uEmif.emif3p1.sdrfc  = 0x000007a2; /* Refresh 500Mhz */ 
+    ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */
+    ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */
+    ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
+
+    /* Ethernet configuration for port 0 */
+    ibl.ethConfig[0].ethPriority      = ibl_HIGHEST_PRIORITY;
+    ibl.ethConfig[0].port             = 0;
+
+    /* Bootp is disabled. The server and file name are provided here */
+    ibl.ethConfig[0].doBootp          = FALSE;
+    ibl.ethConfig[0].useBootpServerIp = FALSE;
+    ibl.ethConfig[0].useBootpFileName = FALSE;
+    ibl.ethConfig[0].bootFormat       = ibl_BOOT_FORMAT_BBLOB;
+
+
+    SETIP(ibl.ethConfig[0].ethInfo.ipAddr,    158,218,100,118);
+    SETIP(ibl.ethConfig[0].ethInfo.serverIp,  158,218,100,25);
+    SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);
+    SETIP(ibl.ethConfig[0].ethInfo.netmask,   255,255,255,0);
+
+    /* There is no e-fuse mac address. A value must be assigned */
+    ibl.ethConfig[0].ethInfo.hwAddress[0] = 10;
+    ibl.ethConfig[0].ethInfo.hwAddress[1] = 224;
+    ibl.ethConfig[0].ethInfo.hwAddress[2] = 166;
+    ibl.ethConfig[0].ethInfo.hwAddress[3] = 102;
+    ibl.ethConfig[0].ethInfo.hwAddress[4] = 87;
+    ibl.ethConfig[0].ethInfo.hwAddress[5] = 25;
+
+
+    ibl.ethConfig[0].ethInfo.fileName[0]  = 't';
+    ibl.ethConfig[0].ethInfo.fileName[1]  = 'e';
+    ibl.ethConfig[0].ethInfo.fileName[2]  = 's';
+    ibl.ethConfig[0].ethInfo.fileName[3]  = 't';
+    ibl.ethConfig[0].ethInfo.fileName[4]  = '.';
+    ibl.ethConfig[0].ethInfo.fileName[5]  = 'b';
+    ibl.ethConfig[0].ethInfo.fileName[6]  = 'l';
+    ibl.ethConfig[0].ethInfo.fileName[7]  = 'o';
+    ibl.ethConfig[0].ethInfo.fileName[8]  = 'b';
+    ibl.ethConfig[0].ethInfo.fileName[9]  = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[10] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[11] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
+    ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
+
+
+    /* Even though the entire range of DDR2 is chosen, the load will
+     * stop when the ftp reaches the end of the file */
+    ibl.ethConfig[0].blob.startAddress  = 0xe0000000;       /* Base address of DDR2 */
+    ibl.ethConfig[0].blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
+    ibl.ethConfig[0].blob.branchAddress = 0xe0000000;       /* Base of DDR2 */
+
+    /* There is no ethernet port 1 */
+    ibl.ethConfig[1].ethPriority      = ibl_DEVICE_NOBOOT;
+
+
+    /* SGMII not present */
+       ibl.sgmiiConfig[0].adviseAbility = 0;
+       ibl.sgmiiConfig[0].control       = 0;
+       ibl.sgmiiConfig[0].txConfig      = 0;
+       ibl.sgmiiConfig[0].rxConfig      = 0;
+       ibl.sgmiiConfig[0].auxConfig     = 0;
+
+       ibl.sgmiiConfig[1].adviseAbility = 0;
+       ibl.sgmiiConfig[1].control       = 0;
+       ibl.sgmiiConfig[1].txConfig      = 0;
+       ibl.sgmiiConfig[1].rxConfig      = 0;
+       ibl.sgmiiConfig[1].auxConfig     = 0;
+
+
+
+    /* MDIO configuration */
+    ibl.mdioConfig.nMdioOps = 0;
+    ibl.mdioConfig.mdioClkDiv = 0x20;
+    ibl.mdioConfig.interDelay = 2000;   /* ~2ms at 1000 MHz */
+
+    ibl.mdioConfig.mdio[0] =  (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;
+
+
+    /* Nand boot is disabled */
+    ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
+
+}
+
+
+menuitem "EVM c6678 IBL";
+
+hotmenu setConfig_c6678()
+{
+       ibl.iblMagic = ibl_MAGIC_VALUE;
+
+       /* Main PLL: 100 MHz reference, 1GHz output */
+       ibl.pllConfig[ibl_MAIN_PLL].doEnable      = 1;
+       ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
+       ibl.pllConfig[ibl_MAIN_PLL].mult          = 20;
+       ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 2;
+       ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
+
+       /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 1; 
+       ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
+       ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
+       ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
+       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 400;
+
+    /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
+       ibl.pllConfig[ibl_NET_PLL].doEnable       = 1;
+       ibl.pllConfig[ibl_NET_PLL].prediv         = 1;
+       ibl.pllConfig[ibl_NET_PLL].mult                   = 21;
+       ibl.pllConfig[ibl_NET_PLL].postdiv        = 2;
+       ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz  = 1050;
+
+
+       ibl.ddrConfig.configDdr = 1;
+       ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
+
+       ibl.ddrConfig.uEmif.emif4p0.sdRamConfig                         = 0x63C452B2;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2                        = 0;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl                     = 0x000030D4;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1                        = 0x0AAAE51B;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2                        = 0x2A2F7FDA;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3                        = 0x057F82B8;
+       ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming                      = 0;
+       ibl.ddrConfig.uEmif.emif4p0.powerManageCtl                      = 0;
+       ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic                      = 0;
+       ibl.ddrConfig.uEmif.emif4p0.performCountCfg                     = 0;
+       ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel       = 0;
+       ibl.ddrConfig.uEmif.emif4p0.readIdleCtl                         = 0;
+       ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet            = 0;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg        = 0;
+       ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg                        = 0;
+       ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1                          = 0x0010010d;
+       ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2                          = 0;
+       ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap                     = 0;
+       ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map           = 0;
+       ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map           = 0;
+       ibl.ddrConfig.uEmif.emif4p0.eccCtl                                      = 0;
+       ibl.ddrConfig.uEmif.emif4p0.eccRange1                           = 0;
+       ibl.ddrConfig.uEmif.emif4p0.eccRange2                           = 0;
+       ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh                      = 0;
+
+
+       ibl.sgmiiConfig[0].configure     = 1;
+       ibl.sgmiiConfig[0].adviseAbility = 1;
+       ibl.sgmiiConfig[0].control               = 1;
+       ibl.sgmiiConfig[0].txConfig      = 0x108a1;
+       ibl.sgmiiConfig[0].rxConfig      = 0x700621;
+       ibl.sgmiiConfig[0].auxConfig     = 0x41;
+
+       ibl.sgmiiConfig[1].configure     = 1;
+       ibl.sgmiiConfig[1].adviseAbility = 1;
+       ibl.sgmiiConfig[1].control               = 1;
+       ibl.sgmiiConfig[1].txConfig      = 0x108a1;
+       ibl.sgmiiConfig[1].rxConfig      = 0x700621;
+       ibl.sgmiiConfig[1].auxConfig     = 0x41;
+
+       ibl.mdioConfig.nMdioOps = 0;
+
+       ibl.spiConfig.addrWidth  = 24;
+       ibl.spiConfig.nPins      = 5;
+       ibl.spiConfig.mode       = 1;
+       ibl.spiConfig.csel       = 2;
+       ibl.spiConfig.c2tdelay   = 1;
+       ibl.spiConfig.busFreqMHz = 20;
+
+       ibl.emifConfig[0].csSpace    = 0;
+       ibl.emifConfig[0].busWidth   = 0;
+       ibl.emifConfig[0].waitEnable = 0;
+
+       ibl.emifConfig[1].csSpace    = 0;
+       ibl.emifConfig[1].busWidth   = 0;
+       ibl.emifConfig[1].waitEnable = 0;
+
+       ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
+       ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+       ibl.bootModes[0].port     = 0;
+
+       ibl.bootModes[0].u.norBoot.bootFormat   = ibl_BOOT_FORMAT_ELF;
+       ibl.bootModes[0].u.norBoot.bootAddress  = 0;
+       ibl.bootModes[0].u.norBoot.interface    = ibl_PMEM_IF_SPI;
+    ibl.bootModes[1].u.norBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.norBoot.blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
+    ibl.bootModes[1].u.norBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
+
+       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_TFTP;
+       ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY+1;
+       ibl.bootModes[1].port     = ibl_PORT_SWITCH_ALL;
+
+       ibl.bootModes[1].u.ethBoot.doBootp          = FALSE;
+       ibl.bootModes[1].u.ethBoot.useBootpServerIp = FALSE;
+       ibl.bootModes[1].u.ethBoot.useBootpFileName = FALSE;
+       ibl.bootModes[1].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_ELF;
+
+
+    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.ipAddr,    192,168,1,100);
+    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.serverIp,  192,168,1,101);
+    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
+    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.netmask,   255,255,255,0);
+
+    /* Use the e-fuse value */
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[0] = 0;
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[1] = 0;
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[2] = 0;
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[3] = 0;
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[4] = 0;
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[0]  = 't';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[1]  = 'e';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[2]  = 's';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[3]  = 't';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[4]  = '.';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[5]  = 'o';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[6]  = 'u';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[7]  = 't';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[8]  = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[9]  = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[10] = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[11] = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[12] = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[13] = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+    ibl.bootModes[1].u.ethBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.ethBoot.blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
+    ibl.bootModes[1].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
+
+       ibl.chkSum = 0;
+
+}
index 1bb44daf94b0de1722b4571904e7f7a110368ccf..c5a80ecba527feb76c2dbf61e6dfbf6e0a730506 100644 (file)
@@ -59,8 +59,8 @@ ibl_t ibl;
 
 /* The configAddress must be programmed. On images which support both endians
  * there can be two seperate configurations, one for big endian, and one for little */
-unsigned int configBusAddress = 0x50;
-unsigned int configAddress    = 0;
+unsigned int configBusAddress = IBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR;
+unsigned int configAddress    = 0x500;
 
 
 /**
index 09d218e3ee87d99812d5542bbb65aa79ce9abafd..29c6240b75244e8014557989d57c66141c3b8434 100644 (file)
@@ -47,6 +47,7 @@ CLEAN_MODULES+=$(addprefix clean_,$(CFG_MODULES))
 
 CSRC= i2cparam.c
 
+CDEFS+= -DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=$(I2C_BUS_ADDR) 
 
 # enable debug info in the compile
 UTIL=yes
index b4100adc22aa2700699f3f46124e7a6e0e3e936f..ea9a4858d67fffeede22a81f02a6ceb017c0f726 100644 (file)
@@ -54,7 +54,7 @@
 
 /* Run time configuration */
 unsigned int   deviceFreqMhz = 1000;
-unsigned short busAddress    = 0x50;
+unsigned short busAddress    = IBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR;
 unsigned int   nbytes        = I2C_SIZE_BYTES;
 unsigned int   firstByte     = 0;
 
index ad3e751ceecb73103c1001ec520c7ff4cc800e88..d12e0edd3a6faf16c1ef119a5c5448d4b9cd6972 100644 (file)
@@ -27,6 +27,8 @@ CLEAN_MODULES=$(addprefix clean_,$(MODULES))
 
 CSRC= i2cRead.c
 
+CDEFS+= -DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=$(I2C_BUS_ADDR) 
+
 # enable debug info in the compile
 UTIL=yes
 
index f6e6576e63f3f347a1b19bec33ae473a3e24e011..80d0dffab2f0a140021b8a088c38785e0f147d21 100644 (file)
@@ -54,7 +54,7 @@
 #include <string.h>
 
 #ifndef I2C_SIZE_BYTES
- #define I2C_SIZE_BYTES  0x20000
+ #define I2C_SIZE_BYTES  0x10000
 #endif
 
 /* Run time configuration */
@@ -63,12 +63,12 @@ unsigned int   prediv        = 1;       /* Pre-divider  */
 unsigned int   mult          = 20;      /* Multiplier   */
 unsigned int   postdiv       = 1;       /* Post-divider */
 
-unsigned int   busAddress    = 0x50;
+unsigned int   busAddress    = IBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR;
 unsigned int   i2cBlockSize  = 64;
 unsigned int   nbytes        = I2C_SIZE_BYTES;
 unsigned int   dataAddress   = 0;
 
-#define I2C_DATA_ADDRESS_MASK   0x0fffff        /* 20 bits specifiy the address (4 msb roll into dev address) */
+#define I2C_DATA_ADDRESS_MASK   0xffff          /* 16 bits specifiy the address (4 msb roll into dev address) */
 
 
 #pragma DATA_SECTION(i2cData, ".i2cData")
index d913ef5b240d812b559e436240eeb31a31c562e6..d4abe80cb3b151292d3cae907cee852c450cd686 100644 (file)
@@ -50,6 +50,7 @@ CLEAN_MODULES+=$(addprefix clean_,$(CFG_MODULES))
 CSRC= i2cWrite.c
 
 CDEFS+= -DI2C_SIZE_BYTES=$(I2C_SIZE_BYTES)
+CDEFS+= -DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=$(I2C_BUS_ADDR) 
 
 # enable debug info in the compile
 UTIL=yes
index d5b5720f8c59900e6a72d830201da711a0372063..869a19f68d2e563dee62a7f4721da3b8211be285 100644 (file)
@@ -41,7 +41,7 @@ endif
 all: gen_cdefdep romparse
 
 romparse: cdefdep rparse.tab.o lex.yy.o romparse.c
-       gcc -o romparse -g romparse.c rparse.tab.o lex.yy.o -I../.. -I. -I../../device/$(TARGET) -D$(TARGET)
+       gcc -DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=$(I2C_BUS_ADDR) -o romparse -g romparse.c rparse.tab.o lex.yy.o -I../.. -I. -I../../device/$(TARGET) -D$(TARGET)
 
 
 rparse.tab.o: rparse.y
index 1b8dc3400bbe22eaf9e449168b5f476a9b4a6c29..6f57aea9d6ffa3e246b017f9cca7a757788bc3bf 100644 (file)
@@ -62,7 +62,7 @@
  * Declaration: The base address of the i2c ROM being created. This is just
  *              the I2C bus address. The default is 0x50
  *************************************************************************************/
-int i2cRomBase = 0x50;
+int i2cRomBase = IBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR;
 
 /*************************************************************************************
  * Declaration: The flex input file is assigned based on the command line
@@ -475,7 +475,7 @@ void assignKeyVal (int field, int value)
 
         case CORE_FREQ_MHZ:    
                                #ifdef c661x
-                                   if (current_table.common.boot_mode = BOOT_MODE_SPI)  {
+                                   if (current_table.common.boot_mode == BOOT_MODE_SPI)  {
                                         current_table.spi.cpuFreqMhz = value;
                                         break;
                                    }