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raw | patch | inline | side by side (from parent 1: e3c9180)
raw | patch | inline | side by side (from parent 1: e3c9180)
author | Mike Line <m-line1@ti.com> | |
Tue, 21 Dec 2010 16:04:51 +0000 (11:04 -0500) | ||
committer | Mike Line <m-line1@ti.com> | |
Tue, 21 Dec 2010 16:04:51 +0000 (11:04 -0500) |
12 files changed:
index bffe7f0aed14eda98dd4cc4fc1fec10cf8e8e114..ab4d8893189f4a875e4f4706b98ea5f5522d11cc 100644 (file)
* Device DDR controller definitions
*/
#define DEVICE_DDR_BASE 0x78000000
+#define targetEmifType() ibl_EMIF_TYPE_31
/**
* @brief
index fc12659d5944a0940ab4aac54a59b1ad8e979e48..516056358b50875f98e37d87a1d678fbad7683df 100644 (file)
* Device DDR controller definitions
*/
#define DEVICE_DDR_BASE 0x80000000
+#define targetEmifType() ibl_EMIF_TYPE_31
/**
* @brief
index d779fa1f54894180cdd85f44d968215f9c9c166f..3af48b3eb8ffe01b984052f72179dbc86245a761 100644 (file)
* Device DDR controller definitions
*/
#define DEVICE_DDR_BASE 0x78000000
+#define targetEmifType() ibl_EMIF_TYPE_31
/**
* @brief
index 1e6b736defbfe0ec3ca5675d2da367c40c88d5be..53eb54330565fede411ba169f7be01740274af9d 100644 (file)
* Device DDR controller definitions
*/
#define DEVICE_DDR_BASE 0x70000000
+#define targetEmifType() ibl_EMIF_TYPE_31
/**
* @brief
index 954c0791499792c2c2fe9f8081ee675dd2119e4c..96e5edcfdfd6a6c12ba95fd23334ba67d60b2619 100644 (file)
--- a/src/device/c661x/c661x.c
+++ b/src/device/c661x/c661x.c
*/
int32 devicePowerPeriph (int32 modNum)
{
+ int32 ret;
+
/* If the input value is < 0 there is nothing to power up */
if (modNum < 0)
return (0);
if (modNum >= TARGET_PWR_MAX_MOD)
return (-1);
+
+ /* Note that if the sgmii power enable is requested the PA must be
+ * powered up first */
+ if (modNum == TARGET_PWR_ETH(x)) {
+ ret = (int32)pscEnableModule (TARGET_PWR_PA);
+ if (ret != 0)
+ return (ret);
+ }
+
return ((int32)pscEnableModule(modNum));
}
index a491647e9329fbdff61ca3b0229f3b30af774036..159455b1f3dc475f2551a8ea5f56a3a75f9fc194 100644 (file)
*/
void devicePllConfig (void)
{
+
+ /* Unlock the chip registers and leave them unlocked */
+ *((Uint32 *)0x2620038) = 0x83e70b13;
+ *((Uint32 *)0x262003c) = 0x95a4f1e0;
+
if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
hwPllSetPll (MAIN_PLL,
ibl.pllConfig[ibl_MAIN_PLL].prediv,
index 3b34bc8788017c06ad9e48faeeeecfd0cbb53a1e..a282ecdedc54386d3687bd7c3854770a28621528 100644 (file)
* Device DDR controller definitions
*/
#define DEVICE_EMIF4_BASE 0x21000000
+#define targetEmifType() ibl_EMIF_TYPE_40
/**
* @brief
#define TARGET_SGMII_EXTERNAL_SERDES
+#define TARGET_SGMII_TYPE_2 /* Use second sgmii setup sequence */
#define TARGET_SGMII_BASE_ADDRESSES { 0x02090100, 0x02090200 }
#define TARGET_SGMII_SERDES_BASE 0x2620340
#define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
diff --git a/src/driver/nand/nand.c b/src/driver/nand/nand.c
index 25e8a0c12b7edd8825654989ab3b8b0495bbc36b..496b7bdee12c9c9759a2f2a63abe6b345c9a42f3 100644 (file)
--- a/src/driver/nand/nand.c
+++ b/src/driver/nand/nand.c
* This function initializes the nand control structure and reads the bad block info
* from the nand.
*/
-Int32 nand_open (void *ptr_driver, void (*asyncComplete)(void *))
+Int32 nand_open (void *ptr_driver, void (*asyncComplete)(void *), int32 chipSelect)
{
iblNand_t *ibln = (iblNand_t *)ptr_driver;
nandmcb.physToLogicalMap = NULL;
nandmcb.blocks = NULL;
- ret = nandHwDriverInit (&nandmcb.devInfo);
+ ret = nandHwDriverInit (ibln->cs, &nandmcb.devInfo);
if (ret < 0)
nand_free_return (ret);
diff --git a/src/hw/sgmii/sgmii.c b/src/hw/sgmii/sgmii.c
index 54f423863ec424bda7734f37f5b3283a3e5727b1..c8d50ea7f861cdcf9bb46518af3a3869aa6b3f48 100644 (file)
--- a/src/hw/sgmii/sgmii.c
+++ b/src/hw/sgmii/sgmii.c
#define SGMII_ACCESS(port,reg) *((volatile unsigned int *)(sgmiis[port] + reg))
+
+#ifdef TARGET_SGMII_TYPE_2
+/**
+ * @brief
+ * Configure the sgmii on devices using the type 2 initialization sequence
+ */
+int32 hwSgmiiConfig (int32 port, iblSgmii_t *iblSgmii)
+{
+ unsigned int sgmiis[] = TARGET_SGMII_BASE_ADDRESSES;
+
+
+ SGMII_ACCESS(port, TARGET_SGMII_CONTROL) = 0; /* Disable negotiation */
+
+#ifdef TARGET_SGMII_EXTERNAL_SERDES
+
+ targetSgmiiSerdesConfig (port, (void *)iblSgmii);
+
+#else
+
+ /* Serdes configuration */
+ SGMII_ACCESS(port, TARGET_SGMII_TX_CFG) = iblSgmii->txConfig;
+ SGMII_ACCESS(port, TARGET_SGMII_RX_CFG) = iblSgmii->rxConfig;
+ SGMII_ACCESS(port, TARGET_SGMII_AUX_CFG) = iblSgmii->auxConfig;
+
+#endif
+
+ SGMII_ACCESS(port, TARGET_SGMII_MR_ADV_ABILITY) = iblSgmii->adviseAbility;
+ SGMII_ACCESS(port, TARGET_SGMII_CONTROL) = iblSgmii->control;
+
+ return (0);
+
+}
+
+
+#else
/**
* @brief
* Configure the sgmii
}
+#endif
+
diff --git a/src/ibl.h b/src/ibl.h
index 200a86a0387406478caa1436bdbcfe76ea7649c3..0ab5f75c59ed16d6f911c97eeceb2336f07febf1 100644 (file)
--- a/src/ibl.h
+++ b/src/ibl.h
/* @} */
+
+/**
+ * @defgroup iblEmifType Defines the EMIF4 type on a device
+ *
+ * @ingroup iblEmifType
+ * @{
+ */
+/** @def ibl_EMIF_TYPE_31 */
+#define ibl_EMIF_TYPE_31 31
+
+/** @def ibl_EMIF_TYPE_40 */
+#define ibl_EMIF_TYPE_40 40
+
+/* @} */
/**
* @brief
diff --git a/src/main/iblinit.c b/src/main/iblinit.c
index b6f5a80245aa32ad6a5f27190a7c1833f9ccfbdc..0e81aebf0666d5b2d1bcfee8e5342b040beac6f3 100644 (file)
--- a/src/main/iblinit.c
+++ b/src/main/iblinit.c
ibl.ddrConfig.configDdr = swap16val (ibl.ddrConfig.configDdr);
- ibl.ddrConfig.uEmif.emif3p1.sdcfg = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdcfg);
- ibl.ddrConfig.uEmif.emif3p1.sdrfc = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdrfc);
- ibl.ddrConfig.uEmif.emif3p1.sdtim1 = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdtim1);
- ibl.ddrConfig.uEmif.emif3p1.sdtim2 = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdtim2);
- ibl.ddrConfig.uEmif.emif3p1.dmcctl = swap32val(ibl.ddrConfig.uEmif.emif3p1.dmcctl);
+#define targetEmifType() ibl_EMIF_TYPE_40
+
+ if (targetEmifType() == ibl_EMIF_TYPE_31) {
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdcfg);
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdrfc);
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdtim1);
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = swap32val(ibl.ddrConfig.uEmif.emif3p1.sdtim2);
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = swap32val(ibl.ddrConfig.uEmif.emif3p1.dmcctl);
+
+ } else if (targetEmifType() == ibl_EMIF_TYPE_40) {
+ ibl.ddrConfig.uEmif.emif4p0.registerMask = swap32val(ibl.ddrConfig.uEmif.emif4p0.registerMask);
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = swap32val(ibl.ddrConfig.uEmif.emif4p0.sdRamConfig);
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = swap32val(ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2);
+ ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = swap32val(ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl);
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = swap32val(ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1);
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = swap32val(ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2);
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = swap32val(ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3);
+ ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = swap32val(ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming);
+ ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = swap32val(ibl.ddrConfig.uEmif.emif4p0.powerManageCtl);
+ ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = swap32val(ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic);
+ ibl.ddrConfig.uEmif.emif4p0.performCountCfg = swap32val(ibl.ddrConfig.uEmif.emif4p0.performCountCfg);
+ ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = swap32val(ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel);
+ ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = swap32val(ibl.ddrConfig.uEmif.emif4p0.readIdleCtl);
+ ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = swap32val(ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet);
+ ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = swap32val(ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg);
+ ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = swap32val(ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg);
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = swap32val(ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1);
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = swap32val(ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2);
+ ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = swap32val(ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap);
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = swap32val(ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map);
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = swap32val(ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map);
+ ibl.ddrConfig.uEmif.emif4p0.eccCtl = swap32val(ibl.ddrConfig.uEmif.emif4p0.eccCtl);
+ ibl.ddrConfig.uEmif.emif4p0.eccRange1 = swap32val(ibl.ddrConfig.uEmif.emif4p0.eccRange1);
+ ibl.ddrConfig.uEmif.emif4p0.eccRange2 = swap32val(ibl.ddrConfig.uEmif.emif4p0.eccRange2);
+ ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = swap32val(ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh);
+ }
+
for (i = 0; i < ibl_N_ETH_PORTS; i++) {
ibl.ethConfig[i].ethPriority = swap32val (ibl.ethConfig[i].ethPriority);
index e7e4c1de71cee885ea26952e91beb35697b9493f..f2bea38779f51195656a91778ee329d5cf38645c 100644 (file)
MEMORY
{
- TEXT_INIT : origin = 0x800000, length = 0x2c00
- TEXT : origin = 0x802c00, length = 0xd300
+ TEXT_INIT : origin = 0x800000, length = 0x3000
+ TEXT : origin = 0x803000, length = 0xd000
STACK : origin = 0x810000, length = 0x0800
HEAP : origin = 0x810800, length = 0x6000
DATA_INIT : origin = 0x816800, length = 0x0200