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Added support for C6670
authorSandeep Nair <a0875039@gt48xvq51.gt.design.ti.com>
Tue, 5 Apr 2011 15:27:27 +0000 (11:27 -0400)
committerSandeep Nair <a0875039@gt48xvq51.gt.design.ti.com>
Tue, 5 Apr 2011 15:27:27 +0000 (11:27 -0400)
release.sh patch | blob | history
src/ibl.h patch | blob | history
src/make/Makefile patch | blob | history
src/util/i2cConfig/i2cConfig.gel patch | blob | history

diff --git a/release.sh b/release.sh
index 215f8401d367cc3820b3f9f188936ec554d8364c..f1e4b5a6ef1bef34462f2943b659feaea73dfeda 100755 (executable)
--- a/release.sh
+++ b/release.sh
@@ -32,6 +32,9 @@ mkdir ibl_bin_$IBL_VERSION/c6457/le
 mkdir ibl_bin_$IBL_VERSION/c6678/
 mkdir ibl_bin_$IBL_VERSION/c6678/le
 
+mkdir ibl_bin_$IBL_VERSION/c6670/
+mkdir ibl_bin_$IBL_VERSION/c6670/le
+
 # Copy i2cConfig GEL file
 cp -f src/util/i2cConfig/i2cConfig.gel ibl_bin_$IBL_VERSION/i2cConfig.gel
 
@@ -124,6 +127,15 @@ cp -f src/make/ibl_c661x/i2crom.dat ibl_bin_$IBL_VERSION/c6678/le/i2crom_0x51_c6
 cp -f src/util/i2cWrite/i2cWrite_le.out   ibl_bin_$IBL_VERSION/c6678/le/i2cWrite_c6678_le.out
 cp -f src/util/i2cConfig/i2cparam_c661x_le.out ibl_bin_$IBL_VERSION/c6678/le/i2cparam_c6678_le.out
 
+# Build c6670 EVM 
+pushd src/make
+make clean
+make evm_c6670_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
+popd
+cp -f src/make/ibl_c661x/i2crom.dat ibl_bin_$IBL_VERSION/c6670/le/i2crom_0x51_c6670_le.dat
+cp -f src/util/i2cWrite/i2cWrite_le.out   ibl_bin_$IBL_VERSION/c6670/le/i2cWrite_c6670_le.out
+cp -f src/util/i2cConfig/i2cparam_c661x_le.out ibl_bin_$IBL_VERSION/c6670/le/i2cparam_c6670_le.out
+
 # Create Tar archive for binary package
 tar -czf ibl_bin_$IBL_VERSION.tgz ibl_bin_$IBL_VERSION
 
diff --git a/src/ibl.h b/src/ibl.h
index 35b6db501f419698c08100b75d715c9abd1961e6..e576be0c0ead256b269a2be9d5cbee9ebc7a74ec 100644 (file)
--- a/src/ibl.h
+++ b/src/ibl.h
@@ -65,9 +65,9 @@
 
 /**
  * @brief
- *  The version number, 1.0.0.0
+ *  The version number, 1.0.0.2
  */
-#define ibl_VERSION  ibl_MAKE_VERSION(1,0,0,1)
+#define ibl_VERSION  ibl_MAKE_VERSION(1,0,0,2)
 
 
 /**
diff --git a/src/make/Makefile b/src/make/Makefile
index 71e3939f6c248eb19a6e7b3f95a7a5cd927a5910..6885e3634630a7f4d9e15801cf5b1196acff5aa0 100644 (file)
--- a/src/make/Makefile
+++ b/src/make/Makefile
@@ -306,6 +306,9 @@ evm_c6678_spi:
 evm_c6678_i2c:
        make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
 
+evm_c6670_i2c:
+       make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_6608_SPI_DEFS)' c661x
+
 test_c661x:
        make -f makestg1 ARCH=c64x TARGET=c661x ENDIAN_MODE=both CEXCLUDES='NOR_SPI' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c661x
        make -f makestg1 ARCH=c64x TARGET=c661x ENDIAN_MODE=both CEXCLUDES='NAND_SPI' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c661x
diff --git a/src/util/i2cConfig/i2cConfig.gel b/src/util/i2cConfig/i2cConfig.gel
index e7ba2a0966c329d4171ecd6e3860c5b8a0d1d135..33419e3ab68f4f717aeea2e3751f49e011826620 100755 (executable)
--- a/src/util/i2cConfig/i2cConfig.gel
+++ b/src/util/i2cConfig/i2cConfig.gel
@@ -776,3 +776,148 @@ hotmenu setConfig_c6678_nand()
     ibl.bootModes[0].u.nandBoot.nandInfo.postCommand     = FALSE;
 }
 
+menuitem "EVM c6670 IBL";
+
+hotmenu setConfig_c6670_main()
+{
+       ibl.iblMagic = ibl_MAGIC_VALUE;
+
+       /* Main PLL: 100 MHz reference, 1GHz output */
+       ibl.pllConfig[ibl_MAIN_PLL].doEnable      = 1;
+       ibl.pllConfig[ibl_MAIN_PLL].prediv        = 1;
+       ibl.pllConfig[ibl_MAIN_PLL].mult          = 16;
+       ibl.pllConfig[ibl_MAIN_PLL].postdiv       = 2;
+       ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
+
+       /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */
+       ibl.pllConfig[ibl_DDR_PLL].doEnable       = 0; 
+       ibl.pllConfig[ibl_DDR_PLL].prediv         = 1;
+       ibl.pllConfig[ibl_DDR_PLL].mult           = 12;
+       ibl.pllConfig[ibl_DDR_PLL].postdiv        = 2;
+       ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz  = 400;
+
+    /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */
+       ibl.pllConfig[ibl_NET_PLL].doEnable       = 0;
+       ibl.pllConfig[ibl_NET_PLL].prediv         = 1;
+       ibl.pllConfig[ibl_NET_PLL].mult                   = 21;
+       ibl.pllConfig[ibl_NET_PLL].postdiv        = 2;
+       ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz  = 1050;
+
+
+       ibl.ddrConfig.configDdr = 1;
+       ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
+
+       ibl.ddrConfig.uEmif.emif4p0.sdRamConfig                         = 0x63C452B2;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2                        = 0;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl                     = 0x000030D4;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1                        = 0x0AAAE51B;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2                        = 0x2A2F7FDA;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3                        = 0x057F82B8;
+       ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming                      = 0;
+       ibl.ddrConfig.uEmif.emif4p0.powerManageCtl                      = 0;
+       ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic                      = 0;
+       ibl.ddrConfig.uEmif.emif4p0.performCountCfg                     = 0;
+       ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel       = 0;
+       ibl.ddrConfig.uEmif.emif4p0.readIdleCtl                         = 0;
+       ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet            = 0;
+       ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg        = 0;
+       ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg                        = 0;
+       ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1                          = 0x0010010d;
+       ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2                          = 0;
+       ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap                     = 0;
+       ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map           = 0;
+       ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map           = 0;
+       ibl.ddrConfig.uEmif.emif4p0.eccCtl                                      = 0;
+       ibl.ddrConfig.uEmif.emif4p0.eccRange1                           = 0;
+       ibl.ddrConfig.uEmif.emif4p0.eccRange2                           = 0;
+       ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh                      = 0;
+
+
+       ibl.sgmiiConfig[0].configure     = 1;
+       ibl.sgmiiConfig[0].adviseAbility = 1;
+       ibl.sgmiiConfig[0].control               = 1;
+       ibl.sgmiiConfig[0].txConfig      = 0x108a1;
+       ibl.sgmiiConfig[0].rxConfig      = 0x700621;
+       ibl.sgmiiConfig[0].auxConfig     = 0x41;
+
+       ibl.sgmiiConfig[1].configure     = 1;
+       ibl.sgmiiConfig[1].adviseAbility = 1;
+       ibl.sgmiiConfig[1].control               = 1;
+       ibl.sgmiiConfig[1].txConfig      = 0x108a1;
+       ibl.sgmiiConfig[1].rxConfig      = 0x700621;
+       ibl.sgmiiConfig[1].auxConfig     = 0x41;
+
+       ibl.mdioConfig.nMdioOps = 0;
+
+       ibl.spiConfig.addrWidth  = 24;
+       ibl.spiConfig.nPins      = 5;
+       ibl.spiConfig.mode       = 1;
+       ibl.spiConfig.csel       = 2;
+       ibl.spiConfig.c2tdelay   = 1;
+       ibl.spiConfig.busFreqMHz = 20;
+
+       ibl.emifConfig[0].csSpace    = 2;
+       ibl.emifConfig[0].busWidth   = 8;
+       ibl.emifConfig[0].waitEnable = 0;
+
+       ibl.emifConfig[1].csSpace    = 0;
+       ibl.emifConfig[1].busWidth   = 0;
+       ibl.emifConfig[1].waitEnable = 0;
+
+       ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
+       ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+       ibl.bootModes[0].port     = 0;
+
+       ibl.bootModes[0].u.norBoot.bootFormat   = ibl_BOOT_FORMAT_ELF;
+       ibl.bootModes[0].u.norBoot.bootAddress  = 0;
+       ibl.bootModes[0].u.norBoot.interface    = ibl_PMEM_IF_SPI;
+    ibl.bootModes[0].u.norBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[0].u.norBoot.blob.sizeBytes     = 0x80000;          /* 512 KB */
+    ibl.bootModes[0].u.norBoot.blob.branchAddress = 0x80000000;       /* Base address of DDR2 */
+
+       ibl.bootModes[1].bootMode = ibl_BOOT_MODE_TFTP;
+       ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY+1;
+       ibl.bootModes[1].port     = ibl_PORT_SWITCH_ALL;
+
+       ibl.bootModes[1].u.ethBoot.doBootp          = FALSE;
+       ibl.bootModes[1].u.ethBoot.useBootpServerIp = FALSE;
+       ibl.bootModes[1].u.ethBoot.useBootpFileName = FALSE;
+       ibl.bootModes[1].u.ethBoot.bootFormat       = ibl_BOOT_FORMAT_ELF;
+
+
+    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.ipAddr,    192,168,1,100);
+    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.serverIp,  192,168,1,101);
+    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
+    SETIP(ibl.bootModes[1].u.ethBoot.ethInfo.netmask,   255,255,255,0);
+
+    /* Use the e-fuse value */
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[0] = 0;
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[1] = 0;
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[2] = 0;
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[3] = 0;
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[4] = 0;
+    ibl.bootModes[1].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[0]  = 'a';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[1]  = 'p';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[2]  = 'p';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[3]  = '.';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[4]  = 'o';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[5]  = 'u';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[6]  = 't';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[7]  = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[8]  = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[9]  = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[10] = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[11] = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[12] = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[13] = '\0';
+    ibl.bootModes[1].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+    ibl.bootModes[1].u.ethBoot.blob.startAddress  = 0x80000000;       /* Base address of DDR2 */
+    ibl.bootModes[1].u.ethBoot.blob.sizeBytes     = 0x20000000;       /* All of DDR2 */
+    ibl.bootModes[1].u.ethBoot.blob.branchAddress = 0x80000000;       /* Base of DDR2 */
+
+       ibl.chkSum = 0;
+}
\ No newline at end of file
Project to include GIT repos for RTOS components including user mode CSL & NetCP LLDs (CPPI/QMSS/PA/RM), PDK components (NWAL/PKTLIB) and Transport Net Lib components (NetAPI/HPLIB) - secondary bootloader for legacy K1 SOCs: C6678/C6657.