Fixes to make the build work for C66x and C64x devices
authorSandeep Nair <sandeep_n@ti.com>
Wed, 25 May 2011 15:22:52 +0000 (11:22 -0400)
committerSandeep Nair <sandeep_n@ti.com>
Wed, 25 May 2011 15:22:52 +0000 (11:22 -0400)
Documentation changes

13 files changed:
doc/README.txt
doc/release_info.txt
release.sh
src/cfg/c6455/iblcfg.h
src/cfg/c6457/iblcfg.h
src/cfg/c6472/iblcfg.h
src/cfg/c6474/iblcfg.h
src/hw/c64x/make/makefile
src/hw/nands/gpio/nandwrgpio.c
src/ibl.h
src/make/Makefile
src/make/ibl_c661x/ibl_objs_template.inc
src/make/setupenvLnx.sh

index 225490b4cf0e906efa0732a6046b7135a3497563..67e90427d4345fb480197fb88eb8aac748c9b9ae 100644 (file)
@@ -3,5 +3,6 @@ This directory contains the following documents:
 1. release_info.txt: IBL release Notes
 2. IBL-software-manifest.html: Software manifest
 3. IBL-Configuration: Folder containing documentation on IBL configuration
-4. evmc6678-instructions.txt: Documents describing steps to use IBL on the c6678 EVM
+4. evmc6678-instructions.txt: Document describing steps to use IBL on the c6678 EVM
+5. evmc6670-instructions.txt: Document describing steps to use IBL on the c6670 EVM
 
index 135c5beb4642e64a3f9221b84a883a92e27af347..00cd5daf9c09a0a354140b0bd984ec7b5b7e86a6 100644 (file)
@@ -39,9 +39,12 @@ May 2011
          On a Linux Bash shell run  "source setupenvLnx.sh"
          On a MinGW-MSYS Bash shell "source setupenvMsys.sh"
     - For building run the following make command:
-    For C6678/C6670 Low Cost EVM:
-        make evm_c667x_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
-      or:
+        For C6678 Low Cost EVM:
+        make evm_c6678_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
+        For C6670 Low Cost EVM:
+        make evm_c6670_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
+
+      or for generic build option:
         make <TARGET>  ENDIAN=[little|big]
         make c6455 ENDIAN=liitle
         make c6455 ENDIAN=big
index 7c7fef611c4a14ff145fbe6c157530e1ccc524ce..ed531418e2529b56d719b1f724ed6ec9a407e82b 100755 (executable)
@@ -1,6 +1,6 @@
 #!/bin/sh
 # Generate the source release tarballs
-export IBL_VERSION="1_0_0_4"
+export IBL_VERSION="1_0_0_5"
 cd ../
 if [ -f ibl_src_$IBL_VERSION.tgz ]; then rm ibl_src_$IBL_VERSION.tgz; fi
 
@@ -118,10 +118,10 @@ cp -f src/make/ibl_c6457/i2crom_0x50_c6457_be.bin ibl_bin_$IBL_VERSION/c6457/be/
 cp -f src/util/i2cConfig/i2cparam_c6457_le.out   ibl_bin_$IBL_VERSION/c6457/le/
 cp -f src/util/i2cConfig/i2cparam_c6457_be.out   ibl_bin_$IBL_VERSION/c6457/be/
 
-# Build c6678/c6670 EVM 
+# Build c6678 EVM 
 pushd src/make
 make clean
-make evm_c667x_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
+make evm_c6678_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
 popd
 cp -f src/make/ibl_c661x/i2crom.dat ibl_bin_$IBL_VERSION/c6678/le/i2crom_0x51_c6678_le.dat
 cp -f src/make/ibl_c661x/i2crom.bin ibl_bin_$IBL_VERSION/c6678/le/i2crom_0x51_c6678_le.bin
@@ -130,6 +130,15 @@ cp -f src/make/ibl_c661x/i2crom.dat ibl_bin_$IBL_VERSION/c6670/le/i2crom_0x51_c6
 cp -f src/make/ibl_c661x/i2crom.bin ibl_bin_$IBL_VERSION/c6670/le/i2crom_0x51_c6670_le.bin
 cp -f src/util/i2cConfig/i2cparam_c661x_le.out ibl_bin_$IBL_VERSION/c6670/le/i2cparam_c6670_le.out
 
+# Build c6670 EVM 
+pushd src/make
+make clean
+make evm_c6670_i2c ENDIAN=little I2C_BUS_ADDR=0x51 
+popd
+cp -f src/make/ibl_c661x/i2crom.dat ibl_bin_$IBL_VERSION/c6670/le/i2crom_0x51_c6670_le.dat
+cp -f src/make/ibl_c661x/i2crom.bin ibl_bin_$IBL_VERSION/c6670/le/i2crom_0x51_c6670_le.bin
+cp -f src/util/i2cConfig/i2cparam_c661x_le.out ibl_bin_$IBL_VERSION/c6670/le/i2cparam_c6670_le.out
+
 # Create Tar archive for binary package
 tar -czf ibl_bin_$IBL_VERSION.tgz ibl_bin_$IBL_VERSION
 
index b165d003c80a8e2aa1ecb103e35c1c3b6ae80cc9..93f17ba3bab9f282122b713a73fe8f9f40682cd8 100644 (file)
 #define NAND_CLE_GPIO_PIN      GPIO_8     // High: Command Cycle occuring
 #define NAND_ALE_GPIO_PIN      GPIO_9     // High: Address input cycle oddcuring
 #define NAND_NWE_GPIO_PIN      GPIO_10
+#define NAND_BSY_GPIO_PIN   GPIO_11     /* NAND Ready/Busy pin */
 #define NAND_NRE_GPIO_PIN      GPIO_12
 #define NAND_NCE_GPIO_PIN      GPIO_13
 #define NAND_MODE_GPIO         GPIO_14
  *      The standard NAND delay must be big enough to handle the highest possible
  *      operating frequency of the device */
 #define TARGET_NAND_STD_DELAY                          25 // In cpu cycles
+#define NAND_WAIT_PIN_POLL_ST_DLY      (10000)
 
 
 
index 88592c86baabf80bdb54af83a2338534999c2b50..77a0d0df6bc412a0bee20b36d70be487c7de395a 100644 (file)
 #define NAND_CLE_GPIO_PIN      GPIO_8     // High: Command Cycle occuring
 #define NAND_ALE_GPIO_PIN      GPIO_9     // High: Address input cycle oddcuring
 #define NAND_NWE_GPIO_PIN      GPIO_10
+#define NAND_BSY_GPIO_PIN   GPIO_11     /* NAND Ready/Busy pin */
 #define NAND_NRE_GPIO_PIN      GPIO_12
 #define NAND_NCE_GPIO_PIN      GPIO_13
 #define NAND_MODE_GPIO         GPIO_14
  *      The standard NAND delay must be big enough to handle the highest possible
  *      operating frequency of the device */
 #define TARGET_NAND_STD_DELAY                          25 // In cpu cycles
+#define NAND_WAIT_PIN_POLL_ST_DLY      (10000)
 
 
 #endif
index 4cf552a8e3a110e091e0f5c9cce622c41518167c..0caf0d014c75a38462bf7f24e97cab9f3ef8cd3e 100644 (file)
 #define NAND_CLE_GPIO_PIN      GPIO_8     // High: Command Cycle occuring
 #define NAND_ALE_GPIO_PIN      GPIO_9     // High: Address input cycle oddcuring
 #define NAND_NWE_GPIO_PIN      GPIO_10
+#define NAND_BSY_GPIO_PIN   GPIO_11     /* NAND Ready/Busy pin */
 #define NAND_NRE_GPIO_PIN      GPIO_12
 #define NAND_NCE_GPIO_PIN      GPIO_13
 #define NAND_MODE_GPIO         GPIO_14
  *      The standard NAND delay must be big enough to handle the highest possible
  *      operating frequency of the device */
 #define TARGET_NAND_STD_DELAY                          25 // In cpu cycles
+#define NAND_WAIT_PIN_POLL_ST_DLY      (10000)
 
 
 
index 7b17be32bef389adc8499f58bd56c928269e3e99..63ec273e79e9f9c4510b95b960d948637a466d8c 100755 (executable)
 #define NAND_CLE_GPIO_PIN      GPIO_8     // High: Command Cycle occuring
 #define NAND_ALE_GPIO_PIN      GPIO_9     // High: Address input cycle oddcuring
 #define NAND_NWE_GPIO_PIN      GPIO_10
+#define NAND_BSY_GPIO_PIN   GPIO_11     /* NAND Ready/Busy pin */
 #define NAND_NRE_GPIO_PIN      GPIO_12
 #define NAND_NCE_GPIO_PIN      GPIO_13
 #define NAND_MODE_GPIO         GPIO_14
  *      The standard NAND delay must be big enough to handle the highest possible
  *      operating frequency of the device */
 #define TARGET_NAND_STD_DELAY                          25 // In cpu cycles
+#define NAND_WAIT_PIN_POLL_ST_DLY      (10000)
 
  
 #endif
index 1a9b6f365b25616879d99bc9ce976d7f07af5604..ff20aace618be5e634b40bcbcedb026d0421f52e 100644 (file)
@@ -48,25 +48,25 @@ ECODIR= $(IBL_ROOT)/hw
 
 # If no target specified, set CSRC to all files (used for clean)
 ifeq ($(TARGET),c6472)
- CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c
+ CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c 
 else
  ifeq ($(TARGET),c6474)
-  CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c sgmii.c
+  CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c sgmii.c
  else
   ifeq ($(TARGET),c6474l)
-   CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c sgmii.c
+   CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c sgmii.c
   else
    ifeq ($(TARGET),c6457)
-    CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c sgmiicur.c
+    CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c sgmiicur.c
    else
     ifeq ($(TARGET),c6455)
-     CSRC= t64.c cpmacdrv.c pll.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c
+     CSRC= t64.c cpmacdrv.c pll.c emif31.c mdio.c gpio.c nandgpio.c i2c.c
        else
         ifeq ($(TARGET),c661x)
          CSRC= t64.c pll.c cfgpll.c cfgpll2.c mdio.c i2c.c psc.c cpsw.c qm.c cpdma.c pa.c sgmii.c serdes.c gmacsl.c emif4.c gpio.c
          CSRC+= nandemif25.c nandgpio.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c
      else
-      CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c sgmii.c cfgpll.c cfgpll2.c
+      CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c sgmii.c cfgpll.c cfgpll2.c
          CSRC+= qm.c cpdma.c pa.c serdes.c gmacsl.c emif4.c nandemif25.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c
      endif
     endif
index cdcd77baae655e4142b5f489a48261e58cce95f7..f72df959626ca94bc89d22406a259f07a89b0e46 100644 (file)
@@ -129,8 +129,8 @@ Int32 nandHwDriverWritePage (Uint32 block, Uint32 page, Uint8 *data, nandProgram
     if (winfo->pageWritePost == TRUE) 
            ptNandCmdSet(winfo->pageWriteCommandPost);
 
-       ptNandWaitRdy();
-       ptNandWaitRdy();
+       ptNandWaitRdy(100000);
+       ptNandWaitRdy(100000);
        
        hwGpioSetOutput(NAND_NCE_GPIO_PIN);
        
index 73da665144ab779dea67f1ad33c000340761727c..e9053b4a392dccfa5dbf974ea6e4df8e6b7271ba 100644 (file)
--- a/src/ibl.h
+++ b/src/ibl.h
@@ -65,9 +65,9 @@
 
 /**
  * @brief
- *  The version number, 1.0.0.4
+ *  The version number, 1.0.0.5
  */
-#define ibl_VERSION  ibl_MAKE_VERSION(1,0,0,4)
+#define ibl_VERSION  ibl_MAKE_VERSION(1,0,0,5)
 
 
 /**
index 664bea2055b7dc01effba17841bec5e91b1a37c3..fdc38a1021f3c358c6494b42c7083f7c63f0f5d8 100644 (file)
@@ -88,7 +88,7 @@ EVMS_C6X= evm_c6455 evm_c6472 evm_c6474
 # speeds the initial boot time. Note that boot table cannot be excluded
 # because it is required for the two stage I2C load process
 
-CEXCLUDES ?=
+CEXCLUDES=
 
 ifeq ($(ETH),no)
  CEXCLUDES+= ETH
@@ -322,9 +322,15 @@ EVM_667x_SPI_DEFS= SPI_MODE=1 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL
 evm_c667x_spi:
        make -f makestg1 ARCH=c64x TARGET=c661x I2C=no I2C_BUS_ADDR=0x51 I2C_MAP_ADDR=0x500 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_667x_SPI_DEFS)' c661x
 
-evm_c667x_i2c:
+evm_c6678_i2c:
        make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) \
-ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_667x_SPI_DEFS)' CEXCLUDES='$(CEXCLUDES)' c661x
+ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_667x_SPI_DEFS)' \
+CEXCLUDES='COFF BIS NAND_GPIO' c661x
+
+evm_c6670_i2c:
+       make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) \
+ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c661x SPI=no SPI_DEFS='$(EVM_667x_SPI_DEFS)' \
+CEXCLUDES='COFF BIS NAND_EMIF' c661x
 
 test_c661x:
        make -f makestg1 ARCH=c64x TARGET=c661x ENDIAN_MODE=both CEXCLUDES='NOR_SPI' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c661x
index 46b2a84a762a5d7b182dd9005a95072e5a7ae7b1..d861fa594d3232f29932fd5bcbc6f543970cbb01 100644 (file)
@@ -56,7 +56,7 @@
 
 
 /* -------------- */
-#if (!defined(EXCLUDE_NAND_EMIF) || !defined(EXCLUDE_NAND_SPI) || !defined(EXCLUDE_NAND_GPIO)
+#if (!defined(EXCLUDE_NAND_EMIF) || !defined(EXCLUDE_NAND_SPI) || !defined(EXCLUDE_NAND_GPIO))
 
 ../nandboot/c64x/make/nandboot.ENDIAN_TAG.oc
 ../driver/c64x/make/nand.ENDIAN_TAG.oc
index e2e47d4e45676a91350ad6ccf737238d715bb3fb..15b84ebb634f66bc9707fa37b6a171fcc88fd1bb 100755 (executable)
@@ -1,6 +1,7 @@
 #!/bin/bash
 export OS="Linux"
-export C6X_BASE_DIR=/apps/ti/cgt/TI_CGT_C6000_6.1.12
+#export C6X_BASE_DIR=/apps/ti/cgt/TI_CGT_C6000_6.1.12
+export C6X_BASE_DIR=/apps/ti/cgt/C6000CGT7.2.0
 export PATH=$C6X_BASE_DIR/bin:$PATH
 export TOOLSC6X=$C6X_BASE_DIR
 export TOOLSC6XDOS=$C6X_BASE_DIR