Merge branch 'linux-c6x-2.0.x' into boot-rel-exp
authorPrabhu Kuttiyam <pkuttiyam@ti.com>
Mon, 28 Nov 2011 14:42:40 +0000 (09:42 -0500)
committerPrabhu Kuttiyam <pkuttiyam@ti.com>
Mon, 28 Nov 2011 14:42:40 +0000 (09:42 -0500)
Conflicts:
src/device/c66x/c66x.c
src/main/iblmain.c

src/device/c66x/c66x.c
src/device/c66x/c66xutil.c
src/device/c66x/target.h
src/hw/c64x/make/makefile
src/hw/uart/c66x_uart/c66x_uart.c [moved from src/hw/uart/c66x_uart/evmc66x_uart.c with 99% similarity]
src/hw/uart/c66x_uart/c66x_uart.h [moved from src/hw/uart/c66x_uart/evmc66x_uart.h with 98% similarity]
src/make/ibl_c66x/ibl_objs_template.inc
src/make/setupenvLnx.sh

index e7a2cf7ec894cd4066d0632de80e3d0dd7513cbf..7fe8c3e50d9f0bff891fe2dcec5d631300d416e8 100755 (executable)
@@ -66,6 +66,7 @@
 #include "spi_api.h"
 #include <string.h>
 #include <stdint.h>
+#include "target.h"
 #include "uart.h"
 
 #define PLL_DDR_INIT_LOOPMAX 10
 #define IBL_RESULT_CODE_LOC 17
 
 extern cregister unsigned int DNUM;
-#define DDR3_TEST_ENABLE
-
-#ifdef DDR3_TEST_ENABLE
-/**
- *  @brief Simple DDR3 test
- *
- *  @details
- *      This function performs a simple DDR3 test for a memory range
- *      specified below and returns -1 for failure and 0 for success.
- */
-
-#define DDR3_TEST_START_ADDRESS 0x80000000
-
-#define DDR3_TEST_END_ADDRESS   (DDR3_TEST_START_ADDRESS + (128 *1024))
-
-static int32_t ddr3_memory_test (void)
-{
-       uint32_t index, value;
-
-       /* Write a pattern */
-       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
-               *(volatile uint32_t *) index = (uint32_t)index;
-       }
-
-       /* Read and check the pattern */
-       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
-
-               value = *(uint32_t *) index;
-
-               if (value  != index) {
-                       return -1;
-               }
-       }
-
-       /* Write a pattern for complementary values */
-       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
-               *(volatile uint32_t *) index = (uint32_t)~index;
-       }
-
-       /* Read and check the pattern */
-       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
-
-               value = *(uint32_t *) index;
-
-               if (value  != ~index) {
-                       return -1;
-               }
-       }
-
-       return 0;
-}
-
-#endif
 
 /**
  *  @brief Determine if an address is local
@@ -187,46 +135,45 @@ void deviceDdrConfig (void)
     DEVICE_REG_XMPAX_L(2) =  0x10000000 | 0xff;     /* replacement addr + perm*/
     DEVICE_REG_XMPAX_H(2) =  0x2100000B;         /* base addr + seg size (64KB)*/      
     
+    if (ibl.ddrConfig.configDdr != 0)
+        hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
+
+#ifdef DDR3_TEST_ENABLE
     for (loopcount = 0; loopcount < PLL_DDR_INIT_LOOPMAX; loopcount++)
     {
-        if(loopcount !=0) /*Do not call PLL sequence for the first time */
-        {
+       if (ddr3_memory_test() == 0) 
+       {
+           break;
+       }
        /* Calling MAIN, PA, DDR PLL init  */
-           if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
-               hwPllSetPll (MAIN_PLL, 
-                            ibl.pllConfig[ibl_MAIN_PLL].prediv,
-                                 ibl.pllConfig[ibl_MAIN_PLL].mult,
-                                 ibl.pllConfig[ibl_MAIN_PLL].postdiv);
+       if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
+            hwPllSetPll (MAIN_PLL, 
+                         ibl.pllConfig[ibl_MAIN_PLL].prediv,
+                         ibl.pllConfig[ibl_MAIN_PLL].mult,
+                         ibl.pllConfig[ibl_MAIN_PLL].postdiv);
     
-            if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
-                hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
-                                ibl.pllConfig[ibl_NET_PLL].prediv,
-                                ibl.pllConfig[ibl_NET_PLL].mult,
-                                ibl.pllConfig[ibl_NET_PLL].postdiv,
-                                ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
-                                ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
+        if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
+            hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
+                            ibl.pllConfig[ibl_NET_PLL].prediv,
+                            ibl.pllConfig[ibl_NET_PLL].mult,
+                            ibl.pllConfig[ibl_NET_PLL].postdiv,
+                            ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+                            ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
     
-            if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
-                hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
-                                 ibl.pllConfig[ibl_DDR_PLL].prediv,
-                                 ibl.pllConfig[ibl_DDR_PLL].mult,
-                                 ibl.pllConfig[ibl_DDR_PLL].postdiv,
-                                 ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
-                                 ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
-         }
+        if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
+            hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
+                             ibl.pllConfig[ibl_DDR_PLL].prediv,
+                             ibl.pllConfig[ibl_DDR_PLL].mult,
+                             ibl.pllConfig[ibl_DDR_PLL].postdiv,
+                             ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+                             ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
          
         if (ibl.ddrConfig.configDdr != 0)
             hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
-        /* Init UART */
-        uart_init();
-#ifdef DDR3_TEST_ENABLE
-       if (ddr3_memory_test() == 0) 
-       {
-           break;
-       }
-#endif
-
+        /* Init UART 
+        uart_init();*/
     }
+
     if (loopcount < 10) 
     {
         ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + '0';
@@ -249,7 +196,7 @@ void deviceDdrConfig (void)
         uart_write_string("IBL: PLL and DDR Initialization Complete",0);
     }
     uart_write_string(ddr_result_code_str,0);
-
+#endif
 }
         
 
index 387039b1818842a6fa1ea159a96e817cef5d1f64..c895bcfdf72711dc0a8bcd6bb85445edea8a755d 100644 (file)
@@ -7,6 +7,11 @@
 
 #include "device.h"
 #include "pllapi.h"
+#include <string.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
 
 
 /**
@@ -126,3 +131,52 @@ int32 devicePowerPeriph (int32 modNum)
         
 }
 
+#ifdef DDR3_TEST_ENABLE
+/**
+ *  @brief Simple DDR3 test
+ *
+ *  @details
+ *      This function performs a simple DDR3 test for a memory range
+ *      specified below and returns -1 for failure and 0 for success.
+ */
+
+
+int32_t ddr3_memory_test (void)
+{
+       uint32_t index, value;
+
+       /* Write a pattern */
+       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+               *(volatile uint32_t *) index = (uint32_t)index;
+       }
+
+       /* Read and check the pattern */
+       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+
+               value = *(uint32_t *) index;
+
+               if (value  != index) {
+                       return -1;
+               }
+       }
+
+       /* Write a pattern for complementary values */
+       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+               *(volatile uint32_t *) index = (uint32_t)~index;
+       }
+
+       /* Read and check the pattern */
+       for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+
+               value = *(uint32_t *) index;
+
+               if (value  != ~index) {
+                       return -1;
+               }
+       }
+
+       return 0;
+}
+
+#endif
+
index cda57677153ee2128707e3fedd1ae6701e2679de..bd4065143b0a301ebf329d5dfc7720e0001e5f43 100644 (file)
 #ifndef _TARGET_H
 #define _TARGET_H
 #include "types.h"
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
  
  
 /** 
@@ -401,5 +405,20 @@ Int32 targetMacRcv (void *ptr_device, UINT8 *buffer);
  */
 #define IBL_ENABLE_PCIE_WORKAROUND 1
 
+/**
+ *  @brief
+ *     DDR start and end address needed for DDR memory test 
+ */
+#define DDR3_TEST_START_ADDRESS 0x80000000
+#define DDR3_TEST_END_ADDRESS   (DDR3_TEST_START_ADDRESS + (128 *1024))
+
+/**
+ *  @brief
+ *     Software workaround for DDR3 memory corruption is to re-init the PLL's and DDR controller. This flag enables the workaround
+ */
+#define DDR3_TEST_ENABLE
+
+extern int32_t ddr3_memory_test();
+
 #endif /* _TARGET_H */
 
index 009331d0a2ef71dfc7180cc04003319d8c267f50..94f80d35827c88996121159a1feee48483c33e48 100644 (file)
@@ -64,7 +64,7 @@ else
        else
         ifeq ($(TARGET),c66x)
          CSRC= t64.c pll.c cfgpll.c cfgpll2.c mdio.c i2c.c psc.c cpsw.c qm.c cpdma.c pa.c sgmii.c serdes.c gmacsl.c emif4.c gpio.c
-         CSRC+= nandemif25.c nandgpio.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c evmc66x_uart.c
+         CSRC+= nandemif25.c nandgpio.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c c66x_uart.c
      else
       CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c sgmii.c cfgpll.c cfgpll2.c
          CSRC+= qm.c cpdma.c pa.c serdes.c gmacsl.c emif4.c nandemif25.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c
similarity index 99%
rename from src/hw/uart/c66x_uart/evmc66x_uart.c
rename to src/hw/uart/c66x_uart/c66x_uart.c
index 1f0472efb86f39772c961730495501d9a89aeed5..eb596f2b19a4d9b35cc1a4a6ca4d113dbf5b8347 100755 (executable)
@@ -31,7 +31,7 @@
  *
  *****************************************************************************/
 
-#include "evmc66x_uart.h"
+#include "c66x_uart.h"
 
 static void uart_delay_cycles(uint32_t cycles)
 {
similarity index 98%
rename from src/hw/uart/c66x_uart/evmc66x_uart.h
rename to src/hw/uart/c66x_uart/c66x_uart.h
index 6f8067a8e6a9bcb423eb0b9b7e5403850d09ad7f..e45515f81f54aadbe9c9a572e5801d849e13247e 100755 (executable)
@@ -33,7 +33,7 @@
 
 /******************************************************************************
  *
- * File    Name:    evmc66x_uart.h
+ * File    Name:    c66x_uart.h
  *
  * Description:    This contains UART specific structure, typedefs, function
  *        prototypes.
index 1d6a7b36d2422a644df55977ce402dc48cb94191..963d3973a81c9a315f961fdd10ec776560a02ce6 100644 (file)
@@ -14,7 +14,7 @@
 ../hw/c64x/make/pll.ENDIAN_TAG.oc
 ../hw/c64x/make/cfgpll.ENDIAN_TAG.oc
 ../hw/c64x/make/cfgpll2.ENDIAN_TAG.oc
-../hw/c64x/make/evmc66x_uart.ENDIAN_TAG.oc
+../hw/c64x/make/c66x_uart.ENDIAN_TAG.oc
 
 #ifndef EXCLUDE_BIS
 ../interp/c64x/make/bis.ENDIAN_TAG.oc
index 752799b9ec1398b0f4d680749b56abbb690ce964..d6a0245a6d6e1aa6f7e2238f6b68fb70f0d6040c 100755 (executable)
@@ -2,7 +2,7 @@
 export OS="Linux"
 
 if [ -z $C6X_CGT_VERSION ]; then
-    C6X_CGT_VERSION=7.2.1
+    C6X_CGT_VERSION=7.2.4
 fi
 
 if [ -z "$C6X_BASE_DIR" ]; then