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raw | patch | inline | side by side (parent: def313e)
raw | patch | inline | side by side (parent: def313e)
author | Sandeep Paulraj <s-paulraj@ti.com> | |
Thu, 21 Oct 2010 02:09:04 +0000 (22:09 -0400) | ||
committer | Sandeep Paulraj <s-paulraj@ti.com> | |
Thu, 21 Oct 2010 02:09:04 +0000 (22:09 -0400) |
This commit makes additions to the gel file for
all 3 devices supported so far.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
all 3 devices supported so far.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
src/util/i2cConfig/i2cConfig.gel | patch | blob | history |
index be8eaea1662eec30ceed5be4368abb12ec822740..eacfddd6fee48011eed65ed91417c980f068b498 100644 (file)
-#define TRUE 1
-#define FALSE 0
-
-#define ibl_MAGIC_VALUE 0xCEC11EBB
-
-#define ibl_HIGHEST_PRIORITY 1
-#define ibl_LOWEST_PRIORITY 10
-#define ibl_DEVICE_NOBOOT 20
-
-#define SETIP(array,i0,i1,i2,i3) array[0]=(i0); \
- array[1]=(i1); \
- array[2]=(i2); \
- array[3]=(i3)
-
-#define ibl_BOOT_FORMAT_AUTO 0
-#define ibl_BOOT_FORMAT_NAME 1
-#define ibl_BOOT_FORMAT_BIS 2
-#define ibl_BOOT_FORMAT_COFF 3
-#define ibl_BOOT_FORMAT_ELF 4
-#define ibl_BOOT_FORMAT_BBLOB 5
-#define ibl_BOOT_FORMAT_BTBL 6
-
-#define ibl_MAIN_PLL 0
-#define ibl_DDR_PLL 1
-#define ibl_NET_PLL 2
-
-
-menuitem "EVM c6472 IBL";
-
-hotmenu setConfig_c6472()
-{
- ibl.iblMagic = ibl_MAGIC_VALUE;
-
- ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
- ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
- ibl.pllConfig[ibl_MAIN_PLL].mult = 28;
- ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
- ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;
-
- /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
- ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
-
- /* The network PLL. The multipliers/dividers are fixed */
- ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
-
- /* EMIF configuration. The values are for DDR at 533 MHz */
- ibl.ddrConfig.configDdr = TRUE;
-
- ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */
- ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */
- ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */
- ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */
- ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
-
- /* Ethernet configuration for port 0 */
- ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
- ibl.ethConfig[0].port = 0;
-
- /* Bootp is disabled. The server and file name are provided here */
- ibl.ethConfig[0].doBootp = FALSE;
- ibl.ethConfig[0].useBootpServerIp = FALSE;
- ibl.ethConfig[0].useBootpFileName = FALSE;
- ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
-
-
- SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,35);
- SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);
- SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,1);
- SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
-
- /* Leave the hardware address as 0 so the e-fuse value will be used */
-
- strcpy (ibl.ethConfig[0].ethInfo.fileName, "test.blob");
-
- /* Even though the entire range of DDR2 is chosen, the load will
- * stop when the ftp reaches the end of the file */
- ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
- ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
-
- /* For port 1 use bootp */
- /* Ethernet configuration for port 0 */
- ibl.ethConfig[1].ethPriority = ibl_HIGHEST_PRIORITY + 1;
- ibl.ethConfig[1].port = 1;
-
- /* Bootp is disabled. The server and file name are provided here */
- ibl.ethConfig[1].doBootp = TRUE;
- ibl.ethConfig[1].useBootpServerIp = TRUE;
- ibl.ethConfig[1].useBootpFileName = TRUE;
- ibl.ethConfig[1].bootFormat = ibl_BOOT_FORMAT_BBLOB;
-
-
- /* SGMII not present */
- ibl.sgmiiConfig[0].adviseAbility = 0;
- ibl.sgmiiConfig[0].control = 0;
- ibl.sgmiiConfig[0].txConfig = 0;
- ibl.sgmiiConfig[0].rxConfig = 0;
- ibl.sgmiiConfig[0].auxConfig = 0;
-
- ibl.sgmiiConfig[1].adviseAbility = 0;
- ibl.sgmiiConfig[1].control = 0;
- ibl.sgmiiConfig[1].txConfig = 0;
- ibl.sgmiiConfig[1].rxConfig = 0;
- ibl.sgmiiConfig[1].auxConfig = 0;
-
-
- /* Leave the hardware address as 0 so the e-fuse value will be used */
- /* Leave all remaining fields as 0 since bootp will fill them in */
-
-
- /* Even though the entire range of DDR2 is chosen, the load will
- * stop when the ftp reaches the end of the file */
- ibl.ethConfig[1].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
- ibl.ethConfig[1].blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.ethConfig[1].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
-
-
-
- /* MDIO configuration */
- ibl.mdioConfig.nMdioOps = 8;
- ibl.mdioConfig.mdioClkDiv = 0x20;
- ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */
-
- ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;
- ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;
- ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;
- ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;
-
- ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;
- ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;
- ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;
- ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;
-
-
- /* Nand boot is disabled */
- ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
-
-}
-
-
-menuitem "EVM c6474 Mez IBL";
-
-hotmenu setConfig_c6474()
-{
- ibl.iblMagic = ibl_MAGIC_VALUE;
-
- ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
- ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
- ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
- ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
- ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
-
- /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
- ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
-
- /* The network PLL. The multipliers/dividers are fixed */
- ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
-
- /* EMIF configuration. The values are for DDR at 533 MHz */
- ibl.ddrConfig.configDdr = TRUE;
-
- ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
- ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
- ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
- ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
- ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
-
-
- /* Ethernet configuration for port 0 */
- ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
- ibl.ethConfig[0].port = 0;
-
- /* Bootp is disabled. The server and file name are provided here */
- ibl.ethConfig[0].doBootp = FALSE;
- ibl.ethConfig[0].useBootpServerIp = FALSE;
- ibl.ethConfig[0].useBootpFileName = FALSE;
- ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BLOB;
-
- SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,35);
- SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);
- SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,1);
- SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
-
- /* Set the hardware address as 0 so the e-fuse value will be used */
- ibl.ethConfig[0].hwAddress[0] = 0;
- ibl.ethConfig[0].hwAddress[1] = 0;
- ibl.ethConfig[0].hwAddress[2] = 0;
- ibl.ethConfig[0].hwAddress[3] = 0;
- ibl.ethConfig[0].hwAddress[4] = 0;
- ibl.ethConfig[0].hwAddress[5] = 0;
-
-
- ibl.ethConfig[0].ethInfo.fileName[0] = 't';
- ibl.ethConfig[0].ethInfo.fileName[1] = 'e';
- ibl.ethConfig[0].ethInfo.fileName[2] = 's';
- ibl.ethConfig[0].ethInfo.fileName[3] = 't';
- ibl.ethConfig[0].ethInfo.fileName[4] = '.';
- ibl.ethConfig[0].ethInfo.fileName[5] = 'b';
- ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
- ibl.ethConfig[0].ethInfo.fileName[7] = 'o';
- ibl.ethConfig[0].ethInfo.fileName[8] = 'b';
- ibl.ethConfig[0].ethInfo.fileName[9] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[10] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[11] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
-
-
- /* Even though the entire range of DDR2 is chosen, the load will
- * stop when the ftp reaches the end of the file */
- ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
- ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
-
- /* There is no port 1 on the 6474 */
- ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
-
-
- /* MDIO configuration */
- ibl.mdioConfig.nMdioOps = 8;
- ibl.mdioConfig.mdioClkDiv = 0x26;
- ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
-
- ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;
- ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;
- ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;
- ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;
-
- ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;
- ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
- ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;
- ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;
-
-
- /* Nand boot is disabled */
- ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
-
-}
-
-
-menuitem "EVM c6455 IBL";
-
-hotmenu setConfig_c6455()
-{
- ibl.iblMagic = ibl_MAGIC_VALUE;
-
- ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
- ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
- ibl.pllConfig[ibl_MAIN_PLL].mult = 20;
- ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
- ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
-
- /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
- ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
-
- /* The network PLL. The multipliers/dividers are fixed */
- ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
-
- /* EMIF configuration. The values are for DDR at 500 MHz */
- ibl.ddrConfig.configDdr = TRUE;
-
- ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */
- ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */
- ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */
- ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */
- ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
-
- /* Ethernet configuration for port 0 */
- ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;
- ibl.ethConfig[0].port = 0;
-
- /* Bootp is disabled. The server and file name are provided here */
- ibl.ethConfig[0].doBootp = FALSE;
- ibl.ethConfig[0].useBootpServerIp = FALSE;
- ibl.ethConfig[0].useBootpFileName = FALSE;
- ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;
-
-
- SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,35);
- SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196);
- SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,1);
- SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);
-
- /* There is no e-fuse mac address. A value must be assigned
- ibl.ethConfig[0].hwAddress[0] = 0x00;
- ibl.ethConfig[0].hwAddress[1] = 0xe0;
- ibl.ethConfig[0].hwAddress[2] = 0xa6;
- ibl.ethConfig[0].hwAddress[3] = 0x66;
- ibl.ethConfig[0].hwAddress[4] = 0x57;
- ibl.ethConfig[0].hwAddress[5] = 0x19;
-
-
- ibl.ethConfig[0].ethInfo.fileName[0] = 't';
- ibl.ethConfig[0].ethInfo.fileName[1] = 'e';
- ibl.ethConfig[0].ethInfo.fileName[2] = 's';
- ibl.ethConfig[0].ethInfo.fileName[3] = 't';
- ibl.ethConfig[0].ethInfo.fileName[4] = '.';
- ibl.ethConfig[0].ethInfo.fileName[5] = 'b';
- ibl.ethConfig[0].ethInfo.fileName[6] = 'l';
- ibl.ethConfig[0].ethInfo.fileName[7] = 'o';
- ibl.ethConfig[0].ethInfo.fileName[8] = 'b';
- ibl.ethConfig[0].ethInfo.fileName[9] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[10] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[11] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[12] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[13] = '\0';
- ibl.ethConfig[0].ethInfo.fileName[14] = '\0';
-
-
- /* Even though the entire range of DDR2 is chosen, the load will
- * stop when the ftp reaches the end of the file */
- ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */
- ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */
-
- /* There is no ethernet port 1 */
- ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
-
-
- /* SGMII not present */
- ibl.sgmiiConfig[0].adviseAbility = 0;
- ibl.sgmiiConfig[0].control = 0;
- ibl.sgmiiConfig[0].txConfig = 0;
- ibl.sgmiiConfig[0].rxConfig = 0;
- ibl.sgmiiConfig[0].auxConfig = 0;
-
- ibl.sgmiiConfig[1].adviseAbility = 0;
- ibl.sgmiiConfig[1].control = 0;
- ibl.sgmiiConfig[1].txConfig = 0;
- ibl.sgmiiConfig[1].rxConfig = 0;
- ibl.sgmiiConfig[1].auxConfig = 0;
-
-
-
- /* MDIO configuration */
- ibl.mdioConfig.nMdioOps = 0;
- ibl.mdioConfig.mdioClkDiv = 0x20;
- ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */
-
- ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;
-
-
- /* Nand boot is disabled */
- ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;
-
-}
-
-
+#define TRUE 1\r
+#define FALSE 0\r
+\r
+#define ibl_MAGIC_VALUE 0xCEC11EBB\r
+\r
+#define ibl_HIGHEST_PRIORITY 1 \r
+#define ibl_LOWEST_PRIORITY 10\r
+#define ibl_DEVICE_NOBOOT 20\r
+\r
+#define SETIP(array,i0,i1,i2,i3) array[0]=(i0); \\r
+ array[1]=(i1); \\r
+ array[2]=(i2); \\r
+ array[3]=(i3)\r
+\r
+#define ibl_BOOT_FORMAT_AUTO 0\r
+#define ibl_BOOT_FORMAT_NAME 1\r
+#define ibl_BOOT_FORMAT_BIS 2\r
+#define ibl_BOOT_FORMAT_COFF 3\r
+#define ibl_BOOT_FORMAT_ELF 4\r
+#define ibl_BOOT_FORMAT_BBLOB 5\r
+#define ibl_BOOT_FORMAT_BTBL 6\r
+\r
+#define ibl_MAIN_PLL 0\r
+#define ibl_DDR_PLL 1\r
+#define ibl_NET_PLL 2\r
+\r
+\r
+menuitem "EVM c6472 IBL";\r
+\r
+hotmenu setConfig_c6472()\r
+{\r
+ ibl.iblMagic = ibl_MAGIC_VALUE;\r
+\r
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 28;\r
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700;\r
+\r
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
+\r
+ /* The network PLL. The multipliers/dividers are fixed */\r
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
+\r
+ /* EMIF configuration. The values are for DDR at 533 MHz */\r
+ ibl.ddrConfig.configDdr = TRUE;\r
+\r
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */\r
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */ \r
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */\r
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */\r
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
+\r
+ /* Ethernet configuration for port 0 */\r
+ ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
+ ibl.ethConfig[0].port = 0;\r
+\r
+ /* Bootp is disabled. The server and file name are provided here */\r
+ ibl.ethConfig[0].doBootp = FALSE;\r
+ ibl.ethConfig[0].useBootpServerIp = FALSE;\r
+ ibl.ethConfig[0].useBootpFileName = FALSE;\r
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
+\r
+\r
+ SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,113);\r
+ SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);\r
+ SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
+ SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
+\r
+ /* Leave the hardware address as 0 so the e-fuse value will be used */\r
+\r
+\r
+\r
+\r
+ ibl.ethConfig[0].ethInfo.fileName[0] = 'c';\r
+ ibl.ethConfig[0].ethInfo.fileName[1] = '6';\r
+ ibl.ethConfig[0].ethInfo.fileName[2] = '4';\r
+ ibl.ethConfig[0].ethInfo.fileName[3] = '7';\r
+ ibl.ethConfig[0].ethInfo.fileName[4] = '2';\r
+ ibl.ethConfig[0].ethInfo.fileName[5] = '-';\r
+ ibl.ethConfig[0].ethInfo.fileName[6] = 'l';\r
+ ibl.ethConfig[0].ethInfo.fileName[7] = 'e';\r
+ ibl.ethConfig[0].ethInfo.fileName[8] = '.';\r
+ ibl.ethConfig[0].ethInfo.fileName[9] = 'b';\r
+ ibl.ethConfig[0].ethInfo.fileName[10] = 'i';\r
+ ibl.ethConfig[0].ethInfo.fileName[11] = 'n';\r
+ ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
+\r
+ /* Even though the entire range of DDR2 is chosen, the load will\r
+ * stop when the ftp reaches the end of the file */\r
+ ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */\r
+ ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
+ ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */\r
+\r
+ /* For port 1 use bootp */\r
+ /* Ethernet configuration for port 0 */\r
+ ibl.ethConfig[1].ethPriority = ibl_HIGHEST_PRIORITY + 1;\r
+ ibl.ethConfig[1].port = 1;\r
+\r
+ /* Bootp is disabled. The server and file name are provided here */\r
+ ibl.ethConfig[1].doBootp = TRUE;\r
+ ibl.ethConfig[1].useBootpServerIp = TRUE;\r
+ ibl.ethConfig[1].useBootpFileName = TRUE;\r
+ ibl.ethConfig[1].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
+\r
+\r
+ /* SGMII not present */\r
+ ibl.sgmiiConfig[0].adviseAbility = 0;\r
+ ibl.sgmiiConfig[0].control = 0;\r
+ ibl.sgmiiConfig[0].txConfig = 0;\r
+ ibl.sgmiiConfig[0].rxConfig = 0;\r
+ ibl.sgmiiConfig[0].auxConfig = 0;\r
+\r
+ ibl.sgmiiConfig[1].adviseAbility = 0;\r
+ ibl.sgmiiConfig[1].control = 0;\r
+ ibl.sgmiiConfig[1].txConfig = 0;\r
+ ibl.sgmiiConfig[1].rxConfig = 0;\r
+ ibl.sgmiiConfig[1].auxConfig = 0;\r
+\r
+\r
+ /* Leave the hardware address as 0 so the e-fuse value will be used */\r
+ ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
+\r
+\r
+ /* Leave all remaining fields as 0 since bootp will fill them in */\r
+\r
+\r
+ /* Even though the entire range of DDR2 is chosen, the load will */\r
+ /* stop when the ftp reaches the end of the file */\r
+ \r
+ ibl.ethConfig[1].blob.startAddress = 0xe0000000; /* Base address of DDR2 */\r
+ ibl.ethConfig[1].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
+ ibl.ethConfig[1].blob.branchAddress = 0xe0000000; /* Base of DDR2 */\r
+ \r
+\r
+\r
+ /* MDIO configuration */\r
+ ibl.mdioConfig.nMdioOps = 8;\r
+ ibl.mdioConfig.mdioClkDiv = 0x20;\r
+ ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */\r
+\r
+ ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;\r
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;\r
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;\r
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;\r
+\r
+ ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;\r
+ ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;\r
+ ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;\r
+ ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;\r
+\r
+\r
+ /* Nand boot is disabled */\r
+ ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
+\r
+}\r
+\r
+\r
+menuitem "EVM c6474 Mez IBL";\r
+\r
+hotmenu setConfig_c6474()\r
+{\r
+ ibl.iblMagic = ibl_MAGIC_VALUE;\r
+\r
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;\r
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
+\r
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
+\r
+ /* The network PLL. The multipliers/dividers are fixed */\r
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
+\r
+ /* EMIF configuration. The values are for DDR at 533 MHz */\r
+ ibl.ddrConfig.configDdr = TRUE;\r
+\r
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */\r
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */ \r
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */\r
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */\r
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */\r
+\r
+\r
+ /* Ethernet configuration for port 0 */\r
+ ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
+ ibl.ethConfig[0].port = 0;\r
+\r
+ /* Bootp is disabled. The server and file name are provided here */\r
+ ibl.ethConfig[0].doBootp = FALSE;\r
+ ibl.ethConfig[0].useBootpServerIp = FALSE;\r
+ ibl.ethConfig[0].useBootpFileName = FALSE;\r
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
+\r
+ SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,114);\r
+ SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);\r
+ SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
+ SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
+\r
+ /* Set the hardware address as 0 so the e-fuse value will be used */\r
+ ibl.ethConfig[0].ethInfo.hwAddress[0] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[1] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[2] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[3] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[4] = 0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[5] = 0;\r
+\r
+\r
+ ibl.ethConfig[0].ethInfo.fileName[0] = 'c';\r
+ ibl.ethConfig[0].ethInfo.fileName[1] = '6';\r
+ ibl.ethConfig[0].ethInfo.fileName[2] = '4';\r
+ ibl.ethConfig[0].ethInfo.fileName[3] = '7';\r
+ ibl.ethConfig[0].ethInfo.fileName[4] = '4';\r
+ ibl.ethConfig[0].ethInfo.fileName[5] = '-';\r
+ ibl.ethConfig[0].ethInfo.fileName[6] = 'l';\r
+ ibl.ethConfig[0].ethInfo.fileName[7] = 'e';\r
+ ibl.ethConfig[0].ethInfo.fileName[8] = '.';\r
+ ibl.ethConfig[0].ethInfo.fileName[9] = 'b';\r
+ ibl.ethConfig[0].ethInfo.fileName[10] = 'i';\r
+ ibl.ethConfig[0].ethInfo.fileName[11] = 'n';\r
+ ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
+\r
+\r
+ /* Even though the entire range of DDR2 is chosen, the load will\r
+ * stop when the ftp reaches the end of the file */\r
+ ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */\r
+ ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
+ ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */\r
+\r
+ /* There is no port 1 on the 6474 */\r
+ ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;\r
+\r
+ /* SGMII is present */\r
+ ibl.sgmiiConfig[0].adviseAbility = 0;\r
+ ibl.sgmiiConfig[0].control = 0;\r
+ ibl.sgmiiConfig[0].txConfig = 0;\r
+ ibl.sgmiiConfig[0].rxConfig = 0;\r
+ ibl.sgmiiConfig[0].auxConfig = 0;\r
+\r
+ /* MDIO configuration */\r
+ ibl.mdioConfig.nMdioOps = 8;\r
+ ibl.mdioConfig.mdioClkDiv = 0x26;\r
+ ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */\r
+\r
+ ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081;\r
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047;\r
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047;\r
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140;\r
+\r
+ ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140;\r
+ ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
+ ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e;\r
+ ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100;\r
+\r
+\r
+ /* Nand boot is disabled */\r
+ ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
+\r
+}\r
+\r
+\r
+menuitem "EVM c6455 IBL";\r
+\r
+hotmenu setConfig_c6455()\r
+{\r
+ ibl.iblMagic = ibl_MAGIC_VALUE;\r
+\r
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;\r
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;\r
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 20;\r
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;\r
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;\r
+\r
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */\r
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;\r
+\r
+ /* The network PLL. The multipliers/dividers are fixed */\r
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;\r
+\r
+ /* EMIF configuration. The values are for DDR at 500 MHz */\r
+ ibl.ddrConfig.configDdr = TRUE;\r
+\r
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */\r
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */ \r
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */\r
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */\r
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */\r
+\r
+ /* Ethernet configuration for port 0 */\r
+ ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY;\r
+ ibl.ethConfig[0].port = 0;\r
+\r
+ /* Bootp is disabled. The server and file name are provided here */\r
+ ibl.ethConfig[0].doBootp = FALSE;\r
+ ibl.ethConfig[0].useBootpServerIp = FALSE;\r
+ ibl.ethConfig[0].useBootpFileName = FALSE;\r
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB;\r
+\r
+\r
+ SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,118);\r
+ SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25);\r
+ SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2);\r
+ SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0);\r
+\r
+ /* There is no e-fuse mac address. A value must be assigned\r
+ ibl.ethConfig[0].ethInfo.hwAddress[0] = 0x00;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[1] = 0xe0;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[2] = 0xa6;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[3] = 0x66;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[4] = 0x57;\r
+ ibl.ethConfig[0].ethInfo.hwAddress[5] = 0x19;\r
+\r
+\r
+ ibl.ethConfig[0].ethInfo.fileName[0] = 't';\r
+ ibl.ethConfig[0].ethInfo.fileName[1] = 'e';\r
+ ibl.ethConfig[0].ethInfo.fileName[2] = 's';\r
+ ibl.ethConfig[0].ethInfo.fileName[3] = 't';\r
+ ibl.ethConfig[0].ethInfo.fileName[4] = '.';\r
+ ibl.ethConfig[0].ethInfo.fileName[5] = 'b';\r
+ ibl.ethConfig[0].ethInfo.fileName[6] = 'l';\r
+ ibl.ethConfig[0].ethInfo.fileName[7] = 'o';\r
+ ibl.ethConfig[0].ethInfo.fileName[8] = 'b';\r
+ ibl.ethConfig[0].ethInfo.fileName[9] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[10] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[11] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[12] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[13] = '\0';\r
+ ibl.ethConfig[0].ethInfo.fileName[14] = '\0';\r
+\r
+\r
+ /* Even though the entire range of DDR2 is chosen, the load will\r
+ * stop when the ftp reaches the end of the file */\r
+ ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */\r
+ ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */\r
+ ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */\r
+\r
+ /* There is no ethernet port 1 */\r
+ ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;\r
+\r
+\r
+ /* SGMII not present */\r
+ ibl.sgmiiConfig[0].adviseAbility = 0;\r
+ ibl.sgmiiConfig[0].control = 0;\r
+ ibl.sgmiiConfig[0].txConfig = 0;\r
+ ibl.sgmiiConfig[0].rxConfig = 0;\r
+ ibl.sgmiiConfig[0].auxConfig = 0;\r
+\r
+ ibl.sgmiiConfig[1].adviseAbility = 0;\r
+ ibl.sgmiiConfig[1].control = 0;\r
+ ibl.sgmiiConfig[1].txConfig = 0;\r
+ ibl.sgmiiConfig[1].rxConfig = 0;\r
+ ibl.sgmiiConfig[1].auxConfig = 0;\r
+\r
+\r
+\r
+ /* MDIO configuration */\r
+ ibl.mdioConfig.nMdioOps = 0;\r
+ ibl.mdioConfig.mdioClkDiv = 0x20;\r
+ ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */\r
+\r
+ ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0;\r
+\r
+\r
+ /* Nand boot is disabled */\r
+ ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT;\r
+\r
+}\r
+\r
+\r