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raw | patch | inline | side by side (parent: 04d72ed)
raw | patch | inline | side by side (parent: 04d72ed)
author | Mike Line <m-line1@ti.com> | |
Thu, 14 Oct 2010 19:49:20 +0000 (15:49 -0400) | ||
committer | Mike Line <m-line1@ti.com> | |
Thu, 14 Oct 2010 19:49:20 +0000 (15:49 -0400) |
Signed-off-by: Mike Line <m-line1@ti.com>
19 files changed:
src/cfg/c6472/iblcfg.h | patch | blob | history | |
src/cfg/c6474/iblcfg.h | [new file with mode: 0644] | patch | blob |
src/device/c6472/target.h | patch | blob | history | |
src/device/c6474/c6474.c | [new file with mode: 0644] | patch | blob |
src/device/c6474/target.h | [new file with mode: 0644] | patch | blob |
src/device/c64x/make/makefile | patch | blob | history | |
src/driver/eth/net.h | patch | blob | history | |
src/ethboot/c64x/make/makefile | patch | blob | history | |
src/ethboot/ethboot.c | patch | blob | history | |
src/hw/c64x/make/makefile | patch | blob | history | |
src/hw/macs/cpmac/cpmacdrv.c | patch | blob | history | |
src/hw/sgmii/sgmii.c | [new file with mode: 0644] | patch | blob |
src/hw/sgmii/sgmii.h | [new file with mode: 0644] | patch | blob |
src/ibl.h | patch | blob | history | |
src/main/iblmain.c | patch | blob | history | |
src/make/Makefile | patch | blob | history | |
src/make/c64x/makedefs.mk | patch | blob | history | |
src/make/ibl_c6474/ibl.cmd | [new file with mode: 0644] | patch | blob |
src/make/makestg2 | patch | blob | history |
diff --git a/src/cfg/c6472/iblcfg.h b/src/cfg/c6472/iblcfg.h
index d0f8e7c7b6eea7a1732b92ffbf381444ad03edbd..6fd37b40d152856f15339fa7a85d4040c98bed39 100644 (file)
--- a/src/cfg/c6472/iblcfg.h
+++ b/src/cfg/c6472/iblcfg.h
#define IBL_I2C_CFG_ADDR_DELAY 0x100 /* Delay between sending the address and reading data */
#ifndef IBL_I2C_CFG_EEPROM_BUS_ADDR
- #error hello
#define IBL_I2C_CFG_EEPROM_BUS_ADDR 0x50
#endif
diff --git a/src/cfg/c6474/iblcfg.h b/src/cfg/c6474/iblcfg.h
--- /dev/null
+++ b/src/cfg/c6474/iblcfg.h
@@ -0,0 +1,66 @@
+/**************************************************************************
+ * FILE PURPOSE: Provide build time configurations for the IBL
+ **************************************************************************
+ * FILE NAME: iblcfg.h
+ *
+ * DESCRIPTION: Build time configuration
+ *
+ * @file iblcfg.h
+ *
+ * @brief
+ * Build time configurations for the c6474 ibl are defined
+ *
+ ***************************************************************************/
+#ifndef IBLCFG_H
+#define IBLCFG_H
+
+/**
+ * @brief The maximum number of UDP sockets in the system
+ */
+#define MAX_UDP_SOCKET 3
+
+
+/**
+ * @brief The maximum number of timers in the system
+ */
+#define MAX_TIMER_BLOCKS 5
+
+
+/**
+ * @brief The size in bytes of the internal stream buffer
+ */
+#define MAX_SIZE_STREAM_BUFFER 1024
+
+
+/**
+ * @brief The maximum number of functions supported for BIS mode
+ */
+#define MAX_BIS_FUNCTION_SUPPORT 3
+
+
+/**
+ * @brief No I/O sections accepted in boot table format
+ */
+#define BOOTCONFIG_NO_BTBL_IO
+
+/**
+ * @brief The I2C bus address and data address of the ibl table.
+ */
+#define IBL_I2C_DEV_FREQ_MHZ 1000
+#define IBL_I2C_CLK_FREQ_KHZ 100
+#define IBL_I2C_OWN_ADDR 10
+#define IBL_I2C_CFG_ADDR_DELAY 0x100 /* Delay between sending the address and reading data */
+
+#ifndef IBL_I2C_CFG_EEPROM_BUS_ADDR
+ #define IBL_I2C_CFG_EEPROM_BUS_ADDR 0x50
+#endif
+
+#define IBL_I2C_CFG_TABLE_DATA_ADDR (0x10000 - 0x300)
+
+
+
+
+
+#endif
+
+
index bf00acf6fb96d875e4908cbbcfd24b1fde44ee5d..84eb30d01468c97bce23fc7f782c62004af6a854 100644 (file)
/* Leave mdio disabled */
#define dev_mdio_open() 1
+/* The mac control register values used */
+#define TARGET_MAC_CONTROL CPMAC_MACCONTROL_RXOWNERSHIP | \
+ CPMAC_MACCONTROL_RXOFFLENBLOCK | \
+ CPMAC_MACCONTROL_MIIEN
+
+/* There is no sgmii on the 6472, so the sgmii config is defined to a void statement */
+#define hwSgmiiConfig(x,y)
+
+
/**
* @brief
diff --git a/src/device/c6474/c6474.c b/src/device/c6474/c6474.c
--- /dev/null
+++ b/src/device/c6474/c6474.c
@@ -0,0 +1,293 @@
+/************************************************************************************
+ * FILE PURPOSE: C6474 Device Specific functions
+ ************************************************************************************
+ * FILE NAME: c6474.c
+ *
+ * DESCRIPTION: Implements the device specific functions for the IBL
+ *
+ * @file c6474.c
+ *
+ * @brief
+ * This file implements the device specific functions for the IBL
+ *
+ ************************************************************************************/
+#include "ibl.h"
+#include "device.h"
+#include "pllapi.h"
+#include "emif31api.h"
+#include "pscapi.h"
+#include "gpio.h"
+#include <string.h>
+
+extern cregister unsigned int DNUM;
+
+
+/**
+ * @brief The default boot configuration table is filled in
+ *
+ * @details
+ * A default ibl configuraiton table is provided when one is not found
+ * preloaded.
+ */
+void deviceLoadDefaultIblTable (void)
+{
+ uint32 macA, macB;
+
+#if 0 /* This is really the default. Switching to a direct tftp boot until I have a bootp server
+ * on a private lan for test */
+ ibl.ethConfig[0].ethPriority = ibl_LOWEST_PRIORITY;
+ ibl.ethConfig[0].port = 0;
+ ibl.ethConfig[0].doBootp = TRUE;
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_AUTO;
+
+ memset (&ibl.ethConfig[0].ethInfo, 0, sizeof(ibl.ethConfig[0].ethInfo));
+#endif
+
+ /* This is the temporary code */
+ ibl.ethConfig[0].ethPriority = ibl_LOWEST_PRIORITY;
+ ibl.ethConfig[0].port = 0;
+ ibl.ethConfig[0].doBootp = FALSE;
+ ibl.ethConfig[0].useBootpServerIp = FALSE;
+ ibl.ethConfig[0].useBootpFileName = FALSE;
+ ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_NAME;
+
+ memset (&ibl.ethConfig[0].ethInfo, 0, sizeof(ibl.ethConfig[0].ethInfo));
+
+ ibl.ethConfig[0].ethInfo.ipAddr[0] = 10;
+ ibl.ethConfig[0].ethInfo.ipAddr[1] = 218;
+ ibl.ethConfig[0].ethInfo.ipAddr[2] = 109;
+ ibl.ethConfig[0].ethInfo.ipAddr[3] = 21;
+
+ ibl.ethConfig[0].ethInfo.serverIp[0] = 10;
+ ibl.ethConfig[0].ethInfo.serverIp[1] = 218;
+ ibl.ethConfig[0].ethInfo.serverIp[2] = 109;
+ ibl.ethConfig[0].ethInfo.serverIp[3] = 196;
+
+ ibl.ethConfig[0].ethInfo.gatewayIp[0] = 10;
+ ibl.ethConfig[0].ethInfo.gatewayIp[1] = 218;
+ ibl.ethConfig[0].ethInfo.gatewayIp[2] = 109;
+ ibl.ethConfig[0].ethInfo.gatewayIp[3] = 1;
+
+ /* Leave hw address as 0 */
+
+ strcpy (ibl.ethConfig[0].ethInfo.fileName, "test2_little.out");
+
+ ibl.ethConfig[0].blob.startAddress = 0x00200000; /* Base address of SL2 */
+ ibl.ethConfig[0].blob.sizeBytes = 0x000c0000; /* All of SL2 */
+ ibl.ethConfig[0].blob.branchAddress = 0x00200000; /* Base of SL2 */
+
+
+
+ macA = *((uint32 *)0x2a80700);
+ macB = *((uint32 *)0x2a80704);
+
+ ibl.ethConfig[0].ethInfo.hwAddress[0] = (macA >> 24) & 0xff;
+ ibl.ethConfig[0].ethInfo.hwAddress[1] = (macA >> 16) & 0xff;
+ ibl.ethConfig[0].ethInfo.hwAddress[2] = (macA >> 8) & 0xff;
+ ibl.ethConfig[0].ethInfo.hwAddress[3] = (macA >> 0) & 0xff;
+ ibl.ethConfig[0].ethInfo.hwAddress[4] = (macB >> 24) & 0xff;
+ ibl.ethConfig[0].ethInfo.hwAddress[5] = (macB >> 16) & 0xff;
+
+
+ ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT;
+
+
+ /* MDIO configuration */
+ ibl.mdioConfig.nMdioOps = 8;
+ ibl.mdioConfig.mdioClkDiv = 0x20;
+ ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */
+
+ ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b;
+ ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0;
+ ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101;
+ ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140;
+
+ ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b;
+ ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0;
+ ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101;
+ ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140;
+
+
+ /* Main Pll configuration */
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 28;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1;
+
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 500;
+
+ /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE;
+
+ /* The network PLL. The multipliers/dividers are fixed */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE;
+
+ /* EMIF configuration */
+ ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */
+ ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */
+ ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
+
+
+ /* NAND configuration for the MT29F1G08 flash */
+ ibl.nandConfig.nandPriority = ibl_HIGHEST_PRIORITY;
+ ibl.nandConfig.bootFormat = ibl_BOOT_FORMAT_COFF;
+
+ ibl.nandConfig.nandInfo.busWidthBits = 8;
+ ibl.nandConfig.nandInfo.pageSizeBytes = 2048;
+ ibl.nandConfig.nandInfo.pageEccBytes = 64;
+ ibl.nandConfig.nandInfo.pagesPerBlock = 64;
+ ibl.nandConfig.nandInfo.totalBlocks = 1024;
+
+ ibl.nandConfig.nandInfo.addressBytes = 4;
+ ibl.nandConfig.nandInfo.lsbFirst = TRUE;
+ ibl.nandConfig.nandInfo.blockOffset = 22;
+ ibl.nandConfig.nandInfo.pageOffset = 16;
+ ibl.nandConfig.nandInfo.columnOffset = 0;
+
+ ibl.nandConfig.nandInfo.resetCommand = 0xff;
+ ibl.nandConfig.nandInfo.readCommandPre = 0;
+ ibl.nandConfig.nandInfo.readCommandPost = 0x30;
+ ibl.nandConfig.nandInfo.postCommand = TRUE;
+
+
+}
+
+/**
+ * @brief Determine if an address is local
+ *
+ * @details
+ * Examines an input address to determine if it is a local address
+ */
+bool address_is_local (Uint32 addr)
+{
+ /* L2 */
+ if ((addr >= 0x00800000) && (addr < 0x00898000))
+ return (TRUE);
+
+ /* L1P */
+ if ((addr >= 0x00e00000) && (addr < 0x00e08000))
+ return (TRUE);
+
+ /* L2D */
+ if ((addr >= 0x00f00000) && (addr < 0x00f08000))
+ return (TRUE);
+
+ return (FALSE);
+
+}
+
+
+/**
+ * @brief Convert a local l1d, l1p or l2 address to a global address
+ *
+ * @details
+ * The global address is formed. If the address is not local then
+ * the input address is returned
+ */
+Uint32 deviceLocalAddrToGlobal (Uint32 addr)
+{
+
+ if (address_is_local (addr))
+ addr = (1 << 28) | (DNUM << 24) | addr;
+
+ return (addr);
+
+}
+
+
+/**
+ * @brief Configure the PLLs
+ *
+ * @details
+ * Only the main PLL can be configured here. The DDR pll is enabled by default,
+ * and the network PLL is enabled through serdes configuration.
+ * the multiplier and dividers.
+ */
+void devicePllConfig (void)
+{
+ if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
+ hwPllSetPll (MAIN_PLL,
+ ibl.pllConfig[ibl_MAIN_PLL].prediv,
+ ibl.pllConfig[ibl_MAIN_PLL].mult,
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv);
+
+}
+
+/**
+ * @brief
+ * Enable the DDR
+ *
+ * @details
+ * The DDR controller on the c6474 is an emif 3.1. The controller is
+ * initialized directly with the supplied values
+ */
+void deviceDdrConfig (void)
+{
+ if (ibl.ddrConfig.configDdr != 0)
+ hwEmif3p1Enable (&ibl.ddrConfig.uEmif.emif3p1);
+
+}
+
+
+/**
+ * @brief Power up a peripheral
+ *
+ * @details
+ * Boot peripherals are powered up
+ */
+int32 devicePowerPeriph (int32 modNum)
+{
+ /* If the input value is < 0 there is nothing to power up */
+ if (modNum < 0)
+ return (0);
+
+
+ if (modNum >= TARGET_PWR_MAX_MOD)
+ return (-1);
+
+ return ((int32)pscEnableModule(modNum));
+
+}
+
+
+/**
+ * @brief Enable the pass through version of the nand controller
+ *
+ * @details On the evm the nand controller is enabled by setting
+ * gpio 14 high
+ */
+int32 deviceConfigureForNand(void)
+{
+ hwGpioSetDirection(NAND_MODE_GPIO, GPIO_OUT);
+ hwGpioSetOutput(NAND_MODE_GPIO);
+ return (0);
+
+}
+
+
+/**
+ * @brief
+ * The e-fuse mac address is loaded
+ */
+void deviceLoadDefaultEthAddress (uint8 *maddr)
+{
+ uint32 macA, macB;
+
+ /* Read the e-fuse mac address */
+ macA = *((uint32 *)0x2880834);
+ macB = *((uint32 *)0x2880834);
+
+ maddr[0] = (macA >> 24) & 0xff;
+ maddr[1] = (macA >> 16) & 0xff;
+ maddr[2] = (macA >> 8) & 0xff;
+ maddr[3] = (macA >> 0) & 0xff;
+ maddr[4] = (macB >> 24) & 0xff;
+ maddr[5] = (macB >> 16) & 0xff;
+}
+
+
+
+
+
diff --git a/src/device/c6474/target.h b/src/device/c6474/target.h
--- /dev/null
@@ -0,0 +1,158 @@
+/**************************************************************************
+ * FILE PURPOSE: Target specific definitions
+ **************************************************************************
+ * FILE NAME: target.h
+ *
+ * DESCRIPTION: This file defines target specific values used by low level
+ * drivers.
+ *
+ * @file target.h
+ *
+ * @brief
+ * Low level target specific values are defined
+ *
+ ***************************************************************************/
+
+
+/**
+ * @brief
+ * Device EMAC definitions
+ */
+#define TARGET_DEVICE_CPMAC
+
+#define TARGET_EMAC_N_PORTS 1
+
+#define TARGET_EMAC_BASE_ADDRESSES { 0x02c80000u }
+#define TARGET_EMAC_DSC_BASE_ADDR { 0x02c82000u }
+
+#define TARGET_SGMII_BASE_ADDRESSES { 0x02c40000u }
+
+/* SGMII offsets (at least the serdes configs, vary between devices, so
+ * they are defined here. */
+#define TARGET_SGMII_IDVER 0x000
+#define TARGET_SGMII_SOFT_RESET 0x004
+#define TARGET_SGMII_CONTROL 0x010
+#define TARGET_SGMII_STATUS 0x014
+#define TARGET_SGMII_MR_ADV_ABILITY 0x018
+#define TARGET_SGMII_MR_LP_ADV_ABILITY 0x020
+#define TARGET_SGMII_TX_CFG 0x030
+#define TARGET_SGMII_RX_CFG 0x034
+#define TARGET_SGMII_AUX_CFG 0x038
+
+/* Leave mdio disabled */
+#define dev_mdio_open() 1
+
+
+/* The mac control register values */
+#define TARGET_MAC_CONTROL ( 1 << 18) /* EXT_EN */ \
+ | ( 0 << 9 ) /* Round robin */ \
+ | ( 1 << 7 ) /* GIG */ \
+ | ( 0 << 6 ) /* TX pacing disabled */ \
+ | ( 1 << 5 ) /* GMII RX & TX */ \
+ | ( 0 << 4 ) /* TX flow disabled */ \
+ | ( 0 << 3 ) /* RX flow disabled */ \
+ | ( 0 << 1 ) /* Loopback enabled */ \
+ | ( 1 << 0 ) /* full duplex */
+
+
+/**
+ * @brief
+ * Device Timer definitions
+ */
+#define TIMER0_BASE 0x02910000u
+
+#define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
+
+
+/**
+ * @def MAIN_PLL
+ */
+#define MAIN_PLL 0 /**< The index to the main PLL */
+
+
+/**
+ * @brief
+ * Device PLL definitions
+ */
+#define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x29a0000 : 0)
+
+
+/**
+ * @brief
+ * Device PSC definitions
+ */
+#define DEVICE_PSC_BASE 0x02ac0000u
+
+/**
+ * @brief
+ * The ethernet is in the always on domain */
+#define TARGET_PWR_ETH(x) -1
+
+/**
+ * @brief
+ * The nand is done through gpio, which is always powered up.
+ * A value < 0 tells the low level psc driver to simply return success
+ */
+#define TARGET_PWR_NAND -1
+
+
+/**
+ * @brief
+ * Device DDR controller definitions
+ */
+#define DEVICE_DDR_BASE 0x70000000
+
+/**
+ * @brief
+ * The highest module number
+ */
+#define TARGET_PWR_MAX_MOD 5
+
+
+/**
+ * @brief
+ * The base address of MDIO
+ */
+#define TARGET_MDIO_BASE 0x2c81800
+
+/**
+ * @brief
+ * GPIO address
+ */
+#define GPIO_GPIOPID_REG 0x02B00000
+#define GPIO_GPIOEMU_REG 0x02B00004
+#define GPIO_BINTEN_REG 0x02B00008
+#define GPIO_DIR_REG 0x02B00010
+#define GPIO_OUT_DATA_REG 0x02B00014
+#define GPIO_SET_DATA_REG 0x02B00018
+#define GPIO_CLEAR_DATA_REG 0x02B0001C
+#define GPIO_IN_DATA_REG 0x02B00020
+#define GPIO_SET_RIS_TRIG_REG 0x02B00024
+#define GPIO_CLR_RIS_TRIG_REG 0x02B00028
+#define GPIO_SET_FAL_TRIG_REG 0x02B0002C
+#define GPIO_CLR_FAL_TRIG_REG 0x02B00030
+
+/**
+ * @brief
+ * GPIO pin mapping
+ */
+#define NAND_CLE_GPIO_PIN GPIO_8 // High: Command Cycle occuring
+#define NAND_ALE_GPIO_PIN GPIO_9 // High: Address input cycle oddcuring
+#define NAND_NWE_GPIO_PIN GPIO_10
+#define NAND_NRE_GPIO_PIN GPIO_12
+#define NAND_NCE_GPIO_PIN GPIO_13
+#define NAND_MODE_GPIO GPIO_14
+
+/**
+ * @brief
+ * The standard NAND delay must be big enough to handle the highest possible
+ * operating frequency of the device */
+#define TARGET_NAND_STD_DELAY 25 // In cpu cycles
+
+/**
+ * @brief
+ * The base address of the I2C peripheral, and the module divisor of the cpu clock
+ */
+#define DEVICE_I2C_BASE 0x02b04000
+#define DEVICE_I2C_MODULE_DIVISOR 6
+
index 5dfd801bb11a7bb0ed615b07bc53a377a38d167d..ffcf4ac5f59d301d2f2deb1730ba5fda546c455b 100644 (file)
ifeq ($(TARGET),c6455)
CSRC= c6455.c
else
- CSRC= c6472.c c6455.c
+ ifeq ($(TARGET),c6474)
+ CSRC= c6474.c
+ else
+ CSRC= c6472.c c6455.c c6474.c
+ endif
endif
endif
diff --git a/src/driver/eth/net.h b/src/driver/eth/net.h
index 28e1e12b39e85cf32bdaacf3da96768480e26b71..9d40e2202a50a2216065320a44d607582c6095cc 100644 (file)
--- a/src/driver/eth/net.h
+++ b/src/driver/eth/net.h
* has been received then the function returns 0
*/
Int32 (*receive) (struct NET_DRV_DEVICE* ptr_device, Uint8* buffer);
+
}NET_DRV_DEVICE;
/**
index 2e27527350000ea62e2ca2b1a24cd532fe5d8dee..895d51a9147efbca6ac1fddabc642bfee2a8601d 100644 (file)
C6X_C_DIR+= ;$(STDINC)
C6X_C_DIR+= ;$(IBL_ROOT)/hw/macs
C6X_C_DIR+= ;$(IBL_ROOT)/hw/mdio
+C6X_C_DIR+= ;$(IBL_ROOT)/hw/sgmii
export C6X_C_DIR
diff --git a/src/ethboot/ethboot.c b/src/ethboot/ethboot.c
index 07b8c3c65f8ae801995a90d3a9e52aeb6d6e235b..090c9b6db7e7aa39191795702ac51c9a6a1ebab0 100644 (file)
--- a/src/ethboot/ethboot.c
+++ b/src/ethboot/ethboot.c
#include "ethboot.h"
#include "net.h"
#include "cpmacdrv.h"
+#include "sgmii.h"
#include "device.h"
#include "mdioapi.h"
#include <string.h>
ibl.mdioConfig.mdioClkDiv, ibl.mdioConfig.interDelay);
+ /* SGMII configuration. If sgmii is not present this statement is defined
+ * to void in target.h */
+ hwSgmiiConfig (ibl.ethConfig[eIdx].port, &ibl.sgmiiConfig[eIdx]);
+
+
nDevice.port_num = ibl.ethConfig[eIdx].port;
/* Simple transation to initialize the driver */
index a09110b1170ca9b8e8d868740bd7c44a7f3afcc5..993aea62e00659bd0a6292fbaee2eebc65812595 100644 (file)
ifeq ($(TARGET),c6472)
CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c
else
- CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c
+ ifeq ($(TARGET),c6474)
+ CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c sgmii.c
+ else
+ CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c nandwrgpio.c sgmii.c
+ endif
endif
CDEFS += -DIBL_I2C_CFG_EEPROM_BUS_ADDR=$(I2C_PARAM_BUS_ADDR)
C6X_C_DIR+= ;$(IBL_ROOT)/hw/nands
C6X_C_DIR+= ;$(IBL_ROOT)/hw/nands/gpio
C6X_C_DIR+= ;$(IBL_ROOT)/hw/i2c
+C6X_C_DIR+= ;$(IBL_ROOT)/hw/sgmii
C6X_C_DIR+= ;$(IBL_ROOT)/ecc
export C6X_C_DIR
vpath % $(ECODIR)/i2c
endif
+ifeq ($(TARGET),c6474)
+ vpath % $(ECODIR)/macs/cpmac
+ vpath % $(ECODIR)/plls/pllxx1p8
+ vpath % $(ECODIR)/pscs/psc2
+ vpath % $(ECODIR)/ddrs/emif31
+ vpath % $(ECODIR)/mdio
+ vpath % $(ECODIR)/gpio
+ vpath % $(ECODIR)/nands/gpio
+ vpath % $(ECODIR)/i2c
+ vpath % $(ECODIR)/sgmii
+endif
+
hw: gen_cdefdep makefile $(OBJS)
index 939d9cbd1e3b809a29c71bcf9ac702b127d48387..d35f37ffd8e499af37ddf08dd58c98a03d6be57d 100644 (file)
if (ptr_device->port_num >= TARGET_EMAC_N_PORTS)
return (-1);
+
ptr_EMACRegs = (CPMAC_REGS *)(aptr_EMACRegs[ptr_device->port_num]);
pDesc = (EMAC_Desc *)(aptr_EmacDesc[ptr_device->port_num]);
/* Initialize the MAC Control: We set the Receive Ownership Bit and the Receive
* Offset Length Word and enable the MII. */
- ptr_EMACRegs->MACCONTROL = CPMAC_MACCONTROL_RXOWNERSHIP |
- CPMAC_MACCONTROL_RXOFFLENBLOCK |
- CPMAC_MACCONTROL_MIIEN;
+ ptr_EMACRegs->MACCONTROL = TARGET_MAC_CONTROL;
/* Startup RX */
ptr_EMACRegs->RX0HDP = (Uint32)emacMCB.rx_bd;
diff --git a/src/hw/sgmii/sgmii.c b/src/hw/sgmii/sgmii.c
--- /dev/null
+++ b/src/hw/sgmii/sgmii.c
@@ -0,0 +1,61 @@
+/**
+ * @file sgmii.c
+ *
+ * @brief
+ * The sgmii driver for the ibl
+ *
+ */
+
+#include "types.h"
+#include "ibl.h"
+#include "sgmii.h"
+#include "target.h"
+
+#define SGMII_ACCESS(port,reg) *((volatile unsigned int *)(sgmiis[port] + reg))
+
+/**
+ * @brief
+ * Configure the sgmii
+ */
+int32 hwSgmiiConfig (int32 port, iblSgmii_t *iblSgmii)
+{
+ unsigned int sgmiis[] = TARGET_SGMII_BASE_ADDRESSES;
+ int32 v;
+
+ if (port >= TARGET_EMAC_N_PORTS)
+ return (-1);
+
+
+ SGMII_ACCESS(port, TARGET_SGMII_SOFT_RESET) = 1;
+
+ do {
+
+ v = SGMII_ACCESS(port, TARGET_SGMII_SOFT_RESET);
+
+ } while (v & 1);
+
+ /* Bit 1 holds tx/rx in reset. Used during loopback state change in
+ * the control register */
+ SGMII_ACCESS(port, TARGET_SGMII_SOFT_RESET) = 2;
+
+
+ SGMII_ACCESS(port, TARGET_SGMII_CONTROL) = iblSgmii->control;
+ SGMII_ACCESS(port, TARGET_SGMII_SOFT_RESET) = 0;
+
+ SGMII_ACCESS(port, TARGET_SGMII_MR_ADV_ABILITY) = iblSgmii->adviseAbility;
+
+ /* Serdes configuration */
+ SGMII_ACCESS(port, TARGET_SGMII_TX_CFG) = iblSgmii->txConfig;
+ SGMII_ACCESS(port, TARGET_SGMII_RX_CFG) = iblSgmii->rxConfig;
+ SGMII_ACCESS(port, TARGET_SGMII_AUX_CFG) = iblSgmii->auxConfig;
+
+ return (0);
+
+}
+
+
+
+
+
+
+
diff --git a/src/hw/sgmii/sgmii.h b/src/hw/sgmii/sgmii.h
--- /dev/null
+++ b/src/hw/sgmii/sgmii.h
@@ -0,0 +1,28 @@
+#ifndef _SGMII_H
+#define _SGMII_H
+/**
+ * @file sgmii.h
+ *
+ * @brief
+ * Defines the sgmii api
+ */
+
+
+#include "types.h"
+#include "device.h"
+
+
+/**
+ * @brief
+ * The function prototype. If sgmii is not present in the device then hwSgmiiConfig will
+ * have been defined to a void statement in the device configuration header file
+ */
+#ifndef hwSgmiiConfig
+int32 hwSgmiiConfig (int32 port, iblSgmii_t *iblSgmii);
+#endif
+
+
+
+
+
+#endif /* _SGMII_H */
diff --git a/src/ibl.h b/src/ibl.h
index aeca8808d47237f55bd67fc0d80c3f806dd44104..a2b73a2de6deef294580b1e7c50306071725cb88 100644 (file)
--- a/src/ibl.h
+++ b/src/ibl.h
} iblEth_t;
+/**
+ * @brief
+ * This structure is used to control the operation of the ibl sgmii ports
+ *
+ * @details
+ * The physical register configuration is provided
+ */
+typedef struct iblSgmii_s
+{
+ uint32 adviseAbility; /**< The advise ability register */
+ uint32 control; /**< The control register */
+ uint32 txConfig; /**< Serdes Tx config */
+ uint32 rxConfig; /**< Serdes Rx config */
+ uint32 auxConfig; /**< Serdes Aux config */
+
+} iblSgmii_t;
+
+
/**
* @def ibl_N_ETH_PORTS
*/
iblEth_t ethConfig[ibl_N_ETH_PORTS]; /**< Ethernet boot configuration. @ref iblEth_t */
+ iblSgmii_t sgmiiConfig[ibl_N_ETH_PORTS]; /**< SGMII boot configuration. @ref iblSgmii_t */
+
iblMdio_t mdioConfig; /**< MDIO configuration. @ref iblMdio_t */
iblNand_t nandConfig; /**< NAND configuration @ref iblNand_t */
diff --git a/src/main/iblmain.c b/src/main/iblmain.c
index 36a2f7ecc7dd6c25ae5a6695d842a3531f53e485..d687b3825d12ec4dbebf47fb8c97195a031e0549 100644 (file)
--- a/src/main/iblmain.c
+++ b/src/main/iblmain.c
}
#endif
+
+#if 0 /* debugging c6472 using ccs download. Remove for i2c config download */
+
/* Load the default configuration table from the i2c. The actual speed of the device
* isn't really known here, since it is part of the table, so a compile time
* value is used (the pll may have been configured during the initial load) */
/* There is no recovery if the load of the configuration table failed */
iblStatus.tableLoadFail = 0x11111111;
for (;;);
+
}
+#endif
+
/* Load default mac addresses for ethernet boot if requested */
for (i = 0; i < ibl_N_ETH_PORTS; i++) {
diff --git a/src/make/Makefile b/src/make/Makefile
index e3101fab0a1d6491985ba986d7e70db3a16a3220..98e414786d802d9182bb9ea9d3dd9e436e989023 100644 (file)
--- a/src/make/Makefile
+++ b/src/make/Makefile
#*
#*******************************************************************************************
-IBLS_C6X= c6455 c6472
+IBLS_C6X= c6455 c6472 c6474
all:
clean:
make -f makestg2 clean ARCH=c64x
make -f makestg2 cleant ARCH=c64x TARGET=c6472
+ make -f makestg2 cleant ARCH=c64x TARGET=c6474
make -C ../util/bconvert clean
make -C ../util/btoccs clean
make -C ../util/i2cConfig clean
index 5c98b6e30a9ffe8021ae16b7901a9907f6a30376..6d1eba2da91d09169ba19768dc5d9b1225251e5f 100644 (file)
# -pds837: shut off #pragma symbol warnings (can be applied to file level symbol only)
# -pds97: shut off no source in file warning
#CFLAGS = -c -k -mi200 -ml3 -o2 -pm -pds1111 -pds827 -pds824 -pds837 -pds1037 -pds195 -pds97 -pden -pdr $(CPUFLAGS)
-#CFLAGS = -c -k -mi200 -ml3 -ms3 -o2 -pm -pds1111 -pds827 -pds824 -pds837 -pds1037 -pds195 -pds97 -pden -pdr $(CPUFLAGS)
-CFLAGS = -c -k -mi200 -ml0 -ms3 -o2 -pm -pds1111 -pds827 -pds824 -pds837 -pds1037 -pds195 -pds97 -pden -pdr $(CPUFLAGS)
+CFLAGS = -c -k -mi200 -ml3 -ms3 -o2 -pm -pds1111 -pds827 -pds824 -pds837 -pds1037 -pds195 -pds97 -pden -pdr $(CPUFLAGS)
+#CFLAGS = -c -k -mi200 -ml0 -ms3 -o2 -pm -pds1111 -pds827 -pds824 -pds837 -pds1037 -pds195 -pds97 -pden -pdr $(CPUFLAGS)
ifeq ($(ENDIAN),big)
CFLAGS+= -me
# -as : keep local symbols
# -g : enable debugging
# -ss : interlist C source and optimizer with .asm source
-#DCFLAGS = -g -as -ss
-DCFLAGS = -as -ss
+DCFLAGS = -g -as -ss
+#DCFLAGS = -as -ss
#DCFLAGS = -gp
diff --git a/src/make/ibl_c6474/ibl.cmd b/src/make/ibl_c6474/ibl.cmd
--- /dev/null
@@ -0,0 +1,81 @@
+/************************************************************************************
+ * FILE PURPOSE: Define the memory usage of the ibl module for the c6474
+ ************************************************************************************
+ * FILE NAME: ibl.cmd
+ *
+ * DESCRIPTION: The memory placement for the IBL is defined
+ *
+ ************************************************************************************/
+
+
+../main/c64x/make/iblmain.oc
+../device/c64x/make/c6474.oc
+../ethboot/c64x/make/ethboot.oc
+../nandboot/c64x/make/nandboot.oc
+../driver/c64x/make/net.oc
+../driver/c64x/make/arp.oc
+../driver/c64x/make/ip.oc
+../driver/c64x/make/udp.oc
+../driver/c64x/make/stream.oc
+../driver/c64x/make/timer.oc
+../driver/c64x/make/bootp.oc
+../driver/c64x/make/tftp.oc
+../driver/c64x/make/nand.oc
+../hw/c64x/make/t64.oc
+../hw/c64x/make/cpmacdrv.oc
+../hw/c64x/make/pll.oc
+../hw/c64x/make/psc.oc
+../hw/c64x/make/emif31.oc
+../hw/c64x/make/mdio.oc
+../hw/c64x/make/gpio.oc
+../hw/c64x/make/nandgpio.oc
+../hw/c64x/make/i2c.oc
+../hw/c64x/make/sgmii.oc
+../interp/c64x/make/bis.oc
+../interp/c64x/make/cload.oc
+../interp/c64x/make/osal.oc
+../interp/c64x/make/btblwrap.oc
+../interp/c64x/make/btblpr.oc
+../interp/c64x/make/gem.oc
+../interp/c64x/make/blob.oc
+
+../interp/c64x/make/dload.oc
+../interp/c64x/make/elfwrap.oc
+../interp/c64x/make/dlw_client.oc
+../interp/c64x/make/dload_endian.oc
+../interp/c64x/make/ArrayList.oc
+
+../ecc/c64x/make/3byte_ecc.oc
+
+-c
+-stack 0x800
+-heap 0x6000
+
+
+
+MEMORY
+{
+ TEXT : origin = 0x801000, length = 0x20000
+ STACK : origin = 0x821000, length = 0x0800
+ HEAP : origin = 0x821800, length = 0x6000
+ DATA : origin = 0x827800, length = 0x3000
+ CFG : origin = 0x831800, length = 0x0300
+ STAT : origin = 0x831b00, length = 0x0200
+}
+
+SECTIONS
+{
+ .stack > STACK
+ .sysmem > HEAP
+ .cinit > TEXT
+ .const > TEXT
+ .text > TEXT
+ .switch > TEXT
+ .far > DATA
+ .bss > DATA
+
+ .ibl_config_table > CFG
+ .ibl_status_table > STAT
+
+}
+
diff --git a/src/make/makestg2 b/src/make/makestg2
index 7f56ff30f1c9838979272f8473e3b1df3914c892..8df3ede64765da85b581e406d313475fe0df568b 100644 (file)
--- a/src/make/makestg2
+++ b/src/make/makestg2
MODULES= main device ethboot nandboot driver hw interp ecc
CLEAN_MODULES=$(addprefix clean_,$(MODULES))
+TARGETS= c6472 c6474
+
ifeq ($(ENDIAN),little)
HEX_OPT= -order L
IEXT= le
$(LD) -o ibl_$@/ibl_$@.out -m ibl_$@/ibl_$@.map ibl_$@/ibl.cmd $(RTLIBS)
-c6472: $(MODULES) utils
+$(TARGETS): $(MODULES) utils
$(LD) -o ibl_$@/ibl_$@.out -m ibl_$@/ibl_$@.map ibl_$@/ibl.cmd $(RTLIBS)
hex6x $(HEX_OPT) ibl_$@/ibl.rmd ibl_$@/ibl_$@.out
../util/bconvert/bconvert64x -$(IEXT) ibl_le.b ibl.b
utils:
make -C $(IBL_ROOT)/util/btoccs
- make -C $(IBL_ROOT)/util/romparse_$(TARGET)
+# make -C $(IBL_ROOT)/util/romparse_$(TARGET)
make -C $(IBL_ROOT)/util/bconvert
clean: $(CLEAN_MODULES)