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raw | patch | inline | side by side (parent: 48d86f7)
raw | patch | inline | side by side (parent: 48d86f7)
| author | Hao Zhang <hzhang@ti.com> | |
| Mon, 19 Nov 2012 20:45:00 +0000 (15:45 -0500) | ||
| committer | Hao Zhang <hzhang@ti.com> | |
| Mon, 19 Nov 2012 20:45:00 +0000 (15:45 -0500) |
49 files changed:
diff --git a/doc/README.txt b/doc/README.txt
--- a/doc/README.txt
+++ b/doc/README.txt
4. evmc6678-instructions.txt: Document describing steps to use IBL on the c6678 EVM
5. evmc6670-instructions.txt: Document describing steps to use IBL on the c6670 EVM
6. evmc6657-instructions.txt: Document describing steps to use IBL on the c6657 EVM
+7. evmtci6634k2k-instructions.txt: Document describing steps to use IBL on the tci6634k2k EVM
- C6472 LC EVM
- C6457 LC EVM
- DSK6455 EVM
+ - C6657 LC EVM
+ - TCI6634K2K EVM
2) Supported ENDIAN
- big
- little
3) Required toolset
- - TI CGEN compiler CGT_C6000_7.2.0
+ - TI CGEN compiler CGT_C6000_7.3.0
Requirements for building IBL on Windows:
For building on a Windows machine, a GNU development environment is
On a MinGW-MSYS Bash shell "source setupenvMsys.sh"
- Following are the commands for building IBL:
+ For TCI6634K2K Low Cost EVM:
+
+ make evm_tci6634k2k_i2c ENDIAN=little I2C_BUS_ADDR=0x51
+ Output images:
+ IBL image: bin/i2crom_0x51_tci6634k2k_le.dat (CCS data format)
+ : bin/i2crom_0x51_tci6634k2k_le.bin (raw binary)
+
+ make evm_tci6634k2k_i2c ENDIAN=big I2C_BUS_ADDR=0x51
+ Output images:
+ IBL image: bin/i2crom_0x51_tci6634k2k_be.dat (CCS data format)
+ : bin/i2crom_0x51_tci6634k2k_be.bin (raw binary)
+
For C6657 Low Cost EVM:
make evm_c6657_i2c ENDIAN=little I2C_BUS_ADDR=0x51
diff --git a/doc/evmtci6634k2k-instructions.txt b/doc/evmtci6634k2k-instructions.txt
--- /dev/null
@@ -0,0 +1,49 @@
+Steps to use IBL on the TCI6634K2K EVM
+
+1. Programing "IBL" on the EEPROM at bus address 0x51
+ (a) Use the I2C EEPROM writer for tci6634k2k EVM from the MCSDK distribution.
+ (b) Program i2crom_0x51_tci6634k2k_le.bin (IBL image) to the EEPROM at I2C BUS
+ address 0x51 following the EEPROM writer's procedure.
+
+2. Programming the application on NAND or NOR flash
+ NOTE: This step is not needed if the application is booted from Ethernet.
+ (a) Use the NAND or NOR writer tci6634k2k EVM from the tools directory.
+ (a) Flash the Application to NAND or NOR. For instructions please follow
+ the instructions given along with the NAND/NOR writer.
+
+3. Booting the Application using IBL
+ Supported boot modes:
+ IBL supports three I2C boot modes: NOR boot, NAND boot and EMAC boot.
+ Both NOR boot and NAND boot support maximum 2 images, EMAC boot supports only 1 image.
+ For all the I2C boot modes, user needs to set the boot dip switches to I2C master, bus address 0x51.
+
+ NOR Boot:
+ Set the dip switches (pin1, pin2, pin3, pin4, pin5, pin6, pin7, pin8) to:
+
+ SW3(off, off, on, off, on, on, on, on),
+ SW5(on, on, on, off, on, on, on, on),
+
+ This will set the boot param index to 0 to boot the NOR image, by default
+ the boot configuration table sets the NOR offset address to be 0 and
+ image format to be ELF for image 0.
+
+ NAND Boot:
+ Set the dip switches (pin1, pin2, pin3, pin4, pin5, pin6, pin7, pin8) to:
+
+ SW3(off, off, on, off, on, off, on, on),
+ SW5(on, on, on, off, on, on, on, on),
+
+ This will set the boot param index to 2 to boot the NAND image, by default
+ the boot configuration table sets the NAND offset address to be 16384
+ (start of block 1) and image format to be BBLOB for image 0.
+
+ EMAC Boot:
+ Set the dip switches (pin1, pin2, pin3, pin4, pin5, pin6, pin7, pin8) to:
+
+ SW3(off, off, on, off, on, on, off, on),
+ SW5(on, on, on, off, on, on, on, on),
+
+ This will set the boot param index to 4 to boot an image from a remote TFTP
+ server, by default the boot configuration table sets the server IP to be
+ 192.168.2.101, board IP to be 192.168.2.100 and image format to be BBLOB.
+
make EVM=c6670l I2C_MAP_ADDR=0x500
For C6657
-make EVM=c6670l I2C_MAP_ADDR=0x500
+make EVM=c6657l I2C_MAP_ADDR=0x500
+
+For TCI6634K2K
+make EVM=tci6634k2k I2C_MAP_ADDR=0x500
- There will an '''iblConfig.out''' that gets generated.
diff --git a/release.sh b/release.sh
index fc38b2a2cb16166aec1a2f806e5379b34edde600..682ca7dca82333966e71a366f63722b1d1664acf 100755 (executable)
--- a/release.sh
+++ b/release.sh
#!/bin/sh
# Generate the source release tarballs
-export IBL_VERSION="1_0_0_16"
+export IBL_VERSION="1_0_0_17"
cd ../
if [ -f ibl_src_$IBL_VERSION.tgz ]; then rm ibl_src_$IBL_VERSION.tgz; fi
mkdir ibl_bin_$IBL_VERSION/c6670/le
mkdir ibl_bin_$IBL_VERSION/c6670/be
+mkdir ibl_bin_$IBL_VERSION/tci6634k2k/
+mkdir ibl_bin_$IBL_VERSION/tci6634k2k/le
+mkdir ibl_bin_$IBL_VERSION/tci6634k2k/be
+
+
# Copy i2cConfig GEL file
cp -f src/util/i2cConfig/i2cConfig.gel ibl_bin_$IBL_VERSION/i2cConfig.gel
cp -f src/make/bin/i2crom_0x51_c6670_be.bin ibl_bin_$IBL_VERSION/c6670/be/
cp -f src/make/bin/i2cparam_0x51_c6670_be_0x500.out ibl_bin_$IBL_VERSION/c6670/be/
+# Build tci6634k2k EVM LE
+pushd src/make
+make clean
+make evm_tci6634k2k_i2c ENDIAN=little I2C_BUS_ADDR=0x51
+popd
+cp -f src/make/bin/i2crom_0x51_tci6634k2k_le.bin ibl_bin_$IBL_VERSION/tci6634k2k/le/
+cp -f src/make/bin/i2cparam_0x51_tci6634k2k_le_0x500.out ibl_bin_$IBL_VERSION/tci6634k2k/le/
+
+# Build tci6634k2k EVM BE
+pushd src/make
+make clean
+make evm_tci6634k2k_i2c ENDIAN=big I2C_BUS_ADDR=0x51
+popd
+cp -f src/make/bin/i2crom_0x51_tci6634k2k_be.bin ibl_bin_$IBL_VERSION/tci6634k2k/be/
+cp -f src/make/bin/i2cparam_0x51_tci6634k2k_be_0x500.out ibl_bin_$IBL_VERSION/tci6634k2k/be/
+
# Create Tar archive for binary package
tar -czf ibl_bin_$IBL_VERSION.tgz ibl_bin_$IBL_VERSION
diff --git a/src/cfg/c66xk2x/iblcfg.h b/src/cfg/c66xk2x/iblcfg.h
--- /dev/null
+++ b/src/cfg/c66xk2x/iblcfg.h
@@ -0,0 +1,134 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/**************************************************************************
+ * FILE PURPOSE: Provide build time configurations for the IBL
+ **************************************************************************
+ * FILE NAME: iblcfg.h
+ *
+ * DESCRIPTION: Build time configuration
+ *
+ * @file iblcfg.h
+ *
+ * @brief
+ * Build time configurations for the c66x ibl are defined
+ *
+ ***************************************************************************/
+#ifndef IBLCFG_H
+#define IBLCFG_H
+
+/**
+ * @brief The maximum number of UDP sockets in the system
+ */
+#define MAX_UDP_SOCKET 3
+
+
+/**
+ * @brief The maximum number of timers in the system
+ */
+#define MAX_TIMER_BLOCKS 5
+
+
+/**
+ * @brief The size in bytes of the internal stream buffer
+ */
+#define MAX_SIZE_STREAM_BUFFER 1520
+
+
+/**
+ * @brief The maximum number of functions supported for BIS mode
+ */
+#define MAX_BIS_FUNCTION_SUPPORT 3
+
+
+/**
+ * @brief No I/O sections accepted in boot table format
+ */
+#define BOOTCONFIG_NO_BTBL_IO
+
+/**
+ * @brief Estimates of operating parameters. Actual values will be known once they are
+ * read from the i2c.
+ */
+#define IBL_CFG_I2C_DEV_FREQ_MHZ 1200
+#define IBL_CFG_I2C_CLK_FREQ_KHZ 100
+#define IBL_CFG_I2C_OWN_ADDR 10
+#define IBL_CFG_I2C_ADDR_DELAY 0x100 /* Delay between sending the address and reading data */
+
+
+/**
+ * @brief The default location for the i2c map information can be overridden during make
+ */
+#ifndef IBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR
+ #define IBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR 0x51
+#endif
+
+
+#ifndef IBL_CFG_I2C_MAP_TABLE_DATA_ADDR
+ #define IBL_CFG_I2C_MAP_TABLE_DATA_ADDR 0x420
+#endif
+
+
+/**
+ * @brief The default location for the spi map information can be overridden during make
+ */
+#ifndef IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_LSW
+ #define IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_LSW 0x400
+#endif
+
+#ifndef IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW
+ #define IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW 0
+#endif
+
+#define NAND_CLE_GPIO_PIN GPIO_8 /*High: Command Cycle occuring */
+#define NAND_ALE_GPIO_PIN GPIO_9 /* High: Address input cycle oddcuring */
+#define NAND_NWE_GPIO_PIN GPIO_10
+#define NAND_BSY_GPIO_PIN GPIO_11 /* NAND Ready/Busy pin */
+#define NAND_NRE_GPIO_PIN GPIO_12
+#define NAND_NCE_GPIO_PIN GPIO_13
+
+/**
+ * @brief
+ * The standard NAND delay must be big enough to handle the highest possible
+ * operating frequency of the device */
+#define TARGET_NAND_STD_DELAY 50 // In cpu cycles
+#define NAND_WAIT_PIN_POLL_ST_DLY (10000)
+
+
+#endif
+
+
ifeq ($(TARGET),c665x)
CSRC= c665x.c c665xinit.c c665xutil.c
else
- CSRC= c6472.c c6455.c c6474.c c6474l.c c6457.c c6472init.c c6455init.c c6474linit.c c6474init.c c66x.c c66xinit.c c66xutil.c c665x.c c665xinit.c c665xutil.c
+ ifeq ($(TARGET),c66xk2x)
+ CSRC= c66xk2x.c c66xk2xinit.c c66xk2xutil.c
+ else
+ CSRC= c6472.c c6455.c c6474.c c6474l.c c6457.c c6472init.c c6455init.c c6474linit.c c6474init.c c66x.c c66xinit.c c66xutil.c c665x.c c665xinit.c c665xutil.c c66xk2x.c c66xk2xinit.c c66xk2xutil.c
+ endif
endif
endif
endif
/*
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
* are met:
*
- * Redistributions of source code must retain the above copyright
+ * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include "types.h"
-
-/**
+
+/**
* @brief
* Device EMAC definitions
*/
| ( 0 << 3 ) /* RX flow disabled */ \
| ( 0 << 1 ) /* Loopback enabled */ \
| ( 1 << 0 ) /* full duplex */
-
+
/**
* @brief
#define chipPllExternalPrediv(x) TRUE
/**
- * @brief
+ * @brief
* Device PSC definitions
*/
#define DEVICE_PSC_BASE 0x02350000u
*/
#define DEVICE_SPI_BASE(x) 0x20bf0000u
#define DEVICE_SPI_MOD_DIVIDER 6
-#define DEVICE_SPI_MAX_DIVIDER 0xff
+#define DEVICE_SPI_MAX_DIVIDER 0xff
/**
* The PSC number for the EMAC */
#define TARGET_PWR_ETH(x) 3
-/**
+/**
* @brief
* The PSC numbers for EMIF16 and SPI vary between devices. The devices are run time
* identified by reading the JTAG ID register,
- * NOTE: Have the variant bits as zero while defining the JTAG ID
+ * NOTE: Have the variant bits as zero while defining the JTAG ID
*/
-#define DEVICE_C6657_JTAG_ID_VAL 0xb97a02f /* C6657 */
+#define DEVICE_C6657_JTAG_ID_VAL 0xb97a02f /* C6657 */
#define DEVICE_C6678_JTAG_ID_VAL 0x9e02f /* C6678 */
#define DEVICE_C6670_JTAG_ID_VAL 0xb94102f /* C6670 */
+#define DEVICE_TCI6636K2H_JTAG_ID_VAL 0xb58102f /* TCI6636K2H */
#define DEVICE_JTAG_ID_REG 0x2620018
#define DEVICE_JTAG_ID_MASK 0x0fffffff /* exclude variant bits(31:28) */
* @brief
* The LPSC number for PCIe. PCIe is 10 for C6657
*/
-#define TARGET_PWR_PCIE 10
+#define TARGET_PWR_PCIE 10
/**
* @brief
*/
#define DEVICE_EMIF25_BASE 0x20c00000
-/**
+/**
* @brief
* NAND memory regions
*/
-#define TARGET_MEM_NAND_CS_2 0x70000000
-#define TARGET_MEM_NAND_CS_3 0x74000000
-#define TARGET_MEM_NAND_CS_4 0x78000000
-#define TARGET_MEM_NAND_CS_5 0x7c000000
+#define TARGET_MEM_NAND_CS_2 0x70000000
+#define TARGET_MEM_NAND_CS_3 0x74000000
+#define TARGET_MEM_NAND_CS_4 0x78000000
+#define TARGET_MEM_NAND_CS_5 0x7c000000
uint32 deviceNandMemBase (int32 cs);
#define TARGET_SHFL(x) _shfl(x) /* The shuffle intrinsic */
* The highest module number. The value for nyquist is used
*/
#define TARGET_PWR_MAX_MOD 30
-
+
/**
* @brief
- * The base address of MDIO
+ * The base address of MDIO
*/
#define TARGET_MDIO_BASE 0x2C080800
*/
#define DEVICE_I2C_BASE 0x02530000
#define DEVICE_I2C_MODULE_DIVISOR 6
-
+
/**
* @brief
* The address of the DEVSTAT register
#define BOOT_READ_BITFIELD(z,x,y) (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
#define BOOT_SET_BITFIELD(z,f,x,y) (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )
-/**
+/**
* @brief
- * Mpax configuration registers
+ * Mpax configuration registers
*/
#define DEVICE_REG_XMPAX_L(x) *((volatile unsigned int *)(0x08000000 + (8*(x))))
#define DEVICE_REG_XMPAX_H(x) *((volatile unsigned int *)(0x08000004 + (8*(x))))
* @brief
* Support for enabling EDC for internal memory.
*/
-#define IBL_ENABLE_EDC 1
+#define IBL_ENABLE_EDC 1
/**
* @brief
* Support for enabling PCIe workarond for C6678/C6670.
*/
-#define IBL_ENABLE_PCIE_WORKAROUND 1
+#define IBL_ENABLE_PCIE_WORKAROUND 1
/**
* @brief
- * DDR start and end address needed for DDR memory test
+ * DDR start and end address needed for DDR memory test
*/
#define DDR3_TEST_START_ADDRESS 0x80000000
#define DDR3_TEST_END_ADDRESS (DDR3_TEST_START_ADDRESS + (128 *1024))
--- a/src/device/c66x/target.h
+++ b/src/device/c66x/target.h
/*
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
* are met:
*
- * Redistributions of source code must retain the above copyright
+ * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#define _TARGET_H
#include "types.h"
-
-/**
+
+/**
* @brief
* Device EMAC definitions
*/
-
+
/**
* @brief
#define chipPllExternalPrediv(x) TRUE
/**
- * @brief
+ * @brief
* Device PSC definitions
*/
#define DEVICE_PSC_BASE 0x02350000u
*/
#define DEVICE_SPI_BASE(x) 0x20bf0000u
#define DEVICE_SPI_MOD_DIVIDER 6
-#define DEVICE_SPI_MAX_DIVIDER 0xff
+#define DEVICE_SPI_MAX_DIVIDER 0xff
/**
* @brief
* The PSC number for the SGMII */
#define TARGET_PWR_ETH(x) 8
-/**
+/**
* @brief
* The PSC numbers for EMIF16 and SPI vary between devices. The devices are run time
* identified by reading the JTAG ID register,
- * NOTE: Have the variant bits as zero while defining the JTAG ID
+ * NOTE: Have the variant bits as zero while defining the JTAG ID
*/
-#define DEVICE_C6678_JTAG_ID_VAL 0x9e02f /* C6678 */
-#define DEVICE_C6670_JTAG_ID_VAL 0xb94102f /* C6670 */
+#define DEVICE_C6678_JTAG_ID_VAL 0x9e02f /* C6678 */
+#define DEVICE_C6670_JTAG_ID_VAL 0xb94102f /* C6670 */
#define DEVICE_C6657_JTAG_ID_VAL 0xb97a02f /* C6657 */
+#define DEVICE_TCI6636K2H_JTAG_ID_VAL 0xb58102f /* TCI6636K2H */
#define DEVICE_JTAG_ID_REG 0x2620018
#define DEVICE_JTAG_ID_MASK 0x0fffffff /* exclude variant bits(31:28) */
* @brief
* The LPSC number for PCIe. PCIe is 10 for C6678/C6770
*/
-#define TARGET_PWR_PCIE 10
+#define TARGET_PWR_PCIE 10
/**
* @brief
*/
#define DEVICE_EMIF25_BASE 0x20c00000
-/**
+/**
* @brief
* NAND memory regions
*/
-#define TARGET_MEM_NAND_CS_2 0x70000000
-#define TARGET_MEM_NAND_CS_3 0x74000000
-#define TARGET_MEM_NAND_CS_4 0x78000000
-#define TARGET_MEM_NAND_CS_5 0x7c000000
+#define TARGET_MEM_NAND_CS_2 0x70000000
+#define TARGET_MEM_NAND_CS_3 0x74000000
+#define TARGET_MEM_NAND_CS_4 0x78000000
+#define TARGET_MEM_NAND_CS_5 0x7c000000
uint32 deviceNandMemBase (int32 cs);
#define TARGET_SHFL(x) _shfl(x) /* The shuffle intrinsic */
* The highest module number. The value for nyquist is used
*/
#define TARGET_PWR_MAX_MOD 30
-
+
/**
* @brief
- * The base address of MDIO
+ * The base address of MDIO
*/
#define TARGET_MDIO_BASE 0x2090300
*/
#define DEVICE_I2C_BASE 0x02530000
#define DEVICE_I2C_MODULE_DIVISOR 6
-
+
/**
* @brief
* The address of the DEVSTAT register
#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a20000
#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02a40000
#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a00000
+
+/* QM base address register */
+#define DEVICE_QM1_QUEUE_MANAGEMENT_REGS(x) (0x23A00000 + 0x80000 + 0x10000*(x))
+
#define DEVICE_QM_NUM_LINKRAMS 2
#define DEVICE_QM_NUM_MEMREGIONS 20
void *targetGetQmConfig(void);
#define BOOT_READ_BITFIELD(z,x,y) (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
#define BOOT_SET_BITFIELD(z,f,x,y) (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )
-/**
+/**
* @brief
- * Mpax configuration registers
+ * Mpax configuration registers
*/
#define DEVICE_REG_XMPAX_L(x) *((volatile unsigned int *)(0x08000000 + (8*(x))))
#define DEVICE_REG_XMPAX_H(x) *((volatile unsigned int *)(0x08000004 + (8*(x))))
* @brief
* Support for enabling EDC for internal memory.
*/
-#define IBL_ENABLE_EDC 1
+#define IBL_ENABLE_EDC 1
/**
* @brief
/**
* @brief
- * DDR start and end address needed for DDR memory test
+ * DDR start and end address needed for DDR memory test
*/
#define DDR3_TEST_START_ADDRESS 0x80000000
#define DDR3_TEST_END_ADDRESS (DDR3_TEST_START_ADDRESS + (128 *1024))
diff --git a/src/device/c66xk2x/c66xk2x.c b/src/device/c66xk2x/c66xk2x.c
--- /dev/null
@@ -0,0 +1,709 @@
+/*
+ *
+ * Copyright (C) 2010-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/************************************************************************************
+ * FILE PURPOSE: C66xK2x Device Specific functions
+ ************************************************************************************
+ * FILE NAME: c66xk2x.c
+ *
+ * DESCRIPTION: Implements the device specific functions for the IBL
+ *
+ * @file c66xk2x.c
+ *
+ * @brief
+ * This file implements the device specific functions for the IBL
+ *
+ ************************************************************************************/
+#include "ibl.h"
+#include "iblloc.h"
+#include "iblcfg.h"
+#include "device.h"
+#include "pllapi.h"
+#include "emif31api.h"
+#include "pscapi.h"
+#include "gpio.h"
+#include "qm_api.h"
+#include "cpdma_api.h"
+#include "pa_api.h"
+#include "serdes_api.h"
+#include "net.h"
+#include "nandhwapi.h"
+#include "nor_api.h"
+#include "spi_api.h"
+#include <string.h>
+#include <stdint.h>
+#include "target.h"
+#include "uart.h"
+
+#define PLL_DDR_INIT_LOOPMAX 10
+#define IBL_RESULT_CODE_STR_LEN 20
+#define IBL_RESULT_CODE_LOC 17
+
+extern cregister unsigned int DNUM;
+
+/**
+ * @brief Determine if an address is local
+ *
+ * @details
+ * Examines an input address to determine if it is a local address. Using the largest
+ * L2 size on the c66xk2x.
+ */
+bool address_is_local (Uint32 addr)
+{
+ /* L2 */
+ if ((addr >= 0x00800000) && (addr < 0x00900000))
+ return (TRUE);
+
+ /* L1P */
+ if ((addr >= 0x00e00000) && (addr < 0x00e08000))
+ return (TRUE);
+
+ /* L2D */
+ if ((addr >= 0x00f00000) && (addr < 0x00f08000))
+ return (TRUE);
+
+ return (FALSE);
+
+}
+
+
+/**
+ * @brief Convert a local l1d, l1p or l2 address to a global address
+ *
+ * @details
+ * The global address is formed. If the address is not local then
+ * the input address is returned
+ */
+Uint32 deviceLocalAddrToGlobal (Uint32 addr)
+{
+
+ if (address_is_local (addr))
+ addr = (1 << 28) | (DNUM << 24) | addr;
+
+ return (addr);
+
+}
+
+
+/**
+ * @brief
+ * Enable the DDR
+ *
+ * @details
+ * The DDR controller on the c66x is an emif 4.0. The controller is
+ * initialized directly with the supplied values
+ */
+void deviceDdrConfig (void)
+{
+ uint32 loopcount=0;
+ int8 ddr_result_code_str[IBL_RESULT_CODE_STR_LEN] = "IBL Result code 0";
+ /* The emif registers must be made visible. MPAX mapping 2 is used */
+ DEVICE_REG_XMPAX_L(2) = 0x10000000 | 0xff; /* replacement addr + perm*/
+ DEVICE_REG_XMPAX_H(2) = 0x2100000B; /* base addr + seg size (64KB)*/
+
+ if (ibl.ddrConfig.configDdr != 0)
+ hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
+
+#ifdef PLL_REINIT_WORKAROUND
+ for (loopcount = 0; loopcount < PLL_DDR_INIT_LOOPMAX; loopcount++)
+ {
+ /* Calling MAIN, PA, DDR PLL init */
+ if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
+ hwPllSetPll (MAIN_PLL,
+ ibl.pllConfig[ibl_MAIN_PLL].prediv,
+ ibl.pllConfig[ibl_MAIN_PLL].mult,
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv);
+
+ if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
+ hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
+ ibl.pllConfig[ibl_NET_PLL].prediv,
+ ibl.pllConfig[ibl_NET_PLL].mult,
+ ibl.pllConfig[ibl_NET_PLL].postdiv,
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+ ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
+
+ if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
+ hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
+ ibl.pllConfig[ibl_DDR_PLL].prediv,
+ ibl.pllConfig[ibl_DDR_PLL].mult,
+ ibl.pllConfig[ibl_DDR_PLL].postdiv,
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+ ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
+
+ if (ibl.ddrConfig.configDdr != 0)
+ hwEmif4p0Enable (&ibl.ddrConfig.uEmif.emif4p0);
+
+ if (ddr3_memory_test() == 0)
+ {
+ break;
+ }
+ }
+ /* Init UART again because we are re-initializing the PLL's */
+ uart_init();
+
+ if (loopcount < 10)
+ {
+ ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + '0';
+ }
+ else if ((loopcount >= 10) && (loopcount < 35))
+ {
+ ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + 'A';
+ }
+ else
+ {
+ ddr_result_code_str[IBL_RESULT_CODE_LOC] = loopcount + 'Z';
+ }
+
+ if (loopcount == PLL_DDR_INIT_LOOPMAX)
+ {
+ uart_write_string("IBL: DDR INITIALIZATION FAILED",0);
+ }
+ else
+ {
+ uart_write_string("IBL: PLL and DDR Initialization Complete",0);
+ }
+ uart_write_string(ddr_result_code_str,0);
+#endif
+}
+
+
+
+/**
+ * @brief Enable EMIF25 or SPI interface to the NAND
+ *
+ */
+int32 deviceConfigureForNand(void)
+{
+
+ return (0);
+
+}
+
+/**
+ * @brief
+ * Return the base memory address for emif25 in a given chip select space
+ */
+uint32 deviceEmif25MemBase (int32 cs)
+{
+ switch (cs) {
+
+ case 2: return (TARGET_MEM_NAND_CS_2);
+
+ case 3: return (TARGET_MEM_NAND_CS_3);
+
+ case 4: return (TARGET_MEM_NAND_CS_4);
+
+ case 5: return (TARGET_MEM_NAND_CS_5);
+
+ }
+
+ return (0xffffffff);
+
+}
+
+
+/**
+ * @brief
+ * Return the PSC number for NAND/NOR through emif. Only 6678 has the emif
+ */
+Int32 deviceEmifPscNum (void)
+{
+ Uint32 v;
+
+ v = *((Uint32 *)DEVICE_JTAG_ID_REG);
+ v &= DEVICE_JTAG_ID_MASK;
+ if (v == DEVICE_TCI6636K2H_JTAG_ID_VAL)
+ return (TARGET_PWR_EMIF_TCI6634K2K);
+
+ /* Return a negative number to indicate no PSC module is associated with NAND */
+ return (-1);
+
+}
+
+
+
+/**
+ * @brief
+ * The e-fuse mac address is loaded
+ */
+void deviceLoadDefaultEthAddress (uint8 *maddr)
+{
+ uint32 macA, macB;
+
+ /* Read the e-fuse mac address */
+ macA = *((uint32 *)0x2620110);
+ macB = *((uint32 *)0x2620114);
+
+ maddr[0] = (macB >> 8) & 0xff;
+ maddr[1] = (macB >> 0) & 0xff;
+ maddr[2] = (macA >> 24) & 0xff;
+ maddr[3] = (macA >> 16) & 0xff;
+ maddr[4] = (macA >> 8) & 0xff;
+ maddr[5] = (macA >> 0) & 0xff;
+}
+
+
+/**
+ * @brief
+ * Compile time queue manager information
+ */
+#define DEVICE_NUM_RX_CPPIS 1
+#define DEVICE_NUM_TX_CPPIS 1
+#define DEVICE_NUM_CPPIS (DEVICE_NUM_RX_CPPIS + DEVICE_NUM_TX_CPPIS)
+
+/* The linking RAM */
+#pragma DATA_SECTION(qm_linkram_buf, ".linkram")
+#pragma DATA_ALIGN(qm_linkram_buf, 16)
+uint8 qm_linkram_buf[DEVICE_NUM_CPPIS * 2 * (sizeof(uint32)/sizeof(uint8))];
+
+
+/* The CPPI RAM */
+#pragma DATA_SECTION(qm_cppi_buf, ".cppi")
+#pragma DATA_ALIGN(qm_cppi_buf, 16)
+uint8 qm_cppi_buf[QM_DESC_SIZE_BYTES * DEVICE_NUM_CPPIS];
+
+
+/* The rx data buffers */
+#pragma DATA_SECTION(qm_buffer, ".mac_buffer")
+#pragma DATA_ALIGN(qm_buffer, 16)
+uint8 qm_buffer[MAX_SIZE_STREAM_BUFFER * DEVICE_NUM_RX_CPPIS];
+
+const qmConfig_t qmConfig = {
+ (UINT32) qm_linkram_buf,
+ sizeof (qm_cppi_buf),
+ (UINT32) qm_cppi_buf,
+
+ DEVICE_NUM_CPPIS,
+ DEVICE_QM_FREE_Q
+};
+
+/**
+ * @brief
+ * Return the queue manager memory configuration information
+ */
+void *targetGetQmConfig (void)
+{
+ return ((void *)&qmConfig);
+}
+
+/**
+ * @brief
+ * Attach a packet buffer to each descriptor and push onto the linked buffer queue
+ */
+void targetInitQs (void)
+{
+ int32 i;
+ qmHostDesc_t *hd;
+
+ for (i = 0; i < DEVICE_NUM_RX_CPPIS; i++) {
+
+ hd = hwQmQueuePop (DEVICE_QM_FREE_Q);
+ hd->buffLen = sizeof (qm_buffer) / DEVICE_NUM_CPPIS;
+ hd->buffPtr = (UINT32) &(qm_buffer[MAX_SIZE_STREAM_BUFFER * i]);
+ hd->nextBDPtr = 0;
+ hd->origBufferLen = MAX_SIZE_STREAM_BUFFER;
+ hd->origBuffPtr = hd->buffPtr;
+
+ hwQmQueuePush (hd, DEVICE_QM_LNK_BUF_Q, QM_DESC_SIZE_BYTES);
+
+ }
+
+
+ for (i = 0; i < DEVICE_NUM_TX_CPPIS; i++) {
+
+ hd = hwQmQueuePop (DEVICE_QM_FREE_Q);
+ hd->buffLen = 0;
+ hd->buffPtr = 0;
+ hd->nextBDPtr = 0;
+ hd->origBufferLen = 0;
+ hd->origBuffPtr = 0;
+
+ hwQmQueuePush (hd, DEVICE_QM_TX_Q, QM_DESC_SIZE_BYTES);
+
+ }
+
+
+}
+
+
+
+const cpdmaRxCfg_t cpdmaEthRxCfg = {
+
+ DEVICE_PA_CDMA_RX_CHAN_CFG_BASE, /* Base address of PA CPDMA rx config registers */
+ DEVICE_PA_CDMA_RX_NUM_CHANNELS, /* Number of rx channels */
+
+ DEVICE_PA_CDMA_RX_FLOW_CFG_BASE, /* Base address of PA CPDMA rx flow registers */
+ DEVICE_PA_CDMA_RX_NUM_FLOWS, /* Number of rx flows */
+
+ 0, /* Queue manager for descriptor / buffer for received packets */
+ DEVICE_QM_LNK_BUF_Q, /* Queue of descriptors /buffers for received packets */
+
+ 0, /* Queue manager for received packets */
+ DEVICE_QM_RCV_Q, /* Queue for received packets (overridden by PA) */
+
+ DEVICE_RX_CDMA_TIMEOUT_COUNT /* Teardown maximum loop wait */
+};
+
+
+/**
+ * @brief
+ * Return the cpdma configuration information
+ */
+void *targetGetCpdmaRxConfig (void)
+{
+ return ((void *)&cpdmaEthRxCfg);
+
+}
+
+
+const cpdmaTxCfg_t cpdmaEthTxCfg = {
+
+ DEVICE_PA_CDMA_GLOBAL_CFG_BASE, /* Base address of global config registers */
+ DEVICE_PA_CDMA_TX_CHAN_CFG_BASE, /* Base address of PA CPDMA tx config registers */
+ DEVICE_PA_CDMA_TX_NUM_CHANNELS /* Number of tx channels */
+
+};
+
+
+/**
+ * @brief
+ * return the tx cpdma configuration information
+ */
+void *targetGetCpdmaTxConfig (void)
+{
+ return ((void *)&cpdmaEthTxCfg);
+
+}
+
+/**
+ * @brief
+ * Configure the PA
+ */
+void targetPaConfig (uint8 *macAddr)
+{
+ paConfig_t paCfg;
+ qmHostDesc_t *hd;
+ SINT16 ret;
+
+ /* Filter everything except the desired mac address and the broadcast mac */
+ paCfg.mac0ms = ((uint32)macAddr[0] << 24) | ((uint32)macAddr[1] << 16) | ((uint32)macAddr[2] << 8) | (uint32)(macAddr[3]);
+ paCfg.mac0ls = ((uint32)macAddr[4] << 24) | ((uint32)macAddr[5] << 16);
+
+ paCfg.mac1ms = 0xffffffff;
+ paCfg.mac1ls = 0xffff0000;
+
+ paCfg.rxQnum = DEVICE_QM_RCV_Q;
+
+ /* Form the configuration command in a buffer linked to a descriptor */
+ hd = hwQmQueuePop (DEVICE_QM_LNK_BUF_Q);
+ paCfg.cmdBuf = (uint8 *)hd->origBuffPtr;
+
+ ret = hwPaEnable (&paCfg);
+ if (ret != 0) {
+ iblStatus.iblFail = ibl_FAIL_CODE_PA;
+ return;
+ }
+
+
+ /* Send the command to the PA through the QM */
+ hd->softwareInfo0 = PA_MAGIC_ID;
+ hd->buffLen = 16;
+ QM_DESC_DESCINFO_SET_PKT_LEN(hd->descInfo, 16);
+
+ /* Set the return Queue */
+ QM_DESC_PINFO_SET_QM (hd->packetInfo, 0);
+ QM_DESC_PINFO_SET_QUEUE (hd->packetInfo, DEVICE_QM_LNK_BUF_Q);
+
+ hwQmQueuePush (hd, DEVICE_QM_PA_CFG_Q, QM_DESC_SIZE_BYTES);
+
+
+}
+
+/**
+ * @brief
+ * Chip level SGMII serdes configuration
+ *
+ * @details
+ * Both lanes are always setup, regardless of the port value
+ */
+void targetSgmiiSerdesConfig (int32 port, void *viblSgmii)
+{
+ serdesConfig_t scfg;
+ iblSgmii_t *sgmii = (iblSgmii_t *)viblSgmii;
+
+ scfg.cfg = sgmii->auxConfig;
+ scfg.nLanes = 2;
+ scfg.rxCfg[0] = scfg.rxCfg[1] = sgmii->rxConfig;
+ scfg.txCfg[0] = scfg.txCfg[1] = sgmii->txConfig;
+
+#if 0 /* TBD */
+ hwSerdesConfig (TARGET_SGMII_SERDES_BASE, &scfg);
+
+ hwSerdesWaitLock (TARGET_SGMII_SERDES_STATUS_BASE);
+#endif
+}
+
+
+Int32 targetMacSend (void *vptr_device, Uint8* buffer, int num_bytes)
+{
+ qmHostDesc_t *hd;
+ NET_DRV_DEVICE *ptr_device = (NET_DRV_DEVICE *)vptr_device;
+ int i;
+
+
+ /* Must always setup the descriptor to have the minimum packet length */
+ if (num_bytes < 64)
+ num_bytes = 64;
+
+
+ for (i = 0, hd = NULL; hd == NULL; i++, chipDelay32 (1000))
+ hd = hwQmQueuePop (DEVICE_QM_TX_Q);
+
+ if (hd == NULL)
+ return (-1);
+
+ QM_DESC_DESCINFO_SET_PKT_LEN(hd->descInfo, num_bytes);
+
+ hd->buffLen = num_bytes;
+ hd->origBufferLen = num_bytes;
+
+ hd->buffPtr = deviceLocalAddrToGlobal((UINT32)buffer);
+ hd->origBuffPtr = deviceLocalAddrToGlobal((UINT32)buffer);
+
+
+ /* Return the descriptor back to the transmit queue */
+ QM_DESC_PINFO_SET_QM(hd->packetInfo, 0);
+ QM_DESC_PINFO_SET_QUEUE(hd->packetInfo, DEVICE_QM_TX_Q);
+
+ hwQmQueuePush (hd, DEVICE_QM_ETH_TX_Q, QM_DESC_SIZE_BYTES);
+
+ return (0);
+
+}
+
+
+Int32 targetMacRcv (void *vptr_device, UINT8 *buffer)
+{
+ Int32 pktSizeBytes;
+ qmHostDesc_t *hd;
+ NET_DRV_DEVICE *ptr_device = (NET_DRV_DEVICE *)vptr_device;
+
+ hd = hwQmQueuePop (DEVICE_QM_RCV_Q);
+ if (hd == NULL)
+ return (0);
+
+ pktSizeBytes = QM_DESC_DESCINFO_GET_PKT_LEN(hd->descInfo);
+ iblMemcpy ((void *)buffer, (void *)hd->buffPtr, pktSizeBytes);
+
+ hd->buffLen = hd->origBufferLen;
+ hd->buffPtr = hd->origBuffPtr;
+
+ hwQmQueuePush (hd, DEVICE_QM_LNK_BUF_Q, QM_DESC_SIZE_BYTES);
+
+ return (pktSizeBytes);
+
+}
+
+void targetFreeQs (void)
+{
+ qmHostDesc_t *hd;
+
+ do {
+
+ hd = hwQmQueuePop (DEVICE_QM_FREE_Q);
+
+ } while (hd != NULL);
+
+ do {
+
+ hd = hwQmQueuePop (DEVICE_QM_LNK_BUF_Q);
+
+ } while (hd != NULL);
+
+ do {
+
+ hd = hwQmQueuePop (DEVICE_QM_RCV_Q);
+
+ } while (hd != NULL);
+
+ do {
+
+ hd = hwQmQueuePop (DEVICE_QM_TX_Q);
+
+ } while (hd != NULL);
+
+}
+
+extern nandCtbl_t nandEmifCtbl;
+/**
+ * @brief Return the NAND interface (GPIO, EMIF25 or SPI) used based on the value
+ * of interface
+ */
+#ifndef EXCLUDE_NAND_GPIO
+nandCtbl_t nandGpioCtbl = {
+
+ nandHwGpioDriverInit,
+ nandHwGpioDriverReadBytes,
+ nandHwGpioDriverReadPage,
+ nandHwGpioDriverClose
+
+};
+#endif
+
+#ifndef EXCLUDE_NAND_EMIF
+extern Int32 nandHwEmifDriverInit (int32 cs, void *vdevInfo);
+extern Int32 nandHwEmifDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32 nbytes, Uint8 *data);
+extern Int32 nandHwEmifDriverReadPage (Uint32 block, Uint32 page, Uint8 *data);
+extern Int32 nandHwEmifDriverClose (void);
+
+nandCtbl_t nandEmifCtbl = {
+
+ nandHwEmifDriverInit,
+ nandHwEmifDriverReadBytes,
+ nandHwEmifDriverReadPage,
+ nandHwEmifDriverClose
+
+};
+#endif
+
+#ifndef EXCLUDE_NAND_SPI
+nandCtbl_t nandSpiCtbl = {
+
+
+ nandHwSpiDriverInit,
+ nandHwSpiDriverReadBytes,
+ nandHwSpiDriverReadPage,
+ nandHwSpiDriverClose
+
+};
+#endif
+
+nandCtbl_t *deviceGetNandCtbl (int32 interface)
+{
+#ifndef EXCLUDE_NAND_GPIO
+
+ if (interface == ibl_PMEM_IF_GPIO)
+ return (&nandGpioCtbl);
+
+#endif
+
+#ifndef EXCLUDE_NAND_SPI
+
+ if (interface == ibl_PMEM_IF_SPI)
+ return (&nandSpiCtbl);
+
+#endif
+
+#ifndef EXCLUDE_NAND_EMIF
+
+ if ((interface >= ibl_PMEM_IF_CHIPSEL_2) && (interface <= ibl_PMEM_IF_CHIPSEL_5))
+ return (&nandEmifCtbl);
+
+#endif
+
+ return (NULL);
+
+}
+
+
+/**
+ * @brief
+ * Get the nor call table for the specified nor interface
+ */
+
+#ifndef EXCLUDE_NOR_EMIF
+norCtbl_t norEmifCtbl = {
+
+ norHwEmifDriverInit,
+ norHwEmifDriverReadBytes,
+ norHwEmifDriverClose
+
+};
+
+#endif
+
+#ifndef EXCLUDE_NOR_SPI
+
+norCtbl_t norSpiCtbl = {
+
+ norHwSpiDriverInit,
+ norHwSpiDriverReadBytes,
+ norHwSpiDriverClose
+
+};
+
+#endif
+
+norCtbl_t *deviceGetNorCtbl (int32 interface)
+{
+
+#ifndef EXCLUDE_NOR_SPI
+
+ if (interface == ibl_PMEM_IF_SPI)
+ return (&norSpiCtbl);
+
+#endif
+
+#ifndef EXCLUDE_NOR_EMIF
+
+ if ((interface >= ibl_PMEM_IF_CHIPSEL_2) && (interface <= ibl_PMEM_IF_CHIPSEL_5))
+ return (&norEmifCtbl);
+
+#endif
+
+ return (NULL);
+
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/device/c66xk2x/c66xk2xinit.c b/src/device/c66xk2x/c66xk2xinit.c
--- /dev/null
@@ -0,0 +1,476 @@
+/*
+ *
+ * Copyright (C) 2010-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @file c66xk2xinit.c
+ *
+ * @brief
+ * c66xk2x functions used during the initial stage of the ibl load
+ *
+ */
+#include "ibl.h"
+#include "iblloc.h"
+#include "device.h"
+#include "pllapi.h"
+#include "spi_api.h"
+#include "spi_loc.h"
+#include "tiboot_c66xk2x.h"
+
+
+/**
+ * @brief Configure the PLLs
+ *
+ * @details
+ * The three PLLs are enabled. Only the main PLL has the ability to configure
+ * the multiplier and dividers.
+ */
+void devicePllConfig (void)
+{
+ /* Unlock the chip registers and leave them unlocked */
+ *((Uint32 *)0x2620038) = 0x83e70b13;
+ *((Uint32 *)0x262003c) = 0x95a4f1e0;
+
+ if (ibl.pllConfig[ibl_MAIN_PLL].doEnable == TRUE)
+ hwPllSetPll (MAIN_PLL,
+ ibl.pllConfig[ibl_MAIN_PLL].prediv,
+ ibl.pllConfig[ibl_MAIN_PLL].mult,
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv);
+
+ if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE)
+ hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL),
+ ibl.pllConfig[ibl_NET_PLL].prediv,
+ ibl.pllConfig[ibl_NET_PLL].mult,
+ ibl.pllConfig[ibl_NET_PLL].postdiv,
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+ ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz);
+
+ if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE)
+ hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL),
+ ibl.pllConfig[ibl_DDR_PLL].prediv,
+ ibl.pllConfig[ibl_DDR_PLL].mult,
+ ibl.pllConfig[ibl_DDR_PLL].postdiv,
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz,
+ ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz);
+
+}
+
+
+/**
+ * @brief
+ * Return the endian status of the device
+ *
+ * @details
+ * Returns true if the device is executing in little endian mode
+ */
+extern cregister volatile unsigned int CSR;
+
+bool deviceIsLittleEndian (void)
+{
+ if ((CSR & (1 << 8)) == 0)
+ return (FALSE);
+
+ return (TRUE);
+
+}
+
+
+/**
+ * @brief
+ * Return the device used for the second stage program load.
+ * For SPI NAND a second stage loader is required and this
+ * function must be changed to locate that fingerprint.
+ */
+int32 deviceReadBootDevice (void)
+{
+ uint32 v;
+ int32 w;
+
+ BOOT_PARAMS_COMMON_T *params;
+
+#if (defined(EXCLUDE_NOR_SPI) && defined(EXCLUDE_NAND_SPI) && !defined(EXCLUDE_I2C))
+
+ return (BOOT_DEVICE_I2C);
+
+#elif (defined(EXCLUDE_NOR_SPI) && !defined(EXCLUDE_NAND_SPI) && defined(EXCLUDE_I2C))
+
+ return (BOOT_DEVICE_NAND_SPI);
+
+#elif (!defined(EXCLUDE_NOR_SPI) && defined(EXCLUDE_NAND_SPI) && defined(EXCLUDE_I2C))
+
+ return (BOOT_DEVICE_NOR_SPI);
+
+#endif
+
+ v = *((Uint32 *)DEVICE_JTAG_ID_REG);
+ v &= DEVICE_JTAG_ID_MASK;
+
+ if (v == DEVICE_TCI6636K2H_JTAG_ID_VAL)
+ params = (BOOT_PARAMS_COMMON_T *)ROM_BOOT_PARAMS_ADDR_TCI6634K2K;
+
+ switch (params->boot_mode) {
+
+#ifndef EXCLUDE_I2C
+ case BOOT_MODE_I2C: w = BOOT_DEVICE_I2C;
+ break;
+#endif
+
+#ifndef EXCLUDE_NOR_SPI
+ case BOOT_MODE_SPI: w = BOOT_DEVICE_SPI_NOR;
+ break;
+#endif
+
+ default: w = BOOT_DEVICE_INVALID;
+ break;
+
+ }
+
+ return (w);
+}
+
+#define L1PEDCMD 0x01846408
+#define L2EDCEN 0x01846030
+#define L2EDCMD 0x01846008
+#define SMEDCC 0x0BC00010
+/**
+ * @brief
+ * Enable the EDC for the local memory
+ */
+void iblEnableEDC ()
+{
+ /* Enable L1P EDC */
+ *(volatile unsigned int *)(L1PEDCMD) = 0x1; //Set EN(bit0)=1
+
+ /* Enable EDC L2EDCEN, set DL2CEN(bit0),PL2CEN(bit1),DL2SEN(bit2),PL2SEN(bit3),SDMAEN(bit4)=1 */
+ *(volatile unsigned int *)(L2EDCEN) |= 0x1F;
+
+ /* Enalble L2 EDC */
+ *(volatile unsigned int *)(L2EDCMD) = 0x1;
+
+ /* Enalbe MSMC EDC */
+ *(volatile unsigned int *)(SMEDCC) &= 0x7FFFFFFF; //Clear SEN(bit31)=0
+ *(volatile unsigned int *)(SMEDCC) |= 0x40000000; //Set ECM(bit30)=1
+}
+
+#ifdef IBL_ENABLE_PCIE_WORKAROUND
+
+/* undocumented register in data manual
+ * Bit 0 of this register is supposed to give the status of PCIe PLL lock*/
+#define PCIE_STS_REG 0x262015C
+
+/* Workaround for PCIe boot mode support for C6678/C6670 */
+/* This is a temporary workaround should be removed once fixed in RBL */
+
+/* PCIe Config register base on C6678/C6670 */
+#define PCIE_BASE_ADDR 0x21800000
+
+/* PCIe Application registers */
+#define PCIE_APP_CMD_STATUS 0x4
+#define PCIE_APP_OB_SIZE 0x30
+#define PCIE_APP_SERDES_CFG0 0x390
+#define PCIE_APP_SERDES_CFG1 0x394
+
+/* PCIe Local Configuration registers */
+#define PCIE_VENDER_DEVICE_ID 0x1000
+#define PCIE_STATUS_CMD 0x1004
+#define PCIE_CLASSCODE_REVID 0x1008
+#define PCIE_BAR0 0x1010
+#define PCIE_BAR1 0x1014
+#define PCIE_BAR2 0x1018
+#define PCIE_BAR3 0x101c
+#define PCIE_DEVICE_CAP 0x1074
+#define PCIE_DEV_STAT_CTRL 0x1078
+#define PCIE_LINK_STAT_CTRL 0x1080
+#define PCIE_ACCR 0x1118
+#define PCIE_DEBUG0 0x1728
+#define PCIE_PL_GEN2 0x180C
+
+/* SERDES Configuration registers */
+#define PCIE_SERDES_CFG_PLL 0x2620358
+
+void waitForBoot(UINT32 MAGIC_ADDR)
+{
+ void (*exit)();
+ UINT32 i, entry_addr;
+
+ while(1)
+ {
+ entry_addr = DEVICE_REG32_R(MAGIC_ADDR);
+ if (entry_addr != 0)
+ {
+ /* jump to the exit point, which will be the entry point for the full IBL */
+ exit = (void (*)())entry_addr;
+ (*exit)();
+ }
+ for (i=0; i < 100; i++)
+ asm("nop");
+ }
+}
+
+void iblPCIeWorkaround()
+{
+ UINT32 v, flag_k2k = 0, MAGIC_ADDR;
+ UINT32 i;
+
+ /* Power up PCIe */
+ devicePowerPeriph (TARGET_PWR_PCIE);
+ for(i=0; i<1000; i++) asm (" NOP");
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_SERDES_CFG0), 0x00062320); /* ss clock */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_SERDES_CFG1), 0x00022320); /* ss clock */
+
+ /* Wait for PCIe PLL lock */
+ while(!(DEVICE_REG32_R(PCIE_STS_REG) & 1));
+
+ v = *((Uint32 *)DEVICE_JTAG_ID_REG);
+ v &= DEVICE_JTAG_ID_MASK;
+
+ if (v == DEVICE_TCI6636K2H_JTAG_ID_VAL)
+ {
+ MAGIC_ADDR = 0x8ffffc;
+ flag_k2k = 1;
+ }
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_CLASSCODE_REVID), 0x04800001); /* class 0x04, sub-class 0x80, Prog I/F 0x00, Other multimedia device */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_LINK_STAT_CTRL), 0x10110080); /* extended sync, slot_clk_cfg = 1 */
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_VENDER_DEVICE_ID), 0xb005104c); /* Vendor and Device ID */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_DEVICE_CAP), 0x288701); /* L0 = 4, L1 = 3 */
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_OB_SIZE), 0x00000003); /* OB_SIZE = 8M */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_PL_GEN2), 0x0000000F); /* num_fts = 0xF*/
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0020); /* Set dbi_cs2 to allow access to the BAR registers */
+
+ if (flag_k2k) {
+ /* TCI6634K2K TBD */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR0), 0x00000FFF); /* 4K */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR1), 0x000FFFFF); /* 1M */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR2), 0x001FFFFF); /* 2M */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR3), 0x00FFFFFF); /* 16M */
+ }
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0); /* dbi_cs2=0 */
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_STATUS_CMD), 0x00100146); /* ENABLE mem access */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_DEV_STAT_CTRL), 0x0000281F); /* Error control */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_ACCR), 0x000001E0); /* Error control */
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_BAR0), 0); /* non-prefetch, 32-bit, mem bar */
+
+ DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_APP_CMD_STATUS), 0x0000007); /* enable LTSSM, IN, OB */
+ while((DEVICE_REG32_R(PCIE_BASE_ADDR + PCIE_DEBUG0) & 0x11)!=0x11); /* Wait for training to complete */
+
+ /* Wait for the Boot from Host */
+ DEVICE_REG32_W(MAGIC_ADDR, 0);
+ waitForBoot(MAGIC_ADDR);
+
+ /* Will never reach here */
+ return;
+}
+
+#endif
+
+#define FPGA_BM_GPI_STATUS_LO_REG 4 /* Boot Mode GPI Status (07-00 Low Byte) Register */
+#define FPGA_BM_GPI_STATUS_HI_REG 5 /* Boot Mode GPI Status (15-08 High Byte) Register */
+#define FPGA_ICS557_SEL_CTRL_REG 0x50 /* ICS 557 Clock Selection
+ Control Register*/
+#define FPGA_READ_REG_CMD(x) ((x | 0x80) << 8)
+#define FPGA_WRITE_REG_CMD(addr,byte) (((addr & 0x7f) << 8) | (byte & 0xff))
+
+/**
+ * @brief
+ * Enter the ROM boot loader if the FPGA boot register
+ * indicates it was not I2C address 0x51 boot, this is necessary
+ * to apply the PLL workaround for non-I2C boot modes
+ */
+void iblEnterRom ()
+{
+ uint32 v, dev_stat, bm_lo, bm_hi;
+ void (*exit)();
+
+ /* Power up the SPI */
+ devicePowerPeriph (TARGET_PWR_SPI);
+
+ /* Reset SPI */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
+
+ /* Release Reset */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_ENABLE);
+
+ /* CS1, CLK, in and out are functional pins, FPGA uses SPI CS1 */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIPC0, 0xe02);
+
+ /* prescale=7, char len=16 */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIFMT(0), 0x710);
+
+ /* C2TDELAY=0x6, T2CDELAY=0x3 */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIDELAY, 0x6030000);
+
+ /* Clear the SPIDAT0 */
+ //DEVICE_REG32_R (DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0);
+
+ /* Master mode, enable SPI */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR1, 0x01000003);
+
+ /* Read the BM status lo register */
+ DEVICE_REG32_W(DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0, FPGA_READ_REG_CMD(FPGA_BM_GPI_STATUS_LO_REG));
+ chipDelay32(10000);
+ v = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIFLG);
+ if ( v & 0x100)
+ {
+ bm_lo = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIBUF) & 0xff;
+ }
+ else
+ {
+ return;
+ }
+
+ /* Read the BM status hi register */
+ DEVICE_REG32_W(DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0, FPGA_READ_REG_CMD(FPGA_BM_GPI_STATUS_HI_REG));
+ chipDelay32(10000);
+ v = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIFLG);
+ if ( v & 0x100)
+ {
+ bm_hi = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIBUF) & 0xff;
+ }
+ else
+ {
+ return;
+ }
+
+
+ if ( (BOOT_READ_BITFIELD(bm_lo,3,1) != 0x5) ||
+ (BOOT_READ_BITFIELD(bm_hi,3,3) == 0x0) )
+ {
+ /* Not i2c boot or i2c boot with address 0x50 */
+
+ /* Update the DEVSTAT to v1 */
+ dev_stat = DEVICE_REG32_R(DEVICE_REG_DEVSTAT );
+ dev_stat &= ~(0x0000080E);
+ dev_stat |= ((bm_hi << 8) | bm_lo);
+
+ /* Update the DEVSTAT register for the intended Boot Device and i2c Addr */
+ DEVICE_REG32_W (DEVICE_REG_DEVSTAT, dev_stat);
+
+#ifdef IBL_ENABLE_PCIE_WORKAROUND /* TBD */
+#define BOOT_DEVICE_MASK 0xE
+#define DEVSTAT_BOOTDEVICE_SHIFT 1
+#define PCI_BOOT_MODE 0x4
+
+ if (((dev_stat & BOOT_DEVICE_MASK)>>DEVSTAT_BOOTDEVICE_SHIFT) == PCI_BOOT_MODE) {
+ /* Write ICS 557 Clock Selection Control Register in the FPGA */
+ /* 1 : FPGA_ICS557_SEL s driven high */
+ DEVICE_REG32_W(DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0,
+ FPGA_WRITE_REG_CMD(FPGA_ICS557_SEL_CTRL_REG,1));
+ chipDelay32(10000);
+ /* Reset SPI */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
+
+ iblPCIeWorkaround();
+ /* Will never reach here */
+ }
+#endif
+ /* Reset SPI */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
+
+ exit = (void (*)())BOOT_ROM_ENTER_ADDRESS;
+ (*exit)();
+ }
+ else
+ {
+ /* Update the DEVSTAT register for the actual boot configuration */
+ DEVICE_REG32_W (DEVICE_REG_DEVSTAT, ((bm_hi << 8) | bm_lo));
+ }
+
+ /* Reset SPI */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
+}
+
+#if (!defined(EXCLUDE_NOR_SPI) || !defined(EXCLUDE_NAND_SPI))
+/**
+ * @brief
+ * Return the default hardware configuration for SPI. If this information
+ * is available in the boot ROM it is used, otherwise defaults are used.
+ */
+void deviceLoadInitSpiConfig (void *vcfg)
+{
+ uint32 v;
+
+ spiConfig_t *cfg = (spiConfig_t *)vcfg;
+
+ BOOT_PARAMS_COMMON_T *params;
+ BOOT_PARAMS_SPI_T *spip;
+
+ v = *((Uint32 *)DEVICE_JTAG_ID_REG);
+ v &= DEVICE_JTAG_ID_MASK;
+
+ if (v == DEVICE_TCI6636K2H_JTAG_ID_VAL)
+ params = (BOOT_PARAMS_COMMON_T *)ROM_BOOT_PARAMS_ADDR_TCI6634K2K;
+
+ /* SPI_ROM is a constant defined during make which enables the use of the
+ * parameters from the ROM boot loader */
+ if ((SPI_ROM == 1) && (params->boot_mode == BOOT_MODE_SPI)) {
+
+ spip = (BOOT_PARAMS_SPI_T *)params;
+
+ cfg->port = 0;
+ cfg->mode = spip->mode;
+ cfg->addrWidth = spip->addrWidth;
+ cfg->npin = spip->nPins;
+ cfg->csel = spip->csel;
+ cfg->c2tdelay = spip->c2tdelay;
+
+ v = (UINT32)spip->cpuFreqMhz * 1000; /* CPU frequency in kHz */
+ v = v / (DEVICE_SPI_MOD_DIVIDER * (((UINT32)(spip->busFreqMhz) * 1000) + spip->busFreqKhz));
+
+ if (v > DEVICE_SPI_MAX_DIVIDER)
+ v = DEVICE_SPI_MAX_DIVIDER;
+
+ cfg->clkdiv = v;
+
+ } else {
+
+ cfg->port = 0;
+ cfg->mode = SPI_MODE;
+ cfg->addrWidth = SPI_ADDR_WIDTH;
+ cfg->npin = SPI_NPIN;
+ cfg->csel = SPI_CSEL;
+ cfg->c2tdelay = SPI_C2TDEL;
+ cfg->clkdiv = SPI_CLKDIV;
+
+ }
+
+}
+#endif
+
diff --git a/src/device/c66xk2x/c66xk2xutil.c b/src/device/c66xk2x/c66xk2xutil.c
--- /dev/null
@@ -0,0 +1,212 @@
+/*
+ *
+ * Copyright (C) 2010-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @file c66xk2xutil.c
+ *
+ * @brief
+ * c66xk2x functions used by both the ibl and utility programs
+ */
+
+#include "device.h"
+#include "target.h"
+#include "pllapi.h"
+#include "types.h"
+
+/**
+ * @brief
+ * Configure the predivider for the main PLL, which resides outside the PLL controller
+ */
+SINT16 chipPllSetExternalPrediv(UINT16 pllNum, UINT32 predivRegVal)
+{
+ UINT32 reg;
+
+ reg = DEVICE_REG32_R (DEVICE_MAIN_PLL_CTL_0);
+ reg = BOOT_SET_BITFIELD(reg, predivRegVal, 5, 0);
+ DEVICE_REG32_W (DEVICE_MAIN_PLL_CTL_0, reg);
+
+
+ return (0);
+
+} /* chipPllSetExternalPrediv */
+
+
+/**
+ * @brief
+ * Configure the bandwidth adjustment for the main PLL, which resides outside the PLL controller
+ */
+SINT16 chipPllExternalBwAdj (UINT16 pllNum, UINT16 mult)
+{
+ UINT32 reg;
+ UINT32 bwAdj;
+
+ bwAdj = (mult >> 1) - 1;
+
+ reg = DEVICE_REG32_R (DEVICE_MAIN_PLL_CTL_0);
+ reg = BOOT_SET_BITFIELD(reg, bwAdj & 0x00ff, 31, 24);
+ DEVICE_REG32_W (DEVICE_MAIN_PLL_CTL_0, reg);
+
+ reg = DEVICE_REG32_R (DEVICE_MAIN_PLL_CTL_1);
+ reg = BOOT_SET_BITFIELD(reg, bwAdj >> 8, 3, 0);
+ DEVICE_REG32_W (DEVICE_MAIN_PLL_CTL_1, reg);
+
+ return (0);
+
+} /* chipPllExternalBwAdj */
+
+
+/**
+ * @brief
+ * Configure the multiplier fields for the main PLL which reside outside the PLL controller
+ */
+UINT32 chipPllExternalMult (UINT16 pllNum, UINT16 mult)
+{
+ UINT32 pmult;
+ UINT32 reg;
+ UINT32 v;
+
+
+ pmult = mult-1;
+
+ v = BOOT_READ_BITFIELD(pmult, 12, 6);
+
+
+ reg = DEVICE_REG32_R (DEVICE_MAIN_PLL_CTL_0);
+ reg = BOOT_SET_BITFIELD(reg, v, 18, 12);
+ DEVICE_REG32_W (DEVICE_MAIN_PLL_CTL_0, reg);
+
+
+ v = BOOT_READ_BITFIELD(pmult, 5, 0);
+
+ return (v);
+
+} /* chipPllExternalMult */
+
+/**
+ * @brief return the PSC module number for SPI
+ */
+int32 deviceSpiPscNum (void)
+{
+ uint32 v;
+
+ /* SPI is module number 3 for c66xk2x devices. the SPI is in the
+ * always on domain */
+ v = *((Uint32 *)DEVICE_JTAG_ID_REG);
+ v &= DEVICE_JTAG_ID_MASK;
+ if (v == DEVICE_TCI6636K2H_JTAG_ID_VAL)
+ return (TARGET_SPI_EMIF_TCI6634K2K);
+
+ return (-1); /* A negative number indicates the always on domain */
+}
+
+/**
+ * @brief Power up a peripheral
+ *
+ * @details
+ * Boot peripherals are powered up
+ */
+int32 devicePowerPeriph (int32 modNum)
+{
+ int32 ret;
+
+ /* If the input value is < 0 there is nothing to power up */
+ if (modNum < 0)
+ return (0);
+
+
+ if (modNum >= TARGET_PWR_MAX_MOD)
+ return (-1);
+
+
+ /* Note that if the sgmii power enable is requested the PA must be
+ * powered up first */
+ if (modNum == TARGET_PWR_ETH(x)) {
+ ret = (int32)pscEnableModule (TARGET_PWR_PA);
+ if (ret != 0)
+ return (ret);
+ }
+
+ return ((int32)pscEnableModule(modNum));
+
+}
+
+#ifdef PLL_REINIT_WORKAROUND
+/**
+ * @brief Simple DDR3 test
+ *
+ * @details
+ * This function performs a simple DDR3 test for a memory range
+ * specified below and returns -1 for failure and 0 for success.
+ */
+
+
+UINT32 ddr3_memory_test (void)
+{
+ UINT32 index, value;
+
+ /* Write a pattern */
+ for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+ *(VUint32 *) index = (UINT32)index;
+ }
+
+ /* Read and check the pattern */
+ for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+
+ value = *(UINT32 *) index;
+
+ if (value != index) {
+ return -1;
+ }
+ }
+
+ /* Write a pattern for complementary values */
+ for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+ *(VUint32 *) index = (UINT32)~index;
+ }
+
+ /* Read and check the pattern */
+ for (index = DDR3_TEST_START_ADDRESS; index < DDR3_TEST_END_ADDRESS; index += 4) {
+
+ value = *(UINT32 *) index;
+
+ if (value != ~index) {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+#endif
+
diff --git a/src/device/c66xk2x/target.h b/src/device/c66xk2x/target.h
--- /dev/null
@@ -0,0 +1,428 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/**************************************************************************
+ * FILE PURPOSE: Target specific definitions
+ **************************************************************************
+ * FILE NAME: target.h
+ *
+ * DESCRIPTION: This file defines target specific values used by low level
+ * drivers.
+ *
+ * @file target.h
+ *
+ * @brief
+ * Low level target specific values are defined
+ *
+ ***************************************************************************/
+#ifndef _TARGET_H
+#define _TARGET_H
+#include "types.h"
+
+
+/**
+ * @brief
+ * Device EMAC definitions
+ */
+
+
+/**
+ * @brief
+ * Device Timer definitions
+ */
+#define TIMER0_BASE 0x02200000u
+
+#define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
+
+
+/**
+ * @def MAIN_PLL
+ */
+#define MAIN_PLL 0 /**< The index to the main PLL */
+
+/**
+ * @def NET_PLL
+ */
+#define NET_PLL 1 /**< The index to the network PLL */
+
+/**
+ * @def DDR_PLL
+ */
+#define DDR_PLL 2 /**< The index to the DDR PLL */
+
+
+/**
+ * @brief
+ * Device PLL definitions
+ */
+#define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x2310000 : ((x) == NET_PLL ? 0x2620358 : 0x2620360))
+#define DEVICE_MAIN_PLL_CTL_0 0x2620350
+#define DEVICE_MAIN_PLL_CTL_1 0x2620354
+
+
+/**
+ * @brief
+ * The c66x devices use a register external to the PLL controller for prediv configuration
+ */
+#define chipPllExternalPrediv(x) TRUE
+
+/**
+ * @brief
+ * Device PSC definitions
+ */
+#define DEVICE_PSC_BASE 0x2350000u
+
+/**
+ * @brief
+ * The SPI module base and module divider
+ */
+#define DEVICE_SPI_BASE(x) 0x21000400u
+#define DEVICE_SPI_MOD_DIVIDER 6
+#define DEVICE_SPI_MAX_DIVIDER 0xff
+
+/**
+ * @brief
+ * The PSC number for the PA sub-system */
+#define TARGET_PWR_PA 7
+
+/**
+ * @brief
+ * The PSC number for the SGMII */
+#define TARGET_PWR_ETH(x) 8
+
+/**
+ * @brief
+ * The PSC numbers for EMIF16 and SPI vary between devices. The devices are run time
+ * identified by reading the JTAG ID register,
+ * NOTE: Have the variant bits as zero while defining the JTAG ID
+ */
+#define DEVICE_C6657_JTAG_ID_VAL 0xb97a02f /* C6657 */
+#define DEVICE_C6678_JTAG_ID_VAL 0x9e02f /* C6678 */
+#define DEVICE_C6670_JTAG_ID_VAL 0xb94102f /* C6670 */
+#define DEVICE_TCI6636K2H_JTAG_ID_VAL 0xb58102f /* TCI6636K2H */
+
+#define DEVICE_JTAG_ID_REG 0x2620018
+#define DEVICE_JTAG_ID_MASK 0x0fffffff /* exclude variant bits(31:28) */
+
+
+/**
+ * @brief
+ * The PSC number for NAND depends on the device
+ */
+#define TARGET_PWR_EMIF deviceEmifPscNum()
+#define TARGET_PWR_EMIF_TCI6634K2K 3
+
+/*
+ * @brief
+ * The PSC number for SPI depends on the device
+ */
+#define TARGET_PWR_SPI deviceSpiPscNum()
+#define TARGET_SPI_EMIF_TCI6634K2K 3
+
+/**
+ * @brief
+ * The PSC number for GPIO. GPIO is in the always on domain
+ */
+#define TARGET_PWR_GPIO -1
+
+/**
+ * @brief
+ * The LPSC number for PCIe. PCIe is 10 for C6678/C6770
+ */
+#define TARGET_PWR_PCIE 10
+
+/**
+ * @brief
+ * Flag to indicate timer 0 power up requested. The time is always on in the 6472
+ */
+#define TARGET_PWR_TIMER_0 -1
+
+/**
+ * @brief
+ * Device DDR controller definitions
+ */
+#define DEVICE_EMIF4_BASE 0x21000000
+/* TBD: #define DEVICE_EMIF4_BASE(x) (0x21010000 + (0x10000 * (x))) */
+#define targetEmifType() ibl_EMIF_TYPE_40
+
+/**
+ * @brief
+ * Device EMIF 2.5 controller definitions
+ */
+#define DEVICE_EMIF25_BASE 0x21000A00
+
+/**
+ * @brief
+ * NAND memory regions
+ */
+#define TARGET_MEM_NAND_CS_2 0x30000000
+#define TARGET_MEM_NAND_CS_3 0x34000000
+#define TARGET_MEM_NAND_CS_4 0x38000000
+#define TARGET_MEM_NAND_CS_5 0x3c000000
+uint32 deviceNandMemBase (int32 cs);
+#define TARGET_SHFL(x) _shfl(x) /* The shuffle intrinsic */
+
+
+/**
+ * @brief
+ * The highest module number. The value for nyquist is used
+ */
+#define TARGET_PWR_MAX_MOD 52
+
+
+/**
+ * @brief
+ * The base address of MDIO
+ */
+#define TARGET_MDIO_BASE 0x2090300
+
+/**
+ * @brief
+ * The number of external ethernet ports
+ */
+#define TARGET_EMAC_N_PORTS 2
+
+/**
+ * @brief
+ * GPIO address
+ */
+#define GPIO_CFG_BASE 0x260BF00
+#define GPIO_GPIOPID_REG (GPIO_CFG_BASE + 0x0)
+#define GPIO_GPIOEMU_REG (GPIO_CFG_BASE + 0x4)
+#define GPIO_BINTEN_REG (GPIO_CFG_BASE + 0x8)
+#define GPIO_DIR_REG (GPIO_CFG_BASE + 0x10)
+#define GPIO_OUT_DATA_REG (GPIO_CFG_BASE + 0x14)
+#define GPIO_SET_DATA_REG (GPIO_CFG_BASE + 0x18)
+#define GPIO_CLEAR_DATA_REG (GPIO_CFG_BASE + 0x1c)
+#define GPIO_IN_DATA_REG (GPIO_CFG_BASE + 0x20)
+#define GPIO_SET_RIS_TRIG_REG (GPIO_CFG_BASE + 0x24)
+#define GPIO_CLR_RIS_TRIG_REG (GPIO_CFG_BASE + 0x28)
+#define GPIO_SET_FAL_TRIG_REG (GPIO_CFG_BASE + 0x2c)
+#define GPIO_CLR_FAL_TRIG_REG (GPIO_CFG_BASE + 0x30)
+
+/**
+ * @brief
+ * The base address of the I2C peripheral, and the module divisor of the cpu clock
+ */
+#define DEVICE_I2C_BASE 0x02530000
+#define DEVICE_I2C_MODULE_DIVISOR 6
+
+/**
+ * @brief
+ * The address of the DEVSTAT register
+ */
+#define DEVICE_REG_DEVSTAT 0x02620020
+
+/**
+ * @brief
+ * Prototypes for the PLL functions handled outside the main PLL registers
+ */
+SINT16 chipPllSetExternalPrediv(UINT16 pllNum, UINT32 predivRegVal);
+SINT16 chipPllExternalBwAdj (UINT16 pllNum, UINT16 mult);
+UINT32 chipPllExternalMult (UINT16 pllNum, UINT16 mult);
+
+
+/**
+ * @brief
+ * Hardware network subsystem support, ethernet switch
+ */
+#define DEVICE_CPSW
+#define DEVICE_CPSW_NUM_PORTS 5 /* 3 switch ports */
+#define DEVICE_CPSW_BASE (0x02090800)
+#define targetGetSwitchCtl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
+#define targetGetSwitchMaxPktSize() 9000
+
+#define DEVICE_QM
+#define DEVICE_QM_MANAGER_BASE 0x02A02000
+#define DEVICE_QM_DESC_SETUP_BASE 0x02A03000
+#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02A80000
+#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02AC0000
+#define DEVICE_QM_QUEUE_STATUS_BASE 0x02A40000
+
+/* QM base address register */
+#define DEVICE_QM1_QUEUE_MANAGEMENT_REGS(x) (0x23A00000 + 0x80000 + 0x10000*(x))
+#define DEVICE_QM2_QUEUE_MANAGEMENT_REGS(x) (0x23A00000 + 0xA0000 + 0x10000*(x))
+
+#define DEVICE_QM_NUM_LINKRAMS 2
+#define DEVICE_QM_NUM_MEMREGIONS 20
+void *targetGetQmConfig(void);
+void targetInitQs (void);
+
+#define chipLmbd(x,y) _lmbd(x,y)
+
+
+
+
+#define DEVICE_CPDMA
+
+#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
+#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
+#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
+#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
+
+#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
+#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
+#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
+
+
+#define DEVICE_QM_FREE_Q 910
+#define DEVICE_QM_LNK_BUF_Q 911
+#define DEVICE_QM_RCV_Q 912
+#define DEVICE_QM_TX_Q 913
+#define DEVICE_QM_PA_CFG_Q 640
+#define DEVICE_QM_ETH_TX_Q 648
+
+#define DEVICE_RX_CDMA_TIMEOUT_COUNT 1000
+
+
+
+#define DEVICE_PA
+#define DEVICE_PA_BASE 0x02000000
+#define DEVICE_PA_NUM_PDSPS 6
+#define DEVICE_PA_RUN_CHECK_COUNT 100 /* Number of loops to verify PA firmware is running */
+#define DEVICE_PA_PLL_BASE 0x02620338
+#define chipLower8(x) ((x) & 0x00ff)
+
+
+#define TARGET_SGMII_EXTERNAL_SERDES
+#define TARGET_SGMII_TYPE_2 /* Use second sgmii setup sequence */
+#define TARGET_SGMII_BASE_ADDRESSES { 0x02090100, 0x02090200 }
+#define TARGET_SGMII_SERDES_BASE 0x2620340
+#define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
+#define TARGET_SGMII_SOFT_RESET 0x04
+#define TARGET_SGMII_CONTROL 0x10
+#define TARGET_SGMII_MR_ADV_ABILITY 0x18
+void targetSgmiiSerdesConfig (int32 port, void *cfg);
+#define chipKickOpenSerdes(x) *((uint32 *)0x2620038) = 0x83e70b13; *((uint32 *)0x262003c) = 0x95a4f1e0
+#define chipKickClosedSerdes(x) ; /* never lock the registers */
+#define TARGET_SERDES_LOCK_DELAY (1600*1000)
+
+#define DEVICE_EMACSL_BASE(x) (0x02090900 + (x)*0x040)
+#define DEVICE_N_GMACSL_PORTS 2
+#define DEVICE_EMACSL_RESET_POLL_COUNT 100
+Int32 targetMacSend (void *ptr_device, Uint8* buffer, int num_bytes);
+Int32 targetMacRcv (void *ptr_device, UINT8 *buffer);
+
+#define DEVICE_SS
+#define DEVICE_PSTREAM_CFG_REG_ADDR 0x2000604
+#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0 0
+#define hwConfigStreamingSwitch() DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0);
+
+#define ECC_BLOCK_SIZE 256
+
+/* NAND address pack macro */
+#define PACK_ADDR(col, page, block) \
+ ((col & 0x000000ff) | ((page & 0x0000001f) << 9) | ((block & 0x00000fff) << 14))
+
+/**
+ * @brief
+ * Register access macros
+ */
+#define DEVICE_REG32_W(x,y) *(volatile unsigned int *)(x)=(y)
+#define DEVICE_REG32_R(x) (*(volatile unsigned int *)(x))
+
+#define BOOTBITMASK(x,y) ( ( ( ((UINT32)1 << (((UINT32)x)-((UINT32)y)+(UINT32)1) ) - (UINT32)1 ) ) << ((UINT32)y) )
+#define BOOT_READ_BITFIELD(z,x,y) (((UINT32)z) & BOOTBITMASK(x,y)) >> (y)
+#define BOOT_SET_BITFIELD(z,f,x,y) (((UINT32)z) & ~BOOTBITMASK(x,y)) | ( (((UINT32)f) << (y)) & BOOTBITMASK(x,y) )
+
+/**
+ * @brief
+ * Mpax configuration registers
+ */
+#define DEVICE_REG_XMPAX_L(x) *((volatile unsigned int *)(0x08000000 + (8*(x))))
+#define DEVICE_REG_XMPAX_H(x) *((volatile unsigned int *)(0x08000004 + (8*(x))))
+
+
+/**
+ * @brief
+ * ROM boot loader boot modes and table locations
+ */
+#define BOOT_MODE_I2C 40
+#define BOOT_MODE_SPI 50
+
+
+#define ROM_BOOT_PARAMS_ADDR_TCI6634K2K 0x8fff00
+
+/**
+ * @brief
+ * No device specific configuration required for NOR boot, so
+ * the function call is defined to return success.
+ */
+#define deviceConfigureForNor() 0
+
+
+/****************************************************************
+ *
+ * NOTE: Following build flags enable DEVICE specific workarounds
+ * and have code which is specific to C6670/C6678 LC EVMs
+ *
+ ****************************************************************/
+
+/**
+ * @brief
+ * Support for PLL workaround to re-enter ROM boot loader.
+ */
+#define IBL_ENTER_ROM 0
+
+/**
+ * @brief
+ * Support for enabling EDC for internal memory.
+ */
+#define IBL_ENABLE_EDC 1
+
+/**
+ * @brief
+ * Support for enabling PCIe workarond for C6678/C6670.
+ */
+/* #define IBL_ENABLE_PCIE_WORKAROUND 1 TBD */
+
+/**
+ * @brief
+ * DDR start and end address needed for DDR memory test
+ */
+#define DDR3_TEST_START_ADDRESS 0x80000000
+#define DDR3_TEST_END_ADDRESS (DDR3_TEST_START_ADDRESS + (128 *1024))
+
+/**
+ * @brief
+ * Software workaround for DDR3 memory corruption is to re-init the PLL's and DDR controller. This flag enables the workaround
+ */
+#define PLL_REINIT_WORKAROUND
+
+UINT32 ddr3_memory_test();
+#endif /* _TARGET_H */
+
diff --git a/src/device/c66xk2x/tiboot_c66xk2x.h b/src/device/c66xk2x/tiboot_c66xk2x.h
--- /dev/null
@@ -0,0 +1,946 @@
+/*
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+#ifndef __TIBOOT_H__
+#define __TIBOOT_H__
+
+#include "types.h"
+
+/*******************************************************************************
+ * Utility Macro definitions
+ ******************************************************************************/
+#define HEX_DIGIT(digit) ((digit) + '0')
+#define BOOT_BIT_TO_MASK(bit) (1 << (bit))
+
+/*******************************************************************************
+ * Data Definition: Error Handling relatBOOT_ENTRY_POINT_ADDRed definition:
+ *******************************************************************************
+ * Description: Define Handling related macros, constants
+ *
+ ******************************************************************************/
+/* Define Module IDs */
+#define BOOT_MODULE_ID_MAIN 0
+#define BOOT_MODULE_ID_BTBL 1
+#define BOOT_MODULE_ID_BETH 2
+#define BOOT_MODULE_ID_I2C 3
+#define BOOT_MODULE_ID_CHIP 4
+#define BOOT_MODULE_ID_HW 5
+
+/* Boot error codes */
+enum {
+ BOOT_NOERR = 0,
+ BOOT_GEN_ERROR = 1, /* General error */
+ BOOT_INVALID_BOOT_MODE = 2,
+ BOOT_INVALID_I2C_DEV_ADDR = 3,
+ BOOT_INVALID_CHECKSUM = 4, /* Invalid checksum of the boot parameters */
+ BOOT_INVALID_PARAMS_SIZE = 5, /* the size of boot parameters is too big */
+ BOOT_RX_ETH_QUEUE_FULL = 6, /* ethmain.c, hw_rxPacket */
+ BOOT_CACHE_INIT_FAIL = 7, /* rmain.c, cache init failed */
+ BOOT_CACHE_DISABLE_FAIL = 8, /* rmain.c, cache disable failed */
+ BOOT_INVALID_CPPI_SIZE = 9, /* ethmain.c, invalid compile sizes */
+ BOOT_INVALID_CORE_ID = 10, /* Invalid core ID in cold boot */
+ BOOT_INVALID_MAC_ADDR = 11, /* Invalid MAC address (all 0's) */
+ BOOT_ETH_TX_SCRATCH = 12, /* tx scratch size invalid */
+ BOOT_ETH_TX_PACKET = 13, /* tx packet formation failure */
+ BOOT_ETH_MAC_INIT = 14, /* ethmain.c - mac init failed */
+ BOOT_PERIPH_POWER = 15, /* peripheral failed to powerup */
+ BOOT_MAIN_FAIL = 16, /* Failed in initial boot setup (wrong core) */
+ BOOT_SK_REGISTERSCWP = 17, /* Failed at SK_registerSCWP */
+ BOOT_SK_ALLOCSC = 18, /* Failed at SK_allocSC */
+ BOOT_CPSGMII_CONFIGINDEX = 19, /* Failed at wrong CPSGMII config index */
+ BOOT_SRIO_CONFIGINDEX = 20, /* Failed at wrong SRIO config index */
+ BOOT_RETURN_FROM_CHAIN = 21, /* Code returned from boot main chaining, should never happen */
+ BOOT_INVALID_HIB_ADDR = 22 /* Invalid hibernation return address */
+};
+
+/* Error tracking prototypes (functions in rmain.c)*/
+void bootException (UINT16 errorCode);
+void bootError (UINT16 errorCode);
+
+/* Error code = (module ID * 100) + module specific error */
+#define BOOT_ERROR_CODE(id, code) ((UINT16)((id<<8) + code))
+#define BOOT_EXCEPTION(error_code) bootException(error_code)
+#define BOOT_ERROR(error_code) bootError(error_code)
+
+/*******************************************************************************
+ * Begin Boot Parameter definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Boot Parameter Common
+ ******************************************************************************/
+typedef struct boot_params_common_s{
+ UINT16 length; /* size of the entire boot parameters in bytes */
+ UINT16 checksum; /* non-zero: 1's complement checksum of the boot
+ * parameters
+ * zero: checksum is not applicable
+ */
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
+ UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
+
+ /* swPllCfg
+ *
+ * /----------------------------------------------------------------\
+ * | 31 30 | 29 16 | 15 8 | 7 0 |
+ * | PLL Ctl | multiplier | pre-divider | post divider |
+ * \----------------------------------------------------------------/
+ */
+
+#define BOOT_PARAMS_PLL_CFG_CTL_MASK 0xc000
+#define BOOT_PARAMS_PLL_CFG_CTL_SHIFT 14
+
+#define BOOT_PARAMS_PLL_CFG_CTL_NO_INIT 0 /* Pll is not initialized */
+#define BOOT_PARAMS_PLL_CFG_CTL_INIT_CONDITIONAL 1 /* Initialize only if PLL is currently disabled or in bypass */
+#define BOOT_PARAMS_PLL_CFG_CTL_INIT 2 /* Initialize PLL regardless of current PLL state */
+#define BOOT_PARAMS_PLL_CFG_CTL_BYPASS 3 /* Put the PLL into bypass */
+
+
+#define BOOT_PARAMS_PLL_CFG_MSW_MULT_MASK 0x3fff
+#define BOOT_PARAMS_PLL_CFG_MSW_MULT_SHIFT 0
+
+#define BOOT_PARAMS_PLL_CFG_LSW_PREDIV_MASK 0xff00
+#define BOOT_PARAMS_PLL_CFG_LSW_PREDIV_SHIFT 8
+
+#define BOOT_PARAMS_PLL_CFG_LSW_POSTDIV_MASK 0x00ff
+#define BOOT_PARAMS_PLL_CFG_LSW_POSTDIV_SHIFT 0
+
+} BOOT_PARAMS_COMMON_T;
+
+typedef struct boot_params_ethernet_s{
+
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
+ UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
+
+ /* Etherent specific portion of the Boot Parameters */
+ UINT16 options;
+ /*
+ * Ethernet Specific Options
+ *
+ * Bits 2:0 interface
+ * 000 - MII
+ * 001 - RMII
+ * 010 - GMII
+ * 011 - RGMII
+ * 100 - SMII
+ * 101 - S3MII
+ * 110 - RMII 10Mbs
+ * 111 - RMII 100Mbs
+ *
+ * Bit 3: HD:
+ * 0 - Full Duplex
+ * 1 - Half Duplex
+ * Bit 4: SKIP TX
+ * 0 - Send the Ethernet Ready Frame
+ * 1 - Skip sending the Ethernet Ready Frame
+ * Bits 6:5 - Ethernet Initialization
+ * 00 - Entire system configured
+ * 01 - No initialization of peripherals that are already enabled and running
+ * 10 - Reserved
+ * 11 - No initialization at all
+ *
+ * Other bits: Reserved
+ */
+ #define BOOT_PARAMS_ETH_OPTIONS_MII 0x0000
+ #define BOOT_PARAMS_ETH_OPTIONS_RMII 0x0001
+ #define BOOT_PARAMS_ETH_OPTIONS_GMII 0x0002
+ #define BOOT_PARAMS_ETH_OPTIONS_RGMII 0x0003
+ #define BOOT_PARAMS_ETH_OPTIONS_SMII 0x0004
+ #define BOOT_PARAMS_ETH_OPTIONS_S3MII 0x0005
+ #define BOOT_PARAMS_ETH_OPTIONS_RMII_10 0x0006
+ #define BOOT_PARAMS_ETH_OPTIONS_RMII_100 0x0007
+
+ /* Faraday only supports SGMII */
+ #define BOOT_PARAMS_ETH_OPTIONS_SGMII 0x0006
+
+ #define BOOT_PARAMS_ETH_OPTIONS_HD 0x0008
+ #define BOOT_PARAMS_ETH_OPTIONS_SKIP_TX 0x0010
+
+ #define BOOT_PARAMS_ETH_OPTIONS_INIT_MASK 0x0060
+ #define BOOT_PARAMS_ETH_OPTIONS_INIT_SHIFT 5
+ #define BOOT_PARAMS_ETH_OPTIONS_INIT(x) (((x) & BOOT_PARAMS_ETH_OPTIONS_INIT_MASK) >> BOOT_PARAMS_ETH_OPTIONS_INIT_SHIFT)
+
+ #define BOOT_PARAMS_ETH_OPTIONS_INIT_FULL 0
+ #define BOOT_PARAMS_ETH_OPTIONS_INIT_PARTIAL 1
+ #define BOOT_PARAMS_ETH_OPTIONS_INIT_NONE 3
+
+ /*
+ * he device MAC address to be used for Boot:
+ * All zero mac address indicates that the device E-fuse address should
+ * be used.
+ */
+ UINT16 mac_addr_h;
+ UINT16 mac_addr_m;
+ UINT16 mac_addr_l;
+
+ /*
+ * The multicast or broadcast MAC address which should be accepted as
+ * a destination MAC address for boot table frames
+ */
+ UINT16 mmac_addr_h;
+ UINT16 mmac_addr_m;
+ UINT16 mmac_addr_l;
+
+ UINT16 src_port; /* Source UDP port number to be used during boot process */
+ /* 0: allow any SRC UDP port */
+ UINT16 dest_port; /* Destination UDP port number to be used during boot process */
+
+ /* The Device ID to be included in the boot ready announcement frame */
+ UINT16 device_id_12;
+ UINT16 device_id_34;
+ #define BOOT_PARAMS_DEVICE_ID_HIGH_MASK 0xFF00
+ #define BOOT_PARAMS_DEVICE_ID_HIGH_SHIFT 8
+ #define BOOT_PARAMS_DEVICE_ID_LOW_MASK 0x00FF
+ #define BOOT_PARAMS_DEVICE_ID_LOW_SHIFT 0
+ #define BOOT_PARAMS_GET_DEVICE_ID_13(device_id) \
+ (((device_id) & BOOT_PARAMS_DEVICE_ID_HIGH_MASK) > BOOT_PARAMS_DEVICE_ID_HIGH_SHIFT)
+ #define BOOT_PARAMS_GET_DEVICE_ID_24(device_id) \
+ (((device_id) & BOOT_PARAMS_DEVICE_ID_LOW_MASK) > BOOT_PARAMS_DEVICE_ID_LOW_SHIFT)
+
+ /*
+ * The destination MAC address used for the boot ready announce frame
+ */
+ UINT16 hmac_addr_h;
+ UINT16 hmac_addr_m;
+ UINT16 hmac_addr_l;
+
+ /*
+ * The CPSGMII configurations for Faraday
+ */
+
+ UINT16 sgmiiConfig;
+
+ #define BOOT_PARAMS_SGMII_CONFIG_INDEX_MASK 0x0F /* bit 3 to 0 is index */
+ #define BOOT_PARAMS_SGMII_CONFIG_DIRECT_CONFIG (1<<4) /* set to use direct configurations */
+ #define BOOT_PARAMS_SGMII_CONFIG_NO_CONFIG (1<<5) /* set to bypass CPSGMII config */
+
+ UINT16 sgmiiControl;
+ #define BOOT_PARAMS_SGMII_CONTROL_MASK 0x7F
+
+ UINT16 sgmiiMr_Adv_Ability;
+ #define BOOT_PARAMS_SGMII_ABILITY_MASK 0x0000FFFF
+
+ /* These registers are the serdes configuration registers */
+ UINT16 sgmiiTx_Cfg_h;
+ UINT16 sgmiiTx_Cfg_l;
+ UINT16 sgmiiRx_Cfg_h;
+ UINT16 sgmiiRx_Cfg_l;
+ UINT16 sgmiiAux_Cfg_h;
+ UINT16 sgmiiAux_Cfg_l;
+
+ UINT16 pktPllCfg_msw; /* Packet subsystem PLL configuration */
+ UINT16 pktPllCfg_lsw;
+
+} BOOT_PARAMS_ETHERNET_T;
+
+/**************************************************************************************
+ * Utopia boot options
+ **************************************************************************************/
+typedef struct boot_params_utopia_s{
+
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
+ UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
+
+ /* Utopia specific portion of the Boot Parameters */
+ /* Options
+ * ---------------------------------------------------------------
+ * | 15 3 | 2 | 1 | 0 |
+ * ----------------------------------------------------------------
+ * reserved | | \-> 0 = multi phy
+ * | | 1 = single phy
+ * | \-> 0 = 8 bit utopia
+ * | 1 = 16 bit utopis
+ * \-> 0 = Init port
+ * 1 = skip port init
+ */
+ UINT16 options;
+
+ #define BOOT_PARAMS_UTOPIA_SINGLE_PHY (1<<0)
+ #define BOOT_PARAMS_UTOPIA_16BIT (1<<1)
+ #define BOOT_PARAMS_UTOPIA_SKIP_INIT (1<<2)
+
+ UINT16 cellSizeBytes; /* Cell Size */
+ UINT16 busWidthBits; /* Bus width (8 or 16) */
+ UINT16 slid; /* Slave ID */
+ UINT16 coreFreqMhz; /* CPU frequency after pll mult */
+
+
+} BOOT_PARAMS_UTOPIA_T;
+
+typedef struct boot_params_i2c_s{
+
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
+ UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
+
+ /* I2C specific portion of the Boot Parameters */
+ UINT16 options;
+ /*
+ * I2C Specific Options
+ * Bit 01-00: BT:
+ * 00 - Boot Parameter Mode
+ * 01 - Boot Table Mode
+ * 10 - Boot Config mode
+ * 11 - Slave receive boot config
+ * Bit 04-02: EETYPE: EEPROM type
+ * Other bits: Reserved
+ */
+ #define BOOT_PARAMS_I2C_OPTIONS_BP 0x0000
+ #define BOOT_PARAMS_I2C_OPTIONS_BT 0x0001
+ #define BOOT_PARAMS_I2C_OPTIONS_BC 0x0002
+ #define BOOT_PARAMS_I2C_OPTIONS_SLVOPT 0x0003
+
+ #define BOOT_PARAMS_I2C_OPTIONS_MASK 0x0003
+ #define BOOT_PARAMS_I2C_OPTIONS_SHIFT 0
+
+ #define BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK 0x001C
+ #define BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT 2
+
+ #define BOOT_PARAMS_I2C_IS_BOOTTBL_MODE(options) \
+ (((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_BT)
+
+ #define BOOT_PARAMS_I2C_IS_BOOTCONFIG_MODE(options) \
+ (((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_BC)
+
+ #define BOOT_PARAMS_I2C_IS_SLAVE_RCV_OPTIONS_MODE(options) \
+ (((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_SLVOPT)
+
+ #define BOOT_PARAMS_I2C_IS_BOOTPARAM_MODE(options) \
+ (((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_BP)
+
+ #define BOOT_PARAMS_I2C_SET_BOOTTBL_MODE(options, mode) \
+ (options) = ((options) & ~BOOT_PARAMS_I2C_OPTIONS_MASK) | \
+ (((mode) & BOOT_PARAMS_I2C_OPTIONS_MASK) << \
+ BOOT_PARAMS_I2C_OPTIONS_SHIFT)
+
+
+ #define BOOT_PARAMS_I2C_GET_EETYPE(options) \
+ (((options) & BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK) >> BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT)
+ #define BOOT_PARAMS_I2C_SET_EETYPE(options, ee_type) \
+ (options) = (((options) & ~BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK) | \
+ (((ee_type) << BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT) & BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK))
+
+ /* The device address to be used for Boot */
+ UINT16 dev_addr; /* 16-bit device address (low) */
+ UINT16 dev_addr_ext; /* 16-bit extended device address (high)
+ * set to zero if not used
+ * Note: some I2C device requires 32-bit
+ * address
+ */
+ UINT16 multi_i2c_id; /* Multi device master write boot ID */
+ UINT16 my_i2c_id; /* This parts I2C address */
+
+ UINT16 core_freq_mhz; /* Core frequency, MHz */
+ UINT16 i2c_clk_freq_khz; /* Desired I2C clock frequency, kHz */
+
+ UINT16 next_dev_addr; /* Used only for the boot config mode. */
+ UINT16 next_dev_addr_ext; /* Copied into dev_addr* after config complete */
+
+ UINT16 address_delay; /* Rough number of cycles delay between address write
+ * and read to the i2c eeprom */
+
+
+} BOOT_PARAMS_I2C_T;
+
+
+typedef struct boot_params_rapidio_s{
+
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
+ UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
+
+ /* Options */
+ UINT16 options;
+
+ #define BOOT_PARAMS_RIO_OPTIONS_TX_ENABLE (1<<0) /* set to enable transmit */
+ #define BOOT_PARAMS_RIO_OPTIONS_BOOT_TABLE (1<<1) /* set to use boot tables */
+ #define BOOT_PARAMS_RIO_OPTIONS_NO_CONFIG (1<<2) /* set to bypass port config */
+ #define BOOT_PARAMS_RIO_OPTIONS_NO_QM_CONFIG (1<<3) /* set to bypass QM config */
+
+ UINT16 lane_port_setup; /* Lane port configuration */
+ #define BOOT_PARAMS_RIO_LPS_1X_1X_1X_1X 0 /* 4 ports 1 lane each */
+ #define BOOT_PARAMS_RIO_LPS_2X_1X_1X 1 /* 3 ports, lanes 0,1 are a 2 lane port */
+ #define BOOT_PARAMS_RIO_LPS_1X_1X_2X 2 /* 3 ports, lanes 2,3 are a 2 lane port */
+ #define BOOT_PARAMS_RIO_LPS_2X_2X 3 /* 2 ports, each 2 lanes */
+ #define BOOT_PARAMS_RIO_LPS_4X 4 /* 1 port of 4 lanes */
+
+ UINT16 cfg_index; /* The table of base configuration parameters */
+
+
+
+ UINT16 node_id; /* The node id for this device */
+ UINT16 serdes_ref_clk; /* The serdes reference clock freq, in hundredths
+ * of MHz (1 MHz would be 100) */
+ UINT16 link_rate; /* Data link rate (mega bits per second */
+ UINT16 pf_low; /* Packet forward range, low */
+ UINT16 pf_high; /* Packet forward range, high */
+
+} BOOT_PARAMS_RIO_T;
+
+
+typedef struct boot_params_pcie_s
+{
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
+ UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
+
+ UINT16 options;
+
+#define BOOT_PARAMS_PCIE_OPTIONS_COMPUTE_PLL_MASK (1 << 4)
+#define BOOT_PARAMS_PCIE_OPTIONS_COMPUTE_PLL (1 << 4)
+#define BOOT_PARAMS_PCIE_OPTIONS_NO_COMPUTE_PLL (0 << 4)
+
+#define BOOT_PARAMS_PCIE_OPTIONS_NO_INIT_MASK (1 << 1)
+#define BOOT_PARAMS_PCIE_OPTIONS_NO_INIT (1 << 1)
+#define BOOT_PARAMS_PCIE_OPTIONS_INIT (0 << 1)
+
+#define BOOT_PARAMS_PCIE_OPTIONS_BOOT_TABLE_MASK (1 << 0)
+#define BOOT_PARAMS_PCIE_OPTIONS_BOOT_TABLE (1 << 0)
+#define BOOT_PARAMS_PCIE_OPTIONS_HOST_BOOT (0 << 0)
+
+
+
+ UINT16 addressWidth; /* The PCI address width. Valid values are 32 or 64 */
+ UINT16 linkRateMhz; /* The serdes frequency. Valid values are 2500 and 5000 */
+ UINT16 refClock10kHz; /* The reference clock in 10kHz units. Valid values are 10000, 12500, 15625, 25000, 31250 */
+ UINT16 window0Size; /* Window 0 size, in units of megabytes */
+ UINT16 window1Size; /* Window 1 size */
+ UINT16 window2Size; /* Window 2 size. Valid only if the address width is 32 */
+ UINT16 window3Size; /* Window 3 size. Valid only if the address width is 32 */
+
+ UINT16 vendorId; /* Vendor ID field */
+ UINT16 deviceId; /* Device ID field */
+ UINT16 classCodeRevId_Msw; /* Class code rev ID, MSW */
+ UINT16 classCodeRevId_Lsw; /* Class code rev ID, LSW*/
+
+
+
+ UINT16 serdesCfgMsw; /* Serdes auxillary config, MSW */
+ UINT16 serdesCfgLsw; /* Serdes auxillary config, LSW */
+
+ UINT16 serdesCfgLane0Msw; /* Serdes Lane 0 config, MSW */
+ UINT16 serdesCfgLane0Lsw; /* Serdes Lane 0 config, LSW */
+
+ UINT16 serdesCfgLane1Msw; /* Serdes Lane 1 config, MSW */
+ UINT16 serdesCfgLane1Lsw; /* Serdes Lane 1 config, LSW */
+
+
+} BOOT_PARAMS_PCIE_T;
+
+
+typedef struct boot_params_emif_nor_s {
+ UINT16 waitEnable;
+} boot_params_emif_nor_t;
+
+
+typedef struct boot_params_emif_s
+{
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
+ UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
+
+ UINT16 options;
+
+ UINT16 type;
+#define BOOT_PARAMS_EMIF_TYPE_NOR 0
+
+ UINT16 branchAddrMsw;
+ UINT16 branchAddrLsw;
+
+ UINT16 csNum;
+ UINT16 memWidth;
+
+ union {
+ boot_params_emif_nor_t nor;
+ } u;
+
+} BOOT_PARAMS_EMIF_T;
+
+
+typedef struct boot_params_vusr_s
+{
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
+ UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
+
+ UINT16 options;
+#define BOOT_PARAMS_VUSR_OPTIONS_NO_INIT_MASK (1 << 1)
+#define BOOT_PARAMS_VUSR_OPTIONS_NO_INIT (1 << 1)
+#define BOOT_PARAMS_VUSR_OPTIONS_INIT (0 << 1)
+
+#define BOOT_PARAMS_VUSR_OPTIONS_BOOT_TABLE_MASK (1 << 0)
+#define BOOT_PARAMS_VUSR_OPTIONS_BOOT_TABLE (1 << 0)
+#define BOOT_PARAMS_VUSR_OPTIONS_HOST_BOOT (0 << 0)
+
+ UINT16 nLanes; /* The number of lanes to configure */
+
+ UINT16 serdesCfgMsw; /* Serdes auxillary config, MSW */
+ UINT16 serdesCfgLsw; /* Serdes auxillary config, LSW */
+
+ UINT16 serdesCfgRxLane0Msw; /* Serdes Rx Lane 0 config, MSW */
+ UINT16 serdesCfgRxLane0Lsw; /* Serdes Rx Lane 0 config, LSW */
+
+ UINT16 serdesCfgTxLane0Msw; /* Serdes Tx Lane 0 config, MSW */
+ UINT16 serdesCfgTxLane0Lsw; /* Serdes Tx Lane 0 config, LSW */
+
+
+
+ UINT16 serdesCfgRxLane1Msw; /* Serdes Rx Lane 1 config, MSW */
+ UINT16 serdesCfgRxLane1Lsw; /* Serdes Rx Lane 1 config, LSW */
+
+ UINT16 serdesCfgTxLane1Msw; /* Serdes Tx Lane 1 config, MSW */
+ UINT16 serdesCfgTxLane1Lsw; /* Serdes Tx Lane 1 config, LSW */
+
+
+ UINT16 serdesCfgRxLane2Msw; /* Serdes Rx Lane 2 config, MSW */
+ UINT16 serdesCfgRxLane2Lsw; /* Serdes Rx Lane 2 config, LSW */
+
+ UINT16 serdesCfgTxLane2Msw; /* Serdes Tx Lane 2 config, MSW */
+ UINT16 serdesCfgTxLane2Lsw; /* Serdes Tx Lane 2 config, LSW */
+
+
+
+ UINT16 serdesCfgRxLane3Msw; /* Serdes Rx Lane 3 config, MSW */
+ UINT16 serdesCfgRxLane3Lsw; /* Serdes Rx Lane 3 config, LSW */
+
+ UINT16 serdesCfgTxLane3Msw; /* Serdes Tx Lane 3 config, MSW */
+ UINT16 serdesCfgTxLane3Lsw; /* Serdes Tx Lane 3 config, LSW */
+
+} BOOT_PARAMS_VUSR_T;
+
+typedef struct boot_params_spi_s
+{
+ /* common portion of the Boot parameters */
+ UINT16 length;
+ UINT16 checksum;
+ UINT16 boot_mode;
+ UINT16 portNum;
+ UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
+ UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
+
+ UINT16 options;
+ /*
+ * SPI Specific Options
+ * Bit 01-00: BT:
+ * 00 - Boot Parameter Mode
+ * 01 - Boot Table Mode
+ * 10 - Boot Config mode
+ * 11 - Reserved, but if seen will act as boot parameter table
+ * Other bits: Reserved
+ */
+ #define BOOT_PARAMS_SPI_OPTIONS_BP 0x0000
+ #define BOOT_PARAMS_SPI_OPTIONS_BT 0x0001
+ #define BOOT_PARAMS_SPI_OPTIONS_BC 0x0002
+
+ #define BOOT_PARAMS_SPI_OPTIONS_MASK 0x0003
+ #define BOOT_PARAMS_SPI_OPTIONS_SHIFT 0
+
+ #define BOOT_PARAMS_SPI_IS_BOOTTBL_MODE(options) \
+ (((options) & BOOT_PARAMS_SPI_OPTIONS_MASK) == BOOT_PARAMS_SPI_OPTIONS_BT)
+
+ #define BOOT_PARAMS_SPI_IS_BOOTCONFIG_MODE(options) \
+ (((options) & BOOT_PARAMS_SPI_OPTIONS_MASK) == BOOT_PARAMS_SPI_OPTIONS_BC)
+
+ #define BOOT_PARAMS_SPI_IS_BOOTPARAM_MODE(options) \
+ (((options) & BOOT_PARAMS_SPI_OPTIONS_MASK) == BOOT_PARAMS_SPI_OPTIONS_BP)
+
+
+ #define BOOT_PARAMS_SPI_SET_BOOTTBL_MODE(options, mode) \
+ (options) = ((options) & ~BOOT_PARAMS_SPI_OPTIONS_MASK) | \
+ (((mode) & BOOT_PARAMS_SPI_OPTIONS_MASK) << \
+ BOOT_PARAMS_SPI_OPTIONS_SHIFT)
+
+
+ UINT16 addrWidth; /* 16 or 24 are the only valid values */
+ UINT16 nPins; /* 4 or 5 pins are the only valid values */
+ UINT16 csel; /* only values 0b10 (cs0 low) or 0b01 (cs1 low) are valid */
+ UINT16 mode; /* Clock phase/polarity. These are the standard SPI modes 0-3 */
+ UINT16 c2tdelay; /* Setup time between chip select assert and the transaction */
+
+ UINT16 cpuFreqMhz; /* Speed the CPU is running after PLL configuration */
+ UINT16 busFreqMhz; /* The speed of the SPI bus, the megahertz portion */
+ UINT16 busFreqKhz; /* The KHz portion of the bus frequency. A frequency of 1.5 MHz would have the value 5 here */
+
+ UINT16 read_addr_msw; /* The base address to read from the SPI, upper 16 bits */
+ UINT16 read_addr_lsw; /* The base address to read from the SPI, lower 16 bits */
+
+ UINT16 next_csel; /* The next chip select to use if in boot config mode, when the config is complete */
+ UINT16 next_read_addr_msw; /* The next read address to use if in boot config mode */
+ UINT16 next_read_addr_lsw; /* The next read address to use if in boot config mode */
+
+} BOOT_PARAMS_SPI_T;
+
+
+/*
+ * UNION of boot parameter structures in all modes
+ * Note: We need to make sure that the structures genertaed by the C-compiler
+ * match with the boot parameter table data format i.e. a set of 16-bit
+ * data array.
+ */
+#define BOOT_PARAMS_SIZE_IN_BYTES 128
+typedef union {
+ BOOT_PARAMS_COMMON_T common;
+ BOOT_PARAMS_ETHERNET_T eth;
+ BOOT_PARAMS_I2C_T i2c;
+ BOOT_PARAMS_UTOPIA_T utopia;
+ BOOT_PARAMS_RIO_T rio;
+ BOOT_PARAMS_PCIE_T pcie;
+ BOOT_PARAMS_EMIF_T emif;
+ BOOT_PARAMS_VUSR_T vusr;
+ BOOT_PARAMS_SPI_T spi;
+ UINT16 parameter[BOOT_PARAMS_SIZE_IN_BYTES/2];
+} BOOT_PARAMS_T;
+
+
+/*******************************************************************************
+ * Definition: The time stamp and version number are placed into the stats.
+ * This will be two characters packed per 16bits . The length
+ * value must be 32 bit divisible
+ *******************************************************************************/
+#define BOOT_VERSION_LEN_UINT16 32
+typedef struct BOOT_VERSION_S {
+
+ UINT16 vstring[BOOT_VERSION_LEN_UINT16];
+
+} BOOT_VERSION_T;
+extern BOOT_VERSION_T bootVersion;
+
+
+/*******************************************************************************
+ * Definition: Runs time stats that are not initialized on cold boot entry
+ * !!!!!! boot.s assumes that the nonInit stats are at the top of the structure
+ * !!!!!! and that stage is the first element
+ *******************************************************************************/
+typedef struct BOOT_STATS_NONINIT_S {
+ UINT16 stage; /* Record the SharedROM code execution stage */
+ #define BOOT_STAGE_ASM_START_UP 1
+ #define BOOT_STAGE_INIT_CACHE 2
+ #define BOOT_STAGE_CHCHE_INITED 3
+ #define BOOT_STAGE_ENTER_WARMBOOT 4
+ #define BOOT_STAGE_INIT_CPGMAC 5
+ #define BOOT_STAGE_SEND_ERA_FRAME 6
+ #define BOOT_STAGE_ETH_MAIN_LOOP 7
+ #define BOOT_STAGE_I2C_BOOTTBL_LOOP 8
+ #define BOOT_STAGE_I2C_BOOTPARAM_LOOP 9
+ #define BOOT_STAGE_DISABLE_CACHE 10
+ #define BOOT_STAGE_CHCHE_DISABLED 11
+ #define BOOT_STAGE_EXIT 12
+ #define BOOT_STAGE_ERROR_LOOP 13
+ #define BOOT_STAGE_I2C_BOOTCONFIG_LOOP 14
+ #define BOOT_STAGE_I2C_SLV_RCV_OPTIONS_LOOP 15
+ #define BOOT_STAGE_UTOPIA_MAIN_LOOP 16
+ UINT16 coldBootEntries;
+
+} BOOT_STATS_NONINIT_T;
+
+/*******************************************************************************
+ * Definition: Run time statistics and error counts. These stats are
+ * initialized on cold boot entry.
+ ******************************************************************************/
+
+typedef struct BOOT_STATS_COMMON_S {
+ UINT32 bootStatus;
+ UINT16 nColdBootEntries;
+ UINT16 nBootReentries;
+ UINT16 nPllWarns;
+ UINT16 nResetWarns;
+} BOOT_STATS_COMMON_T;
+
+
+typedef struct BOOT_STATS_MAIN_S {
+ UINT16 errorCode; /* (module ID <<8 ) + module specific error */
+
+ /* I2C operation related statistics */
+ UINT16 numI2Cpkts; /* number of I2C boot table packets processed */
+ UINT16 numI2CchksumError;/* number of I2C checksum errors */
+ UINT16 numI2ClengthError;/* number of I2C block length errors */
+ UINT16 numI2CotherError; /* number of I2C section with invalid length and etc */
+ UINT16 numI2Cretrys; /* number of I2C retrys due to read access errors */
+ UINT16 numI2cWrites; /* number of I2C master writes to passive devices */
+ UINT16 numI2cWriteError; /* number of I2C master write errors */
+
+ UINT16 warmBootEntry; /* Count of entries into warm boot routine */
+} BOOT_STATS_MAIN_T;
+
+
+
+/*****************************************************************************
+ * Definition: I2C stats, Boot table and Ethernrt stats initialized
+ * on cold boot entry
+ *****************************************************************************/
+typedef struct I2C_STATS_tag
+{
+ UINT16 num_trans;
+ UINT16 num_trys;
+ UINT16 num_try_ok;
+ UINT16 num_try_lost_arb;
+ UINT16 num_try_idle_to;
+ UINT16 num_try_no_ack;
+ UINT16 num_try_other_err;
+ UINT32 extra_idle_waits;
+ UINT32 extra_clock_waits;
+ UINT32 tx_bytes;
+ UINT32 rx_bytes;
+ UINT32 data_re_reads;
+} I2C_STATS_T;
+
+typedef struct BTBL_STATS_tag
+{
+ UINT16 num_sections; /* number of boot table sections received */
+ UINT16 num_pdma_copies; /* number of PDMA copies performed */
+} BTBL_STATS_T;
+
+typedef struct ETH_STATS_tag
+{
+ /* MAC packets related statistics */
+ UINT16 uniMacPkts; /* Count of packets received with valid unicast mac
+ address */
+ UINT16 multiMacPkts; /* Count of packets received with valid multicast or
+ broadcast mac address */
+ UINT16 invalidMacPkts; /* Count of packets received with invalid mac
+ address */
+ UINT16 invalidLLCPkts; /* Count of 802.3 packets with wrong LLC/SNAP header */
+ UINT16 nonIpPkts; /* Count of non-IP packets received with valid
+ MAC address */
+
+ /* IP packets related statistics */
+ UINT16 nEra; /* Number of ERA packets transmitted */
+ UINT16 nonIP4Pkts; /* Count of non-IP4 packets */
+ UINT16 ipfragments; /* Count of IP fragments received */
+ UINT16 ipTruncatedError; /* Count of truncated IP frame */
+ UINT16 nonUDPPkts; /* Count of IP packets with non-UDP paylaod */
+
+ /* UDP packets related statistics */
+ UINT16 udpSizeError; /* Count of UDP packet with invalid (odd) size */
+ UINT16 udpPortError; /* Count of UDP packets with invalid port number */
+ UINT16 udpChksumError; /* Count of UDP packets with checksum error */
+
+ /* Boot table packets related statistics */
+ UINT16 nonBtblPkts; /* Count of UDP packets with invalid boot table paylaod */
+ UINT16 outSeqPkts; /* Count of out of sequence boot table packets received
+ i.e. packets with unexpected seq_num */
+ UINT16 expSeqNum; /* Expected Sequence Number */
+ UINT16 lastSeqNum; /* Last sequence number received */
+
+ /* Driver errors */
+ UINT16 sizeZeroPackets; /* Count of packets arriving with 0 size */
+} ETH_STATS_T;
+
+typedef struct PCI_EEAI_STATS_tag
+{
+ UINT16 pciI2cReads; /* Count of block reads of i2c eeprom */
+ UINT16 pciI2cRetries; /* Count of i2c read retries */
+ UINT16 pciChkSumErr; /* Count of block check sum errors */
+ UINT16 pciEeaiFail; /* Count of aborted pci attempts */
+} PCI_EEAI_STATS_T;
+
+/* Rapid I/O stats */
+typedef struct RAPIDIO_STATS_tag
+{
+ UINT16 rapidIoFailReady; /* If set rapid I/O peripheral failed to report ready */
+ UINT16 rapidIoBtblBlocks; /* Count of number of boot table blocks received */
+ UINT16 rapidIoBtblBadBlocks; /* Count of boot table blocks rejected */
+ UINT16 rapidIoDescrEmpty; /* Count of times ROM found rx descriptor queue empty */
+} RAPIDIO_STATS_T;
+
+typedef struct HPI_STATS_Tag
+{
+ UINT16 hpiBtblBlocks; /* Count of boot table blocks received */
+ UINT16 hpiBtblBadBlocks; /* Count of boot table blocks rejected */
+} HPI_STATS_T;
+
+/* Utopia stats */
+typedef struct UTOPIA_STATS_tag
+{
+ UINT16 cellCount; /* Count of cells received */
+ UINT16 invalidPtr; /* Count of invalid pointers received in processing */
+ UINT16 invalidSize; /* Count of cells that were too small */
+ UINT16 cellMagicCount; /* Count of cells received with valid magic */
+ UINT16 cellMagicFailed; /* Count of cells received with invalid magic */
+ UINT16 trapNoCellMem; /* Trapped due to no cell space in memory */
+ UINT16 possibleOverrun; /* Count of possible cell buffer overruns */
+} UTOPIA_STATS_T;
+
+/*******************************************************************************
+ * Definition: The statistics
+ *
+ * !!!!!! boot.s assumes that the nonInit stats are at the top of the structure!
+ *******************************************************************************/
+typedef struct BOOT_STATS_S {
+
+ BOOT_STATS_COMMON_T common;
+ BOOT_STATS_NONINIT_T nonInit;
+ BOOT_STATS_MAIN_T main;
+ I2C_STATS_T i2c;
+ BTBL_STATS_T btbl;
+ union {
+ ETH_STATS_T eth;
+ PCI_EEAI_STATS_T pci_eeai;
+ RAPIDIO_STATS_T rapidIo;
+ UTOPIA_STATS_T utopia;
+ HPI_STATS_T hpi;
+ } u;
+} BOOT_STATS_T;
+
+extern BOOT_STATS_T bootStats;
+
+/*******************************************************************************
+ * Definition: The magic start address, known to all modules
+ *******************************************************************************/
+extern volatile UINT32 *p_boot_entry_addr;
+
+
+/*******************************************************************************
+ * Emif4 (DDR3) configuration table
+ *******************************************************************************/
+typedef struct bootEmif4Tbl_s {
+
+ UINT32 configSelect; /* Bit map defining which registers to set */
+
+ UINT32 pllPrediv; /* Values of all 0s will disable the pll */
+ UINT32 pllMult;
+ UINT32 pllPostDiv;
+
+ UINT32 sdRamConfig;
+ UINT32 sdRamConfig2;
+ UINT32 sdRamRefreshCtl;
+ UINT32 sdRamTiming1;
+ UINT32 sdRamTiming2;
+ UINT32 sdRamTiming3;
+ UINT32 lpDdrNvmTiming;
+ UINT32 powerManageCtl;
+ UINT32 iODFTTestLogic;
+ UINT32 performCountCfg;
+ UINT32 performCountMstRegSel;
+ UINT32 readIdleCtl;
+ UINT32 sysVbusmIntEnSet;
+ UINT32 sdRamOutImpdedCalCfg;
+ UINT32 tempAlterCfg;
+ UINT32 ddrPhyCtl1;
+ UINT32 ddrPhyCtl2;
+ UINT32 priClassSvceMap;
+ UINT32 mstId2ClsSvce1Map;
+ UINT32 mstId2ClsSvce2Map;
+ UINT32 eccCtl;
+ UINT32 eccRange1;
+ UINT32 eccRange2;
+ UINT32 rdWrtExcThresh;
+
+} BOOT_EMIF4_TBL_T;
+
+#define BOOT_EMIF4_ENABLE_pllCtl (1 << 0)
+
+#define BOOT_EMIF4_ENABLE_sdRamConfig (1 << 2)
+#define BOOT_EMIF4_ENABLE_sdRamConfig2 (1 << 3)
+#define BOOT_EMIF4_ENABLE_sdRamRefreshCtl (1 << 4)
+#define BOOT_EMIF4_ENABLE_sdRamTiming1 (1 << 5)
+#define BOOT_EMIF4_ENABLE_sdRamTiming2 (1 << 6)
+#define BOOT_EMIF4_ENABLE_sdRamTiming3 (1 << 7)
+#define BOOT_EMIF4_ENABLE_lpDdrNvmTiming (1 << 8)
+#define BOOT_EMIF4_ENABLE_powerManageCtl (1 << 9)
+#define BOOT_EMIF4_ENABLE_iODFTTestLogic (1 << 10)
+#define BOOT_EMIF4_ENABLE_performCountCfg (1 << 11)
+#define BOOT_EMIF4_ENABLE_performCountMstRegSel (1 << 12)
+#define BOOT_EMIF4_ENABLE_readIdleCtl (1 << 13)
+#define BOOT_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 14)
+#define BOOT_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 15)
+#define BOOT_EMIF4_ENABLE_tempAlterCfg (1 << 16)
+#define BOOT_EMIF4_ENABLE_ddrPhyCtl1 (1 << 17)
+#define BOOT_EMIF4_ENABLE_ddrPhyCtl2 (1 << 18)
+#define BOOT_EMIF4_ENABLE_priClassSvceMap (1 << 19)
+#define BOOT_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 20)
+#define BOOT_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 21)
+#define BOOT_EMIF4_ENABLE_eccCtl (1 << 22)
+#define BOOT_EMIF4_ENABLE_eccRange1 (1 << 23)
+#define BOOT_EMIF4_ENABLE_eccRange2 (1 << 24)
+#define BOOT_EMIF4_ENABLE_rdWrtExcThresh (1 << 25)
+
+#define BOOT_EMIF4_ENABLE_ALL 0x00ffffff
+
+
+
+
+/* Hibernation function control */
+#define TIBOOT_CTL_HIBERNATION_MODE1 1
+#define TIBOOT_CTL_HIBERNATION_MODE2 2
+
+
+/* Hibernation function return */
+#define TIBOOT_ERR_HIBERNATION_MODE_INVALID -1
+#define TIBOOT_ERR_HIBERNATION_ADDR_MISALIGNED -2
+#define TIBOOT_ERR_HIBERNATION_ADDR_INVALID -3
+
+/* Boot mode values */
+#define BOOT_MODE_I2C 40
+#define BOOT_MODE_SPI 50
+
+/* ROM boot loader enter address */
+#define BOOT_ROM_ENTER_ADDRESS 0x20b00000
+
+#endif /* __TIBOOT_H__ */
+
+/* nothing past this point */
-C6X_C_DIR+= $(IBL_ROOT)
+C6X_C_DIR= $(IBL_ROOT)
C6X_C_DIR+= ;$(IBL_ROOT)/arch/$(ARCH)
C6X_C_DIR+= ;$(IBL_ROOT)/device
C6X_C_DIR+= ;$(IBL_ROOT)/device/$(TARGET)
ifeq ($(TARGET),c665x)
CSRC= t64.c pll.c cfgpll.c cfgpll2.c mdio.c i2c.c psc.c mdio.c serdes.c sgmii.c emif4.c gpio.c cpmacdrv.c
CSRC+= nandemif25.c nandgpio.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c c66x_uart.c
- else
+ else
+ ifeq ($(TARGET),c66xk2x)
+ CSRC= t64.c pll.c cfgpll.c cfgpll2.c mdio.c i2c.c psc.c cpsw.c qm.c cpdma.c pa.c sgmii.c serdes.c gmacsl.c emif4.c gpio.c
+ CSRC+= nandemif25.c nandgpio.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c c66x_uart.c
+ else
CSRC= t64.c cpmacdrv.c pll.c psc.c emif31.c mdio.c gpio.c nandgpio.c i2c.c sgmii.c cfgpll.c cfgpll2.c
CSRC+= qm.c cpdma.c pa.c serdes.c gmacsl.c emif4.c nandemif25.c spi.c nandspi.c noremif25.c norspi.c emif25.c spiutil.c
+ endif
endif
endif
endif
vpath % $(ECODIR)/uart/c66x_uart
endif
+ifeq ($(TARGET),c66xk2x)
+ vpath % $(ECODIR)/plls/pll014phi
+ vpath % $(ECODIR)/mdio
+ vpath % $(ECODIR)/i2c
+ vpath % $(ECODIR)/pscs/psc2
+ vpath % $(ECODIR)/cpsw
+ vpath % $(ECODIR)/qm
+ vpath % $(ECODIR)/cpdma
+ vpath % $(ECODIR)/pa
+ vpath % $(ECODIR)/sgmii
+ vpath % $(ECODIR)/serdes
+ vpath % $(ECODIR)/gpio
+ vpath % $(ECODIR)/macs/cpmacsl
+ vpath % $(ECODIR)/ddrs/emif4
+ vpath % $(ECODIR)/nands/emif25
+ vpath % $(ECODIR)/nands/gpio
+ vpath % $(ECODIR)/nands/spi
+ vpath % $(ECODIR)/spi
+ vpath % $(ECODIR)/nors/emif25
+ vpath % $(ECODIR)/nors/spi
+ vpath % $(ECODIR)/emif25
+ vpath % $(ECODIR)/uart/c66x_uart
+endif
+
hw: gen_cdefdep makefile $(OBJS)
$(OBJS): cdefdep
#*********************************************************************************
-DEVICES= c6455 c6472 c6474 c6474l c6457 c66x c665x
+DEVICES= c6455 c6472 c6474 c6474l c6457 c66x c665x c66xk2x
ifndef IBL_ROOT
IBL_ROOT=../..
diff --git a/src/hw/cpdma/cpdma.c b/src/hw/cpdma/cpdma.c
--- a/src/hw/cpdma/cpdma.c
+++ b/src/hw/cpdma/cpdma.c
return (0);
} /* hwCpdmaRxDisable */
-
+
/*********************************************************************************************
cfg->qmNumFreeBuf, /* Rx packet destination QM number, subsequent descriptors */
cfg->queueFreeBuf ); /* Rx packet destination queue, subsequent descriptors */
DEVICE_REG32_W (cfg->flowBase + CPDMA_RX_FLOW_CFG(CPDMA_RX_FLOW_REG_D, 0), v);
-
-
+
+
/* Register E uses the same setup as D */
DEVICE_REG32_W (cfg->flowBase + CPDMA_RX_FLOW_CFG(CPDMA_RX_FLOW_REG_E, 0), v);
/* Enable the rx channels */
- for (i = 0; i < cfg->nRxChans; i++)
+ for (i = 0; i < cfg->nRxChans; i++)
DEVICE_REG32_W (cfg->rxBase + CPDMA_REG_RCHAN_CFG_REG_A(i), CPDMA_REG_VAL_RCHAN_A_RX_ENABLE);
*************************************************************************************************/
SINT16 hwCpdmaTxConfig (const cpdmaTxCfg_t *cfg)
{
- UINT32 i;
+ UINT32 i, v;
/* Disable loopback in the tx direction */
DEVICE_REG32_W (cfg->gblCtlBase + CPDMA_REG_EMU_CTL, CPDMA_REG_VAL_EMU_CTL_NO_LOOPBACK);
+ v = *((UINT32 *)DEVICE_JTAG_ID_REG);
+ v &= DEVICE_JTAG_ID_MASK;
+
+ if (v == DEVICE_TCI6636K2H_JTAG_ID_VAL)
+ /* Set QM base address, only for K2x devices */
+ DEVICE_REG32_W (cfg->gblCtlBase + CPDMA_REG_QM_BASE_ADDR(0), DEVICE_QM1_QUEUE_MANAGEMENT_REGS(0));
+
/* Enable all channels. The current state isn't important */
for (i = 0; i < cfg->nTxChans; i++) {
DEVICE_REG32_W (cfg->txBase + CPDMA_REG_TCHAN_CFG_REG_B(i), 0); /* Priority */
return (0);
} /* hwCpdmaTxDisable */
-
+
--- a/src/hw/cpdma/cpdma_loc.h
+++ b/src/hw/cpdma/cpdma_loc.h
* DESCRIPTION: Defines the layout of the cpdma peripheral
*
**************************************************************************************************/
-
+
/* Emulation control register */
#define CPDMA_REG_EMU_CTL 0x08
+#define CPDMA_REG_QM_BASE_ADDR(x) (0x10 + (x)*0x4)
/* CPPI Tx DMA channel control registers */
#define CPDMA_REG_TCHAN_CFG_REG_A(x) (0x00 + (x)*0x20)
/* CPPI Tx DMA Scheduler Confuration value. This sets the priorities of
* the channels. If set to all equal, the actual value doesn't matter */
-#define CPDMA_REG_VAL_TCHAN_SCHED_HIGH_PRIORITY 0
-#define CPDMA_REG_VAL_TCHAN_SCHED_MED_HIGH_PRIORITY 1
-#define CPDMA_REG_VAL_TCHAN_SCHED_MED_LOW_PRIORITY 2
-#define CPDMA_REG_VAL_TCHAN_SCHED_LOW_PRIORITY 3
+#define CPDMA_REG_VAL_TCHAN_SCHED_HIGH_PRIORITY 0
+#define CPDMA_REG_VAL_TCHAN_SCHED_MED_HIGH_PRIORITY 1
+#define CPDMA_REG_VAL_TCHAN_SCHED_MED_LOW_PRIORITY 2
+#define CPDMA_REG_VAL_TCHAN_SCHED_LOW_PRIORITY 3
/* A very simply flow configuration is supported. No queue allocation by bins is supported */
((sopOff & 0x1ff) << 16) | \
((qmgr & 3) << 12) | \
((qnum & 0xfff) << 0) )
-
+
/* CPPI Rx flow configuration register B. No tags are used */
#define CPDMA_REG_VAL_RX_FLOW_B_DEFAULT 0
((fd0Qnum & 0xfff) << 16) | \
((fd1Qm & 3) << 12) | \
((fd1Qnum & 0xfff) << 0) )
-
+
/* CPPI Rx flow configuration register E */
#define CPDMA_REG_VAL_RX_FLOW_E_DEFAULT 0
/* CPPI Rx flow configuration register H */
#define CPDMA_REG_VAL_RX_FLOW_H_DEFAULT 0
-
-/* Default Emulation control register value disables loopback */
+
+/* Default Emulation control register value disables loopback */
#define CPDMA_REG_VAL_EMU_CTL_NO_LOOPBACK 0
index 379955a63f1480dfa51ce5ca23ef6cd3cb5bdc2b..ab4ee9715e2aacbeae03ee72113003dd0db30fce 100755 (executable)
v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
v &= DEVICE_JTAG_ID_MASK;
- if ( (v == DEVICE_C6678_JTAG_ID_VAL) ||
+ if (v == DEVICE_TCI6636K2H_JTAG_ID_VAL)
+ {
+ /* TBD */
+ }
+ else if ( (v == DEVICE_C6678_JTAG_ID_VAL) ||
(v == DEVICE_C6670_JTAG_ID_VAL) )
{
diff --git a/src/ibl.h b/src/ibl.h
--- a/src/ibl.h
+++ b/src/ibl.h
/**
* @brief
- * The version number, 1.0.0.16
+ * The version number, 1.0.0.17
*/
-#define ibl_VERSION ibl_MAKE_VERSION(1,0,0,16)
+#define ibl_VERSION ibl_MAKE_VERSION(1,0,0,17)
/* Version string for UART write */
-#define ibl_VERSION_STR "1.0.0.16"
+#define ibl_VERSION_STR "1.0.0.17"
/**
* @defgroup iblBootModes Defines the boot modes supported by the IBL
#define ibl_EVM_C6670L 0x50 /**< C6670 Low Cost EVM */
#define ibl_EVM_C6678L 0x60 /**< C6678 Low Cost EVM */
#define ibl_EVM_C6657L 0x70 /**< C6657 Low Cost EVM */
+#define ibl_EVM_TCI6634K2K 0x80 /**< TCI6634K2K Low Cost EVM */
/**
* @brief
diff --git a/src/main/iblmain.c b/src/main/iblmain.c
index bd1ac4fdab5ecdf665e63d8c333887e58b48d2b9..d216082d44033c62118ddfd18831ca904943f619 100755 (executable)
--- a/src/main/iblmain.c
+++ b/src/main/iblmain.c
/*
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
* are met:
*
- * Redistributions of source code must retain the above copyright
+ * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/**
* @b Description
* @n
- *
+ *
* For NAND and NOR boots, configure the specified peripheral or memory interface
*/
void iblPmemCfg (int32 interface, int32 port, bool enableNand)
int i;
/* Locate the configuration corresponding to this chip select space */
- for (i = 0; i < ibl_MAX_EMIF_PMEM; i++)
+ for (i = 0; i < ibl_MAX_EMIF_PMEM; i++)
if (ibl.emifConfig[i].csSpace == interface)
break;
-
+
if (i == ibl_MAX_EMIF_PMEM) {
iblStatus.iblFail = ibl_FAIL_CODE_NO_EMIF_CFG;
return;
*
* The main function kicks off the boot. If it does not find the magic value in the
* configuration array then default values are loaded. This default load
- * is done only once at the start of boot.
+ * is done only once at the start of boot.
*
* @retval
* None
v = DEVICE_REG32_R(DEVICE_JTAG_ID_REG);
v &= DEVICE_JTAG_ID_MASK;
if (
- (v == DEVICE_C6678_JTAG_ID_VAL) ||
- (v == DEVICE_C6670_JTAG_ID_VAL) ||
- (v == DEVICE_C6657_JTAG_ID_VAL)
+ (v == DEVICE_C6678_JTAG_ID_VAL) ||
+ (v == DEVICE_C6670_JTAG_ID_VAL) ||
+ (v == DEVICE_C6657_JTAG_ID_VAL) ||
+ (v == DEVICE_TCI6636K2H_JTAG_ID_VAL)
)
{
IER = 0;
/* For C66x devices, check the DEVSTAT register to find which image on which device to boot. */
v = DEVICE_REG32_R(DEVICE_REG_DEVSTAT);
-
+
/* Get the Endianness */
if (ibl_N_ENDIANS == 1)
{
iblStatus.activeBoot = ibl.bootModes[boot_mode_idx].bootMode;
- switch (ibl.bootModes[boot_mode_idx].bootMode)
+ switch (ibl.bootModes[boot_mode_idx].bootMode)
{
#ifndef EXCLUDE_ETH
case ibl_BOOT_MODE_TFTP:
iblEthBoot (boot_mode_idx);
break;
#endif
-
+
#if ((!defined(EXCLUDE_NAND_EMIF)) || (!defined(EXCLUDE_NAND_GPIO)))
case ibl_BOOT_MODE_NAND:
iblPmemCfg (ibl.bootModes[boot_mode_idx].u.nandBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
iblNandBoot (boot_mode_idx);
break;
#endif
-
+
#if (!defined(EXCLUDE_NOR_EMIF) && !defined(EXCLUDE_NOR_SPI))
case ibl_BOOT_MODE_NOR:
iblPmemCfg (ibl.bootModes[boot_mode_idx].u.norBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
#else
dip_setting = get_device_switch_setting();
-
+
if (dip_setting == 0)
boot_mode_idx = 0;
else if (dip_setting == 1)
boot_mode_idx = 1;
-
+
iblStatus.activeBoot = ibl.bootModes[boot_mode_idx].bootMode;
-
- switch (ibl.bootModes[boot_mode_idx].bootMode) {
+
+ switch (ibl.bootModes[boot_mode_idx].bootMode) {
#ifndef EXCLUDE_ETH
case ibl_BOOT_MODE_TFTP:
iblStatus.activeDevice = ibl_ACTIVE_DEVICE_ETH;
iblEthBoot (boot_mode_idx);
break;
#endif
-
+
#if ((!defined(EXCLUDE_NAND_EMIF)) || (!defined(EXCLUDE_NAND_GPIO)))
case ibl_BOOT_MODE_NAND:
iblPmemCfg (ibl.bootModes[boot_mode_idx].u.nandBoot.interface, ibl.bootModes[boot_mode_idx].port, TRUE);
} /* main */
-
+
/**
* @b Description
* @n
- *
+ *
* The ibl boot function links a device to a data format. The data format
* parser pulls data from the boot device
*
* None
*/
Uint32 iblBoot (BOOT_MODULE_FXN_TABLE *bootFxn, Int32 dataFormat, void *formatParams)
-{
+{
Uint32 entry = 0;
Uint32 value32;
- Uint8 dataBuf[4];
+ Uint8 dataBuf[4];
Uint16 value16;
/* Determine the data format if required */
@@ -441,7 +442,7 @@ Uint32 iblBoot (BOOT_MODULE_FXN_TABLE *bootFxn, Int32 dataFormat, void *formatPa
iblStatus.autoDetectFailCnt += 1;
return (0);
}
- }
+ }
iblStatus.activeFileFormat = dataFormat;
@@ -483,7 +484,7 @@ Uint32 iblBoot (BOOT_MODULE_FXN_TABLE *bootFxn, Int32 dataFormat, void *formatPa
break;
}
-
+
return (entry);
diff --git a/src/make/Makefile b/src/make/Makefile
--- a/src/make/Makefile
+++ b/src/make/Makefile
#* make test_build
#*******************************************************************************************
-IBLS_C6X= c6455 c6472 c6474 c6474l c6457 c66x c665x
+IBLS_C6X= c6455 c6472 c6474 c6474l c6457 c66x c665x tci66xk2x
EVMS_C6X= evm_c6455 evm_c6472 evm_c6474 evm_c6474l
SPI_DEFS+= SPI_ROM=$(SPI_ROM)
-.PHONY: all $(IBLS_C6X) evm_c6455 evm_c6472 evm_c6474 evm_c6474l evm_c6457 evm_c6678_i2c evm_c6670_i2c evm_c6657_i2c
-.PHONY: test_c66x test_c665x test_c6455 test_c6472 test_c6474 test_c6457 clean
+.PHONY: all $(IBLS_C6X) evm_c6455 evm_c6472 evm_c6474 evm_c6474l evm_c6457 evm_c6678_i2c evm_c6670_i2c evm_c6657_i2c evm_tci6634k2k_i2c
+.PHONY: test_c66x test_c665x test_c66xk2x test_c6455 test_c6472 test_c6474 test_c6457 clean
all:
make -f makestg1 ARCH=c64x TARGET=c665x ENDIAN_MODE=both CEXCLUDES='SPI NOR_SPI NAND_SPI' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c665x
make -f makestg1 ARCH=c64x TARGET=c665x ENDIAN_MODE=both CEXCLUDES=I2C SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' c665x
+evm_tci6634k2k_spi:
+ make -f makestg1 ARCH=c64x TARGET=c66xk2x I2C=no I2C_BUS_ADDR=0x51 I2C_MAP_ADDR=0x500 ENDIAN_MODE=little CEXCLUDES=I2C SPI_DEFS='$(EVM_667x_SPI_DEFS)' c66xk2x
+
+evm_tci6634k2k_i2c:
+ make -f makestg1 I2C_BUS_ADDR=$(I2C_BUS_ADDR) I2C_MAP_ADDR=$(I2C_MAP_ADDR) \
+ENDIAN_MODE=$(ENDIAN) ARCH=c64x TARGET=c66xk2x EVM=tci6634k2k SPI=no SPI_DEFS='$(EVM_667x_SPI_DEFS)' \
+CEXCLUDES='COFF BIS NAND_GPIO' c66xk2x
+ cp -f ibl_c66xk2x/i2crom.dat bin/i2crom_$(I2C_BUS_ADDR)_tci6634k2k_$(ENDIAN_SFX).dat
+ cp -f ibl_c66xk2x/i2crom.bin bin/i2crom_$(I2C_BUS_ADDR)_tci6634k2k_$(ENDIAN_SFX).bin
+ cp -f ../util/i2cConfig/i2cparam_c66xk2x_$(ENDIAN_SFX).out bin/i2cparam_$(I2C_BUS_ADDR)_tci6634k2k_$(ENDIAN_SFX)_$(I2C_MAP_ADDR).out
+
+
+
+test_c66xk2x:
+ make -f makestg1 ARCH=c64x TARGET=c66xk2x ENDIAN_MODE=both CEXCLUDES='NOR_SPI' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c66xk2x
+ make -f makestg1 ARCH=c64x TARGET=c66xk2x ENDIAN_MODE=both CEXCLUDES='NAND_SPI' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c66xk2x
+ make -f makestg1 ARCH=c64x TARGET=c66xk2x ENDIAN_MODE=both CEXCLUDES='NOR_EMIF' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c66xk2x
+ make -f makestg1 ARCH=c64x TARGET=c66xk2x ENDIAN_MODE=both CEXCLUDES='NAND_EMIF' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c66xk2x
+ make -f makestg1 ARCH=c64x TARGET=c66xk2x ENDIAN_MODE=both CEXCLUDES='NAND_EMIF NOR_EMIF' SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c66xk2x
+ make -f makestg1 ARCH=c64x TARGET=c66xk2x ENDIAN_MODE=both CEXCLUDES='SPI NOR_SPI NAND_SPI' I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=no c66xk2x
+ make -f makestg1 ARCH=c64x TARGET=c66xk2x ENDIAN_MODE=both CEXCLUDES=I2C SPI_DEFS='SPI_ROM=1 SPI_MODE=3 SPI_ADDR_WIDTH=24 SPI_NPIN=5 SPI_CSEL=2 SPI_C2TDEL=8 SPI_CLKDIV=0x20' c66xk2x
+
+
# Test - builds all the targets, with single component exclusion
test_c6455:
make -f makestg1 ARCH=c64x TARGET=c6474 I2C_BUS_ADDR=0x50 I2C_MAP_ADDR=$(I2C_MAP_ADDR) COMPACT_I2C=yes ENDIAN_MODE=both CEXCLUDES=BLOB c6474
-test_build: test_c6455 test_c6457 test_c6472 test_c6474 test_c66x test_c665x
+test_build: test_c6455 test_c6457 test_c6472 test_c6474 test_c66x test_c665x test_c66xk2x
# will need to add a line for each additional ARCH type added
make -f makestg2 cleant ARCH=c64x TARGET=c6457
make -f makestg2 cleant ARCH=c64x TARGET=c66x
make -f makestg2 cleant ARCH=c64x TARGET=c665x
+ make -f makestg2 cleant ARCH=c64x TARGET=c66xk2x
make -C ../util/bconvert clean
make -C ../util/btoccs clean
make -C ../util/i2cConfig clean ARCH=c64x TARGET=c6455
make -C ../util/i2cConfig clean ARCH=c64x TARGET=c6457
make -C ../util/i2cConfig clean ARCH=c64x TARGET=c66x
make -C ../util/i2cConfig clean ARCH=c64x TARGET=c665x
+ make -C ../util/i2cConfig clean ARCH=c64x TARGET=c66xk2x
make -C ../util/romparse clean
make -C ../util/iblConfig/build clean
make -C ../test/test1 clean
diff --git a/src/make/bin/i2cConfig.gel b/src/make/bin/i2cConfig.gel
+++ /dev/null
@@ -1 +0,0 @@
-../../util/i2cConfig/i2cConfig.gel
\ No newline at end of file
diff --git a/src/make/ibl_c66xk2x/i2crom.map.pre b/src/make/ibl_c66xk2x/i2crom.map.pre
--- /dev/null
@@ -0,0 +1,214 @@
+#include "iblcfg.h"
+; This file is run through the C preprocessor to get the build time layout information
+; The following values must be defined:
+; I2C_BUS_ADDR - The I2C bus address of the eeprom holding the ROM boot info and the layout info
+; INIT_EXE_FILE - The I2C blocked stage 1 of the ibl
+; EXE_FILE_1 - The I2C blocked stage 2 of the ibl, must be the little endian version
+; EXE_FILE_2 - The I2C blocked stage 2 of the ibl, must be the big endian version
+; PAD_FILE_ID_1 - This pad holds the IBL configuration structure for the little endian version
+; PAD_FILE_ID_2 - This pad holds the IBL configuration structure for the big endian version
+;
+; The section statement directs the ROM boot loader to load the initial endian independent
+; portion of the IBL
+section
+{
+ param_index = 0
+ boot_mode = 40
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
+ options = 1
+
+ core_freq_mhz = 100
+ i2c_clk_freq_khz = 200
+
+ dev_addr_ext = I2C_BUS_ADDR
+
+ multi_i2c_id = 0
+ my_i2c_id = 1
+ address_delay = 0
+ exe_file = INIT_EXE_FILE
+}
+
+section
+{
+ param_index = 1
+ boot_mode = 40
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
+ options = 1
+
+ core_freq_mhz = 100
+ i2c_clk_freq_khz = 200
+
+ dev_addr_ext = I2C_BUS_ADDR
+
+ multi_i2c_id = 0
+ my_i2c_id = 1
+ address_delay = 0
+ exe_file = INIT_EXE_FILE
+}
+
+section
+{
+ param_index = 2
+ boot_mode = 40
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
+ options = 1
+
+ core_freq_mhz = 100
+ i2c_clk_freq_khz = 200
+
+ dev_addr_ext = I2C_BUS_ADDR
+
+ multi_i2c_id = 0
+ my_i2c_id = 1
+ address_delay = 0
+ exe_file = INIT_EXE_FILE
+}
+
+section
+{
+ param_index = 3
+ boot_mode = 40
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
+ options = 1
+
+ core_freq_mhz = 100
+ i2c_clk_freq_khz = 200
+
+ dev_addr_ext = I2C_BUS_ADDR
+
+ multi_i2c_id = 0
+ my_i2c_id = 1
+ address_delay = 0
+ exe_file = INIT_EXE_FILE
+}
+
+section
+{
+ param_index = 4
+ boot_mode = 40
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
+ options = 1
+
+ core_freq_mhz = 100
+ i2c_clk_freq_khz = 200
+
+ dev_addr_ext = I2C_BUS_ADDR
+
+ multi_i2c_id = 0
+ my_i2c_id = 1
+ address_delay = 0
+ exe_file = INIT_EXE_FILE
+}
+
+section
+{
+ param_index = 5
+ boot_mode = 40
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
+ options = 1
+
+ core_freq_mhz = 100
+ i2c_clk_freq_khz = 200
+
+ dev_addr_ext = I2C_BUS_ADDR
+
+ multi_i2c_id = 0
+ my_i2c_id = 1
+ address_delay = 0
+ exe_file = INIT_EXE_FILE
+}
+
+section
+{
+ param_index = 6
+ boot_mode = 40
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
+ options = 1
+
+ core_freq_mhz = 100
+ i2c_clk_freq_khz = 200
+
+ dev_addr_ext = I2C_BUS_ADDR
+
+ multi_i2c_id = 0
+ my_i2c_id = 1
+ address_delay = 0
+ exe_file = INIT_EXE_FILE
+}
+
+section
+{
+ param_index = 7
+ boot_mode = 40
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
+ options = 1
+
+ core_freq_mhz = 100
+ i2c_clk_freq_khz = 200
+
+ dev_addr_ext = I2C_BUS_ADDR
+
+ multi_i2c_id = 0
+ my_i2c_id = 1
+ address_delay = 0
+ exe_file = INIT_EXE_FILE
+}
+
+; The layout statement defines how the resulting I2C image is layed out. The base address
+; of this (given in the dev_addr) statement must be known to the initial IBL program
+; at compile time. The layout block is simple a group of 32 bit i2c addresses, so
+; the order of the exe_file and pad_file_id statements must be configured so as to
+; match the definition of struct iblI2cMap_t defined in ibl.h.
+layout
+{
+ dev_addr = IBL_CFG_I2C_MAP_TABLE_DATA_ADDR ; Defined in iblcfg.h
+ dev_addr_ext = I2C_BUS_ADDR
+ file_align = 0x80
+
+ exe_file = EXE_FILE_1
+ pad_file_id = PAD_FILE_ID_1
+
+
+ exe_file = EXE_FILE_2
+ pad_file_id = PAD_FILE_ID_2
+}
+
+; The pad statements simply provide space for the IBL configuration structures. It is valid to
+; have a single configuration structure which is used for both endian values.
+pad
+{
+ pad_file_id = 1
+ dev_addr = 0x500
+ dev_addr_ext = I2C_BUS_ADDR
+ len = 0x300
+}
+
+#if (PAD_FILE_ID_1 != PAD_FILE_ID_2)
+pad
+{
+ pad_file_id = 2
+ dev_addr = 0x800
+ dev_addr_ext = I2C_BUS_ADDR
+ len = 0x300
+}
+#endif
+
+
+
+
diff --git a/src/make/ibl_c66xk2x/ibl.cmd b/src/make/ibl_c66xk2x/ibl.cmd
--- /dev/null
@@ -0,0 +1,37 @@
+/************************************************************************************
+ * FILE PURPOSE: Define the memory usage of the ibl module for the c66x
+ ************************************************************************************
+ * FILE NAME: ibl.cmd
+ *
+ * DESCRIPTION: The memory placement for the IBL is defined
+ *
+ ************************************************************************************/
+
+/* In order to speed build time during debug, the object files are saved in
+ * both big and little endian format. The include file is generated by
+ * make to use the correct endian object files
+ */
+#include "ibl_objs.inc"
+
+
+/* Symbols from the 1st portion of the load, generated by the make process */
+#include "ibl_init_symbols.inc"
+
+/* Common memory and section areas between ibl_init and ibl */
+#include "ibl_common.inc"
+
+SECTIONS
+{
+ .cinit > TEXT
+ .const > TEXT
+ .text > TEXT
+ .switch > TEXT
+ .far > DATA
+ .bss > DATA
+
+ .linkram > LINKRAM
+ .cppi > CPPIRAM
+ .mac_buffer > PKTRAM
+
+}
+
diff --git a/src/make/ibl_c66xk2x/ibl.rmd b/src/make/ibl_c66xk2x/ibl.rmd
--- /dev/null
@@ -0,0 +1,11 @@
+-a
+-boot
+-e _c_int00
+
+ROMS
+{
+ ROM1: org = 0x0400, length = 0x20000, memwidth = 32, romwidth = 32
+ files = { ibl_le.b }
+}
+
+
diff --git a/src/make/ibl_c66xk2x/ibl_common.inc b/src/make/ibl_c66xk2x/ibl_common.inc
--- /dev/null
@@ -0,0 +1,42 @@
+/************************************************************************************
+ * FILE PURPOSE: Provide common memory and sections definitions for ibl_init and ibl
+ ************************************************************************************
+ * FILE NAME: ibl_common.inc
+ *
+ * DESCRIPTION: Defines the common memory map and section placement required
+ * to get ibl and ibl_init to work together in a two stage load
+ * process.
+ *************************************************************************************/
+
+-c
+-stack 0x800
+-heap 0x8000
+
+
+MEMORY
+{
+ TEXT_INIT : origin = 0x800000, length = 0x4200
+ TEXT : origin = 0x804200, length = 0xbe00
+ STACK : origin = 0x810000, length = 0x0800
+ HEAP : origin = 0x810800, length = 0x8000
+ DATA_INIT : origin = 0x818800, length = 0x0400
+ DATA : origin = 0x818c00, length = 0x2c00
+ CFG : origin = 0x81b800, length = 0x0300
+ STAT : origin = 0x81bb00, length = 0x0200
+
+ LINKRAM : origin = 0x1081be00, length = 0x0200
+ CPPIRAM : origin = 0x1081c000, length = 0x0200
+ PKTRAM : origin = 0x1081c200, length = 0x0800
+}
+
+
+SECTIONS
+{
+ .stack > STACK
+ .sysmem > HEAP
+
+ .ibl_config_table > CFG
+ .ibl_status_table > STAT
+
+}
+
diff --git a/src/make/ibl_c66xk2x/ibl_init.cmd b/src/make/ibl_c66xk2x/ibl_init.cmd
--- /dev/null
@@ -0,0 +1,31 @@
+/************************************************************************************
+ * FILE PURPOSE: Define the memory usage of the ibl module for the c6472
+ ************************************************************************************
+ * FILE NAME: ibl.cmd
+ *
+ * DESCRIPTION: The memory placement for the IBL is defined
+ *
+ ************************************************************************************/
+
+/* In order to speed build time during debug, the object files are saved in
+ * both big and little endian format. The include file is generated by
+ * make to use the correct endian object files
+ */
+#include "ibl_init_objs.inc"
+
+
+/* Common memory and section areas between ibl_init and ibl */
+#include "ibl_common.inc"
+
+
+SECTIONS
+{
+ .cinit > TEXT_INIT
+ .const > TEXT_INIT
+ .text > TEXT_INIT
+ .switch > TEXT_INIT
+ .far > DATA_INIT
+ .bss > DATA_INIT
+
+}
+
diff --git a/src/make/ibl_c66xk2x/ibl_init.rmd b/src/make/ibl_c66xk2x/ibl_init.rmd
--- /dev/null
@@ -0,0 +1,11 @@
+-a
+-boot
+-e _c_int00
+
+ROMS
+{
+ ROM1: org = 0x0400, length = 0x20000, memwidth = 32, romwidth = 32
+ files = { ibl_le.b }
+}
+
+
diff --git a/src/make/ibl_c66xk2x/ibl_init_image.rmd b/src/make/ibl_c66xk2x/ibl_init_image.rmd
--- /dev/null
@@ -0,0 +1,10 @@
+-a
+-e _c_int00
+
+ROMS
+{
+ ROM1: org = 0x800000, length = 0x20000, memwidth = 32, romwidth = 32
+ files = { ibl_le.b }
+}
+
+
diff --git a/src/make/ibl_c66xk2x/ibl_init_objs_template.inc b/src/make/ibl_c66xk2x/ibl_init_objs_template.inc
--- /dev/null
@@ -0,0 +1,31 @@
+/* ibl_init_objs_template.inc
+ *
+ * list of object files tagged with the endian field for replacement during make
+ */
+
+../main/c64x/make/iblinit.ENDIAN_TAG.oc
+../device/c64x/make/c66xk2xinit.ENDIAN_TAG.oc
+../device/c64x/make/c66xk2xutil.ENDIAN_TAG.oc
+../device/c64x/make/c64x.ENDIAN_TAG.oa
+../hw/c64x/make/pll.ENDIAN_TAG.oc
+../hw/c64x/make/cfgpll.ENDIAN_TAG.oc
+../hw/c64x/make/cfgpll2.ENDIAN_TAG.oc
+../interp/c64x/make/btblwrap.ENDIAN_TAG.oc
+../interp/c64x/make/btblpr.ENDIAN_TAG.oc
+../interp/c64x/make/gem.ENDIAN_TAG.oc
+../hw/c64x/make/psc.ENDIAN_TAG.oc
+
+#ifndef EXCLUDE_I2C
+../main/c64x/make/ibliniti2c.ENDIAN_TAG.oc
+../hw/c64x/make/i2c.ENDIAN_TAG.oc
+#endif
+
+#ifndef EXCLUDE_SPI_NOR
+../main/c64x/make/iblinitspinor.ENDIAN_TAG.oc
+../hw/c64x/make/spi.ENDIAN_TAG.oc
+#endif
+
+
+
+
+
diff --git a/src/make/ibl_c66xk2x/ibl_objs_template.inc b/src/make/ibl_c66xk2x/ibl_objs_template.inc
--- /dev/null
@@ -0,0 +1,107 @@
+/* ibl_objs_template.inc
+ *
+ * list of oject files tagged with the endian field for replacement during make
+ */
+
+../main/c64x/make/iblmain.ENDIAN_TAG.oc
+../device/c64x/make/c66xk2x.ENDIAN_TAG.oc
+../device/c64x/make/c66xk2xutil.ENDIAN_TAG.oc
+../driver/c64x/make/timer.ENDIAN_TAG.oc
+../hw/c64x/make/t64.ENDIAN_TAG.oc
+../hw/c64x/make/psc.ENDIAN_TAG.oc
+../hw/c64x/make/emif4.ENDIAN_TAG.oc
+../device/c64x/make/c64x.ENDIAN_TAG.oa
+../hw/c64x/make/pll.ENDIAN_TAG.oc
+../hw/c64x/make/cfgpll.ENDIAN_TAG.oc
+../hw/c64x/make/cfgpll2.ENDIAN_TAG.oc
+../hw/c64x/make/c66x_uart.ENDIAN_TAG.oc
+
+#ifndef EXCLUDE_BIS
+../interp/c64x/make/bis.ENDIAN_TAG.oc
+#endif
+
+#ifndef EXCLUDE_COFF
+../interp/c64x/make/cload.ENDIAN_TAG.oc
+../interp/c64x/make/osal.ENDIAN_TAG.oc
+#endif
+
+#ifndef EXCLUDE_BLOB
+../interp/c64x/make/blob.ENDIAN_TAG.oc
+#endif
+
+#ifndef EXCLUDE_ELF
+../interp/c64x/make/dload.ENDIAN_TAG.oc
+../interp/c64x/make/elfwrap.ENDIAN_TAG.oc
+../interp/c64x/make/dlw_client.ENDIAN_TAG.oc
+../interp/c64x/make/dload_endian.ENDIAN_TAG.oc
+../interp/c64x/make/ArrayList.ENDIAN_TAG.oc
+#endif
+
+
+#ifndef EXCLUDE_ETH
+../ethboot/c64x/make/ethboot.ENDIAN_TAG.oc
+../driver/c64x/make/net.ENDIAN_TAG.oc
+../driver/c64x/make/arp.ENDIAN_TAG.oc
+../driver/c64x/make/ip.ENDIAN_TAG.oc
+../driver/c64x/make/udp.ENDIAN_TAG.oc
+../driver/c64x/make/stream.ENDIAN_TAG.oc
+../driver/c64x/make/bootp.ENDIAN_TAG.oc
+../driver/c64x/make/tftp.ENDIAN_TAG.oc
+../hw/c64x/make/mdio.ENDIAN_TAG.oc
+../hw/c64x/make/cpsw.ENDIAN_TAG.oc
+../hw/c64x/make/qm.ENDIAN_TAG.oc
+../hw/c64x/make/cpdma.ENDIAN_TAG.oc
+../hw/c64x/make/pa.ENDIAN_TAG.oc
+../hw/c64x/make/serdes.ENDIAN_TAG.oc
+../hw/c64x/make/sgmii.ENDIAN_TAG.oc
+../hw/c64x/make/gmacsl.ENDIAN_TAG.oc
+#endif
+
+
+/* -------------- */
+#if (!defined(EXCLUDE_NAND_EMIF) || !defined(EXCLUDE_NAND_SPI) || !defined(EXCLUDE_NAND_GPIO))
+
+../nandboot/c64x/make/nandboot.ENDIAN_TAG.oc
+../driver/c64x/make/nand.ENDIAN_TAG.oc
+../ecc/c64x/make/3byte_ecc.ENDIAN_TAG.oc
+
+ #ifndef EXCLUDE_NAND_EMIF
+ ../hw/c64x/make/nandemif25.ENDIAN_TAG.oc
+ #endif
+
+ #ifndef EXCLUDE_NAND_GPIO
+ ../hw/c64x/make/gpio.ENDIAN_TAG.oc
+ ../hw/c64x/make/nandgpio.ENDIAN_TAG.oc
+ #endif
+
+ #ifndef EXCLUDE_NAND_SPI
+ ../hw/c64x/make/nandspi.ENDIAN_TAG.oc
+ #endif
+
+#endif
+/* -------------- */
+
+
+
+/* -------------- */
+#if (!defined(EXCLUDE_NOR_EMIF) || !defined(EXCLUDE_NOR_SPI))
+
+../norboot/c64x/make/norboot.ENDIAN_TAG.oc
+../driver/c64x/make/nor.ENDIAN_TAG.oc
+../hw/c64x/make/emif25.ENDIAN_TAG.oc
+
+ #ifndef EXCLUDE_NOR_SPI
+ ../hw/c64x/make/norspi.ENDIAN_TAG.oc
+ #endif
+
+ #ifndef EXCLUDE_NOR_EMIF
+ ../hw/c64x/make/noremif25.ENDIAN_TAG.oc
+ #endif
+
+#endif
+/* -------------- */
+
+
+#if (!defined(EXCLUDE_NOR_SPI) || !defined(EXCLUDE_NAND_SPI))
+../hw/c64x/make/spi.ENDIAN_TAG.oc
+#endif
diff --git a/src/make/ibl_c66xk2x/spiRom.map.pre b/src/make/ibl_c66xk2x/spiRom.map.pre
--- /dev/null
@@ -0,0 +1,80 @@
+#include "iblcfg.h"
+; This file is run through the C preprocessor to get the build time layout information
+; The following values must be defined:
+; SPI_CSEL - The SPI chip select of the eeprom holding the ROM boot info and the layout info
+; SPI_ADDR_WIDTH - Number of bits in the SPI address
+; SPI_NPINS - Number of pins used by the interface (4 or 5)
+; SPI_MODE - SPI operation mode (0-3)
+; INIT_EXE_FILE - The SPI blocked stage 1 of the ibl
+; EXE_FILE_1 - The SPI blocked stage 2 of the ibl, must be the little endian version
+; EXE_FILE_2 - The SPI blocked stage 2 of the ibl, must be the big endian version
+; PAD_FILE_ID_1 - This pad holds the IBL configuration structure for the little endian version
+; PAD_FILE_ID_2 - This pad holds the IBL configuration structure for the big endian version
+;
+; The section statement directs the ROM boot loader to load the initial endian independent
+; portion of the IBL
+section
+{
+ param_index = 0
+ boot_mode = 50
+ sw_pll_prediv = 0
+ sw_pll_mult = 0
+ sw_pll_postdiv = 0
+ sw_pll_flags = 0
+
+ options = 1
+ core_freq_mhz = 800
+
+ bus_freq_mhz = 1
+ bus_freq_khz = 0
+
+ addr_width = SPI_ADDR_WIDTH
+ n_pins = SPI_NPIN
+ mode = SPI_MODE
+ csel = SPI_CSEL
+
+ exe_file = INIT_EXE_FILE
+}
+
+; The layout statement defines how the resulting SPI image is layed out. The base address
+; of this (given in the dev_addr) statement must be known to the initial IBL program
+; at compile time. The layout block is simple a group of 32 bit i2c addresses, so
+; the order of the exe_file and pad_file_id statements must be configured so as to
+; match the definition of struct iblI2cMap_t defined in ibl.h.
+layout
+{
+ dev_addr = IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_LSW ; Defined in iblcfg.h
+ dev_addr_ext = IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW
+ file_align = 0x80
+
+ exe_file = EXE_FILE_1
+ pad_file_id = PAD_FILE_ID_1
+
+
+ exe_file = EXE_FILE_2
+ pad_file_id = PAD_FILE_ID_2
+}
+
+; The pad statements simply provide space for the IBL configuration structures. It is valid to
+; have a single configuration structure which is used for both endian values.
+pad
+{
+ pad_file_id = 1
+ dev_addr = 0x500
+ dev_addr_ext = IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW
+ len = 0x300
+}
+
+#if (PAD_FILE_ID_1 != PAD_FILE_ID_2)
+pad
+{
+ pad_file_id = 2
+ dev_addr = 0x800
+ dev_addr_ext = I2C_BUS_ADDR
+ len = IBL_CFG_SPI_MAP_TABLE_DATA_ADDR_MSW
+}
+#endif
+
+
+
+
diff --git a/src/make/makestg1 b/src/make/makestg1
--- a/src/make/makestg1
+++ b/src/make/makestg1
#* [COMPACT_I2C=yes] [I2C_SIZE_BYTES=..]
#*******************************************************************************************
-IBLS_C6X= c6455 c6472 c6474 c6474l c6457 c66x c665x
+IBLS_C6X= c6455 c6472 c6474 c6474l c6457 c66x c665x c66xk2x
# Excluding functions from the build reduces the I2C eeprom memory used and
diff --git a/src/make/makestg2 b/src/make/makestg2
--- a/src/make/makestg2
+++ b/src/make/makestg2
CLEAN_MODULES+=$(addprefix clean_,$(CFG_MODULES))
-TARGETS= c6472 c6474 c6474l c6455 c6457 c66x c665x
+TARGETS= c6472 c6474 c6474l c6455 c6457 c66x c665x c66xk2x
# The main module needs to know the device address of the i2c where the image map resides
MAINDEFS=-DIBL_CFG_I2C_MAP_TABLE_DATA_BUS_ADDR=$(I2C_BUS_ADDR)
$(TARGETS): iblMain
-ifeq (($(TARGET),c66x) || $(TARGET),c665x )
+ifeq (($(TARGET),c66x) || $(TARGET),c665x || $(TARGET),c66xk2x)
HAS_SPI=1
else
HAS_SPI=0
../util/btoccs/b2i2c ibl_$(TARGET)/ibl.b ibl_$(TARGET)/ibl.i2c.b
../util/btoccs/b2ccs ibl_$(TARGET)/ibl.i2c.b ibl_$(TARGET)/ibl_init.i2c.$(IEXT).ccs
- sed -e 's/\\r//' ../util/symExtract/symExtract > ../util/symExtract/symExtract_unix
+ sed -e 's/\r//' ../util/symExtract/symExtract > ../util/symExtract/symExtract_unix
bash ../util/symExtract/symExtract_unix ibl_$(TARGET)/ibl_$(TARGET)_init.map ibl_$(TARGET)/ibl_init_symbols.inc $(COMMON_SYMBOLS)
rm -f ../util/symExtract/symExtract_unix
index d6a0245a6d6e1aa6f7e2238f6b68fb70f0d6040c..6cb5212e36e6cf5b3028ed3a4f4e0a556684c48f 100755 (executable)
--- a/src/make/setupenvLnx.sh
+++ b/src/make/setupenvLnx.sh
export OS="Linux"
if [ -z $C6X_CGT_VERSION ]; then
- C6X_CGT_VERSION=7.2.4
+ C6X_CGT_VERSION=7.3.4
fi
if [ -z "$C6X_BASE_DIR" ]; then
- for dir in {~,}{,/opt}/{ti,TI,texas_instruments}/TI_CGT_C6000_${C6X_CGT_VERSION} {~,}{,/opt}/{ti,texas_instruments}/ccsv5/tools/compiler/c6000 ; do
+ for dir in {~,}{,/opt}/{ti,TI,texas_instruments}/TI_CGT_C6000_${C6X_CGT_VERSION} {~,}{,/opt}/{ti,texas_instruments}/ccsv5/tools/compiler/{c6000,c6000_${C6X_CGT_VERSION}} ; do
if [ -x $dir/bin/cl6x ]; then
C6X_BASE_DIR=$dir
break
index f01a2d4d50117bd79b51885590e949689aaa7b96..fa6f749a2e02b27a20d8f555502239dd57c1817c 100755 (executable)
--- a/src/make/setupenvMsys.sh
+++ b/src/make/setupenvMsys.sh
# Environment setup to be done if using MSYS Bash shell for build
# Specify the base directory of the c6000 compiler with UNIX style path separator
-export C6X_BASE_DIR='"C:/Program Files/Texas Instruments/C6000 Code Generation Tools 7.2.4"'
+export C6X_BASE_DIR='"C:/ti/ccsv5/tools/compiler/c6000_7.3.4"'
# Specify the base directory of the c6000 compiler in format understandable by the MSYS Bash shell
export C6X_BASE_DIR_MSYS=/c/Program\ Files/Texas\ Instruments/C6000\ Code\ Generation\ Tools\ 7\.2\.4
+export C6X_BASE_DIR_MSYS=/c/ti/ccsv5/tools/compiler/c6000_7\.3\.4
# Don't modify the below variables. They are derived from the above definitions
export PATH=$PATH:$C6X_BASE_DIR_MSYS/bin
-C6X_C_DIR+= $(IBL_ROOT)
+C6X_C_DIR= $(IBL_ROOT)
C6X_C_DIR+= ;$(IBL_ROOT)/arch/$(ARCH)
C6X_C_DIR+= ;$(IBL_ROOT)/device
C6X_C_DIR+= ;$(IBL_ROOT)/device/$(TARGET)
-C6X_C_DIR+= $(IBL_ROOT)
+C6X_C_DIR= $(IBL_ROOT)
C6X_C_DIR+= ;$(IBL_ROOT)/arch/$(ARCH)
C6X_C_DIR+= ;$(IBL_ROOT)/device
C6X_C_DIR+= ;$(IBL_ROOT)/device/$(TARGET)
#*
#***************************************************************
-DEVICES= c6455 c6472 c6474 c6474l c6457 c66x c665x
+DEVICES= c6455 c6472 c6474 c6474l c6457 c66x c665x c66xk2x
all:
@echo must specify a target [ $(DEVICES) ]
index b1a2842c2826ee3d6b798ff770035777eaf6e74a..4d373918db5427b22aae448ff612c04192f24900 100755 (executable)
#define ibl_EVM_C6670L 0x50 /**< C6670 Low Cost EVM */
#define ibl_EVM_C6678L 0x60 /**< C6678 Low Cost EVM */
#define ibl_EVM_C6657L 0x70 /**< C6657 Low Cost EVM */
+#define ibl_EVM_TCI6634K2K 0x80 /**< TCI6634K2K Low Cost EVM */
/* @} */
menuitem "EVM c6472 IBL";
ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
-
ibl.sgmiiConfig[0].configure = 1;
ibl.sgmiiConfig[0].adviseAbility = 1;
ibl.sgmiiConfig[0].control = 1;
}
+menuitem "EVM TCI6634K2K IBL";
+
+hotmenu setConfig_tci6634k2k_main()
+{
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_TCI6634K2K;
+
+ /* Main PLL: 122.88 MHz reference, 983 MHz output */
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 16;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
+
+ /* TBD: DDR PLL: 66.66->100 MHz reference, 400 MHz output, for an 800MHz DDR rate */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
+ ibl.pllConfig[ibl_DDR_PLL].mult = 20;
+ ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 1333;
+
+ /* Net PLL: 122.88 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 348 MHz to PA) */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_NET_PLL].prediv = 1;
+ ibl.pllConfig[ibl_NET_PLL].mult = 17;
+ ibl.pllConfig[ibl_NET_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1044;
+
+
+ ibl.ddrConfig.configDdr = 1;
+ ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
+
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;
+ ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;
+ ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;
+ ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;
+ ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
+
+ /* TBD: check SERDES configuration */
+ ibl.sgmiiConfig[0].configure = 1;
+ ibl.sgmiiConfig[0].adviseAbility = 1;
+ ibl.sgmiiConfig[0].control = 1;
+ ibl.sgmiiConfig[0].txConfig = 0x108a1;
+ ibl.sgmiiConfig[0].rxConfig = 0x700621;
+ ibl.sgmiiConfig[0].auxConfig = 0x41;
+
+ ibl.sgmiiConfig[1].configure = 1;
+ ibl.sgmiiConfig[1].adviseAbility = 1;
+ ibl.sgmiiConfig[1].control = 1;
+ ibl.sgmiiConfig[1].txConfig = 0x108a1;
+ ibl.sgmiiConfig[1].rxConfig = 0x700621;
+ ibl.sgmiiConfig[1].auxConfig = 0x41;
+
+ ibl.mdioConfig.nMdioOps = 0;
+
+ ibl.spiConfig.addrWidth = 24;
+ ibl.spiConfig.nPins = 5;
+ ibl.spiConfig.mode = 1;
+ ibl.spiConfig.csel = 2;
+ ibl.spiConfig.c2tdelay = 1;
+ ibl.spiConfig.busFreqMHz = 20;
+
+ ibl.emifConfig[0].csSpace = 2;
+ ibl.emifConfig[0].busWidth = 8;
+ ibl.emifConfig[0].waitEnable = 0;
+
+ ibl.emifConfig[1].csSpace = 0;
+ ibl.emifConfig[1].busWidth = 0;
+ ibl.emifConfig[1].waitEnable = 0;
+
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
+ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
+ ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x20000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 512) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x20000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 512) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xFFC000; /* Image 0 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xFFC000; /* Image 1 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xFFC000; /* Image 0 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xFFC000; /* Image 1 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 1024;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0x00;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0x30;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = TRUE;
+
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
+ ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
+
+ ibl.bootModes[2].u.ethBoot.doBootp = FALSE;
+ ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 192,168,2,100);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 192,168,2,101);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,2,1);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Use the e-fuse value */
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'a';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = 'p';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = 'p';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '.';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = 'o';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = 'u';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 't';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
+ ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
+ ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
+
+ ibl.chkSum = 0;
+}
#*
#**************************************************************************
-DEVICES= c6455 c6472 c6474 c6474l c6457 c66x c665x
+DEVICES= c6455 c6472 c6474 c6474l c6457 c66x c665x c66xk2x
ifndef IBL_ROOT
IBL_ROOT=../..
PLL_OBJS+= ../../device/c64x/make/c64x.$(IEXT).oa
PSC_OBJS= ../../hw/c64x/make/psc.$(IEXT).oc
else
- PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc
+ ifeq ($(TARGET),c66xk2x)
+ PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc $(PLL_PATH)/cfgpll.$(IEXT).oc $(PLL_PATH)/cfgpll2.$(IEXT).oc
+ PLL_OBJS+= ../../device/c64x/make/c64x.$(IEXT).oa
+ PSC_OBJS= ../../hw/c64x/make/psc.$(IEXT).oc
+ else
+ PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc
+ endif
endif
endif
else
ifeq ($(TARGET),c665x)
TFILES= ../../device/c64x/make/$(TARGET)util.$(IEXT).oc
+ else
+ ifeq ($(TARGET),c66xk2x)
+ TFILES= ../../device/c64x/make/$(TARGET)util.$(IEXT).oc
+ endif
endif
endif
ifeq ($(EVM),c6657l)
DEVICE_ID = 8
endif
+ifeq ($(EVM),tci6634k2k)
+ DEVICE_ID = 9
+endif
LNK_OPTS +=
###############################################################################
ibl_t c6455_ibl_config(void)
{
- ibl_t ibl;
+ ibl_t ibl;
memset(&ibl, 0, sizeof(ibl_t));
-
+
ibl.iblMagic = ibl_MAGIC_VALUE;
ibl.iblEvmType = ibl_EVM_C6455L;
ibl.ddrConfig.configDdr = TRUE;
ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */
- ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */
ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */
ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */
{
ibl_t ibl;
memset(&ibl, 0, sizeof(ibl_t));
-
+
ibl.iblMagic = ibl_MAGIC_VALUE;
ibl.iblEvmType = ibl_EVM_C6474M;
ibl.ddrConfig.configDdr = TRUE;
ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
- ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
{
ibl_t ibl;
memset(&ibl, 0, sizeof(ibl_t));
-
+
ibl.iblMagic = ibl_MAGIC_VALUE;
ibl.iblEvmType = ibl_EVM_C6474L;
ibl.ddrConfig.configDdr = TRUE;
ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
- ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */
ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */
ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
-
+
ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
{
ibl_t ibl;
memset(&ibl, 0, sizeof(ibl_t));
-
+
ibl.iblMagic = ibl_MAGIC_VALUE;
ibl.iblEvmType = ibl_EVM_C6457L;
ibl.ddrConfig.configDdr = TRUE;
ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */
- ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a0e; /* Refresh 333Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a0e; /* Refresh 333Mhz */
ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x832474da; /* Timing 1 */
ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0144c742; /* Timing 2 */
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x001800C6;
ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x200000; /* Image 0 NAND offset address (block 1) in BE mode */
ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 2048) in BE mode */
ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_GPIO;
-
+
ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0xe0000000; /* Image 0 load start address in LE mode */
ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0xe0000000; /* Image 0 branch address after loading in LE mode */
ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
{
ibl_t ibl;
memset(&ibl, 0, sizeof(ibl_t));
-
+
ibl.iblMagic = ibl_MAGIC_VALUE;
ibl.iblEvmType = ibl_EVM_C6472L;
ibl.ddrConfig.configDdr = TRUE;
ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */
- ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */
+ ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */
ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */
ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */
ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */
ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 0;
ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
/* bootMode[2] not configured */
ibl.bootModes[2].bootMode = ibl_BOOT_MODE_NONE;
-
+
ibl.chkSum = 0;
return(ibl);
{
ibl_t ibl;
memset(&ibl, 0, sizeof(ibl_t));
-
+
ibl.iblMagic = ibl_MAGIC_VALUE;
ibl.iblEvmType = ibl_EVM_C6678L;
ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
/* DDR PLL: */
- ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
ibl.pllConfig[ibl_DDR_PLL].mult = 20;
ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
ibl.bootModes[0].port = 0;
ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
- ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
- ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 9;
ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
-
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
-
+
ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
{
ibl_t ibl;
memset(&ibl, 0, sizeof(ibl_t));
-
+
ibl.iblMagic = ibl_MAGIC_VALUE;
ibl.iblEvmType = ibl_EVM_C6670L;
ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
/* DDR PLL */
- ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
ibl.pllConfig[ibl_DDR_PLL].mult = 20;
ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
ibl.bootModes[0].port = 0;
ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
- ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
- ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 9;
ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
- ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0;
ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0;
ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = FALSE;
-
+
ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
{
ibl_t ibl;
memset(&ibl, 0, sizeof(ibl_t));
-
+
ibl.iblMagic = ibl_MAGIC_VALUE;
ibl.iblEvmType = ibl_EVM_C6657L;
ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000;
/* DDR PLL: */
- ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
ibl.pllConfig[ibl_DDR_PLL].prediv = 3;
ibl.pllConfig[ibl_DDR_PLL].mult = 40;
ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
ibl.spiConfig.addrWidth = 24;
ibl.spiConfig.nPins = 5;
- ibl.spiConfig.mode = 1;
+ ibl.spiConfig.mode = 1;
ibl.spiConfig.csel = 2;
ibl.spiConfig.c2tdelay = 1;
ibl.spiConfig.busFreqMHz = 20;
ibl.bootModes[0].port = 0;
ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
- ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
- ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
return(ibl);
}
+ibl_t tci6634k2k_ibl_config(void)
+{
+ /* TBD: sync with gel */
+ ibl_t ibl;
+ memset(&ibl, 0, sizeof(ibl_t));
+
+ ibl.iblMagic = ibl_MAGIC_VALUE;
+ ibl.iblEvmType = ibl_EVM_TCI6634K2K;
+
+ /* Main PLL: 122.88 MHz reference, 983 MHz output */
+ ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].prediv = 1;
+ ibl.pllConfig[ibl_MAIN_PLL].mult = 16;
+ ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983;
+
+ /* TBD: input freq 66.67MHz -> 100 MHz, DDR PLL */
+ ibl.pllConfig[ibl_DDR_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_DDR_PLL].prediv = 1;
+ ibl.pllConfig[ibl_DDR_PLL].mult = 20;
+ ibl.pllConfig[ibl_DDR_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 1333;
+
+ /* Net PLL: 122.88 MHz reference, 1044 MHz output (followed by a built in divide by 3 to give 348 MHz to PA) */
+ ibl.pllConfig[ibl_NET_PLL].doEnable = 1;
+ ibl.pllConfig[ibl_NET_PLL].prediv = 1;
+ ibl.pllConfig[ibl_NET_PLL].mult = 17;
+ ibl.pllConfig[ibl_NET_PLL].postdiv = 2;
+ ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1044;
+
+
+ ibl.ddrConfig.configDdr = 1;
+ ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1;
+
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8;
+ ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0;
+ ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0;
+ ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0;
+ ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0;
+ ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0;
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d;
+ ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0;
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0;
+ ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0;
+ ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0;
+
+ /* TBD: SERDES configurations ?? */
+ ibl.sgmiiConfig[0].configure = 1;
+ ibl.sgmiiConfig[0].adviseAbility = 1;
+ ibl.sgmiiConfig[0].control = 1;
+ ibl.sgmiiConfig[0].txConfig = 0x108a1;
+ ibl.sgmiiConfig[0].rxConfig = 0x700621;
+ ibl.sgmiiConfig[0].auxConfig = 0x41;
+
+ ibl.sgmiiConfig[1].configure = 1;
+ ibl.sgmiiConfig[1].adviseAbility = 1;
+ ibl.sgmiiConfig[1].control = 1;
+ ibl.sgmiiConfig[1].txConfig = 0x108a1;
+ ibl.sgmiiConfig[1].rxConfig = 0x700621;
+ ibl.sgmiiConfig[1].auxConfig = 0x51;
+
+ ibl.mdioConfig.nMdioOps = 0;
+
+ ibl.spiConfig.addrWidth = 24;
+ ibl.spiConfig.nPins = 5;
+ ibl.spiConfig.mode = 1;
+ ibl.spiConfig.csel = 2;
+ ibl.spiConfig.c2tdelay = 1;
+ ibl.spiConfig.busFreqMHz = 20;
+
+ ibl.emifConfig[0].csSpace = 2;
+ ibl.emifConfig[0].busWidth = 8;
+ ibl.emifConfig[0].waitEnable = 0;
+
+ ibl.emifConfig[1].csSpace = 0;
+ ibl.emifConfig[1].busWidth = 0;
+ ibl.emifConfig[1].waitEnable = 0;
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NOR;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
+ ibl.bootModes[0].u.norBoot.bootAddress[0][0] = 0; /* Image 0 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[0][1] = 0xA00000; /* Image 1 NOR offset byte address in LE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][0] = 0; /* Image 0 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.bootAddress[1][1] = 0xA00000; /* Image 1 NOR offset byte address in BE mode */
+ ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
+ ibl.bootModes[0].u.norBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].sizeBytes = 0xA00000; /* Image 0 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].sizeBytes = 0xA00000; /* Image 1 size (10 MB) in BE mode */
+ ibl.bootModes[0].u.norBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+ ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[1].port = 0;
+
+ ibl.bootModes[1].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][0] = 0x20000; /* Image 0 NAND offset address (block 1) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[0][1] = 0x4000000; /* Image 1 NAND offset address (block 512) in LE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][0] = 0x20000; /* Image 0 NAND offset address (block 1) in BE mode */
+ ibl.bootModes[1].u.nandBoot.bootAddress[1][1] = 0x4000000; /* Image 1 NAND offset address (block 512) in BE mode */
+ ibl.bootModes[1].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
+
+ ibl.bootModes[1].u.nandBoot.blob[0][0].startAddress = 0x80000000; /* Image 0 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].sizeBytes = 0xFFC000; /* Image 0 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].startAddress = 0x80000000; /* Image 1 load start address in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].sizeBytes = 0xFFC000; /* Image 1 size in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[0][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in LE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].startAddress = 0x80000000; /* Image 0 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].sizeBytes = 0xFFC000; /* Image 0 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][0].branchAddress = 0x80000000; /* Image 0 branch address after loading in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].startAddress = 0x80000000; /* Image 1 load start address in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].sizeBytes = 0xFFC000; /* Image 1 size in BE mode */
+ ibl.bootModes[1].u.nandBoot.blob[1][1].branchAddress = 0x80000000; /* Image 1 branch address after loading in BE mode */
+
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageSizeBytes = 2048;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageEccBytes = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pagesPerBlock = 64;
+ ibl.bootModes[1].u.nandBoot.nandInfo.totalBlocks = 1024;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[1].u.nandBoot.nandInfo.blockOffset = 22;
+ ibl.bootModes[1].u.nandBoot.nandInfo.pageOffset = 16;
+ ibl.bootModes[1].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[4] = 4;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[5] = 6;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[6] = 7;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[7] = 13;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[8] = 14;
+ ibl.bootModes[1].u.nandBoot.nandInfo.eccBytesIdx[9] = 15;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
+ ibl.bootModes[1].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xff;
+
+ ibl.bootModes[1].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPre = 0x00;
+ ibl.bootModes[1].u.nandBoot.nandInfo.readCommandPost = 0x30;
+ ibl.bootModes[1].u.nandBoot.nandInfo.postCommand = TRUE;
+
+
+ ibl.bootModes[2].bootMode = ibl_BOOT_MODE_TFTP;
+ ibl.bootModes[2].priority = ibl_HIGHEST_PRIORITY+1;
+ ibl.bootModes[2].port = ibl_PORT_SWITCH_ALL;
+
+ ibl.bootModes[2].u.ethBoot.doBootp = TRUE;
+ ibl.bootModes[2].u.ethBoot.useBootpServerIp = TRUE;
+ ibl.bootModes[2].u.ethBoot.useBootpFileName = TRUE;
+ ibl.bootModes[2].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB;
+
+
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.ipAddr, 192,168,1,3);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.serverIp, 192,168,1,2);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.gatewayIp, 192,168,1,1);
+ SETIP(ibl.bootModes[2].u.ethBoot.ethInfo.netmask, 255,255,255,0);
+
+ /* Use the e-fuse value */
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[0] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[1] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[2] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[3] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[4] = 0;
+ ibl.bootModes[2].u.ethBoot.ethInfo.hwAddress[5] = 0;
+
+
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[0] = 'c';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[1] = '6';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[2] = '6';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[3] = '3';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[4] = '4';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[5] = '-';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[6] = 'l';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[7] = 'e';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[8] = '.';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[9] = 'b';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[10] = 'i';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[11] = 'n';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[12] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[13] = '\0';
+ ibl.bootModes[2].u.ethBoot.ethInfo.fileName[14] = '\0';
+
+ ibl.bootModes[2].u.ethBoot.blob.startAddress = 0x80000000; /* Load start address */
+ ibl.bootModes[2].u.ethBoot.blob.sizeBytes = 0x20000000;
+ ibl.bootModes[2].u.ethBoot.blob.branchAddress = 0x80000000; /* Branch address after loading */
+
+ ibl.chkSum = 0;
+
+ return(ibl);
+}
#define ibl_EVM_C6670L 0x50 /**< C6670 Low Cost EVM */
#define ibl_EVM_C6678L 0x60 /**< C6678 Low Cost EVM */
#define ibl_EVM_C6657L 0x70 /**< C6657 Low Cost EVM */
+#define ibl_EVM_TCI6634K2K 0x80 /**< TCI6634K2K Low Cost EVM */
/**
* @brief
ibl_t c6678_ibl_config(void);
ibl_t c6670_ibl_config(void);
ibl_t c6657_ibl_config(void);
+ibl_t tci6634k2k_ibl_config(void);
[6] = &c6678_ibl_config,
[7] = &c6670_ibl_config,
[8] = &c6657_ibl_config,
+ [9] = &tci6634k2k_ibl_config,
};
int ncfgs = ARRAY_SIZE(cfg);
if (device_id > 0 && device_id < ncfgs)
ibl_params = (*cfg[device_id])();
-
+
mfp = fopen(input_file, "r");
modifyIblConfig(mfp, &ibl_params);
fclose(mfp);
-
+
if (fwrite((void*)&ibl_params, sizeof(ibl_t), 1, fp) != 1) {
fclose(fp);
return -1;
return 0;
}
-int32_t
+int32_t
xtoi
(
- char *xs,
+ char *xs,
uint32_t *result
)
{
uint32_t szlen = strlen(xs);
int32_t i, xv, fact;
-
+
if (szlen > 0)
{
/* Converting more than 32bit hexadecimal value? */
if (szlen>8) return 2; /* exit */
-
+
/* Begin conversion here */
*result = 0;
fact = 1;
-
+
/* Run until no more character to convert */
for(i=szlen-1; i>=0 ;i--)
{
}
return 0;
}
-
+
// Nothing to convert
return 1;
}
}
device_id = (uint32_t)atoi(data);
-
+
fgets(line, MAX_LINE_LENGTH, fp);
key = (char *)strtok(line, tokens);
data = (char *)strtok(NULL, tokens);
char tokens[] = " :=;\n\r";
char *key, *data;
unsigned char ethBootIdx=DEFAULT_ETHBOOT_IDX, i0, i1, i2, i3;
- if ((device_id == 6) || (device_id == 7) || (device_id == 8))
+ if ((device_id == 6) || (device_id == 7) || (device_id == 8))
ethBootIdx = EVM_C6678_ETHBOOT_IDX;
memset(line, 0, MAX_LINE_LENGTH);
{
key = (char *)strtok(line, tokens);
data = (char *)strtok(NULL, tokens);
- if ( (key == NULL) || (data == NULL) ) {}
+ if ( (key == NULL) || (data == NULL) ) {}
else if (strcmp(key, DOBOOTP) == 0)
{
if (strcmp(data, "TRUE") == 0)
/*
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
* are met:
*
- * Redistributions of source code must retain the above copyright
+ * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
*************************************************************************************
* FILE NAME: romparse.c
*
- * DESCRIPTION: Creates a ccs hex file which contains the i2c eprom boot parameter
+ * DESCRIPTION: Creates a ccs hex file which contains the i2c eprom boot parameter
* tables as well as any code.
*
*************************************************************************************/
int max_index = 0; /* maximum table index, used for compacting output */
/************************************************************************************
- * Declaration: Layout tables.
+ * Declaration: Layout tables.
************************************************************************************/
-layout_t layouts[MAX_LAYOUTS]; /* Array of layout structures */
+layout_t layouts[MAX_LAYOUTS]; /* Array of layout structures */
int currentLayout; /* Currently active layout */
/************************************************************************************
/*************************************************************************************
* Declaration: The next free address in the ROM for general data usage. For the
- * start address there is room for the initial boot parameter tables,
+ * start address there is room for the initial boot parameter tables,
* plus room for the PCI eeai config.
*************************************************************************************/
int romBase = DATA_BASE;
padLayoutOrder[currentPL].type = LAYOUT;
padLayoutOrder[currentPL].index = currentLayout;
currentPL += 1;
-
+
currentLayout += 1; /* Advance to the next layout */
if (currentLayout < MAX_LAYOUTS)
initLayout (&layouts[currentLayout]);
-}
+}
/*************************************************************************************
* FUNCTION PURPOSE: Initialize a pad structure
current_table.common.length = 30;
- #if (defined(c66x) || defined(c665x))
+ #if (defined(c66x) || defined(c665x) || defined(c66xk2x))
if (current_table.common.boot_mode == BOOT_MODE_SPI)
current_table.common.length = sizeof(BOOT_PARAMS_SPI_T);
else
current_table.common.length = sizeof(BOOT_PARAMS_I2C_T);
#endif
-
+
current_table.common.checksum = 0;
/* Copy the table */
} /* setPciParams */
-
+
/***************************************************************************************
* FUNCTION PURPOSE: Store an assignment
case MY_I2C_ID: current_table.i2c.my_i2c_id = value;
break;
- case CORE_FREQ_MHZ:
- #if (defined(c66x) || defined(c665x))
+ case CORE_FREQ_MHZ:
+ #if (defined(c66x) || defined(c665x) || defined(c66xk2x))
if (current_table.common.boot_mode == BOOT_MODE_SPI) {
current_table.spi.cpuFreqMhz = value;
break;
}
#endif
-
+
current_table.i2c.core_freq_mhz = value;
break;
case NEXT_DEV_ADDR: current_table.i2c.next_dev_addr = value;
break;
-
+
case NEXT_DEV_ADDR_EXT: current_table.i2c.next_dev_addr_ext = value;
break;
case ADDRESS_DELAY: current_table.i2c.address_delay = value;
break;
-#if (!defined(c6455) && !defined(c66x) && !defined(c665x))
+#if (!defined(c6455) && !defined(c66x) && !defined(c665x) && !defined(c66xk2x))
case SWPLL: current_table.i2c.swPll = value;
break;
#endif
-#if (defined(c66x) || defined(c665x))
+#if (defined(c66x) || defined(c665x) || defined(c66xk2x))
case SWPLL_PREDIV: current_table.common.swPllCfg_lsw &= 0x00ff;
current_table.common.swPllCfg_lsw |= ((value & 0xff) << 16);
break;
break;
-#if (defined(c66x) || defined(c665x))
+#if (defined(c66x) || defined(c665x) || defined(c66xk2x))
case N_PINS: current_table.spi.nPins = value;
break;
case LAYOUT:
- if (currentLayout >= MAX_LAYOUTS) {
+ if (currentLayout >= MAX_LAYOUTS) {
fprintf (stderr, "romparse: Too many layout sections (max = %d)\n", MAX_LAYOUTS);
exit (-1);
}
/*******************************************************************************
* FUNCTION PURPOSE: Parse a string input.
*******************************************************************************
- * DESCRIPTION: Takes a string input. Currently only the i2c exe file name can be
- * assigned a string.
+ * DESCRIPTION: Takes a string input. Currently only the i2c exe file name can be
+ * assigned a string.
*******************************************************************************/
void assignKeyStr (int value, char *y)
{
fprintf (stderr, "romparse: Number of layout sections exceeded (max = %d)\n", MAX_LAYOUTS);
}
-
+
return;
}
current_table.i2c.dev_addr_ext = i2cRomBase;
} else { /* LAYOUT */
-
+
if (currentLayout < MAX_LAYOUTS) {
if (layouts[currentLayout].nPlt <= MAX_LAYOUT_FILES) {
layouts[currentLayout].plt[layouts[currentLayout].nPlt].type = PLT_FILE;
fprintf (stderr, "romparse: Number of layout sections exceeded (max = %d)\n", MAX_LAYOUTS);
}
-
-
+
+
}
} /* assignKeyStr */
/* Compact the i2c eeprom to use the minimum memory possible */
base = (i2cRomBase << 16) + PCI_PARAM_BASE;
- nTables = NUM_BOOT_PARAM_TABLES;
+ nTables = NUM_BOOT_PARAM_TABLES;
if ((compact != 0) && (pciSet == 0)) {
nTables = max_index + 1;
/* Change the layout index value for pad mapping to a true array index value.
* Also reflect the device address from the layout into the pad */
for (i = 0; i < currentLayout; i++) {
-
+
for (j = 0; j < layouts[i].nPlt; j++) {
if (layouts[i].plt[j].type == PLT_PAD) {
if (padLayoutOrder[i].type == LAYOUT) {
- /* Determine the size of the table. Four bytes for each file, plus the 4 byte header */
+ /* Determine the size of the table. Four bytes for each file, plus the 4 byte header */
v1 = (layouts[j].nPlt * 4) + 4;
v2 = (layouts[j].dev_addr << 16) + layouts[j].address;
base = v2 + v1; /* new base is the base plus the size */
- }
+ }
} else { /* Otherwise this is a pad */
if (base > ((pads[j].dev_addr << 16) + pads[j].address)) {
}
for (i = 0; i < NUM_BOOT_PARAM_TABLES; i++) {
- if (progFile[i].align > 0)
+ if (progFile[i].align > 0)
base = ((base + progFile[i].align - 1) / progFile[i].align) * progFile[i].align;
progFile[i].addressBytes = base;
base = base + progFile[i].sizeBytes;
for (i = 0; i < NUM_BOOT_PARAM_TABLES; i++) {
for (j = 0; j < NUM_BOOT_PARAM_TABLES; j++) {
if (progFile[i].tag[j] >= 0) {
-
- #if (defined(c66x) || defined(c665x))
+
+ #if (defined(c66x) || defined(c665x) || defined(c66xk2x))
if (boot_params[progFile[i].tag[j]].common.boot_mode == BOOT_MODE_SPI) {
boot_params[progFile[i].tag[j]].spi.read_addr_lsw = (progFile[i].addressBytes & 0xffff);
boot_params[progFile[i].tag[j]].spi.read_addr_msw = (progFile[i].addressBytes >> 16) & 0xffff;
base = (base + 3) & ~3;
i2cRomStart = (i2cRomBase << 16);
-
+
/* The total length of the i2c eeprom is now stored in base */
/* Write out the ccs header */
fprintf (str, "1651 1 10000 1 %x\n", (base - i2cRomStart) >> 2);
base = imageWord(base, i2cRomStart, image, len << 16);
for (j = 0; j < layouts[i].nPlt; j++) {
-
+
if (layouts[i].plt[j].type == PLT_FILE) {
if (layouts[i].plt[j].index == -1) {
base = imageWord (base, i2cRomStart, image, 0xffffffff);
} else {
base = imageWord (base, i2cRomStart, image, progFile[layouts[i].plt[j].index].addressBytes);
- }
+ }
} else {
v1 = pads[layouts[i].plt[j].index].dev_addr;
v2 = pads[layouts[i].plt[j].index].address;
}
}
-
+
/* Write out each of the program files */
for (i = 0; i < nProgFiles; i++) {
}
/* Write out the data file */
- for (i = 0; i < base - i2cRomStart; i += 4)
+ for (i = 0; i < base - i2cRomStart; i += 4)
fprintf (str, "0x%08x\n", formWord (i, image));
free (image);
return (ret);
}
-
+
/************************************************************************************
* FUNCTION PURPOSE: Parse the input arguments.
return (-1);
}
- inputFile = NULL;
+ inputFile = NULL;
for (i = 1; i < argc; ) {
if (parseIt (argc, argv))
return (-1);
-
+
yyin = fopen (inputFile, "r");
if (yyin == NULL) {
fprintf (stderr, "%s: could not open file %s\n", argv[0], inputFile);
/*
*
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
* are met:
*
- * Redistributions of source code must retain the above copyright
+ * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
* table
*
*************************************************************************************/
-
+
/* tiboot.h defines the boot parameters structure that will be created */
#if defined(c6472)
#include "tiboot_c6472.h"
#include "tiboot_c66x.h"
#elif defined(c665x)
#include "tiboot_c665x.h"
+#elif defined(c66xk2x)
+ #include "tiboot_c66xk2x.h"
#else
#error invalid or missing device specification
#endif
} plt_t;
/* Define a layout table. A layout table is a block of data which contains the addresses
- * of data files. Each address is 32 bits, with the upper 16 bits specifying the i2c
+ * of data files. Each address is 32 bits, with the upper 16 bits specifying the i2c
* id, the lower address the byte address of the 1st block in the table */
#define MAX_LAYOUTS 2
#define MAX_LAYOUT_FILES 8
typedef struct {
int nPlt; /* Number of elements in the plt array */
plt_t plt[MAX_LAYOUT_FILES]; /* Index of each file/pad in order */
-
+
unsigned int address; /* I2c data address of the table */
unsigned int dev_addr; /* I2c device address of the table */
int align;
{
int type; /* Either PAD or LAYOUT */
int index; /* The array index for the pad/layout */
-
+
} padLayoutOrder_t;