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raw | patch | inline | side by side (from parent 1: 1ae68f3)
raw | patch | inline | side by side (from parent 1: 1ae68f3)
author | Hao Zhang <hzhang@ti.com> | |
Fri, 4 Mar 2011 13:34:08 +0000 (08:34 -0500) | ||
committer | Hao Zhang <hzhang@ti.com> | |
Fri, 4 Mar 2011 13:34:08 +0000 (08:34 -0500) |
20 files changed:
index 0eaa973680dcfd2287f92afc44a8230596aa1169..512c8f4bcf53d815b943f960436f1abf622b9eb2 100644 (file)
*/
#define deviceReadBootDevice() BOOT_DEVICE_I2C
-#define IBL_REENTER_ROM 0
-#define iblReEnterRom()
+#define IBL_ENTER_ROM 0
+#define iblEnterRom()
+
+#define IBL_ENABLE_EDC 0
+#define iblEnableEDC()
index 9853337a7045f298627347099d43400a548e5c57..ee4e54e3fe14c39f29b29c6b1497cd732e3763e9 100644 (file)
*/
#define deviceReadBootDevice() BOOT_DEVICE_I2C
-#define IBL_REENTER_ROM 0
-#define iblReEnterRom()
+#define IBL_ENTER_ROM 0
+#define iblEnterRom()
+
+#define IBL_ENABLE_EDC 0
+#define iblEnableEDC()
+
index 135f12e8cc6894c2c6908876fc19579a061c979f..ec9c452d1969d9cb433ea80234e7d33fc3de2879 100644 (file)
*/
#define deviceReadBootDevice() BOOT_DEVICE_I2C
-#define IBL_REENTER_ROM 0
-#define iblReEnterRom()
+#define IBL_ENTER_ROM 0
+#define iblEnterRom()
+
+#define IBL_ENABLE_EDC 0
+#define iblEnableEDC()
+
index ef82b36afd48ae1e79c3cc479157fb489a1b25fd..4c714e4d40333f110f7bc6f4689a6efdbb5d68c0 100644 (file)
*/
#define deviceReadBootDevice() BOOT_DEVICE_I2C
-#define IBL_REENTER_ROM 0
-#define iblReEnterRom()
+#define IBL_ENTER_ROM 0
+#define iblEnterRom()
+
+#define IBL_ENABLE_EDC 0
+#define iblEnableEDC()
+
index 9ad2feea13eab6b2fd8e2d07c09b55817ff0ebbf..8be48a888c4adf4cfaed4bdefcdc1d088a836756 100644 (file)
--- a/src/device/c661x/c661x.c
+++ b/src/device/c661x/c661x.c
void deviceDdrConfig (void)
{
/* The emif registers must be made visible. MPAX mapping 2 is used */
- DEVICE_REG_XMPAX_L(2) = 0x10000000 | 0xf6; /* replacement addr + perm*/
+ DEVICE_REG_XMPAX_L(2) = 0x10000000 | 0xff; /* replacement addr + perm*/
DEVICE_REG_XMPAX_H(2) = 0x2100000B; /* base addr + seg size (64KB)*/
if (ibl.ddrConfig.configDdr != 0)
}
-
+extern nandCtbl_t nandEmifCtbl;
/**
- * @brief Return the NAND interface (EMIF25 or SPI) used based on the value
+ * @brief Return the NAND interface (GPIO, EMIF25 or SPI) used based on the value
* of interface
*/
+#ifndef EXCLUDE_NAND_GPIO
+nandCtbl_t nandGpioCtbl = {
+
+ nandHwGpioDriverInit,
+ nandHwGpioDriverReadBytes,
+ nandHwGpioDriverReadPage,
+ nandHwGpioDriverClose
+
+};
+#endif
+
#ifndef EXCLUDE_NAND_EMIF
+extern Int32 nandHwEmifDriverInit (int32 cs, void *vdevInfo);
+extern Int32 nandHwEmifDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32 nbytes, Uint8 *data);
+extern Int32 nandHwEmifDriverReadPage (Uint32 block, Uint32 page, Uint8 *data);
+extern Int32 nandHwEmifDriverClose (void);
+
nandCtbl_t nandEmifCtbl = {
- nandHwDriverInit,
- nandHwDriverReadBytes,
- nandHwDriverReadPage,
- nandHwDriverClose
+ nandHwEmifDriverInit,
+ nandHwEmifDriverReadBytes,
+ nandHwEmifDriverReadPage,
+ nandHwEmifDriverClose
};
#endif
nandCtbl_t *deviceGetNandCtbl (int32 interface)
{
+#ifndef EXCLUDE_NAND_GPIO
+
+ if (interface == ibl_PMEM_IF_GPIO)
+ return (&nandGpioCtbl);
+
+#endif
#ifndef EXCLUDE_NAND_SPI
index 58c144d788c99d039b72be0bb5953a1210f963d0..195e77d68b5b1209a32e0d0477280c051ad58854 100644 (file)
return (w);
}
-#define FPGA_BOOT_MODE_REG 0
-#define FPGA_READ_BOOT_MODE_REG_CMD ((FPGA_BOOT_MODE_REG | 0x80) << 8)
+#define L1PEDCMD 0x01846408
+#define L2EDCEN 0x01846030
+#define L2EDCMD 0x01846008
+#define SMEDCC 0x0BC00010
/**
* @brief
- * Re-enter the ROM boot loader if the FPGA boot register
- * indicates it was not I2C or SPI boot, this is necessary
- * to apply the PLL workaround for ROM boot modes
+ * Enable the EDC for the local memory
*/
-void iblReEnterRom ()
+void iblEnableEDC ()
+{
+ /* Enable L1P EDC */
+ *(volatile unsigned int *)(L1PEDCMD) = 0x1; //Set EN(bit0)=1
+
+ /* Enable EDC L2EDCEN, set DL2CEN(bit0),PL2CEN(bit1),DL2SEN(bit2),PL2SEN(bit3),SDMAEN(bit4)=1 */
+ *(volatile unsigned int *)(L2EDCEN) |= 0x1F;
+
+ /* Enalble L2 EDC */
+ *(volatile unsigned int *)(L2EDCMD) = 0x1;
+
+ /* Enalbe MSMC EDC */
+ *(volatile unsigned int *)(SMEDCC) &= 0x7FFFFFFF; //Clear SEN(bit31)=0
+ *(volatile unsigned int *)(SMEDCC) |= 0x40000000; //Set ECM(bit30)=1
+}
+
+#define FPGA_BM_GPI_STATUS_LO_REG 4 /* Boot Mode GPI Status (07-00 Low Byte) Register */
+#define FPGA_BM_GPI_STATUS_HI_REG 5 /* Boot Mode GPI Status (15-08 High Byte) Register */
+#define FPGA_READ_REG_CMD(x) ((x | 0x80) << 8)
+/**
+ * @brief
+ * Enter the ROM boot loader if the FPGA boot register
+ * indicates it was not I2C address 0x51 boot, this is necessary
+ * to apply the PLL workaround for non-I2C boot modes
+ */
+void iblEnterRom ()
{
uint32 reg = DEVICE_REG32_R (DEVICE_REG_DEVSTAT);
- uint32 v;
+ uint32 v, dev_stat, bm_lo, bm_hi;
void (*exit)();
- /* Reset */
+ /* Power up the SPI */
+ devicePowerPeriph (TARGET_PWR_SPI);
+
+ /* Reset SPI */
DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
/* Release Reset */
/* Master mode, enable SPI */
DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR1, 0x01000003);
- /* Send the read register address to FPGA */
- DEVICE_REG32_W(DEVICE_SPI_BASE(0) + 0x38, FPGA_READ_BOOT_MODE_REG_CMD);
-
+ /* Read the BM status lo register */
+ DEVICE_REG32_W(DEVICE_SPI_BASE(0) + 0x38, FPGA_READ_REG_CMD(FPGA_BM_GPI_STATUS_LO_REG));
chipDelay32(10000);
+ v = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIFLG);
+ if ( v & 0x100)
+ {
+ bm_lo = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIBUF) & 0xff;
+ }
+ else
+ {
+ return;
+ }
- /* Check if received the data */
+ /* Read the BM status hi register */
+ DEVICE_REG32_W(DEVICE_SPI_BASE(0) + 0x38, FPGA_READ_REG_CMD(FPGA_BM_GPI_STATUS_HI_REG));
+ chipDelay32(10000);
v = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIFLG);
if ( v & 0x100)
{
- v = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIBUF) & 0xff;
+ bm_hi = DEVICE_REG32_R(DEVICE_SPI_BASE(0) + SPI_REG_SPIBUF) & 0xff;
+ }
+ else
+ {
+ return;
+ }
+
+ /* Reset SPI */
+ DEVICE_REG32_W (DEVICE_SPI_BASE(0) + SPI_REG_SPIGCR0, SPI_REG_VAL_SPIGCR0_RESET);
- /* Add code to check the boot mode in FPGA register, if not I2C, configure the
- devstat with the actual boot mode and re-enter ROM boot loader */
-#if 0
- exit = (void (*)())BOOT_ROM_REENTER_ADDRESS;
- (*exit)();
+ if ( (BOOT_READ_BITFIELD(bm_lo,3,1) != 0x5) ||
+ (BOOT_READ_BITFIELD(bm_hi,3,3) == 0x0) )
+ {
+ /* Not i2c boot or i2c boot with address 0x50 */
+
+ /* Update the DEVSTAT to v1 */
+ dev_stat = DEVICE_REG32_R(DEVICE_REG_DEVSTAT );
+ dev_stat &= ~(0x0000080E);
+ dev_stat |= ((bm_hi << 8) | bm_lo);
+#if 0
+ /* Unlock Boot Config */
+ *((volatile Uint32 *)0x2620038) = 0x83e70b13;
+ *((volatile Uint32 *)0x262003c) = 0x95a4f1e0;
#endif
+
+ /* Update the DEVSTAT register for the intended Boot Device and i2c Addr */
+ DEVICE_REG32_W (DEVICE_REG_DEVSTAT, dev_stat);
+#if 0
+ /* Lock Boot Config */
+ *((volatile Uint32 *)0x2620038) = 0;
+ *((volatile Uint32 *)0x262003c) = 0;
+#endif
+ exit = (void (*)())BOOT_ROM_ENTER_ADDRESS;
+ (*exit)();
}
-
}
-
-
#if (!defined(EXCLUDE_NOR_SPI) || !defined(EXCLUDE_NAND_SPI))
/**
* @brief
index e8093b3656d8f0db439327b760c5b7478f9a23ca..c8f89d9d7eed491ddb98047a81ff8e03e2a275be 100644 (file)
* @brief
* Support for PLL workaround to re-enter ROM boot loader.
*/
-#define IBL_REENTER_ROM 1
+#define IBL_ENTER_ROM 1
+
+/**
+ * @brief
+ * Support for enabling EDC for internal memory.
+ */
+#define IBL_ENABLE_EDC 1
#endif /* _TARGET_H */
index f481ab8b60f6564d5be8a30597a56070d300f2da..038b78db4fb1dc3714a00f20ff49d74d9c601634 100644 (file)
*
* $Log: $
*
- * (C) Copyright 2004 TELOGY Networks, Inc.
+ * (C) Copyright 2004 TELOGY Networks, Inc.
******************************************************************************/
#include "types.h"
enum {
BOOT_NOERR = 0,
BOOT_GEN_ERROR = 1, /* General error */
- BOOT_INVALID_BOOT_MODE = 2,
+ BOOT_INVALID_BOOT_MODE = 2,
BOOT_INVALID_I2C_DEV_ADDR = 3,
BOOT_INVALID_CHECKSUM = 4, /* Invalid checksum of the boot parameters */
BOOT_INVALID_PARAMS_SIZE = 5, /* the size of boot parameters is too big */
BOOT_PERIPH_POWER = 15, /* peripheral failed to powerup */
BOOT_MAIN_FAIL = 16, /* Failed in initial boot setup (wrong core) */
BOOT_SK_REGISTERSCWP = 17, /* Failed at SK_registerSCWP */
- BOOT_SK_ALLOCSC = 18, /* Failed at SK_allocSC */
+ BOOT_SK_ALLOCSC = 18, /* Failed at SK_allocSC */
BOOT_CPSGMII_CONFIGINDEX = 19, /* Failed at wrong CPSGMII config index */
BOOT_SRIO_CONFIGINDEX = 20, /* Failed at wrong SRIO config index */
BOOT_RETURN_FROM_CHAIN = 21, /* Code returned from boot main chaining, should never happen */
/* Error code = (module ID * 100) + module specific error */
#define BOOT_ERROR_CODE(id, code) ((UINT16)((id<<8) + code))
#define BOOT_EXCEPTION(error_code) bootException(error_code)
-#define BOOT_ERROR(error_code) bootError(error_code)
+#define BOOT_ERROR(error_code) bootError(error_code)
/*******************************************************************************
* Begin Boot Parameter definitions
******************************************************************************/
/*******************************************************************************
- * Boot Parameter Common
+ * Boot Parameter Common
******************************************************************************/
typedef struct boot_params_common_s{
UINT16 length; /* size of the entire boot parameters in bytes */
- UINT16 checksum; /* non-zero: 1's complement checksum of the boot
+ UINT16 checksum; /* non-zero: 1's complement checksum of the boot
* parameters
* zero: checksum is not applicable
*/
UINT16 portNum;
UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
-
+
/* swPllCfg
*
* /----------------------------------------------------------------\
* | PLL Ctl | multiplier | pre-divider | post divider |
* \----------------------------------------------------------------/
*/
-
+
#define BOOT_PARAMS_PLL_CFG_CTL_MASK 0xc000
#define BOOT_PARAMS_PLL_CFG_CTL_SHIFT 14
#define BOOT_PARAMS_PLL_CFG_LSW_POSTDIV_MASK 0x00ff
#define BOOT_PARAMS_PLL_CFG_LSW_POSTDIV_SHIFT 0
-
+
} BOOT_PARAMS_COMMON_T;
typedef struct boot_params_ethernet_s{
UINT16 portNum;
UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
-
+
/* Etherent specific portion of the Boot Parameters */
UINT16 options;
/*
* 110 - RMII 10Mbs
* 111 - RMII 100Mbs
*
- * Bit 3: HD:
- * 0 - Full Duplex
- * 1 - Half Duplex
- * Bit 4: SKIP TX
- * 0 - Send the Ethernet Ready Frame
- * 1 - Skip sending the Ethernet Ready Frame
+ * Bit 3: HD:
+ * 0 - Full Duplex
+ * 1 - Half Duplex
+ * Bit 4: SKIP TX
+ * 0 - Send the Ethernet Ready Frame
+ * 1 - Skip sending the Ethernet Ready Frame
* Bits 6:5 - Ethernet Initialization
* 00 - Entire system configured
* 01 - No initialization of peripherals that are already enabled and running
* 10 - Reserved
* 11 - No initialization at all
*
- * Other bits: Reserved
- */
+ * Other bits: Reserved
+ */
#define BOOT_PARAMS_ETH_OPTIONS_MII 0x0000
#define BOOT_PARAMS_ETH_OPTIONS_RMII 0x0001
#define BOOT_PARAMS_ETH_OPTIONS_GMII 0x0002
#define BOOT_PARAMS_ETH_OPTIONS_S3MII 0x0005
#define BOOT_PARAMS_ETH_OPTIONS_RMII_10 0x0006
#define BOOT_PARAMS_ETH_OPTIONS_RMII_100 0x0007
-
+
/* Faraday only supports SGMII */
#define BOOT_PARAMS_ETH_OPTIONS_SGMII 0x0006
-
+
#define BOOT_PARAMS_ETH_OPTIONS_HD 0x0008
#define BOOT_PARAMS_ETH_OPTIONS_SKIP_TX 0x0010
-
+
#define BOOT_PARAMS_ETH_OPTIONS_INIT_MASK 0x0060
#define BOOT_PARAMS_ETH_OPTIONS_INIT_SHIFT 5
#define BOOT_PARAMS_ETH_OPTIONS_INIT(x) (((x) & BOOT_PARAMS_ETH_OPTIONS_INIT_MASK) >> BOOT_PARAMS_ETH_OPTIONS_INIT_SHIFT)
-
+
#define BOOT_PARAMS_ETH_OPTIONS_INIT_FULL 0
#define BOOT_PARAMS_ETH_OPTIONS_INIT_PARTIAL 1
#define BOOT_PARAMS_ETH_OPTIONS_INIT_NONE 3
-
- /*
+
+ /*
* he device MAC address to be used for Boot:
* All zero mac address indicates that the device E-fuse address should
* be used.
- */
+ */
UINT16 mac_addr_h;
UINT16 mac_addr_m;
UINT16 mac_addr_l;
-
- /*
+
+ /*
* The multicast or broadcast MAC address which should be accepted as
* a destination MAC address for boot table frames
*/
UINT16 mmac_addr_h;
UINT16 mmac_addr_m;
UINT16 mmac_addr_l;
-
+
UINT16 src_port; /* Source UDP port number to be used during boot process */
/* 0: allow any SRC UDP port */
UINT16 dest_port; /* Destination UDP port number to be used during boot process */
-
+
/* The Device ID to be included in the boot ready announcement frame */
- UINT16 device_id_12;
- UINT16 device_id_34;
+ UINT16 device_id_12;
+ UINT16 device_id_34;
#define BOOT_PARAMS_DEVICE_ID_HIGH_MASK 0xFF00
#define BOOT_PARAMS_DEVICE_ID_HIGH_SHIFT 8
#define BOOT_PARAMS_DEVICE_ID_LOW_MASK 0x00FF
(((device_id) & BOOT_PARAMS_DEVICE_ID_HIGH_MASK) > BOOT_PARAMS_DEVICE_ID_HIGH_SHIFT)
#define BOOT_PARAMS_GET_DEVICE_ID_24(device_id) \
(((device_id) & BOOT_PARAMS_DEVICE_ID_LOW_MASK) > BOOT_PARAMS_DEVICE_ID_LOW_SHIFT)
-
- /*
+
+ /*
* The destination MAC address used for the boot ready announce frame
*/
UINT16 hmac_addr_h;
#define BOOT_PARAMS_SGMII_CONFIG_DIRECT_CONFIG (1<<4) /* set to use direct configurations */
#define BOOT_PARAMS_SGMII_CONFIG_NO_CONFIG (1<<5) /* set to bypass CPSGMII config */
- UINT16 sgmiiControl;
+ UINT16 sgmiiControl;
#define BOOT_PARAMS_SGMII_CONTROL_MASK 0x7F
UINT16 sgmiiMr_Adv_Ability;
UINT16 sgmiiRx_Cfg_l;
UINT16 sgmiiAux_Cfg_h;
UINT16 sgmiiAux_Cfg_l;
-
+
UINT16 pktPllCfg_msw; /* Packet subsystem PLL configuration */
UINT16 pktPllCfg_lsw;
-
+
} BOOT_PARAMS_ETHERNET_T;
/**************************************************************************************
UINT16 portNum;
UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
-
+
/* Utopia specific portion of the Boot Parameters */
- /* Options
+ /* Options
* ---------------------------------------------------------------
* | 15 3 | 2 | 1 | 0 |
* ----------------------------------------------------------------
* 1 = skip port init
*/
UINT16 options;
-
+
#define BOOT_PARAMS_UTOPIA_SINGLE_PHY (1<<0)
#define BOOT_PARAMS_UTOPIA_16BIT (1<<1)
#define BOOT_PARAMS_UTOPIA_SKIP_INIT (1<<2)
-
+
UINT16 cellSizeBytes; /* Cell Size */
UINT16 busWidthBits; /* Bus width (8 or 16) */
UINT16 slid; /* Slave ID */
UINT16 coreFreqMhz; /* CPU frequency after pll mult */
-
-
+
+
} BOOT_PARAMS_UTOPIA_T;
typedef struct boot_params_i2c_s{
UINT16 portNum;
UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
-
+
/* I2C specific portion of the Boot Parameters */
UINT16 options;
/*
* I2C Specific Options
- * Bit 01-00: BT:
- * 00 - Boot Parameter Mode
- * 01 - Boot Table Mode
+ * Bit 01-00: BT:
+ * 00 - Boot Parameter Mode
+ * 01 - Boot Table Mode
* 10 - Boot Config mode
* 11 - Slave receive boot config
- * Bit 04-02: EETYPE: EEPROM type
- * Other bits: Reserved
- */
+ * Bit 04-02: EETYPE: EEPROM type
+ * Other bits: Reserved
+ */
#define BOOT_PARAMS_I2C_OPTIONS_BP 0x0000
#define BOOT_PARAMS_I2C_OPTIONS_BT 0x0001
#define BOOT_PARAMS_I2C_OPTIONS_BC 0x0002
#define BOOT_PARAMS_I2C_OPTIONS_SLVOPT 0x0003
-
+
#define BOOT_PARAMS_I2C_OPTIONS_MASK 0x0003
#define BOOT_PARAMS_I2C_OPTIONS_SHIFT 0
-
+
#define BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK 0x001C
- #define BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT 2
-
+ #define BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT 2
+
#define BOOT_PARAMS_I2C_IS_BOOTTBL_MODE(options) \
(((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_BT)
-
+
#define BOOT_PARAMS_I2C_IS_BOOTCONFIG_MODE(options) \
(((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_BC)
-
+
#define BOOT_PARAMS_I2C_IS_SLAVE_RCV_OPTIONS_MODE(options) \
(((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_SLVOPT)
-
+
#define BOOT_PARAMS_I2C_IS_BOOTPARAM_MODE(options) \
(((options) & BOOT_PARAMS_I2C_OPTIONS_MASK) == BOOT_PARAMS_I2C_OPTIONS_BP)
-
+
#define BOOT_PARAMS_I2C_SET_BOOTTBL_MODE(options, mode) \
(options) = ((options) & ~BOOT_PARAMS_I2C_OPTIONS_MASK) | \
(((mode) & BOOT_PARAMS_I2C_OPTIONS_MASK) << \
BOOT_PARAMS_I2C_OPTIONS_SHIFT)
-
-
+
+
#define BOOT_PARAMS_I2C_GET_EETYPE(options) \
(((options) & BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK) >> BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT)
#define BOOT_PARAMS_I2C_SET_EETYPE(options, ee_type) \
(options) = (((options) & ~BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK) | \
- (((ee_type) << BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT) & BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK))
-
+ (((ee_type) << BOOT_PARAMS_I2C_OPTIONS_EETYPE_SHIFT) & BOOT_PARAMS_I2C_OPTIONS_EETYPE_MASK))
+
/* The device address to be used for Boot */
UINT16 dev_addr; /* 16-bit device address (low) */
- UINT16 dev_addr_ext; /* 16-bit extended device address (high)
+ UINT16 dev_addr_ext; /* 16-bit extended device address (high)
* set to zero if not used
- * Note: some I2C device requires 32-bit
+ * Note: some I2C device requires 32-bit
* address
- */
+ */
UINT16 multi_i2c_id; /* Multi device master write boot ID */
UINT16 my_i2c_id; /* This parts I2C address */
-
+
UINT16 core_freq_mhz; /* Core frequency, MHz */
UINT16 i2c_clk_freq_khz; /* Desired I2C clock frequency, kHz */
-
+
UINT16 next_dev_addr; /* Used only for the boot config mode. */
UINT16 next_dev_addr_ext; /* Copied into dev_addr* after config complete */
-
+
UINT16 address_delay; /* Rough number of cycles delay between address write
* and read to the i2c eeprom */
-
-
-} BOOT_PARAMS_I2C_T;
+
+
+} BOOT_PARAMS_I2C_T;
typedef struct boot_params_rapidio_s{
UINT16 portNum;
UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
-
+
/* Options */
UINT16 options;
-
+
#define BOOT_PARAMS_RIO_OPTIONS_TX_ENABLE (1<<0) /* set to enable transmit */
#define BOOT_PARAMS_RIO_OPTIONS_BOOT_TABLE (1<<1) /* set to use boot tables */
#define BOOT_PARAMS_RIO_OPTIONS_NO_CONFIG (1<<2) /* set to bypass port config */
#define BOOT_PARAMS_RIO_OPTIONS_NO_QM_CONFIG (1<<3) /* set to bypass QM config */
-
+
UINT16 lane_port_setup; /* Lane port configuration */
#define BOOT_PARAMS_RIO_LPS_1X_1X_1X_1X 0 /* 4 ports 1 lane each */
#define BOOT_PARAMS_RIO_LPS_2X_1X_1X 1 /* 3 ports, lanes 0,1 are a 2 lane port */
#define BOOT_PARAMS_RIO_LPS_1X_1X_2X 2 /* 3 ports, lanes 2,3 are a 2 lane port */
#define BOOT_PARAMS_RIO_LPS_2X_2X 3 /* 2 ports, each 2 lanes */
#define BOOT_PARAMS_RIO_LPS_4X 4 /* 1 port of 4 lanes */
-
+
UINT16 cfg_index; /* The table of base configuration parameters */
-
-
-
+
+
+
UINT16 node_id; /* The node id for this device */
UINT16 serdes_ref_clk; /* The serdes reference clock freq, in hundredths
* of MHz (1 MHz would be 100) */
UINT16 link_rate; /* Data link rate (mega bits per second */
UINT16 pf_low; /* Packet forward range, low */
UINT16 pf_high; /* Packet forward range, high */
-
+
} BOOT_PARAMS_RIO_T;
UINT16 portNum;
UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
-
+
UINT16 options;
-
+
#define BOOT_PARAMS_PCIE_OPTIONS_COMPUTE_PLL_MASK (1 << 4)
#define BOOT_PARAMS_PCIE_OPTIONS_COMPUTE_PLL (1 << 4)
#define BOOT_PARAMS_PCIE_OPTIONS_NO_COMPUTE_PLL (0 << 4)
UINT16 window1Size; /* Window 1 size */
UINT16 window2Size; /* Window 2 size. Valid only if the address width is 32 */
UINT16 window3Size; /* Window 3 size. Valid only if the address width is 32 */
-
+
UINT16 vendorId; /* Vendor ID field */
UINT16 deviceId; /* Device ID field */
UINT16 classCodeRevId_Msw; /* Class code rev ID, MSW */
UINT16 classCodeRevId_Lsw; /* Class code rev ID, LSW*/
-
-
-
+
+
+
UINT16 serdesCfgMsw; /* Serdes auxillary config, MSW */
UINT16 serdesCfgLsw; /* Serdes auxillary config, LSW */
-
+
UINT16 serdesCfgLane0Msw; /* Serdes Lane 0 config, MSW */
UINT16 serdesCfgLane0Lsw; /* Serdes Lane 0 config, LSW */
-
+
UINT16 serdesCfgLane1Msw; /* Serdes Lane 1 config, MSW */
UINT16 serdesCfgLane1Lsw; /* Serdes Lane 1 config, LSW */
-
-
+
+
} BOOT_PARAMS_PCIE_T;
-
-
+
+
typedef struct boot_params_emif_nor_s {
UINT16 waitEnable;
} boot_params_emif_nor_t;
-
-
+
+
typedef struct boot_params_emif_s
{
/* common portion of the Boot parameters */
UINT16 portNum;
UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
-
+
UINT16 options;
-
+
UINT16 type;
#define BOOT_PARAMS_EMIF_TYPE_NOR 0
UINT16 branchAddrMsw;
UINT16 branchAddrLsw;
-
+
UINT16 csNum;
UINT16 memWidth;
-
+
union {
boot_params_emif_nor_t nor;
} u;
-
+
} BOOT_PARAMS_EMIF_T;
-
-
+
+
typedef struct boot_params_vusr_s
{
/* common portion of the Boot parameters */
UINT16 portNum;
UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
-
+
UINT16 options;
#define BOOT_PARAMS_VUSR_OPTIONS_NO_INIT_MASK (1 << 1)
#define BOOT_PARAMS_VUSR_OPTIONS_NO_INIT (1 << 1)
#define BOOT_PARAMS_VUSR_OPTIONS_BOOT_TABLE_MASK (1 << 0)
#define BOOT_PARAMS_VUSR_OPTIONS_BOOT_TABLE (1 << 0)
#define BOOT_PARAMS_VUSR_OPTIONS_HOST_BOOT (0 << 0)
-
+
UINT16 nLanes; /* The number of lanes to configure */
-
+
UINT16 serdesCfgMsw; /* Serdes auxillary config, MSW */
UINT16 serdesCfgLsw; /* Serdes auxillary config, LSW */
-
+
UINT16 serdesCfgRxLane0Msw; /* Serdes Rx Lane 0 config, MSW */
UINT16 serdesCfgRxLane0Lsw; /* Serdes Rx Lane 0 config, LSW */
-
+
UINT16 serdesCfgTxLane0Msw; /* Serdes Tx Lane 0 config, MSW */
UINT16 serdesCfgTxLane0Lsw; /* Serdes Tx Lane 0 config, LSW */
-
-
-
+
+
+
UINT16 serdesCfgRxLane1Msw; /* Serdes Rx Lane 1 config, MSW */
UINT16 serdesCfgRxLane1Lsw; /* Serdes Rx Lane 1 config, LSW */
-
+
UINT16 serdesCfgTxLane1Msw; /* Serdes Tx Lane 1 config, MSW */
UINT16 serdesCfgTxLane1Lsw; /* Serdes Tx Lane 1 config, LSW */
-
-
+
+
UINT16 serdesCfgRxLane2Msw; /* Serdes Rx Lane 2 config, MSW */
UINT16 serdesCfgRxLane2Lsw; /* Serdes Rx Lane 2 config, LSW */
-
+
UINT16 serdesCfgTxLane2Msw; /* Serdes Tx Lane 2 config, MSW */
UINT16 serdesCfgTxLane2Lsw; /* Serdes Tx Lane 2 config, LSW */
-
-
+
+
UINT16 serdesCfgRxLane3Msw; /* Serdes Rx Lane 3 config, MSW */
UINT16 serdesCfgRxLane3Lsw; /* Serdes Rx Lane 3 config, LSW */
-
+
UINT16 serdesCfgTxLane3Msw; /* Serdes Tx Lane 3 config, MSW */
UINT16 serdesCfgTxLane3Lsw; /* Serdes Tx Lane 3 config, LSW */
-
-} BOOT_PARAMS_VUSR_T;
+
+} BOOT_PARAMS_VUSR_T;
typedef struct boot_params_spi_s
{
UINT16 portNum;
UINT16 swPllCfg_msw; /* CPU PLL configuration, MSW */
UINT16 swPllCfg_lsw; /* CPU PLL configuration, LSW */
-
+
UINT16 options;
/*
* SPI Specific Options
- * Bit 01-00: BT:
- * 00 - Boot Parameter Mode
- * 01 - Boot Table Mode
+ * Bit 01-00: BT:
+ * 00 - Boot Parameter Mode
+ * 01 - Boot Table Mode
* 10 - Boot Config mode
* 11 - Reserved, but if seen will act as boot parameter table
- * Other bits: Reserved
- */
+ * Other bits: Reserved
+ */
#define BOOT_PARAMS_SPI_OPTIONS_BP 0x0000
#define BOOT_PARAMS_SPI_OPTIONS_BT 0x0001
#define BOOT_PARAMS_SPI_OPTIONS_BC 0x0002
-
+
#define BOOT_PARAMS_SPI_OPTIONS_MASK 0x0003
#define BOOT_PARAMS_SPI_OPTIONS_SHIFT 0
-
+
#define BOOT_PARAMS_SPI_IS_BOOTTBL_MODE(options) \
(((options) & BOOT_PARAMS_SPI_OPTIONS_MASK) == BOOT_PARAMS_SPI_OPTIONS_BT)
-
+
#define BOOT_PARAMS_SPI_IS_BOOTCONFIG_MODE(options) \
(((options) & BOOT_PARAMS_SPI_OPTIONS_MASK) == BOOT_PARAMS_SPI_OPTIONS_BC)
-
+
#define BOOT_PARAMS_SPI_IS_BOOTPARAM_MODE(options) \
(((options) & BOOT_PARAMS_SPI_OPTIONS_MASK) == BOOT_PARAMS_SPI_OPTIONS_BP)
-
-
+
+
#define BOOT_PARAMS_SPI_SET_BOOTTBL_MODE(options, mode) \
(options) = ((options) & ~BOOT_PARAMS_SPI_OPTIONS_MASK) | \
(((mode) & BOOT_PARAMS_SPI_OPTIONS_MASK) << \
BOOT_PARAMS_SPI_OPTIONS_SHIFT)
-
-
+
+
UINT16 addrWidth; /* 16 or 24 are the only valid values */
UINT16 nPins; /* 4 or 5 pins are the only valid values */
UINT16 csel; /* only values 0b10 (cs0 low) or 0b01 (cs1 low) are valid */
UINT16 mode; /* Clock phase/polarity. These are the standard SPI modes 0-3 */
UINT16 c2tdelay; /* Setup time between chip select assert and the transaction */
-
+
UINT16 cpuFreqMhz; /* Speed the CPU is running after PLL configuration */
UINT16 busFreqMhz; /* The speed of the SPI bus, the megahertz portion */
UINT16 busFreqKhz; /* The KHz portion of the bus frequency. A frequency of 1.5 MHz would have the value 5 here */
-
+
UINT16 read_addr_msw; /* The base address to read from the SPI, upper 16 bits */
UINT16 read_addr_lsw; /* The base address to read from the SPI, lower 16 bits */
-
+
UINT16 next_csel; /* The next chip select to use if in boot config mode, when the config is complete */
UINT16 next_read_addr_msw; /* The next read address to use if in boot config mode */
UINT16 next_read_addr_lsw; /* The next read address to use if in boot config mode */
-
-} BOOT_PARAMS_SPI_T;
+
+} BOOT_PARAMS_SPI_T;
/*
* Note: We need to make sure that the structures genertaed by the C-compiler
* match with the boot parameter table data format i.e. a set of 16-bit
* data array.
- */
+ */
#define BOOT_PARAMS_SIZE_IN_BYTES 128
typedef union {
- BOOT_PARAMS_COMMON_T common;
+ BOOT_PARAMS_COMMON_T common;
BOOT_PARAMS_ETHERNET_T eth;
BOOT_PARAMS_I2C_T i2c;
BOOT_PARAMS_UTOPIA_T utopia;
BOOT_PARAMS_EMIF_T emif;
BOOT_PARAMS_VUSR_T vusr;
BOOT_PARAMS_SPI_T spi;
- UINT16 parameter[BOOT_PARAMS_SIZE_IN_BYTES/2];
+ UINT16 parameter[BOOT_PARAMS_SIZE_IN_BYTES/2];
} BOOT_PARAMS_T;
/*******************************************************************************
- * Definition: The time stamp and version number are placed into the stats.
+ * Definition: The time stamp and version number are placed into the stats.
* This will be two characters packed per 16bits . The length
* value must be 32 bit divisible
*******************************************************************************/
-#define BOOT_VERSION_LEN_UINT16 32
+#define BOOT_VERSION_LEN_UINT16 32
typedef struct BOOT_VERSION_S {
UINT16 vstring[BOOT_VERSION_LEN_UINT16];
-
+
} BOOT_VERSION_T;
extern BOOT_VERSION_T bootVersion;
-
+
/*******************************************************************************
* Definition: Runs time stats that are not initialized on cold boot entry
#define BOOT_STAGE_DISABLE_CACHE 10
#define BOOT_STAGE_CHCHE_DISABLED 11
#define BOOT_STAGE_EXIT 12
- #define BOOT_STAGE_ERROR_LOOP 13
+ #define BOOT_STAGE_ERROR_LOOP 13
#define BOOT_STAGE_I2C_BOOTCONFIG_LOOP 14
#define BOOT_STAGE_I2C_SLV_RCV_OPTIONS_LOOP 15
#define BOOT_STAGE_UTOPIA_MAIN_LOOP 16
UINT16 coldBootEntries;
-
+
} BOOT_STATS_NONINIT_T;
/*******************************************************************************
- * Definition: Run time statistics and error counts. These stats are
+ * Definition: Run time statistics and error counts. These stats are
* initialized on cold boot entry.
******************************************************************************/
-
+
typedef struct BOOT_STATS_COMMON_S {
UINT32 bootStatus;
UINT16 nColdBootEntries;
UINT16 nPllWarns;
UINT16 nResetWarns;
} BOOT_STATS_COMMON_T;
-
-
+
+
typedef struct BOOT_STATS_MAIN_S {
UINT16 errorCode; /* (module ID <<8 ) + module specific error */
-
+
/* I2C operation related statistics */
UINT16 numI2Cpkts; /* number of I2C boot table packets processed */
UINT16 numI2CchksumError;/* number of I2C checksum errors */
UINT16 numI2Cretrys; /* number of I2C retrys due to read access errors */
UINT16 numI2cWrites; /* number of I2C master writes to passive devices */
UINT16 numI2cWriteError; /* number of I2C master write errors */
-
+
UINT16 warmBootEntry; /* Count of entries into warm boot routine */
} BOOT_STATS_MAIN_T;
/*****************************************************************************
- * Definition: I2C stats, Boot table and Ethernrt stats initialized
+ * Definition: I2C stats, Boot table and Ethernrt stats initialized
* on cold boot entry
*****************************************************************************/
typedef struct I2C_STATS_tag
typedef struct ETH_STATS_tag
{
/* MAC packets related statistics */
- UINT16 uniMacPkts; /* Count of packets received with valid unicast mac
+ UINT16 uniMacPkts; /* Count of packets received with valid unicast mac
address */
UINT16 multiMacPkts; /* Count of packets received with valid multicast or
broadcast mac address */
- UINT16 invalidMacPkts; /* Count of packets received with invalid mac
+ UINT16 invalidMacPkts; /* Count of packets received with invalid mac
address */
UINT16 invalidLLCPkts; /* Count of 802.3 packets with wrong LLC/SNAP header */
- UINT16 nonIpPkts; /* Count of non-IP packets received with valid
+ UINT16 nonIpPkts; /* Count of non-IP packets received with valid
MAC address */
-
- /* IP packets related statistics */
+
+ /* IP packets related statistics */
UINT16 nEra; /* Number of ERA packets transmitted */
UINT16 nonIP4Pkts; /* Count of non-IP4 packets */
UINT16 ipfragments; /* Count of IP fragments received */
UINT16 ipTruncatedError; /* Count of truncated IP frame */
UINT16 nonUDPPkts; /* Count of IP packets with non-UDP paylaod */
-
+
/* UDP packets related statistics */
UINT16 udpSizeError; /* Count of UDP packet with invalid (odd) size */
UINT16 udpPortError; /* Count of UDP packets with invalid port number */
UINT16 udpChksumError; /* Count of UDP packets with checksum error */
-
+
/* Boot table packets related statistics */
UINT16 nonBtblPkts; /* Count of UDP packets with invalid boot table paylaod */
- UINT16 outSeqPkts; /* Count of out of sequence boot table packets received
+ UINT16 outSeqPkts; /* Count of out of sequence boot table packets received
i.e. packets with unexpected seq_num */
UINT16 expSeqNum; /* Expected Sequence Number */
- UINT16 lastSeqNum; /* Last sequence number received */
+ UINT16 lastSeqNum; /* Last sequence number received */
/* Driver errors */
UINT16 sizeZeroPackets; /* Count of packets arriving with 0 size */
typedef struct bootEmif4Tbl_s {
UINT32 configSelect; /* Bit map defining which registers to set */
-
+
UINT32 pllPrediv; /* Values of all 0s will disable the pll */
UINT32 pllMult;
UINT32 pllPostDiv;
UINT32 eccRange1;
UINT32 eccRange2;
UINT32 rdWrtExcThresh;
-
+
} BOOT_EMIF4_TBL_T;
-#define BOOT_EMIF4_ENABLE_pllCtl (1 << 0)
+#define BOOT_EMIF4_ENABLE_pllCtl (1 << 0)
#define BOOT_EMIF4_ENABLE_sdRamConfig (1 << 2)
#define BOOT_EMIF4_ENABLE_sdRamConfig2 (1 << 3)
#define BOOT_EMIF4_ENABLE_rdWrtExcThresh (1 << 25)
#define BOOT_EMIF4_ENABLE_ALL 0x00ffffff
-
-
-
-
-/* Hibernation function control */
+
+
+
+
+/* Hibernation function control */
#define TIBOOT_CTL_HIBERNATION_MODE1 1
#define TIBOOT_CTL_HIBERNATION_MODE2 2
#define BOOT_MODE_I2C 40
#define BOOT_MODE_SPI 50
-/* ROM boot loader re-enter address */
-#define BOOT_ROM_REENTER_ADDRESS 0x20b00008
+/* ROM boot loader enter address */
+#define BOOT_ROM_ENTER_ADDRESS 0x20b00000
#endif /* __TIBOOT_H__ */
diff --git a/src/driver/nand/nand.c b/src/driver/nand/nand.c
index f63f55650e08aa70cfe646a42d1c601750232558..a35ac042472a6fa5a4b9f42231905ee69591c787 100644 (file)
--- a/src/driver/nand/nand.c
+++ b/src/driver/nand/nand.c
#include <string.h>
#include <stdlib.h>
+extern void *iblMalloc (Uint32 size);
+extern void iblFree (void *mem);
/**
* @brief The nand master control block which tracks the current nand boot information
Int32 size;
Int32 ret;
Int32 i, j;
+ Bool badBlock;
/* Initialize the control info */
iblMemset (&nandmcb, 0, sizeof(nandmcb));
ret = (*nandmcb.nand_if->nct_driverInit)(ibln->interface, (void *)&nandmcb.devInfo);
if (ret < 0)
+ {
nand_free_return (ret);
-
- } else {
-
+ return (-1);
+ }
+ }
+ else
+ {
return (-1);
-
}
/* allocate memory for the page data and the logical to physical block map */
size = nandmcb.devInfo.pageSizeBytes + nandmcb.devInfo.pageEccBytes;
nandmcb.page = iblMalloc (size * sizeof(Uint8));
if (nandmcb.page == NULL)
+ {
nand_free_return (NAND_MALLOC_PAGE_FAIL);
+ return (-1);
+ }
/* Logical to physical map data */
nandmcb.logicalToPhysMap = iblMalloc (nandmcb.devInfo.totalBlocks * sizeof(Uint16));
if (nandmcb.logicalToPhysMap == NULL)
+ {
nand_free_return (NAND_MALLOC_MAP_LTOP_FAIL);
+ return (-1);
+ }
/* Physical to logical map data */
nandmcb.physToLogicalMap = iblMalloc (nandmcb.devInfo.totalBlocks * sizeof(Uint16));
if (nandmcb.physToLogicalMap == NULL)
+ {
nand_free_return (NAND_MALLOC_MAP_PTOL_FAIL);
+ return (-1);
+ }
/* Block info */
size = nandmcb.devInfo.totalBlocks * sizeof(Uint8);
nandmcb.blocks = iblMalloc (size);
if (nandmcb.blocks == NULL)
+ {
nand_free_return (NAND_MALLOC_BLOCK_INFO_FAIL);
+ return (-1);
+ }
/* Bad blocks are identified by reading page 0 and page 1. If the first
nandmcb.numBadBlocks = 0;
for (i = 0; i < nandmcb.devInfo.totalBlocks; i++) {
- ret = (*nandmcb.nand_if->nct_driverReadBytes)(i, 0, nandmcb.devInfo.pageSizeBytes, 1, &nandmcb.page[0]);
- if (ret < 0)
- nand_free_return (ret);
-
- ret = (*nandmcb.nand_if->nct_driverReadBytes)(i, 1, nandmcb.devInfo.pageSizeBytes, 1, &nandmcb.page[1]);
- if (ret < 0)
- nand_free_return (ret);
+ badBlock = FALSE;
+ for (j = 0; j < ibl_N_BAD_BLOCK_PAGE; j++)
+ {
+ if (nandmcb.devInfo.badBlkMarkIdx[j] < nandmcb.devInfo.pageEccBytes)
+ {
+ ret = (*nandmcb.nand_if->nct_driverReadBytes)(i,
+ j,
+ 0, //nandmcb.devInfo.pageSizeBytes,
+ nandmcb.devInfo.pageSizeBytes+nandmcb.devInfo.pageEccBytes,//nandmcb.devInfo.pageEccBytes,
+ nandmcb.page);
+ if (ret < 0)
+ {
+ nand_free_return (ret);
+ return (-1);
+ }
+
+ //if (nandmcb.page[nandmcb.devInfo.badBlkMarkIdx[j]] != 0xff)
+ if (nandmcb.page[nandmcb.devInfo.pageSizeBytes+nandmcb.devInfo.badBlkMarkIdx[j]] != 0xff)
+ {
+ badBlock = TRUE;
+ break;
+ }
+ }
+ }
- if ((nandmcb.page[0] != 0xff) || (nandmcb.page[1] != 0xff)) {
+ if (badBlock) {
nandmcb.blocks[i] = 0xff;
nandmcb.numBadBlocks += 1;
} else
index fb362d3c3e3e2d627a845b53b5754a1339ebad7e..e1b6da0a43ab098ef5c027118b2bc00f76b508ae 100644 (file)
*/
Int32 stream_read_peek (Uint8* ptr_data, Int32 num_bytes, Int32 op)
{
- Int32 index;
+ Int32 index, read_index;
Int32 num_bytes_to_read;
/* Determine the number of bytes which can be read. */
{
/* Copy the data to the "write" index. */
if (ptr_data != NULL)
- *(ptr_data + index) = *(stream_mcb.buffer + stream_mcb.read_idx + index);
-
+ {
+ read_index = stream_mcb.read_idx + index;
+ read_index = read_index % MAX_SIZE_STREAM_BUFFER;
+ *(ptr_data + index) = *(stream_mcb.buffer + read_index);
+ }
}
/* Increment the read index.
index 7f2415a72e12292b3449a12c0d820dcc10bc70ce..a170814e53e0cb1436160a19d618b3e8a1572fba 100644 (file)
#include "emif4_loc.h"
#include "device.h"
+#define CHIP_LEVEL_REG 0x02620000
+
+#define KICK0 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0038)
+#define KICK1 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x003C)
+
+#define DDR3PLLCTL0 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330)
+
+// DDR3 definitions
+#define DDR_BASE_ADDR 0x21000000
+
+#define DDR_MIDR (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000000))
+#define DDR_SDCFG (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000008))
+#define DDR_SDRFC (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000010))
+#define DDR_SDTIM1 (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000018))
+#define DDR_SDTIM2 (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000020))
+#define DDR_SDTIM3 (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000028))
+#define DDR_PMCTL (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x00000038))
+#define DDR_RDWR_LVL_RMP_CTRL (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000D8))
+#define DDR_RDWR_LVL_CTRL (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000DC))
+#define DDR_DDRPHYC (*(volatile unsigned int*)(DDR_BASE_ADDR + 0x000000E4))
+
+#define DATA0_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262043C))
+#define DATA1_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620440))
+#define DATA2_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620444))
+#define DATA3_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620448))
+#define DATA4_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262044C))
+#define DATA5_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620450))
+#define DATA6_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620454))
+#define DATA7_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x02620458))
+#define DATA8_GTLVL_INIT_RATIO (*(volatile unsigned int*)(0x0262045C))
+
+#define RDWR_INIT_RATIO_0 (*(volatile unsigned int*)(0x0262040C))
+#define RDWR_INIT_RATIO_1 (*(volatile unsigned int*)(0x02620410))
+#define RDWR_INIT_RATIO_2 (*(volatile unsigned int*)(0x02620414))
+#define RDWR_INIT_RATIO_3 (*(volatile unsigned int*)(0x02620418))
+#define RDWR_INIT_RATIO_4 (*(volatile unsigned int*)(0x0262041C))
+#define RDWR_INIT_RATIO_5 (*(volatile unsigned int*)(0x02620420))
+#define RDWR_INIT_RATIO_6 (*(volatile unsigned int*)(0x02620424))
+#define RDWR_INIT_RATIO_7 (*(volatile unsigned int*)(0x02620428))
+#define RDWR_INIT_RATIO_8 (*(volatile unsigned int*)(0x0262042C))
+
+#define DDR3_CONFIG_REG_0 (*(volatile unsigned int*)(0x02620404))
+#define DDR3_CONFIG_REG_12 (*(volatile unsigned int*)(0x02620434))
+#define DDR3_CONFIG_REG_13 (*(volatile unsigned int*)(0x02620460))
+#define DDR3_CONFIG_REG_23 (*(volatile unsigned int*)(0x02620460))
+#define DDR3_CONFIG_REG_24 (*(volatile unsigned int*)(0x02620464))
+
/*************************************************************************************************
* FUNCTION PUROPSE: Initial EMIF4 setup
*************************************************************************************************
{
UINT32 v;
+#if 0
/* If the config registers or refresh control registers are being written
* disable the initialization sequence until they are all setup */
if ((cfg->registerMask & EMIF4_INIT_SEQ_MASK) != 0) {
v = cfg->sdRamRefreshCtl;
EMIF_REG_VAL_SDRAM_REF_CTL_SET_INITREF_DIS(v,0);
DEVICE_REG32_W (DEVICE_EMIF4_BASE + EMIF_REG_SDRAM_REF_CTL, v);
+#endif
+ KICK0 = 0x83E70B13;
+ KICK1 = 0x95A4F1E0;
+
+ DDR3PLLCTL0 = 0x100807C1;
+
+ DDR_SDTIM1 = 0x0CCF369B;
+ DDR_SDTIM2 = 0x3A3F7FDA;
+ DDR_SDTIM3 = 0x057F83A8;
+ DDR_PMCTL |= (0x9 << 4); // Set up SR_TIM to Enter self-refresh after 4096 clocks
+
+ DDR_DDRPHYC = 0x0010010B;
+
+ DDR_SDRFC = 0x00004111; //500us
+
+
+ DDR_SDCFG = 0x63C51A32; //0x63C51A32; //row-col = 13-10
+
+
+ //Values with invertclkout = 0
+ DATA0_GTLVL_INIT_RATIO = 0x3C;
+ DATA1_GTLVL_INIT_RATIO = 0x3C;
+ DATA2_GTLVL_INIT_RATIO = 0x23;
+ DATA3_GTLVL_INIT_RATIO = 0x2D;
+ DATA4_GTLVL_INIT_RATIO = 0x13;
+ DATA5_GTLVL_INIT_RATIO = 0x11;
+ DATA6_GTLVL_INIT_RATIO = 0x9;
+ DATA7_GTLVL_INIT_RATIO = 0xC;
+ //DATA8_GTLVL_INIT_RATIO = 0x21; //ECC byte lane. Don't care as long as you don't enable ECC by software
+
+ //Values with invertclkout = 0
+ RDWR_INIT_RATIO_0 = 0x0;
+ RDWR_INIT_RATIO_1 = 0x0;
+ RDWR_INIT_RATIO_2 = 0x0;
+ RDWR_INIT_RATIO_3 = 0x0;
+ RDWR_INIT_RATIO_4 = 0x0;
+ RDWR_INIT_RATIO_5 = 0x0;
+ RDWR_INIT_RATIO_6 = 0x0;
+ RDWR_INIT_RATIO_7 = 0x0;
+ //RDWR_INIT_RATIO_8 = 0x0; //ECC byte lane. Don't care as long as you don't enable ECC by software
+
+
+
+ //GEL_TextOut("\nProgrammed initial ratios.\n");
+
+ DDR3_CONFIG_REG_0 = DDR3_CONFIG_REG_0 | 0xF;
+
+ //DDR3_CONFIG_REG_23 = RD_DQS_SLAVE_RATIO_1066 | (WR_DQS_SLAVE_RATIO_1066 << 10) | (WR_DATA_SLAVE_RATIO_1066 << 20);
+
+ DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
+ //GEL_TextOut("\nSet bit 9 = 1 for forced ratio read eye leveling.\n");
+
+ DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling
+ DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value //(0x34) instead
+ //GEL_TextOut("\n Triggered full leveling.\n");
+
+ DDR_SDTIM1; //Read MMR to ensure full leveling is complete
+
+ DDR_SDRFC = 0x00001040; //Refresh rate = Round[7.8*666.5MHz] = 0x1450
+
return (0);
diff --git a/src/hw/emif25/emif25.c b/src/hw/emif25/emif25.c
index 48fd45cbeff08e77479749f12adf91f709437abd..754136cddd2d5d39d88309af6fb895380a590db2 100644 (file)
--- a/src/hw/emif25/emif25.c
+++ b/src/hw/emif25/emif25.c
v = 0;
else if (busWidth == 16)
v = 1;
- else if (busWidth -= 32)
+ else if (busWidth == 32)
v = 2;
else
return (EMIF25_INVALID_BUS_WIDTH);
index 55591a4f1ce5b031c3e6d351832bf25ff423b8cb..2640b421ae312d73a8b3413e377007732f4a5d0c 100644 (file)
#define _EMIF25_LOC_H
/* Register offsets */
-#define EMIF25_ASYNC_CFG_REG(x) (0x10 + (((x)-2)*4))
+#define EMIF25_ASYNC_CFG_REG(x) (0x10 + (x)*4)
#define EMIF25_FLASH_CTL_REG 0x60
-#define EMIF25_FLASH_ECC_REG(x) (0xc0 + (((x)-2)*4))
+#define EMIF25_FLASH_ECC_REG(x) (0xc0 + (x)*4)
/* Setting the bus width in the async config register */
#define EMIF25_SET_ASYNC_WID(x,v) BOOT_SET_BITFIELD((x),(v),1,0)
index 894065b1992809d3da63e96438a1a52bd99d935d..caceb60fc6ff2595bce3946250a5b81e94d78f37 100644 (file)
#include "ecc.h"
#include "target.h"
+#define NAND_DATA_OFFSET 0x0 /* Data register offset */
+#define NAND_ALE_OFFSET 0x2000 /* Address latch enable register offset */
+#define NAND_CMD_OFFSET 0x4000 /* Command latch enable register offset */
+
+#define NAND_DELAY 50000
+
+extern void chipDelay32 (uint32 del);
+extern uint32 deviceEmif25MemBase (int32 cs);
+
int32 gCs; /* The chip select space */
uint32 memBase; /* Base address in device memory map */
nandDevInfo_t *hwDevInfo; /* Pointer to the device configuration */
+void
+nandAleSet
+(
+ Uint32 addr
+)
+{
+ DEVICE_REG32_W (memBase + NAND_ALE_OFFSET, addr);
+}
+
+void
+nandCmdSet
+(
+ Uint32 cmd
+)
+{
+ DEVICE_REG32_W (memBase + NAND_CMD_OFFSET, cmd);
+}
+
+void
+nandReadDataBytes
+(
+ Uint32 nbytes,
+ Uint8* data
+)
+{
+ Int32 i;
+
+ if (hwDevInfo->busWidthBits == 8)
+ {
+ for (i = 0; i < nbytes; i++)
+ data[i] = *(volatile Uint8 *)memBase;
+
+ } else {
+
+ for (i = 0; i < (nbytes+1) >> 1; i++)
+ data[i] = *(volatile Uint16 *)memBase;
+ }
+}
+
/**
* @brief
* Initialize the Nand emif interface
*/
-Int32 nandHwDriverInit (int32 cs, void *vdevInfo)
+Int32 nandHwEmifDriverInit (int32 cs, void *vdevInfo)
{
- nandDevInfo_t *devInfo = (nandDevInfo_t *)vdevInfo;
-
gCs = cs;
- hwDevInfo = devInfo;
+ hwDevInfo = (nandDevInfo_t *)vdevInfo;
memBase = deviceEmif25MemBase (cs);
return (0);
-
}
/**
* @brief
* Read bytes without ecc correction
*/
-
-Int32 nandHwDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32 nbytes, Uint8 *data)
+Int32 nandHwEmifDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32 nbytes, Uint8 *data)
{
- Int32 i;
- Uint32 uAddr;
- Uint8 *v8Addr;
- Uint16 *v16Addr;
- Uint16 *vData;
-
- /* Form the base address */
- uAddr = memBase + (block << hwDevInfo->blockOffset) + (page << hwDevInfo->pageOffset) +
- (byte << hwDevInfo->columnOffset);
+ Uint32 addr;
+ Uint32 cmd;
- if (hwDevInfo->busWidthBits == 8) {
+ addr = (block << hwDevInfo->blockOffset) | (page << hwDevInfo->pageOffset) | ((byte & 0xff) << hwDevInfo->columnOffset);
- v8Addr = (Uint8 *)uAddr;
- for (i = 0; i < nbytes; i++)
- data[i] = v8Addr[i];
+ if (byte < 256)
+ {
+ cmd = hwDevInfo->readCommandPre;
+ }
+ else if (byte < 512)
+ {
+ cmd = hwDevInfo->readCommandPre + 1;
+ }
+ else
+ {
+ cmd = 0x50;
+ }
- } else {
+ nandCmdSet(cmd); // First cycle send 0
- v16Addr = (Uint16 *)uAddr;
- vData = (Uint16 *)data;
+ /* 4 address cycles */
+ nandAleSet((addr >> 0) & 0xFF); /* A0-A7 1st Cycle, column addr */
+ nandAleSet((addr >> 9) & 0xFF); /* A9-A16 2nd Cycle, page addr & blk */
+ nandAleSet((addr >> 17) & 0xFF); /* A17-A24 3rd Cycle, block addr */
+ nandAleSet((addr >> 25) & 0x1); /* A25-A26 4th Cycle, plane addr */
- for (i = 0; i < (nbytes+1) >> 1; i++)
- vData[i] = v16Addr[i];
+ chipDelay32 (NAND_DELAY);
- }
+ nandReadDataBytes(nbytes, data);
return (0);
-
}
/**
* @brief
- * Convert the 32 bit ecc format used by the emif25 into the 3 byte values used by the software
- * ecc algorithm
+ * Read a complete page of data
*/
-void nand_format_ecc (uint32 v32, Uint8 *v8)
+Int32 nandHwEmifDriverReadPage (Uint32 block, Uint32 page, Uint8 *data)
{
- /* An intrinsic is used for devices that support the shfl instruction */
- v32 = TARGET_SHFL(v32);
+ Int32 i, j, nSegs;
+ Int32 addr;
+ Uint8 *blockp, *pSpareArea;
+ Uint8 eccCompute[3];
+ Uint8 eccFlash[3];
- v8[0] = (v32 >> 0) & 0xff;
- v8[1] = (v32 >> 8) & 0xff;
- v8[1] = (v32 >> 16) & 0x3f; /* p2048o and p2048e are unused and must be masked out */
+ addr = (block << hwDevInfo->blockOffset) | (page << hwDevInfo->pageOffset);
-}
+ /* Send the read command */
+ nandCmdSet(hwDevInfo->readCommandPre);
+
+ /* 4 address cycles */
+ nandAleSet((addr >> 0) & 0xFF); /* A0-A7 1st Cycle, column addr */
+ nandAleSet((addr >> 9) & 0xFF); /* A9-A16 2nd Cycle, page addr & blk */
+ nandAleSet((addr >> 17) & 0xFF); /* A17-A24 3rd Cycle, block addr */
+ nandAleSet((addr >> 25) & 0x1); /* A25-A26 4th Cycle, plane addr */
-/**
- * @brief
- * Read a complete page of data
- */
-Int32 nandHwDriverReadPage (Uint32 block, Uint32 page, Uint8 *data)
-{
- Int32 i;
- Int32 nSegs;
- Uint32 v;
- Uint8 *blockp;
- Uint32 eccv;
- Uint8 eccHw[3];
- Uint8 eccFlash[3];
+ chipDelay32 (NAND_DELAY);
+ /* Read the data */
+ nandReadDataBytes(hwDevInfo->pageSizeBytes + hwDevInfo->pageEccBytes, data);
+ pSpareArea = &data[hwDevInfo->pageSizeBytes];
+
/* Break the page into segments of 256 bytes, each with its own ECC */
nSegs = hwDevInfo->pageSizeBytes >> 8;
blockp = &data[i << 8];
-
- /* Read the ecc bytes stored in the extra page data */
- nandHwDriverReadBytes (block, page, hwDevInfo->pageSizeBytes + hwDevInfo->pageEccBytes - ((nSegs - i) * 4), 4, (Uint8 *)eccv);
-
-
- /* Reset the hardware ECC correction by reading the ECC status register */
- v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ECC_REG(gCs));
-
- /* Enable ECC */
- v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_CTL_REG);
- v = v | (1 << (gCs + 8 - 2));
- DEVICE_REG32_W (DEVICE_EMIF25_BASE + EMIF25_FLASH_CTL_REG, v);
-
- nandHwDriverReadBytes (block, page, i << 8, 256, blockp);
-
- /* Read the ECC value computed by the hardware */
- v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ECC_REG(gCs));
-
/* Format the ecc values to match what the software is looking for */
- nand_format_ecc (eccv, eccFlash);
- nand_format_ecc (v, eccHw);
-
- if (eccCorrectData (blockp, eccFlash, eccHw))
+ for (j = 0; j < 3; j++)
+ {
+ eccFlash[j] = pSpareArea[hwDevInfo->eccBytesIdx[i*3+j]];
+ }
+
+ eccComputeECC(blockp, eccCompute);
+ if (eccCorrectData (blockp, eccFlash, eccCompute))
+ {
return (NAND_ECC_FAILURE);
-
+ }
}
return (0);
* @brief
* Close the low level driver
*/
-Int32 nandHwDriverClose (void)
+Int32 nandHwEmifDriverClose (void)
{
- int32 v;
-
/* Simply read the ECC to clear the ECC calculation */
- v = DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ECC_REG(gCs));
+ DEVICE_REG32_R (DEVICE_EMIF25_BASE + EMIF25_FLASH_ECC_REG(gCs));
return (0);
-
-
index 60e5227371225d913f2f0c06fa9c51dcc5e9d13d..22ac31e7c805b11f2f5fcce59788c3a657ec3bca 100644 (file)
* @brief Initialize the driver
*
*/
-Int32 nandHwDriverInit (int32 cs, void *vdevInfo)
+Int32 nandHwGpioDriverInit (int32 cs, void *vdevInfo)
{
Uint32 cmd;
nandDevInfo_t *devInfo = (nandDevInfo_t *)vdevInfo;
* Read a complete page including the extra page bytes.
*/
-Int32 nandHwDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32 nbytes, Uint8 *data)
+Int32 nandHwGpioDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32 nbytes, Uint8 *data)
{
Uint32 addr;
@@ -316,7 +316,7 @@ Int32 nandHwDriverReadBytes (Uint32 block, Uint32 page, Uint32 byte, Uint32 nbyt
* @brief
* Read a complete page including the extra page bytes
*/
-Int32 nandHwDriverReadPage(Uint32 block, Uint32 page, Uint8 *data)
+Int32 nandHwGpioDriverReadPage(Uint32 block, Uint32 page, Uint8 *data)
{
Int32 ret;
Int32 i;
Uint8 eccCalc[3];
/* Read the page, including the extra bytes */
- ret = nandHwDriverReadBytes (block, page, 0, hwDevInfo->pageSizeBytes + hwDevInfo->pageEccBytes, data);
+ ret = nandHwGpioDriverReadBytes (block, page, 0, hwDevInfo->pageSizeBytes + hwDevInfo->pageEccBytes, data);
if (ret < 0)
return (ret);
* @brief
* Close the driver
*/
-int32 nandHwDriverClose (void)
+int32 nandHwGpioDriverClose (void)
{
return (0);
diff --git a/src/ibl.h b/src/ibl.h
index 77d0b0fca820dffaa7884616cfd151b89525cd13..1d25d2711035546061bf75c628f7c08c757631b9 100644 (file)
--- a/src/ibl.h
+++ b/src/ibl.h
} iblMdio_t;
+/**
+ * @def ibl_N_ECC_BYTES
+ */
+#define ibl_N_ECC_BYTES 6 /**< The number of ECC bytes to be computed for each page */
+
+/**
+ * @def ibl_N_BAD_BLOCK_MARKER
+ */
+#define ibl_N_BAD_BLOCK_PAGE 2 /**< The number of pages in each block that has the bad block marker */
/**
* @brief
uint32 pageOffset; /**< Address bits which specify the page number */
uint32 columnOffset; /**< Address bits which specify the column number */
+ uint32 eccBytesIdx[ibl_N_ECC_BYTES];
+ /**< Index of each ECC byte in each page data */
+ uint32 badBlkMarkIdx[ibl_N_BAD_BLOCK_PAGE];
+ /**< Index of bad block marker in each page data */
+
uint8 resetCommand; /**< The command to reset the flash */
uint8 readCommandPre; /**< The read command sent before the address */
uint8 readCommandPost; /**< The read command sent after the address */
diff --git a/src/main/iblinit.c b/src/main/iblinit.c
index aa177ae11a2f3ae79aaa0a0ab5318ae13eca1f1d..65592510db4cbe33f8e0b91057edfb931968a193 100644 (file)
--- a/src/main/iblinit.c
+++ b/src/main/iblinit.c
iblStatus.iblVersion = ibl_VERSION;
iblStatus.activeDevice = ibl_ACTIVE_DEVICE_I2C;
+ /* Pll configuration is device specific */
+ devicePllConfig ();
/* Determine the boot device to read from */
bootDevice = deviceReadBootDevice();
}
- /* Pll configuration is device specific */
- devicePllConfig ();
+ /* Enable the EDC for local memory */
+ if (IBL_ENABLE_EDC)
+ {
+ iblEnableEDC ();
+ }
- /* iblReEnterRom () */
- if (IBL_REENTER_ROM)
+ /* Check if need to enter Rom boot loader again */
+ if (IBL_ENTER_ROM)
{
- iblReEnterRom ();
+ iblEnterRom ();
}
/* Pass control to the boot table processor */
diff --git a/src/main/iblmain.c b/src/main/iblmain.c
index 105c866287cc8d38013bd87d0c2d5f63819d2e95..9731c1b28b7a01cb530fda59aca7015e68a26024 100644 (file)
--- a/src/main/iblmain.c
+++ b/src/main/iblmain.c
switch (interface) {
+ #if (!defined(EXCLUDE_NAND_GPIO))
+
case ibl_PMEM_IF_GPIO:
ret = devicePowerPeriph (TARGET_PWR_GPIO);
break;
-
+ #endif
#if (!defined(EXCLUDE_NOR_SPI) && !defined(EXCLUDE_NAND_SPI))
break;
#endif
- #if (!defined(EXCLUDE_NAND_EMIF) && !defined(EXCLUDE_NAND_SPI) && !defined(EXCLUDE_NAND_GPIO))
+ //#if (!defined(EXCLUDE_NAND_EMIF) && !defined(EXCLUDE_NAND_SPI) && !defined(EXCLUDE_NAND_GPIO))
+ #if ((!defined(EXCLUDE_NAND_EMIF)) )
case ibl_BOOT_MODE_NAND:
iblPmemCfg (ibl.bootModes[j].u.nandBoot.interface, ibl.bootModes[j].port, TRUE);
iblNandBoot (j);
index 1ac5c354289d4a9ec4852a2c817d6b5a59ab1f00..456c77d80250cd7eac0ce85be9a28b92006f2fbc 100644 (file)
-c
-stack 0x800
--heap 0x6000
+-heap 0x8000
MEMORY
TEXT_INIT : origin = 0x800000, length = 0x4000
TEXT : origin = 0x804000, length = 0xc000
STACK : origin = 0x810000, length = 0x0800
- HEAP : origin = 0x810800, length = 0x6000
- DATA_INIT : origin = 0x816800, length = 0x0400
- DATA : origin = 0x816c00, length = 0x2c00
- CFG : origin = 0x819800, length = 0x0300
- STAT : origin = 0x819b00, length = 0x0200
-
- LINKRAM : origin = 0x10819d00, length = 0x0200
- CPPIRAM : origin = 0x10819f00, length = 0x0200
- PKTRAM : origin = 0x1081a100, length = 0x0800
+ HEAP : origin = 0x810800, length = 0x8000
+ DATA_INIT : origin = 0x818800, length = 0x0400
+ DATA : origin = 0x818c00, length = 0x2c00
+ CFG : origin = 0x81b800, length = 0x0300
+ STAT : origin = 0x81bb00, length = 0x0200
+
+ LINKRAM : origin = 0x1081bd00, length = 0x0200
+ CPPIRAM : origin = 0x1081bf00, length = 0x0200
+ PKTRAM : origin = 0x1081c100, length = 0x0800
}
index f15968d6acd3c61d197a293839e3a087e0181a37..a972aac2445967983bc0776882645426e3fa370c 100755 (executable)
#define ibl_BOOT_FORMAT_BIS 2
#define ibl_BOOT_FORMAT_COFF 3
#define ibl_BOOT_FORMAT_ELF 4
-#define ibl_BOOT_FORMAT_BBLOB 5
+#define ibl_BOOT_FORMAT_BLOB 5
#define ibl_BOOT_FORMAT_BTBL 6
-#define ibl_PMEM_IF_SPI 100
+#define ibl_PMEM_IF_GPIO 0
+
+#define ibl_PMEM_IF_CHIPSEL_2 2 /* EMIF interface using chip select 2, no wait enabled */
+#define ibl_PMEM_IF_CHIPSEL_3 3 /* EMIF interface using chip select 3, no wait enabled */
+#define ibl_PMEM_IF_CHIPSEL_4 4 /* EMIF interface using chip select 4 */
+#define ibl_PMEM_IF_CHIPSEL_5 5 /* EMIF interface using chip select 5 */
+
+#define ibl_PMEM_IF_SPI 100 /* Interface through SPI */
+
#define ibl_MAIN_PLL 0
#define ibl_DDR_PLL 1
ibl.spiConfig.c2tdelay = 1;
ibl.spiConfig.busFreqMHz = 20;
- ibl.emifConfig[0].csSpace = 0;
- ibl.emifConfig[0].busWidth = 0;
+ ibl.emifConfig[0].csSpace = 2;
+ ibl.emifConfig[0].busWidth = 8;
ibl.emifConfig[0].waitEnable = 0;
ibl.emifConfig[1].csSpace = 0;
ibl.bootModes[0].u.norBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
ibl.bootModes[0].u.norBoot.bootAddress = 0;
ibl.bootModes[0].u.norBoot.interface = ibl_PMEM_IF_SPI;
- ibl.bootModes[1].u.norBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
- ibl.bootModes[1].u.norBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */
- ibl.bootModes[1].u.norBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */
+ ibl.bootModes[0].u.norBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.norBoot.blob.sizeBytes = 0x80000; /* 512 KB */
+ ibl.bootModes[0].u.norBoot.blob.branchAddress = 0x80000000; /* Base address of DDR2 */
ibl.bootModes[1].bootMode = ibl_BOOT_MODE_TFTP;
ibl.bootModes[1].priority = ibl_HIGHEST_PRIORITY+1;
ibl.chkSum = 0;
}
+
+menuitem "EVM c6678 NAND Boot IBL";
+
+hotmenu setConfig_c6678_nand()
+{
+ /* Nand boot is higher priority */
+ ibl.bootModes[0].bootMode = ibl_BOOT_MODE_NAND;
+ ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY;
+ ibl.bootModes[0].port = 0;
+
+ ibl.bootModes[0].u.nandBoot.bootFormat = ibl_BOOT_FORMAT_ELF;
+ ibl.bootModes[0].u.nandBoot.bootAddress = 0;
+ ibl.bootModes[0].u.nandBoot.interface = ibl_PMEM_IF_CHIPSEL_2;
+ ibl.bootModes[0].u.nandBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */
+ ibl.bootModes[0].u.nandBoot.blob.sizeBytes = 0x80000; /* 512 KB */
+ ibl.bootModes[0].u.nandBoot.blob.branchAddress = 0x80000000; /* Base address of DDR2 */
+
+ ibl.bootModes[0].u.nandBoot.nandInfo.busWidthBits = 8;
+ ibl.bootModes[0].u.nandBoot.nandInfo.pageSizeBytes = 512;
+ ibl.bootModes[0].u.nandBoot.nandInfo.pageEccBytes = 16;
+ ibl.bootModes[0].u.nandBoot.nandInfo.pagesPerBlock = 32;
+ ibl.bootModes[0].u.nandBoot.nandInfo.totalBlocks = 4096;
+
+ ibl.bootModes[0].u.nandBoot.nandInfo.addressBytes = 4;
+ ibl.bootModes[0].u.nandBoot.nandInfo.lsbFirst = TRUE;
+ ibl.bootModes[0].u.nandBoot.nandInfo.blockOffset = 14;
+ ibl.bootModes[0].u.nandBoot.nandInfo.pageOffset = 9;
+ ibl.bootModes[0].u.nandBoot.nandInfo.columnOffset = 0;
+
+ ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[0] = 0;
+ ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[1] = 1;
+ ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[2] = 2;
+ ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[3] = 3;
+ ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[4] = 6;
+ ibl.bootModes[0].u.nandBoot.nandInfo.eccBytesIdx[5] = 7;
+
+ ibl.bootModes[0].u.nandBoot.nandInfo.badBlkMarkIdx[0]= 5;
+ ibl.bootModes[0].u.nandBoot.nandInfo.badBlkMarkIdx[1]= 0xffff;
+
+ ibl.bootModes[0].u.nandBoot.nandInfo.resetCommand = 0xff;
+ ibl.bootModes[0].u.nandBoot.nandInfo.readCommandPre = 0;
+ ibl.bootModes[0].u.nandBoot.nandInfo.readCommandPost = 0;
+ ibl.bootModes[0].u.nandBoot.nandInfo.postCommand = FALSE;
+}