Clearing DDR3 memory in IBL (workaround for failing to load NAND image)

IBL updates. Change to version 1.0.0.13

DDR config updates for Shannon PG 2.0

iblConfig: refix DHCP for 6670

Some one checked in local static IP hacks, this undoes that.

Signed-off-by: Bill Mills <wmills@ti.com>

iblConfig now accepts ethboot changes from input.txt

Code review changes to ensure ddr3_mem_test() picking up types.h definition

Renamed ifdef flag, init uart from iblmain

Merge branch 'linux-c6x-2.0.x' into boot-rel-exp

Conflicts:
src/device/c66x/c66x.c
src/main/iblmain.c

Code review changes, restructuring code

Refix c64x: uart API and null_uart

Recent changes broke c64x platforms because they assume C66 uart.
This commit seperates UART user API from implementation
It also adds a "null" uart for platforms w/o a UART
This null UART is used on all c64x platforms for now

Signed-off-by: Bill Mills <wmills@ti.com>

UPdate Version to 1.0.0.12

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Add volatile to DDRPLLCTL1

Merge branch 'boot-rel-exp'

Clean up UART prints, UART driver, etc.

Fixed length of UART print

Modified IBL to re-init PLL in DDR controller, added UART

setupenvMsys.sh to use CGT 7.2.4 instead of CCS's c6000 library

for loop for pll + ddr_ctr_config

new pll sequence of 1.main 2.pa 3.ddr

IBL Config fixes

Updated ddr_controller wait to reflect proper values, adding DDR PLL init in DDR controller

DDR controller Pre-code review updates/comments, cleaned up c66xinit.c

C66x: DDR3 and PA SS PLL updates based on review

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

C66x PLL: Don't subtract the multiplier/divider twice

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

DDR3 and PA SS PLL driver code update

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: Use DDR3 PLL driver

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x IBL Config: Upadte DDR PLL init values

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

C66x: Update gel file with DDR PLL values

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: Update MAIN PLL config

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: Update PASS PLL init code

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

C66x: remove DDR3 PLL config

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: Move DDR3 PLL config

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: PA PLL updates

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: DDR3 PLL init update

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: PLL init code update based on latest review

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Minor Update to i2c param cmd file

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: Updated PLL init code

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Don't copy .dat files to Release folder

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

6670: Don't init DDR PLL twice

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Adding back support for updating i2c config params

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Add Doc for Single Binary Support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Increase delays in DDR3 init

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: Updated DDR configuration

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Revert "c66x: Updated DDR configuration"

This reverts commit e1253610dc118b365b2475d85008519458eafbec.

This DDR config change is causing boot issues on many (but not all) 6670 boards.
There is also variablity between rebuilds of the same kernel source (ie small address variations)

Signed-off-by: Bill Mills <wmills@ti.com>

GPIO: GPIO Read function returns 8 bits

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Update README.txt with correct release info

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Update device config for DHCP boot

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: Updated DDR configuration

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

setupenvLnx.sh: search more places for cgt

Search more dirs for an installed CGT

Signed-off-by: Bill Mills <wmills@ti.com>

Merge commit 'origin/tmp-wam-top-level-build'

GPIO NAND: Fix for Big Endian Boot

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

GPIO NAND: Add function prototype for Read

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c66x: Update Section sizes

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

GPIO: Read Function should return 32 bits

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Build: update setupenvLnx.sh to do error checking

Do a basic sanity test of C6X_BASE_DIR

Signed-off-by: Bill Mills <wmills@ti.com>

.gitignore: update to ignore all make created files

Signed-off-by: Bill Mills <wmills@ti.com>

setupenvLnx.sh: Don't hard code TI GT specific paths

We should not be hard coding TI GT specific paths into the source files.
We should not make the user edit a source file to do thier build.
This change allows the user to predefine C6X_BASE_DIR.
If not defined it will look in standard places for CCS as is done for Windows.

Signed-off-by: Bill Mills <wmills@ti.com>

clean out old unused files

These files have not been updated when the build procedure changed
but there were still present causing confusion.

Signed-off-by: Bill Mills <wmills@ti.com>

iblConfig: fix undefined return code

When all works fine, main was hitting } w/o a return.
This left the process return code undefined.
It may have worked on some machines but was not correct.

Signed-off-by: Bill Mills <wmills@ti.com>

Minor Cleanup for Single Binary Support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Updates to the documentation due to single binary updates

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Merge commit 'origin/master' into single-bi

Updating the EVM flag

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Makestg2 update for single binary support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Single Binary Support Enhancement

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Single Binary Build Update

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Adding EVM flag to build infrastructure

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Minor update to build infra to add support for single binary

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

i2c Params are no longer built

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

IBL Single Binary Support: Updating Directory Names

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Updated Release version

Adding PCIe boot support for C6670 SDOCM00083134

Single Binary Support: Initial Commit

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

IBL: Bumped up version of IBL to 1.0.0.9

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Modification to IBL main function

Modification was required to add c64x multi boot support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c64x: Updates to gel file for multi boot support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

6472: Remove dual endian support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

6455: Remove dual endian support

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c64x: Add Multi Boot Support

This commit adds multi boot support for
the c64x+ based low cost EVMs.

TFTP and NAND boot were tested on the
c6472, c6474 and c6457 low cost EVMs

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

UART: Start adding UART code

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

6474l: Add infrastructure to build 6474l

This commit adds infrastructure to build the 6474
low cost EVM as a separate target

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

C6457: Update Branch/Start Address for NAND boot

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

C64x: Updates to gel file for NAND boot

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

util: host program to generate ecc test patterns

Signed-off-by: Bill Mills <wmills@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

GPIO NAND: Complete Support for 2k page size NAND

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Cleanup unused MACROS

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

GPIO-NAND: Add check for 2K page size NAND

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

GPIO NAND: ADD Support for c64x devices

This commit adds support for the C64x+ SOCs in the
GPIO NAND Driver

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c64x+ : modify Makefile to build NAND GPIO driver

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

c64x+ : Minor code cleanup

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

C64x+: Additions to gel file

Making additions to the gel file for C64x+ based SOCs/EVMs
which have a NAND

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

GPIO-NAND: Add NAND specific definitions

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

GPIO NAND: Move definitions to header file

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Updating release version to 1.0.0.8

Changed the default parameters for BLOB image format to match Linux Kernel image

Updated release version
modified make clean for i2cConfig

Gel file updates to increase blob size

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Merge branch 'master' of git@gtgit01.gt.design.ti.com:git/teams/mmi/ibl

Fix for IRs 81908, 81906, 81876, 81800

updated Release version