From 2677f90c3ba95697ceefc45b09dbd12294945f37 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Fri, 4 Nov 2011 13:34:22 -0400 Subject: [PATCH] c66x: Move DDR3 PLL config Signed-off-by: Sandeep Paulraj --- src/device/c66x/c66xinit.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/device/c66x/c66xinit.c b/src/device/c66x/c66xinit.c index c46e9ea..a9d72a0 100644 --- a/src/device/c66x/c66xinit.c +++ b/src/device/c66x/c66xinit.c @@ -14,6 +14,18 @@ #include "tiboot_c66x.h" +#define CHIP_LEVEL_REG 0x02620000 +#define DDR3PLLCTL0 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0330) +#define DDR3PLLCTL1 *(volatile unsigned int*)(CHIP_LEVEL_REG + 0x0334) + +static void ddr3_delay (uint32 del) +{ + volatile unsigned int i; + + for (i = 0; i < del; i++); + +} + /** * @brief Configure the PLLs * @@ -23,6 +35,7 @@ */ void devicePllConfig (void) { + unsigned int i; /* Unlock the chip registers and leave them unlocked */ *((Uint32 *)0x2620038) = 0x83e70b13; @@ -34,6 +47,28 @@ void devicePllConfig (void) ibl.pllConfig[ibl_MAIN_PLL].mult, ibl.pllConfig[ibl_MAIN_PLL].postdiv); + + + /* 1333 MHz data rate */ + /***************** 2.2 DDR3 PLL Configuration ************/ + DDR3PLLCTL1 |= 0x00000040; //Set ENSAT bit = 1 + DDR3PLLCTL0 |= 0x00800000; // Set BYPASS = 1 + DDR3PLLCTL1 |= 0x00002000; //Set RESET bit = 1 + + DDR3PLLCTL0 = 0x090804C0; //Configure CLKR, CLKF, CLKOD, BWADJ + + for (i = 0;i < 20;i++) + ddr3_delay(1000); //Wait for reset to complete + + DDR3PLLCTL1 &= ~(0x00002000); //Clear RESET bit + + for (i = 0;i < 500;i++) + ddr3_delay(1000); //Wait for PLL lock + + DDR3PLLCTL0 &= ~(0x00800000); // Set BYPASS = 0 + +#if 0 + if (ibl.pllConfig[ibl_DDR_PLL].doEnable == TRUE) hwPllSetCfg2Pll (DEVICE_PLL_BASE(DDR_PLL), ibl.pllConfig[ibl_DDR_PLL].prediv, @@ -42,6 +77,8 @@ void devicePllConfig (void) ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz, ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz); +#endif + if (ibl.pllConfig[ibl_NET_PLL].doEnable == TRUE) hwPllSetCfgPll (DEVICE_PLL_BASE(NET_PLL), ibl.pllConfig[ibl_NET_PLL].prediv, -- 2.26.2