From 55ed1b1983e1db587cc403c155d73b6b1c5fc119 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Tue, 8 Nov 2011 14:51:34 -0500 Subject: [PATCH 1/1] C66x: Update gel file with DDR PLL values Signed-off-by: Sandeep Paulraj --- src/util/i2cConfig/i2cConfig.gel | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/util/i2cConfig/i2cConfig.gel b/src/util/i2cConfig/i2cConfig.gel index 392dd31..ef70296 100755 --- a/src/util/i2cConfig/i2cConfig.gel +++ b/src/util/i2cConfig/i2cConfig.gel @@ -781,11 +781,11 @@ hotmenu setConfig_c6678_main() ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000; /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */ - ibl.pllConfig[ibl_DDR_PLL].doEnable = 0; + ibl.pllConfig[ibl_DDR_PLL].doEnable = 1; ibl.pllConfig[ibl_DDR_PLL].prediv = 1; - ibl.pllConfig[ibl_DDR_PLL].mult = 12; + ibl.pllConfig[ibl_DDR_PLL].mult = 20; ibl.pllConfig[ibl_DDR_PLL].postdiv = 2; - ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 400; + ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 1333; /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */ ibl.pllConfig[ibl_NET_PLL].doEnable = 1; @@ -995,12 +995,12 @@ hotmenu setConfig_c6670_main() ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2; ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 983; - /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */ - ibl.pllConfig[ibl_DDR_PLL].doEnable = 0; + /* DDR PLL */ + ibl.pllConfig[ibl_DDR_PLL].doEnable = 1; ibl.pllConfig[ibl_DDR_PLL].prediv = 1; - ibl.pllConfig[ibl_DDR_PLL].mult = 12; + ibl.pllConfig[ibl_DDR_PLL].mult = 20; ibl.pllConfig[ibl_DDR_PLL].postdiv = 2; - ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 400; + ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 1333; /* Net PLL: 122.88 MHz reference, 1044 MHz output (followed by a built in divide by 3 to give 348 MHz to PA) */ ibl.pllConfig[ibl_NET_PLL].doEnable = 1; -- 2.39.2