From d63d6945f9a4fcb8a7419eeb04d7d9318d84c97b Mon Sep 17 00:00:00 2001 From: Sandeep Nair Date: Mon, 2 May 2011 20:28:57 -0400 Subject: [PATCH] Removed spiConfig writer from utils --- src/util/spiConfig/Makefile | 69 --- src/util/spiConfig/i2cConfig.gel | 784 ------------------------------- src/util/spiConfig/makestg2 | 110 ----- src/util/spiConfig/spiparam.c | 190 -------- src/util/spiConfig/spiparam.cmd | 38 -- 5 files changed, 1191 deletions(-) delete mode 100644 src/util/spiConfig/Makefile delete mode 100644 src/util/spiConfig/i2cConfig.gel delete mode 100644 src/util/spiConfig/makestg2 delete mode 100644 src/util/spiConfig/spiparam.c delete mode 100644 src/util/spiConfig/spiparam.cmd diff --git a/src/util/spiConfig/Makefile b/src/util/spiConfig/Makefile deleted file mode 100644 index 55a320f..0000000 --- a/src/util/spiConfig/Makefile +++ /dev/null @@ -1,69 +0,0 @@ -#* -#* -#* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -#* -#* -#* Redistribution and use in source and binary forms, with or without -#* modification, are permitted provided that the following conditions -#* are met: -#* -#* Redistributions of source code must retain the above copyright -#* notice, this list of conditions and the following disclaimer. -#* -#* Redistributions in binary form must reproduce the above copyright -#* notice, this list of conditions and the following disclaimer in the -#* documentation and/or other materials provided with the -#* distribution. -#* -#* Neither the name of Texas Instruments Incorporated nor the names of -#* its contributors may be used to endorse or promote products derived -#* from this software without specific prior written permission. -#* -#* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -#* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -#* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -#* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -#* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -#* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -#* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -#* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -#* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -#* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -#* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -#* - - -#************************************************************** -#* FILE PURPOSE: Top level make for the spi parameter writer -#************************************************************** -#* FILE NAME: Makefile -#* -#* DESCRIPTION: Builds the program to write the parameter table -#* to the spi rom -#* -#*************************************************************** - -DEVICES= c6455 c6472 c6474 c6474l c6457 c661x - -all: - @echo must specify a target [ $(DEVICES) ] - -# Default options that can be overwridden on the command line -ifndef ENDIAN - ENDIAN= little -endif - -export ENDIAN - - -$(DEVICES): - make -f makestg2 ARCH=c64x TARGET=$@ $@ - - -clean: - make -f makestg2 clean2 ARCH=c64x - - - - - diff --git a/src/util/spiConfig/i2cConfig.gel b/src/util/spiConfig/i2cConfig.gel deleted file mode 100644 index cfdf901..0000000 --- a/src/util/spiConfig/i2cConfig.gel +++ /dev/null @@ -1,784 +0,0 @@ -#define TRUE 1 -#define FALSE 0 - -#define ibl_MAGIC_VALUE 0xCEC11EBB - -#define ibl_HIGHEST_PRIORITY 1 -#define ibl_LOWEST_PRIORITY 10 -#define ibl_DEVICE_NOBOOT 20 - -#define ibl_PORT_SWITCH_ALL -2 - -#define SETIP(array,i0,i1,i2,i3) array[0]=(i0); \ - array[1]=(i1); \ - array[2]=(i2); \ - array[3]=(i3) - -#define ibl_BOOT_MODE_TFTP 10 -#define ibl_BOOT_MODE_NAND 11 -#define ibl_BOOT_MODE_NOR 12 -#define ibl_BOOT_MODE_NONE 13 - - -#define ibl_BOOT_FORMAT_AUTO 0 -#define ibl_BOOT_FORMAT_NAME 1 -#define ibl_BOOT_FORMAT_BIS 2 -#define ibl_BOOT_FORMAT_COFF 3 -#define ibl_BOOT_FORMAT_ELF 4 -#define ibl_BOOT_FORMAT_BBLOB 5 -#define ibl_BOOT_FORMAT_BTBL 6 - -#define ibl_MAIN_PLL 0 -#define ibl_DDR_PLL 1 -#define ibl_NET_PLL 2 - -#define ibl_EMIF4_ENABLE_sdRamConfig (1 << 0) -#define ibl_EMIF4_ENABLE_sdRamConfig2 (1 << 1) -#define ibl_EMIF4_ENABLE_sdRamRefreshCtl (1 << 2) -#define ibl_EMIF4_ENABLE_sdRamTiming1 (1 << 3) -#define ibl_EMIF4_ENABLE_sdRamTiming2 (1 << 4) -#define ibl_EMIF4_ENABLE_sdRamTiming3 (1 << 5) -#define ibl_EMIF4_ENABLE_lpDdrNvmTiming (1 << 6) -#define ibl_EMIF4_ENABLE_powerManageCtl (1 << 7) -#define ibl_EMIF4_ENABLE_iODFTTestLogic (1 << 8) -#define ibl_EMIF4_ENABLE_performCountCfg (1 << 9) -#define ibl_EMIF4_ENABLE_performCountMstRegSel (1 << 10) -#define ibl_EMIF4_ENABLE_readIdleCtl (1 << 11) -#define ibl_EMIF4_ENABLE_sysVbusmIntEnSet (1 << 12) -#define ibl_EMIF4_ENABLE_sdRamOutImpdedCalCfg (1 << 13) -#define ibl_EMIF4_ENABLE_tempAlterCfg (1 << 14) -#define ibl_EMIF4_ENABLE_ddrPhyCtl1 (1 << 15) -#define ibl_EMIF4_ENABLE_ddrPhyCtl2 (1 << 16) -#define ibl_EMIF4_ENABLE_priClassSvceMap (1 << 17) -#define ibl_EMIF4_ENABLE_mstId2ClsSvce1Map (1 << 18) -#define ibl_EMIF4_ENABLE_mstId2ClsSvce2Map (1 << 11) -#define ibl_EMIF4_ENABLE_eccCtl (1 << 19) -#define ibl_EMIF4_ENABLE_eccRange1 (1 << 20) -#define ibl_EMIF4_ENABLE_eccRange2 (1 << 21) -#define ibl_EMIF4_ENABLE_rdWrtExcThresh (1 << 22) -#define ibl_BOOT_EMIF4_ENABLE_ALL 0x007fffff - -/* @} */ - -menuitem "EVM c6472 IBL"; - -hotmenu setConfig_c6472() -{ - ibl.iblMagic = ibl_MAGIC_VALUE; - - ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE; - ibl.pllConfig[ibl_MAIN_PLL].prediv = 1; - ibl.pllConfig[ibl_MAIN_PLL].mult = 28; - ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1; - ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 700; - - /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */ - ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE; - - /* The network PLL. The multipliers/dividers are fixed */ - ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE; - - /* EMIF configuration. The values are for DDR at 533 MHz */ - ibl.ddrConfig.configDdr = TRUE; - - ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538832; /* timing, 32bit wide */ - ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x0000073B; /* Refresh 533Mhz */ - ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x47245BD2; /* Timing 1 */ - ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x0125DC44; /* Timing 2 */ - ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */ - - /* Ethernet configuration for port 0 */ - ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY; - ibl.ethConfig[0].port = 0; - - /* Bootp is disabled. The server and file name are provided here */ - ibl.ethConfig[0].doBootp = FALSE; - ibl.ethConfig[0].useBootpServerIp = FALSE; - ibl.ethConfig[0].useBootpFileName = FALSE; - ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_AUTO; - - - SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,21); - SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196); - SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,2); - SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0); - - /* Leave the hardware address as 0 so the e-fuse value will be used */ - - - - - ibl.ethConfig[0].ethInfo.fileName[0] = 't'; - ibl.ethConfig[0].ethInfo.fileName[1] = 'e'; - ibl.ethConfig[0].ethInfo.fileName[2] = 's'; - ibl.ethConfig[0].ethInfo.fileName[3] = 't'; - ibl.ethConfig[0].ethInfo.fileName[4] = '.'; - ibl.ethConfig[0].ethInfo.fileName[5] = 'o'; - ibl.ethConfig[0].ethInfo.fileName[6] = 'u'; - ibl.ethConfig[0].ethInfo.fileName[7] = 't'; - ibl.ethConfig[0].ethInfo.fileName[8] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[9] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[10] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[11] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[12] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[13] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[14] = '\0'; - - /* Even though the entire range of DDR2 is chosen, the load will - * stop when the ftp reaches the end of the file */ - ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */ - ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */ - ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */ - - /* For port 1 use bootp */ - /* Ethernet configuration for port 0 */ - ibl.ethConfig[1].ethPriority = ibl_HIGHEST_PRIORITY + 1; - ibl.ethConfig[1].port = 1; - - /* Bootp is disabled. The server and file name are provided here */ - ibl.ethConfig[1].doBootp = TRUE; - ibl.ethConfig[1].useBootpServerIp = TRUE; - ibl.ethConfig[1].useBootpFileName = TRUE; - ibl.ethConfig[1].bootFormat = ibl_BOOT_FORMAT_AUTO; - - - /* SGMII not present */ - ibl.sgmiiConfig[0].adviseAbility = 0; - ibl.sgmiiConfig[0].control = 0; - ibl.sgmiiConfig[0].txConfig = 0; - ibl.sgmiiConfig[0].rxConfig = 0; - ibl.sgmiiConfig[0].auxConfig = 0; - - ibl.sgmiiConfig[1].adviseAbility = 0; - ibl.sgmiiConfig[1].control = 0; - ibl.sgmiiConfig[1].txConfig = 0; - ibl.sgmiiConfig[1].rxConfig = 0; - ibl.sgmiiConfig[1].auxConfig = 0; - - - /* Leave the hardware address as 0 so the e-fuse value will be used */ - ibl.ethConfig[0].ethInfo.hwAddress[0] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[1] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[2] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[3] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[4] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[5] = 0; - - - /* Leave all remaining fields as 0 since bootp will fill them in */ - - - /* Even though the entire range of DDR2 is chosen, the load will */ - /* stop when the ftp reaches the end of the file */ - - ibl.ethConfig[1].blob.startAddress = 0xe0000000; /* Base address of DDR2 */ - ibl.ethConfig[1].blob.sizeBytes = 0x20000000; /* All of DDR2 */ - ibl.ethConfig[1].blob.branchAddress = 0xe0000000; /* Base of DDR2 */ - - - - /* MDIO configuration */ - ibl.mdioConfig.nMdioOps = 8; - ibl.mdioConfig.mdioClkDiv = 0x20; - ibl.mdioConfig.interDelay = 1400; /* ~2ms at 700 MHz */ - - ibl.mdioConfig.mdio[0] = (1 << 30) | (27 << 21) | (24 << 16) | 0x848b; - ibl.mdioConfig.mdio[1] = (1 << 30) | (20 << 21) | (24 << 16) | 0x0ce0; - ibl.mdioConfig.mdio[2] = (1 << 30) | (24 << 21) | (24 << 16) | 0x4101; - ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (24 << 16) | 0x9140; - - ibl.mdioConfig.mdio[4] = (1 << 30) | (27 << 21) | (25 << 16) | 0x848b; - ibl.mdioConfig.mdio[5] = (1 << 30) | (20 << 21) | (25 << 16) | 0x0ce0; - ibl.mdioConfig.mdio[6] = (1 << 30) | (24 << 21) | (25 << 16) | 0x4101; - ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | (25 << 16) | 0x9140; - - - /* Nand boot is disabled */ - ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT; - - ibl.nandConfig.bootFormat = ibl_BOOT_FORMAT_AUTO; - - ibl.nandConfig.nandInfo.busWidthBits = 8; - ibl.nandConfig.nandInfo.pageSizeBytes = 2048; - ibl.nandConfig.nandInfo.pageEccBytes = 64; - ibl.nandConfig.nandInfo.pagesPerBlock = 64; - ibl.nandConfig.nandInfo.totalBlocks = 1024; - - ibl.nandConfig.nandInfo.addressBytes = 4; - ibl.nandConfig.nandInfo.lsbFirst = TRUE; - ibl.nandConfig.nandInfo.blockOffset = 22; - ibl.nandConfig.nandInfo.pageOffset = 16; - ibl.nandConfig.nandInfo.columnOffset = 0; - - ibl.nandConfig.nandInfo.resetCommand = 0xff; - ibl.nandConfig.nandInfo.readCommandPre = 0; - ibl.nandConfig.nandInfo.readCommandPost = 0x30; - ibl.nandConfig.nandInfo.postCommand = TRUE; - -} - - -menuitem "EVM c6474 Mez IBL"; - -hotmenu setConfig_c6474() -{ - ibl.iblMagic = ibl_MAGIC_VALUE; - - ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE; - ibl.pllConfig[ibl_MAIN_PLL].prediv = 1; - ibl.pllConfig[ibl_MAIN_PLL].mult = 20; - ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1; - ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000; - - /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */ - ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE; - - /* The network PLL. The multipliers/dividers are fixed */ - ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE; - - /* EMIF configuration. The values are for DDR at 533 MHz */ - ibl.ddrConfig.configDdr = TRUE; - - ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */ - ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */ - ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */ - ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */ - ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */ - - - /* Ethernet configuration for port 0 */ - ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY; - ibl.ethConfig[0].port = 0; - - /* Bootp is disabled. The server and file name are provided here */ - ibl.ethConfig[0].doBootp = FALSE; - ibl.ethConfig[0].useBootpServerIp = FALSE; - ibl.ethConfig[0].useBootpFileName = FALSE; - ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB; - - SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 10,218,109,35); - SETIP(ibl.ethConfig[0].ethInfo.serverIp, 10,218,109,196); - SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 10,218,109,1); - SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0); - - /* Set the hardware address as 0 so the e-fuse value will be used */ - ibl.ethConfig[0].ethInfo.hwAddress[0] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[1] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[2] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[3] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[4] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[5] = 0; - - - ibl.ethConfig[0].ethInfo.fileName[0] = 't'; - ibl.ethConfig[0].ethInfo.fileName[1] = 'e'; - ibl.ethConfig[0].ethInfo.fileName[2] = 's'; - ibl.ethConfig[0].ethInfo.fileName[3] = 't'; - ibl.ethConfig[0].ethInfo.fileName[4] = '.'; - ibl.ethConfig[0].ethInfo.fileName[5] = 'b'; - ibl.ethConfig[0].ethInfo.fileName[6] = 'l'; - ibl.ethConfig[0].ethInfo.fileName[7] = 'o'; - ibl.ethConfig[0].ethInfo.fileName[8] = 'b'; - ibl.ethConfig[0].ethInfo.fileName[9] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[10] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[11] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[12] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[13] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[14] = '\0'; - - - /* Even though the entire range of DDR2 is chosen, the load will - * stop when the ftp reaches the end of the file */ - ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */ - ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */ - ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */ - - /* There is no port 1 on the 6474 */ - ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT; - - /* SGMII is present */ - ibl.sgmiiConfig[0].adviseAbility = 0x9801; - ibl.sgmiiConfig[0].control = 0x20; - ibl.sgmiiConfig[0].txConfig = 0x00000ea3; - ibl.sgmiiConfig[0].rxConfig = 0x00081023; - ibl.sgmiiConfig[0].auxConfig = 0x0000000b; - - /* MDIO configuration */ - ibl.mdioConfig.nMdioOps = 8; - ibl.mdioConfig.mdioClkDiv = 0x26; - ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */ - - ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081; - ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047; - ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047; - ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140; - - ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140; - ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e; - ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e; - ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100; - - - /* Nand boot is disabled */ - ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT; - -} - -menuitem "EVM c6474 Lite EVM IBL"; - -hotmenu setConfig_c6474lite() -{ - ibl.iblMagic = ibl_MAGIC_VALUE; - - ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE; - ibl.pllConfig[ibl_MAIN_PLL].prediv = 1; - ibl.pllConfig[ibl_MAIN_PLL].mult = 20; - ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1; - ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000; - - /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */ - ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE; - - /* The network PLL. The multipliers/dividers are fixed */ - ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE; - - /* EMIF configuration. The values are for DDR at 533 MHz */ - ibl.ddrConfig.configDdr = TRUE; - - ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */ - ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a29; /* Refresh 333Mhz */ - ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x4d246c9a; /* Timing 1 */ - ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00993c42; /* Timing 2 */ - ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */ - - - /* Ethernet configuration for port 0 */ - ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY; - ibl.ethConfig[0].port = 0; - - /* Bootp is disabled. The server and file name are provided here */ - ibl.ethConfig[0].doBootp = FALSE; - ibl.ethConfig[0].useBootpServerIp = FALSE; - ibl.ethConfig[0].useBootpFileName = FALSE; - ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB; - - SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,114); - SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25); - SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2); - SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0); - - /* Set the hardware address as 0 so the e-fuse value will be used */ - ibl.ethConfig[0].ethInfo.hwAddress[0] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[1] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[2] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[3] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[4] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[5] = 0; - - - ibl.ethConfig[0].ethInfo.fileName[0] = 'c'; - ibl.ethConfig[0].ethInfo.fileName[1] = '6'; - ibl.ethConfig[0].ethInfo.fileName[2] = '4'; - ibl.ethConfig[0].ethInfo.fileName[3] = '7'; - ibl.ethConfig[0].ethInfo.fileName[4] = '4'; - ibl.ethConfig[0].ethInfo.fileName[5] = 'l'; - ibl.ethConfig[0].ethInfo.fileName[6] = '-'; - ibl.ethConfig[0].ethInfo.fileName[7] = 'l'; - ibl.ethConfig[0].ethInfo.fileName[8] = 'e'; - ibl.ethConfig[0].ethInfo.fileName[9] = '.'; - ibl.ethConfig[0].ethInfo.fileName[10] = 'b'; - ibl.ethConfig[0].ethInfo.fileName[11] = 'i'; - ibl.ethConfig[0].ethInfo.fileName[12] = 'n'; - ibl.ethConfig[0].ethInfo.fileName[13] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[14] = '\0'; - - - /* Even though the entire range of DDR2 is chosen, the load will - * stop when the ftp reaches the end of the file */ - ibl.ethConfig[0].blob.startAddress = 0x80000000; /* Base address of DDR2 */ - ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */ - ibl.ethConfig[0].blob.branchAddress = 0x80000000; /* Base of DDR2 */ - - /* There is no port 1 on the 6474 Lite EVM */ - ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT; - - /* SGMII is present */ - ibl.sgmiiConfig[0].adviseAbility = 0x9801; - ibl.sgmiiConfig[0].control = 0x20; - ibl.sgmiiConfig[0].txConfig = 0x00000e23; - ibl.sgmiiConfig[0].rxConfig = 0x00081023; - ibl.sgmiiConfig[0].auxConfig = 0x0000000b; - - /* MDIO configuration */ - ibl.mdioConfig.nMdioOps = 8; - ibl.mdioConfig.mdioClkDiv = 0x26; - ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */ - - ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081; - ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047; - ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047; - ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140; - - ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140; - ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e; - ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e; - ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100; - - - /* This board has NAND. We will enable later */ - ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT; - -} - -menuitem "EVM c6457 EVM IBL"; - -hotmenu setConfig_c6457() -{ - ibl.iblMagic = ibl_MAGIC_VALUE; - - ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE; - ibl.pllConfig[ibl_MAIN_PLL].prediv = 1; - ibl.pllConfig[ibl_MAIN_PLL].mult = 20; - ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1; - ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000; - - /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */ - ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE; - - /* The network PLL. The multipliers/dividers are fixed */ - ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE; - - /* EMIF configuration */ - ibl.ddrConfig.configDdr = TRUE; - - ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00d38a32; /* cas5, 8 banks, 10 bit column */ - ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x00000a0e; /* Refresh 333Mhz */ - ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x832474da; /* Timing 1 */ - ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x3d44c742; /* Timing 2 */ - ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x50001906; /* PHY read latency for CAS 5 is 5 + 2 - 1 */ - - - /* Ethernet configuration for port 0 */ - ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY; - ibl.ethConfig[0].port = 0; - - /* Bootp is disabled. The server and file name are provided here */ - ibl.ethConfig[0].doBootp = FALSE; - ibl.ethConfig[0].useBootpServerIp = FALSE; - ibl.ethConfig[0].useBootpFileName = FALSE; - ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB; - - SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,115); - SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25); - SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2); - SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0); - - /* Set the hardware address as 0 so the e-fuse value will be used */ - ibl.ethConfig[0].ethInfo.hwAddress[0] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[1] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[2] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[3] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[4] = 0; - ibl.ethConfig[0].ethInfo.hwAddress[5] = 0; - - - ibl.ethConfig[0].ethInfo.fileName[0] = 'c'; - ibl.ethConfig[0].ethInfo.fileName[1] = '6'; - ibl.ethConfig[0].ethInfo.fileName[2] = '4'; - ibl.ethConfig[0].ethInfo.fileName[3] = '5'; - ibl.ethConfig[0].ethInfo.fileName[4] = '7'; - ibl.ethConfig[0].ethInfo.fileName[5] = '-'; - ibl.ethConfig[0].ethInfo.fileName[6] = 'l'; - ibl.ethConfig[0].ethInfo.fileName[7] = 'e'; - ibl.ethConfig[0].ethInfo.fileName[8] = '.'; - ibl.ethConfig[0].ethInfo.fileName[9] = 'b'; - ibl.ethConfig[0].ethInfo.fileName[10] = 'i'; - ibl.ethConfig[0].ethInfo.fileName[11] = 'n'; - ibl.ethConfig[0].ethInfo.fileName[12] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[13] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[14] = '\0'; - - - /* Even though the entire range of DDR2 is chosen, the load will - * stop when the ftp reaches the end of the file */ - ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */ - ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */ - ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */ - - /* There is no port 1 on the 6457 Lite EVM */ - ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT; - - /* SGMII is present */ - ibl.sgmiiConfig[0].adviseAbility = 0x9801; - ibl.sgmiiConfig[0].control = 0x20; - ibl.sgmiiConfig[0].txConfig = 0x00000e23; - ibl.sgmiiConfig[0].rxConfig = 0x00081023; - ibl.sgmiiConfig[0].auxConfig = 0x0000000b; - - /* MDIO configuration */ - ibl.mdioConfig.nMdioOps = 8; - ibl.mdioConfig.mdioClkDiv = 0x26; - ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */ - - ibl.mdioConfig.mdio[0] = (1 << 30) | ( 4 << 21) | (27 << 16) | 0x0081; - ibl.mdioConfig.mdio[1] = (1 << 30) | (26 << 21) | (15 << 16) | 0x0047; - ibl.mdioConfig.mdio[2] = (1 << 30) | (26 << 21) | (14 << 16) | 0x0047; - ibl.mdioConfig.mdio[3] = (1 << 30) | ( 0 << 21) | (15 << 16) | 0x8140; - - ibl.mdioConfig.mdio[4] = (1 << 30) | ( 0 << 21) | (14 << 16) | 0x8140; - ibl.mdioConfig.mdio[5] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e; - ibl.mdioConfig.mdio[6] = (1 << 30) | ( 1 << 21) | (22 << 16) | 0x043e; - ibl.mdioConfig.mdio[7] = (1 << 30) | ( 0 << 21) | ( 1 << 16) | 0xa100; - - - /* This board has NAND. We will enable later */ - ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT; - -} - -menuitem "EVM c6455 IBL"; - -hotmenu setConfig_c6455() -{ - ibl.iblMagic = ibl_MAGIC_VALUE; - - ibl.pllConfig[ibl_MAIN_PLL].doEnable = TRUE; - ibl.pllConfig[ibl_MAIN_PLL].prediv = 1; - ibl.pllConfig[ibl_MAIN_PLL].mult = 20; - ibl.pllConfig[ibl_MAIN_PLL].postdiv = 1; - ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000; - - /* The DDR PLL. The multipliers/dividers are fixed, so are really dont cares */ - ibl.pllConfig[ibl_DDR_PLL].doEnable = TRUE; - - /* The network PLL. The multipliers/dividers are fixed */ - ibl.pllConfig[ibl_NET_PLL].doEnable = TRUE; - - /* EMIF configuration. The values are for DDR at 500 MHz */ - ibl.ddrConfig.configDdr = TRUE; - - ibl.ddrConfig.uEmif.emif3p1.sdcfg = 0x00538822; /* timing, 32bit wide */ - ibl.ddrConfig.uEmif.emif3p1.sdrfc = 0x000007a2; /* Refresh 500Mhz */ - ibl.ddrConfig.uEmif.emif3p1.sdtim1 = 0x3edb4b91; /* Timing 1 */ - ibl.ddrConfig.uEmif.emif3p1.sdtim2 = 0x00a2c722; /* Timing 2 */ - ibl.ddrConfig.uEmif.emif3p1.dmcctl = 0x00000005; /* PHY read latency for CAS 4 is 4 + 2 - 1 */ - - /* Ethernet configuration for port 0 */ - ibl.ethConfig[0].ethPriority = ibl_HIGHEST_PRIORITY; - ibl.ethConfig[0].port = 0; - - /* Bootp is disabled. The server and file name are provided here */ - ibl.ethConfig[0].doBootp = FALSE; - ibl.ethConfig[0].useBootpServerIp = FALSE; - ibl.ethConfig[0].useBootpFileName = FALSE; - ibl.ethConfig[0].bootFormat = ibl_BOOT_FORMAT_BBLOB; - - - SETIP(ibl.ethConfig[0].ethInfo.ipAddr, 158,218,100,118); - SETIP(ibl.ethConfig[0].ethInfo.serverIp, 158,218,100,25); - SETIP(ibl.ethConfig[0].ethInfo.gatewayIp, 158,218,100,2); - SETIP(ibl.ethConfig[0].ethInfo.netmask, 255,255,255,0); - - /* There is no e-fuse mac address. A value must be assigned */ - ibl.ethConfig[0].ethInfo.hwAddress[0] = 10; - ibl.ethConfig[0].ethInfo.hwAddress[1] = 224; - ibl.ethConfig[0].ethInfo.hwAddress[2] = 166; - ibl.ethConfig[0].ethInfo.hwAddress[3] = 102; - ibl.ethConfig[0].ethInfo.hwAddress[4] = 87; - ibl.ethConfig[0].ethInfo.hwAddress[5] = 25; - - - ibl.ethConfig[0].ethInfo.fileName[0] = 't'; - ibl.ethConfig[0].ethInfo.fileName[1] = 'e'; - ibl.ethConfig[0].ethInfo.fileName[2] = 's'; - ibl.ethConfig[0].ethInfo.fileName[3] = 't'; - ibl.ethConfig[0].ethInfo.fileName[4] = '.'; - ibl.ethConfig[0].ethInfo.fileName[5] = 'b'; - ibl.ethConfig[0].ethInfo.fileName[6] = 'l'; - ibl.ethConfig[0].ethInfo.fileName[7] = 'o'; - ibl.ethConfig[0].ethInfo.fileName[8] = 'b'; - ibl.ethConfig[0].ethInfo.fileName[9] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[10] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[11] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[12] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[13] = '\0'; - ibl.ethConfig[0].ethInfo.fileName[14] = '\0'; - - - /* Even though the entire range of DDR2 is chosen, the load will - * stop when the ftp reaches the end of the file */ - ibl.ethConfig[0].blob.startAddress = 0xe0000000; /* Base address of DDR2 */ - ibl.ethConfig[0].blob.sizeBytes = 0x20000000; /* All of DDR2 */ - ibl.ethConfig[0].blob.branchAddress = 0xe0000000; /* Base of DDR2 */ - - /* There is no ethernet port 1 */ - ibl.ethConfig[1].ethPriority = ibl_DEVICE_NOBOOT; - - - /* SGMII not present */ - ibl.sgmiiConfig[0].adviseAbility = 0; - ibl.sgmiiConfig[0].control = 0; - ibl.sgmiiConfig[0].txConfig = 0; - ibl.sgmiiConfig[0].rxConfig = 0; - ibl.sgmiiConfig[0].auxConfig = 0; - - ibl.sgmiiConfig[1].adviseAbility = 0; - ibl.sgmiiConfig[1].control = 0; - ibl.sgmiiConfig[1].txConfig = 0; - ibl.sgmiiConfig[1].rxConfig = 0; - ibl.sgmiiConfig[1].auxConfig = 0; - - - - /* MDIO configuration */ - ibl.mdioConfig.nMdioOps = 0; - ibl.mdioConfig.mdioClkDiv = 0x20; - ibl.mdioConfig.interDelay = 2000; /* ~2ms at 1000 MHz */ - - ibl.mdioConfig.mdio[0] = (1 << 30) | (14 << 21) | (0 << 16) | 0xd5d0; - - - /* Nand boot is disabled */ - ibl.nandConfig.nandPriority = ibl_DEVICE_NOBOOT; - -} - - -menuitem "EVM c6608 IBL"; - -hotmenu setConfig_c6608() -{ - ibl.iblMagic = ibl_MAGIC_VALUE; - - /* Main PLL: 100 MHz reference, 1GHz output */ - ibl.pllConfig[ibl_MAIN_PLL].doEnable = 1; - ibl.pllConfig[ibl_MAIN_PLL].prediv = 1; - ibl.pllConfig[ibl_MAIN_PLL].mult = 20; - ibl.pllConfig[ibl_MAIN_PLL].postdiv = 2; - ibl.pllConfig[ibl_MAIN_PLL].pllOutFreqMhz = 1000; - - /* DDR PLL: 66.66 MHz reference, 400 MHz output, for an 800MHz DDR rate */ - ibl.pllConfig[ibl_DDR_PLL].doEnable = 1; - ibl.pllConfig[ibl_DDR_PLL].prediv = 1; - ibl.pllConfig[ibl_DDR_PLL].mult = 12; - ibl.pllConfig[ibl_DDR_PLL].postdiv = 2; - ibl.pllConfig[ibl_DDR_PLL].pllOutFreqMhz = 400; - - /* Net PLL: 100 MHz reference, 1050 MHz output (followed by a built in divide by 3 to give 350 MHz to PA) */ - ibl.pllConfig[ibl_NET_PLL].doEnable = 1; - ibl.pllConfig[ibl_NET_PLL].prediv = 1; - ibl.pllConfig[ibl_NET_PLL].mult = 21; - ibl.pllConfig[ibl_NET_PLL].postdiv = 2; - ibl.pllConfig[ibl_NET_PLL].pllOutFreqMhz = 1050; - - - ibl.ddrConfig.configDdr = 1; - ibl.ddrConfig.uEmif.emif4p0.registerMask = ibl_EMIF4_ENABLE_sdRamConfig | ibl_EMIF4_ENABLE_sdRamRefreshCtl | ibl_EMIF4_ENABLE_sdRamTiming1 | ibl_EMIF4_ENABLE_sdRamTiming2 | ibl_EMIF4_ENABLE_sdRamTiming3 | ibl_EMIF4_ENABLE_ddrPhyCtl1; - - ibl.ddrConfig.uEmif.emif4p0.sdRamConfig = 0x63C452B2; - ibl.ddrConfig.uEmif.emif4p0.sdRamConfig2 = 0; - ibl.ddrConfig.uEmif.emif4p0.sdRamRefreshCtl = 0x000030D4; - ibl.ddrConfig.uEmif.emif4p0.sdRamTiming1 = 0x0AAAE51B; - ibl.ddrConfig.uEmif.emif4p0.sdRamTiming2 = 0x2A2F7FDA; - ibl.ddrConfig.uEmif.emif4p0.sdRamTiming3 = 0x057F82B8; - ibl.ddrConfig.uEmif.emif4p0.lpDdrNvmTiming = 0; - ibl.ddrConfig.uEmif.emif4p0.powerManageCtl = 0; - ibl.ddrConfig.uEmif.emif4p0.iODFTTestLogic = 0; - ibl.ddrConfig.uEmif.emif4p0.performCountCfg = 0; - ibl.ddrConfig.uEmif.emif4p0.performCountMstRegSel = 0; - ibl.ddrConfig.uEmif.emif4p0.readIdleCtl = 0; - ibl.ddrConfig.uEmif.emif4p0.sysVbusmIntEnSet = 0; - ibl.ddrConfig.uEmif.emif4p0.sdRamOutImpdedCalCfg = 0; - ibl.ddrConfig.uEmif.emif4p0.tempAlterCfg = 0; - ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl1 = 0x0010010d; - ibl.ddrConfig.uEmif.emif4p0.ddrPhyCtl2 = 0; - ibl.ddrConfig.uEmif.emif4p0.priClassSvceMap = 0; - ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce1Map = 0; - ibl.ddrConfig.uEmif.emif4p0.mstId2ClsSvce2Map = 0; - ibl.ddrConfig.uEmif.emif4p0.eccCtl = 0; - ibl.ddrConfig.uEmif.emif4p0.eccRange1 = 0; - ibl.ddrConfig.uEmif.emif4p0.eccRange2 = 0; - ibl.ddrConfig.uEmif.emif4p0.rdWrtExcThresh = 0; - - - ibl.sgmiiConfig[0].configure = 1; - ibl.sgmiiConfig[0].adviseAbility = 1; - ibl.sgmiiConfig[0].control = 1; - ibl.sgmiiConfig[0].txConfig = 0x108a1; - ibl.sgmiiConfig[0].rxConfig = 0x700621; - ibl.sgmiiConfig[0].auxConfig = 0x41; - - ibl.sgmiiConfig[1].configure = 1; - ibl.sgmiiConfig[1].adviseAbility = 1; - ibl.sgmiiConfig[1].control = 1; - ibl.sgmiiConfig[1].txConfig = 0x108a1; - ibl.sgmiiConfig[1].rxConfig = 0x700621; - ibl.sgmiiConfig[1].auxConfig = 0x41; - - ibl.mdioConfig.nMdioOps = 0; - - ibl.spiConfig.addrWidth = 0; - ibl.spiConfig.nPins = 0; - ibl.spiConfig.mode = 0; - ibl.spiConfig.csel = 0; - ibl.spiConfig.c2tdelay = 0; - ibl.spiConfig.busFreqMHz = 0; - - ibl.emifConfig[0].csSpace = 0; - ibl.emifConfig[0].busWidth = 0; - ibl.emifConfig[0].waitEnable = 0; - - ibl.emifConfig[1].csSpace = 0; - ibl.emifConfig[1].busWidth = 0; - ibl.emifConfig[1].waitEnable = 0; - - ibl.bootModes[0].bootMode = ibl_BOOT_MODE_TFTP; - ibl.bootModes[0].priority = ibl_HIGHEST_PRIORITY; - ibl.bootModes[0].port = ibl_PORT_SWITCH_ALL; - - ibl.bootModes[0].u.ethBoot.doBootp = FALSE; - ibl.bootModes[0].u.ethBoot.useBootpServerIp = FALSE; - ibl.bootModes[0].u.ethBoot.useBootpFileName = FALSE; - ibl.bootModes[0].u.ethBoot.bootFormat = ibl_BOOT_FORMAT_BBLOB; - - - SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.ipAddr, 158,218,32,118); - SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.serverIp, 158,218,32,252); - SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.gatewayIp, 158,218,32,2); - SETIP(ibl.bootModes[0].u.ethBoot.ethInfo.netmask, 255,255,255,0); - - /* Use the e-fuse value */ - ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[0] = 0; - ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[1] = 0; - ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[2] = 0; - ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[3] = 0; - ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[4] = 0; - ibl.bootModes[0].u.ethBoot.ethInfo.hwAddress[5] = 0; - - - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[0] = 't'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[1] = 'e'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[2] = 's'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[3] = 't'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[4] = '.'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[5] = 'b'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[6] = 'l'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[7] = 'o'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[8] = 'b'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[9] = '\0'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[10] = '\0'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[11] = '\0'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[12] = '\0'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[13] = '\0'; - ibl.bootModes[0].u.ethBoot.ethInfo.fileName[14] = '\0'; - - ibl.bootModes[0].u.ethBoot.blob.startAddress = 0x80000000; /* Base address of DDR2 */ - ibl.bootModes[0].u.ethBoot.blob.sizeBytes = 0x20000000; /* All of DDR2 */ - ibl.bootModes[0].u.ethBoot.blob.branchAddress = 0x80000000; /* Base of DDR2 */ - - - ibl.bootModes[1].bootMode = ibl_BOOT_MODE_NONE; - - ibl.chkSum = 0; - -} diff --git a/src/util/spiConfig/makestg2 b/src/util/spiConfig/makestg2 deleted file mode 100644 index fec9cda..0000000 --- a/src/util/spiConfig/makestg2 +++ /dev/null @@ -1,110 +0,0 @@ -#************************************************************************** -#* FILE PURPOSE: 2nd stage makefile for the spi parameter writer -#************************************************************************** -#* FILE NAME: makestg2 -#* -#* DESCRIPTION: Builds the spi parameter writer for a specific target -#* -#************************************************************************** - -DEVICES= c6455 c6472 c6474 c6474l c6457 c661x - -ifndef IBL_ROOT - IBL_ROOT=../.. -endif - -ifeq ($(ENDIAN),big) - IEXT=be -else - IEXT=le -endif - -# Add SPI definitions -SPI_CFG= $(addprefix -D,$(SPI_DEFS)) - -# The PLL object files are device specific -PLL_PATH= ../../hw/c64x/make -ifeq ($(TARGET),c661x) - PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc $(PLL_PATH)/cfgpll.$(IEXT).oc $(PLL_PATH)/cfgpll2.$(IEXT).oc - PLL_OBJS+= ../../device/c64x/make/c64x.$(IEXT).oa - PSC_OBJS= ../../hw/c64x/make/psc.$(IEXT).oc -else - PLL_OBJS= $(PLL_PATH)/pll.$(IEXT).oc -endif - -# Device specific helper utilities - - -ECODIR= $(IBL_ROOT)/util/spiConfig -ifeq ($(TARGET),c661x) - TFILES= ../../device/c64x/make/$(TARGET)util.$(IEXT).oc -endif - -MODULES= hw -CFG_MODULES= device - -CLEAN_MODULES=$(addprefix clean_,$(MODULES)) -CLEAN_MODULES+=$(addprefix clean_,$(CFG_MODULES)) - - -CSRC= spiparam.c spiUtil.c - -CDEFS+= $(SPI_CFG) - -# enable debug info in the compile -UTIL=yes - -include $(IBL_ROOT)/make/$(ARCH)/makeeco.mk - -C6X_C_DIR= $(IBL_ROOT) -C6X_C_DIR+=;$(IBL_ROOT)/hw/spi -C6X_C_DIR+=;$(IBL_ROOT)/hw/plls -C6X_C_DIR+=;$(STDINC) -C6X_C_DIR+=;$(IBL_ROOT)/cfg/$(TARGET) -C6X_C_DIR+=;$(IBL_ROOT)/device/$(TARGET) -C6X_C_DIR+=;$(IBL_ROOT)/arch/$(ARCH) -C6X_C_DIR+=;$(IBL_ROOT)/util/spiWrite -export C6X_C_DIR - - -export ARCH -export TARGET - -.PHONY: spiparam.cmd - -$(DEVICES): gen_cdefdep $(MODULES) $(CFG_MODULES) $(OBJS) spiparam.cmd - $(LD) -o spiparam_$(TARGET)_$(IEXT).out -m spiparam_$(TARGET)_$(IEXT).map spiparam.$(IEXT).oc ../spiWrite/spiUtil.$(IEXT).oc ../../hw/c64x/make/spi.$(IEXT).oc ../../hw/c64x/make/spiutil.$(IEXT).oc $(PLL_OBJS) $(PSC_OBJS) $(TFILES) spiparam.cmd $(RTLIBS) - -$(MODULES): - @echo making $@ - make -C $(IBL_ROOT)/$@/$(ARCH)/make $@ - -$(CFG_MODULES): - @echo making $@ - make -C $(IBL_ROOT)/$@/$(ARCH)/make CDEFS='$(MAINDEFS)' $@ - - -clean2: $(CLEAN_MODULES) - @rm -f $(OBJS) - @rm -f $(subst .c,.dc,$(CSRC)) - - -$(CLEAN_MODULES): - @echo cleaning $(subst clean_, ,$@) - make -C $(IBL_ROOT)/$(subst clean_,,$@)/$(ARCH)/make clean - - -$(OBJS): cdefdep - - -gen_cdefdep: - @echo Checking command line dependencies - @echo $(TARGET) $(ARCH) > cdefdep.tmp - @sh -c 'if diff -q cdefdep.tmp cdefdep ; then echo same ; else $(CP) cdefdep.tmp cdefdep ; fi ' - - - - - - - diff --git a/src/util/spiConfig/spiparam.c b/src/util/spiConfig/spiparam.c deleted file mode 100644 index 41bbe7d..0000000 --- a/src/util/spiConfig/spiparam.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/************************************************************************************* - * FILE PURPOSE: Write the ibl configuration table to the spi eeprom - ************************************************************************************* - * @file spiparam.c - * - * @brief - * Creates the ibl configuration table and writes to the spi - * - *************************************************************************************/ - -#include "types.h" -#include "ibl.h" -#include "spi_api.h" -#include "pllapi.h" -#include "iblcfg.h" -#include "target.h" -#include "string.h" -#include "spiWutil.h" -#include -#include - -ibl_t ibl; - -unsigned int configAddress = 0; -unsigned int spiBlockSize = 256; - -#define MAX_SPI_BLOCK_SIZE 2048 -uint8 scratch[MAX_SPI_BLOCK_SIZE]; - -spiConfig_t cfg = { - - 0, /* port */ - SPI_MODE, /* mode */ - SPI_ADDR_WIDTH, /* address width */ - SPI_NPIN, /* number of pins */ - SPI_CSEL, /* csel */ - SPI_CLKDIV, /* clock divider */ - SPI_C2TDEL /* ct2delay */ - -}; - -/** - * @brief - * Ones complement addition - */ -inline uint16 onesComplementAdd (uint16 value1, uint16 value2) -{ - uint32 result; - - result = (uint32)value1 + (uint32)value2; - - result = (result >> 16) + (result & 0xFFFF); /* add in carry */ - result += (result >> 16); /* maybe one more */ - return ((uint16)result); -} - - -/** - * @brief - * Ones complement checksum computation - */ -uint16 onesComplementChksum (uint16 * restrict p_data, uint16 len) -{ - uint16 chksum = 0; - - while (len > 0) - { - chksum = onesComplementAdd(chksum, *p_data); - p_data++; - len--; - } - return (chksum); -} - - -void main (void) -{ - int result; - uint16 chk; - int nblocks; - uint32 addr; - uint32 *iblUi32; - - volatile Int32 i; - - if (spiBlockSize > MAX_SPI_BLOCK_SIZE) { - printf ("Error: spi block size (%d) greater then this program can handle (%d).\n", spiBlockSize, MAX_SPI_BLOCK_SIZE); - printf (" Change the definition of MAX_SPI_BLOCK_SIZE and recompile\n"); - return; - } - - if (configAddress == 0) { - printf ("Error: The global variable config address must be setup prior to running this program\n"); - printf (" This is the address in the I2C eeprom where the parameters live. On configurations\n"); - printf (" which support both big and little endian it is possible to configure the IBL to\n"); - printf (" usage a different configuration table for each endian, so this program must be run\n"); - printf (" twice. The value 0 is invalid for configAddress\n"); - return; - } - - printf ("Run the GEL for for the device to be configured, press return to program the I2C\n"); - getchar (); - - /* Program the main system PLL */ - hwPllSetPll (MAIN_PLL, - ibl.pllConfig[ibl_MAIN_PLL].prediv, /* Pre-divider */ - ibl.pllConfig[ibl_MAIN_PLL].mult, /* Multiplier */ - ibl.pllConfig[ibl_MAIN_PLL].postdiv); /* Post-divider */ - - - result = hwSpiConfig (&cfg); - if (result != 0) { - printf ("hwSpiConfig returned error %d\n", result); - return; - } - - - /* Compute the checksum over the ibl configuration structure */ - ibl.chkSum = 0; - chk = onesComplementChksum ((uint16 *)&ibl, sizeof(ibl_t)/sizeof(uint16)); - if (ibl.chkSum != 0xffff) - ibl.chkSum = ~chk; - - - - /* Write the configuration table out one block at a time */ - nblocks = (sizeof(ibl_t) + spiBlockSize - 1) / spiBlockSize; - iblUi32 = (uint32 *)&ibl; - - for (i = 0, addr = configAddress; i < nblocks; i++, addr += spiBlockSize) { - - result = writeBlock (&cfg, addr, &iblUi32[(i * spiBlockSize) >> 2], spiBlockSize, scratch); - if (result != 0) { - printf ("writeBlock returned error code %d, exiting\n", result); - return; - } - } - - - printf ("SPI table write complete\n"); - -} - - - - - - - - - - - diff --git a/src/util/spiConfig/spiparam.cmd b/src/util/spiConfig/spiparam.cmd deleted file mode 100644 index fe433c7..0000000 --- a/src/util/spiConfig/spiparam.cmd +++ /dev/null @@ -1,38 +0,0 @@ -/************************************************************************* - * @file i2cparam_c6472.cmd - * - * @brief Places the i2c parameter writer program into memory - * - *************************************************************************/ - -/* Object files included in linker invokation */ - --c --a --stack 0x400 - -MEMORY -{ - STACK : origin = 0x810000 length = 0x0400 - TEXT : origin = 0x810400 length = 0x9000 - DATA : origin = 0x819400 length = 0x2000 - SYSMEM : origin = 0x829400 length = 0x0800 -} - -SECTIONS -{ - .stack > STACK - - .text > TEXT - .const > TEXT - .switch > TEXT - .cinit > TEXT - - .far > DATA - .bss > DATA - .data > DATA - - .sysmem > SYSMEM - -} - \ No newline at end of file -- 2.39.2