summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: c59cd6d)
raw | patch | inline | side by side (parent: c59cd6d)
| author | Hao Zhang <hzhang@ti.com> | |
| Wed, 16 Jan 2019 16:40:38 +0000 (11:40 -0500) | ||
| committer | Hao Zhang <hzhang@ti.com> | |
| Wed, 16 Jan 2019 16:40:38 +0000 (11:40 -0500) |
Signed-off-by: Hao Zhang <hzhang@ti.com>
75 files changed:
diff --git a/IOLINK.h b/IOLINK.h
--- /dev/null
+++ b/IOLINK.h
@@ -0,0 +1,280 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/** ============================================================================
+ * @file IOLINK.h
+ *
+ * @brief IOLINK driver interface
+ *
+ * The IOLINK header file should be included in an application as follows:
+ * @code
+ * #include <ti/drv/iolink/IOLINK.h>
+ * @endcode
+ *
+ * ============================================================================
+ */
+
+#ifndef IOLINK_H
+#define IOLINK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/** ===========================================================================
+ *
+ * @defgroup IOLINK_API IOLINK API
+ * @ingroup IOLINK_API
+ *
+ * ============================================================================
+ */
+/**
+@defgroup IOLINK_DATASTRUCT IOLINK Data Structures
+@ingroup IOLINK_API
+*/
+/**
+@defgroup IOLINK_FUNCTION IOLINK Functions
+@ingroup IOLINK_API
+*/
+/**
+@defgroup IOLINK_ENUM IOLINK Enumerated Data Types
+@ingroup IOLINK_API
+*/
+
+/** ===========================================================================
+ * @addtogroup IOLINK_ENUM
+ @{
+ * ============================================================================
+ */
+
+/** ---------------------------------------------------------------------------
+ * @brief This enumerator defines the possible interrupt types. Each source
+ * interrupt is either an active high level or active high pulse.
+ *
+ * ----------------------------------------------------------------------------
+ */
+typedef int32_t IOLINK_STATUS;
+#define IOLINK_STATUS_SUCCESS ((int32_t)(0)) /** Successful status code returned by IOLINK APIs */
+#define IOLINK_STATUS_ERROR ((int32_t)(-1)) /** Error status code returned by IOLINK APIs */
+
+/* @} */
+
+/**
+ * \addtogroup IOLINK_DATASTRUCT
+ * @{
+ */
+
+/*!
+ * @brief Basic IOLINK Parameters
+ */
+typedef struct IOLINK_Params_s
+{
+ /*! Delay in Tbit between the end of the stop bit of last UART frame
+ * being received and the beginning of the start bit of the
+ * first UART frame being sent. */
+ uint32_t tA;
+
+} IOLINK_Params;
+
+
+/*!
+ * @brief A handle that is returned from a IOLINK_open() call.
+ */
+typedef struct IOLINK_Config_s *IOLINK_Handle;
+
+/*!
+ * @brief A function pointer to a driver specific implementation of
+ * IOLINK_init().
+ */
+typedef void (*IOLINK_InitFxn)(IOLINK_Handle handle);
+
+/*!
+ * @brief A function pointer to a driver specific implementation of
+ * IOLINK_OpenFxn().
+ */
+typedef IOLINK_Handle (*IOLINK_OpenFxn)(IOLINK_Handle handle,
+ const IOLINK_Params *params);
+
+/*!
+ * @brief A function pointer to a driver specific implementation of
+ * IOLINK_CloseFxn().
+ */
+typedef IOLINK_STATUS (*IOLINK_CloseFxn) (IOLINK_Handle handle);
+
+/*!
+ * @brief A function pointer to a driver specific implementation of
+ * IOLINK_ControlFxn().
+ */
+typedef IOLINK_STATUS (*IOLINK_ControlFxn)(IOLINK_Handle handle,
+ uint32_t cmd,
+ void *arg);
+
+/*!
+ * @brief The definition of a IOLINK function table that contains the
+ * required set of functions to control a specific IOLINK driver
+ * implementation.
+ */
+typedef struct IOLINK_FxnTable_s {
+ /*! Function to initialize the given data object */
+ IOLINK_InitFxn initFxn;
+
+ /*! Function to open the specified instance */
+ IOLINK_OpenFxn openFxn;
+
+ /*! Function to close the specified instance */
+ IOLINK_CloseFxn closeFxn;
+
+ /*! Function to implementation specific control function */
+ IOLINK_ControlFxn controlFxn;
+
+} IOLINK_FxnTable;
+
+/*!
+ * @brief IOLINK Global configuration
+ *
+ * The IOLINK_Config structure contains a set of pointers used to characterize
+ * the IOLINK driver implementation.
+ *
+ * This structure needs to be defined before calling IOLINK_init() and it must
+ * not be changed thereafter.
+ *
+ * @sa IOLINK_init()
+ */
+typedef struct IOLINK_Config_s {
+ /*! Pointer to a table of driver-specific implementations of IOLINK APIs */
+ IOLINK_FxnTable const *fxnTablePtr;
+
+ /*! Pointer to a driver specific data object */
+ void *object;
+
+ /*! Pointer to a driver specific SW or HW IP attributes structure */
+ void const *ipAttrs;
+} IOLINK_Config;
+
+#define IOLINK_MAX_CONFIG_CNT (2U)
+typedef IOLINK_Config IOLINK_config_list[IOLINK_MAX_CONFIG_CNT];
+
+
+/* @} */
+
+
+/**
+ * \addtogroup IOLINK_FUNCTION
+ * @{
+ */
+
+/*!
+ * @brief Function to initializes the IOLINK module
+ *
+ * @pre The IOLINK_config structure must exist and be persistent before this
+ * function can be called. This function must also be called before
+ * any other IOLINK driver APIs.
+ *
+ * @return none.
+ */
+extern void IOLINK_init(void);
+
+/*!
+ * @brief Function to initialize a given IOLINK instance specified by the
+ * particular index value. The parameter specifies which mode the IOLINK
+ * will operate.
+ *
+ * @pre IOLINK controller has been initialized
+ *
+ * @param index Logical instance number for the IOLINK instance indexed
+ * into the IOLINK_config table
+ *
+ * @param params Pointer to an parameter block, if NULL it will use
+ * default values. All the fields in this structure are
+ * RO (read-only).
+ *
+ * @return A IOLINK_Handle on success or a NULL on an error or if it has been
+ * opened already.
+ *
+ * @sa IOLINK_init()
+ * @sa IOLINK_close()
+ */
+extern IOLINK_Handle IOLINK_open(uint32_t index, IOLINK_Params *params);
+
+/*!
+ * @brief Function to close an IOLINK instance specified by the IOLINK handle
+ *
+ * @pre IOLINK_open() had to be called first.
+ *
+ * @param handle A IOLINK_Handle returned from IOLINK_open
+ *
+ * @return IOLINK_STATUS_SUCCESS on success or IOLINK_STATUS_ERROR on error.
+ *
+ * @sa IOLINK_open()
+ */
+extern IOLINK_STATUS IOLINK_close(IOLINK_Handle handle);
+
+/*!
+ * @brief Function performs specific controls on a given IOLINK_Handle.
+ *
+ * @pre IOLINK_open() has to be called first.
+ *
+ * @param handle A IOLINK handle returned from IOLINK_open()
+ *
+ * @param cmd A control command value defined by the driver specific
+ * implementation
+ *
+ * @param arg An optional R/W (read/write) argument that is
+ * accompanied with cmd
+ *
+ * @return IOLINK_STATUS_SUCCESS on success or IOLINK_STATUS_ERROR on error.
+ *
+ * @sa IOLINK_open()
+ */
+extern IOLINK_STATUS IOLINK_control(IOLINK_Handle handle, uint32_t cmd, void *arg);
+
+/*!
+ * @brief Function to initialize the IOLINK_Params struct to its defaults
+ *
+ * @param params An pointer to IOLINK_Params structure for
+ * initialization
+ *
+ * @return none
+ */
+extern void IOLINK_Params_init(IOLINK_Params *params);
+
+/* @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _IOLINK_H_ */
diff --git a/IOLINKver.h b/IOLINKver.h
--- /dev/null
+++ b/IOLINKver.h
@@ -0,0 +1,68 @@
+#ifndef _IOLINKVER_H
+#define _IOLINKVER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ============================================================= */
+/**
+ * @file IOLINKver.h
+ *
+ * path ti/drv/iolink/IOLINKver.h
+ *
+ * @brief iolink Driver Version Definitions
+ *
+ * ============================================================
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @brief This is the iolink Driver Version. Versions numbers are encoded in the following
+ * format:
+ * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
+ */
+#define IOLINK_DRV_VERSION_ID (0x01000000)
+
+/**
+ * @brief This is the version string which describes the IOLINK driver along with the
+ * date and build information.
+ */
+#define IOLINK_DRV_VERSION_STR "iolink Driver Revision: 01.00.00.00"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _IOLINKVER_H */
diff --git a/IOLINKver.h.xdt b/IOLINKver.h.xdt
--- /dev/null
+++ b/IOLINKver.h.xdt
@@ -0,0 +1,100 @@
+%%{\r
+/*!\r
+ * This template implements the IOLINKver.h\r
+ */ \r
+ /* Versioning */\r
+ var ver = this;\r
+ var ver1 = [00,00,00,00];\r
+ var ver2 = [00,00,00,00];\r
+ \r
+ for each(i=0;i<ver.length;i++)\r
+ {\r
+ if(String(ver[i]).length < 2)\r
+ {\r
+ ver1[i]="0"+ver[i];\r
+ }\r
+ else\r
+ {\r
+ ver1[i] = ver[i];\r
+ }\r
+ \r
+ ver2[i] = Number(ver[i]).toString(16).toUpperCase();\r
+ \r
+ if(String(ver2[i]).length < 2)\r
+ {\r
+ ver2[i]="0"+ver2[i];\r
+ }\r
+ }\r
+ \r
+ var versionStr = "\""+"iolink Driver Revision: "+ver1[0]+"."+ver1[1]+"."+ver1[2]+"."+ver1[3]+"\"";\r
+ var versionID = "(0x"+ver2[0]+ver2[1]+ver2[2]+ver2[3]+")";\r
+\r
+%%}\r
+#ifndef _IOLINKVER_H\r
+#define _IOLINKVER_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* ============================================================= */\r
+/**\r
+ * @file IOLINKver.h\r
+ *\r
+ * path ti/drv/iolink/IOLINKver.h\r
+ *\r
+ * @brief iolink Driver Version Definitions\r
+ *\r
+ * ============================================================\r
+ * Copyright (c) Texas Instruments Incorporated 2009-2017\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the \r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+/**\r
+ * @brief This is the iolink Driver Version. Versions numbers are encoded in the following \r
+ * format:\r
+ * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)\r
+ */\r
+#define IOLINK_DRV_VERSION_ID `versionID`\r
+\r
+/**\r
+ * @brief This is the version string which describes the IOLINK driver along with the\r
+ * date and build information.\r
+ */\r
+#define IOLINK_DRV_VERSION_STR `versionStr`\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+ \r
+\r
+#endif /* _IOLINKVER_H */\r
diff --git a/Settings.xdc.xdt b/Settings.xdc.xdt
--- /dev/null
+++ b/Settings.xdc.xdt
@@ -0,0 +1,60 @@
+\r
+%%{\r
+/*!\r
+ * This template implements the Settings.xdc\r
+ */ \r
+ /* Versioning */\r
+ var ver = this;\r
+ for each(i=0;i<ver.length;i++)\r
+ {\r
+ if(String(ver[i]).length < 2)\r
+ {\r
+ ver[i]="0"+ver[i];\r
+ }\r
+ }\r
+ \r
+ var packageVersion = "\""+ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3]+"\"";\r
+\r
+%%}\r
+\r
+module Settings\r
+{\r
+ config string iolinkVersionString = `packageVersion`;\r
+ /*! This variable is to control the SoC type selection.\r
+ * By default this variable is set to NULL.\r
+ * \r
+ * To use LLD for the selected device, add the following lines to config\r
+ * file and set the deviceType correctly:\r
+ *\r
+ * var iolinkSettings = xdc.useModule ('ti.drv.iolink.Settings');\r
+ * iolinkSettings.socType = "am437x";\r
+ * \r
+ */\r
+ metaonly config string socType = "";\r
+\r
+ /*! This flag is used to indicate whether or not the benchmarking code\r
+ * (defined in the profilingHooks class) will be used in the project.\r
+ * Note that a separate library has been compiled and will be used\r
+ * ($NAME).profiling.a($SUFFIX). This is set in the *.cfg file.\r
+ */\r
+ config Bool enableProfiling = false;\r
+ \r
+ /*! This variable is to control the device library type selection.\r
+ * By default this variable is set to release.\r
+ * \r
+ * To use CSL to use the debug/release library, add the following lines to config\r
+ * file and set the library profile accordingly:\r
+ * \r
+ * var Uart Settings = xdc.useModule ('ti.Uart.Settings');\r
+ * UartSettings.libProfile = "debug";\r
+ * \r
+ */\r
+ metaonly config string libProfile = "release"; \r
+ \r
+ /*! This flag is used to indicate whether to use the AM437x ICSS0\r
+ * IOLINK LLD library.\r
+ */\r
+ config Bool fwIcss0 = false;\r
+\r
+}\r
+\r
diff --git a/build/buildlib.xs b/build/buildlib.xs
--- /dev/null
+++ b/build/buildlib.xs
@@ -0,0 +1,646 @@
+/******************************************************************************\r
+ * FILE PURPOSE: Build Library Utilities\r
+ ******************************************************************************\r
+ * FILE NAME: buildlib.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains common routines that are used by the various IOLINK\r
+ * components.\r
+ *\r
+ * Copyright (C) 2018, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : listAllFiles\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * Utility function which lists all files with a specific extension \r
+ * present in a directory and any directory inside it.\r
+ **************************************************************************/\r
+function listAllFiles(ext, dir, recurse)\r
+{ \r
+ var srcFile = [];\r
+ var d;\r
+\r
+ /* If recurse parameter is not specified we default to recursive search. */\r
+ if (recurse == null)\r
+ recurse = true;\r
+\r
+ if (dir == undefined) \r
+ d = ".";\r
+ else \r
+ d = dir;\r
+\r
+ /* Get access to the current directory. */\r
+ var file = new java.io.File(d);\r
+\r
+ /* Check if the file exists and it is a directory. */\r
+ if (file.exists() && file.isDirectory()) \r
+ {\r
+ /* Get a list of all files in the specific directory. */\r
+ var fileList = file.listFiles();\r
+ for (var i = 0; i < fileList.length; i++) \r
+ {\r
+ /* Dont add the generated directory 'package' and any of its files \r
+ * to the list here. */\r
+ if (fileList[i].getName().matches("package") == false)\r
+ {\r
+ /* Check if the detected file is a directory */\r
+ if (fileList[i].isDirectory())\r
+ {\r
+ /* We will recurse into the subdirectory only if required to do so. */\r
+ if (recurse == true)\r
+ {\r
+ /* Generate the directory Name in which we will recurse. */ \r
+ var directoryName = d + "/" + fileList[i].getName();\r
+\r
+ /* Get a list of all files in this directory */\r
+ var fileListing = listAllFiles (ext, directoryName, recurse);\r
+ if (fileListing != null)\r
+ {\r
+ /* Return a list of all file names in the directory. */\r
+ for (var j = 0 ; j < fileListing.length; j++) \r
+ srcFile[srcFile.length++] = fileListing[j];\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* This was a file. Check if the file name matches the extension */\r
+ if (fileList[i].getName().endsWith(ext) == true)\r
+ srcFile[srcFile.length++] = d + "/" + fileList[i].getName();\r
+ }\r
+ }\r
+ }\r
+\r
+ return srcFile;\r
+ }\r
+ return null;\r
+}\r
+\r
+\r
+function createMake(makefile)\r
+{\r
+ /* Create the main make file */\r
+ var fileModule = xdc.module('xdc.services.io.File');\r
+ if(makefile==undefined)\r
+ {\r
+ try{\r
+ makefile = fileModule.open("makefile", "w");\r
+ } catch (ex)\r
+ {\r
+ print("makefile cannot be written to. Please check Writing Permissions.");\r
+ java.lang.System.exit(1);\r
+ } \r
+ \r
+ Pkg.makePrologue += "\ninclude makefile\n"; \r
+ \r
+ Pkg.makeEpilogue += "\nclean::\n\t-$(RM) makefile\n";\r
+ makefile.writeLine("#*******************************************************************************");\r
+ makefile.writeLine("#* FILE PURPOSE: Top level makefile for Creating Component Libraries");\r
+ makefile.writeLine("#*******************************************************************************");\r
+ makefile.writeLine("#* FILE NAME: makefile");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("#* DESCRIPTION: Defines Compiler tools paths, libraries , Build Options ");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("#*******************************************************************************");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("# (Mandatory) Specify where various tools are installed.");\r
+\r
+ var file = xdc.module('xdc.services.io.File');\r
+ \r
+ \r
+ makefile.writeLine("\n# Output for prebuilt generated libraries");\r
+ makefile.writeLine("export LIBDIR ?= ./lib");\r
+ /* use sectti.exe from path */\r
+ makefile.writeLine("export SECTTI ?= sectti");\r
+\r
+ /* Create INCDIR from XDCPATH */\r
+ \r
+ /* copy the environment array from the current environment */\r
+ var env = java.lang.System.getenv();\r
+ var getxdcpath=String(java.lang.System.getenv("XDCPATH"));\r
+ getxdcpath= getxdcpath.replace(/\\/g,"/");\r
+ var keys = env.keySet().toArray();\r
+ var key;\r
+ var stat={};\r
+ var env_j=[];\r
+ var listxdcpath = new Array();\r
+ for (var i = 0; i < keys.length; i++) {\r
+ key = String(keys[i]);\r
+ if((key.match("INSTALL_PATH")) || (key.match("INSTALLDIR")))\r
+ {\r
+ var keyPath=String(env.get(key));\r
+ keyPath=keyPath.replace(/\\/g,"/");\r
+ var file = xdc.module('xdc.services.io.File');\r
+ keyPath=file.getDOSPath(keyPath);\r
+ if(getxdcpath.toString().match(keyPath))\r
+ {\r
+ listxdcpath.push({keyname: key,keypath: keyPath});\r
+ while(getxdcpath.toString().match(keyPath))\r
+ {\r
+ getxdcpath=getxdcpath.toString().replace(keyPath,"$("+key+")");\r
+ }\r
+ }\r
+ }\r
+ \r
+ }\r
+ var pkgroot="..";\r
+ for (var i = Pkg.name.split('.').length; i > 1; i--) {\r
+ pkgroot+="/..";\r
+ }\r
+ \r
+ makefile.writeLine("\n# ROOT Directory"); \r
+ makefile.writeLine("export ROOTDIR := "+pkgroot);\r
+ \r
+ makefile.writeLine("\n# INCLUDE Directory");\r
+ makefile.writeLine("export INCDIR := "+getxdcpath+";$(ROOTDIR)"); \r
+ \r
+ makefile.writeLine("\n# Common Macros used in make"); \r
+ makefile.writeLine("\nifndef RM"); \r
+ makefile.writeLine("export RM = rm -f");\r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nifndef CP"); \r
+ makefile.writeLine("export CP = cp -p"); \r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nexport MKDIR = mkdir -p");\r
+ \r
+ makefile.writeLine("\nifndef RMDIR"); \r
+ makefile.writeLine("export RMDIR = rm -rf");\r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nifndef SED"); \r
+ makefile.writeLine("export SED = sed"); \r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nifndef MAKE"); \r
+ makefile.writeLine("export MAKE = make"); \r
+ makefile.writeLine("endif"); \r
+\r
+ makefile.writeLine("\n# PHONY Targets"); \r
+ makefile.writeLine(".PHONY: all clean cleanall "); \r
+ \r
+ makefile.writeLine("\n# FORCE Targets"); \r
+ makefile.writeLine("FORCE: "); \r
+ \r
+ makefile.writeLine("\n# all rule"); \r
+ makefile.writeLine("all: .executables"); \r
+ makefile.writeLine(".executables: .libraries");\r
+ makefile.writeLine(".libraries:");\r
+ \r
+ makefile.writeLine("\n# Clean Rule"); \r
+ makefile.writeLine("clean:: clean_package"); \r
+ makefile.writeLine("# Clean Top Level Object Directory "); \r
+ makefile.writeLine("clean_package :\n\t$(RMDIR) $(LIBDIR)/*/"); \r
+ makefile.writeLine("\t$(RMDIR) package/cfg"); \r
+ }\r
+ else\r
+ {\r
+ try{\r
+ makefile = fileModule.open("makefile", "a");\r
+ } catch (ex)\r
+ {\r
+ print("makefile cannot be written to. Please check Writing Permissions.");\r
+ java.lang.System.exit(1);\r
+ } \r
+ \r
+ }\r
+\r
+ return makefile;\r
+}\r
+\r
+function createLibMake(device, objExtDir, makelibname,targetname, objectPath, useProfiling)\r
+{\r
+ var tooldir;\r
+ var cmdprefix;\r
+ var targetDir;\r
+ var stringname=String(targetname).replace("(xdc.bld.ITarget.Module)","");\r
+\r
+ var benchSuffix = "";\r
+\r
+ if (useProfiling == true) {\r
+ benchSuffix = "_bench";\r
+ }\r
+\r
+ switch(stringname)\r
+ {\r
+ case String(C66LE):\r
+ tooldir="C6X_GEN_INSTALL_PATH";\r
+ cmdprefix="";\r
+ targetDir="c66/release";\r
+ targetname=C66LE;\r
+ break;\r
+ case String(C66BE):\r
+ tooldir="C6X_GEN_INSTALL_PATH";\r
+ cmdprefix="";\r
+ targetDir="c66";\r
+ targetname=C66BE;\r
+ break;\r
+ case String(C674LE):\r
+ tooldir="C6X_GEN_INSTALL_PATH";\r
+ cmdprefix="";\r
+ targetDir="c674/release";\r
+ targetname=C674LE;\r
+ break;\r
+ case String(A15LE):\r
+ tooldir="TOOLCHAIN_PATH_A15"; \r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="a15/release";\r
+ targetname=A15LE;\r
+ break;\r
+ case String(A9LE):\r
+ tooldir="TOOLCHAIN_PATH_A9";\r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="a9/release";\r
+ targetname=A9LE;\r
+ break;\r
+ case String(ARM9LE):\r
+ tooldir="TOOLCHAIN_PATH_ARM9";\r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="arm9/release";\r
+ targetname=ARM9LE;\r
+ break;\r
+ case String(A8LE):\r
+ tooldir="TOOLCHAIN_PATH_A8";\r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="a8/release";\r
+ targetname=A8LE;\r
+ break;\r
+ case String(M4LE):\r
+ tooldir="TOOLCHAIN_PATH_M4";\r
+ cmdprefix="";\r
+ targetDir="m4/release";\r
+ targetname=M4LE;\r
+ break;\r
+ }\r
+ \r
+ var fileModule = xdc.module('xdc.services.io.File');\r
+ try{\r
+ var dstFile = new java.io.File(makelibname);\r
+ dstFile.getParentFile().mkdirs(); \r
+ libmakefile = fileModule.open(makelibname, "w");\r
+ /* Add to Archive list */\r
+ } catch (ex)\r
+ {\r
+ print(makelibname+" cannot be written to. Please check Writing Permissions.");\r
+ java.lang.System.exit(1);\r
+ } \r
+ libmakefile.writeLine("#*******************************************************************************");\r
+ libmakefile.writeLine("#* FILE PURPOSE: Lower level makefile for Creating Component Libraries");\r
+ libmakefile.writeLine("#*******************************************************************************");\r
+ libmakefile.writeLine("#* FILE NAME: "+makelibname);\r
+ libmakefile.writeLine("#*");\r
+ libmakefile.writeLine("#* DESCRIPTION: Defines Source Files, Compilers flags and build rules");\r
+ libmakefile.writeLine("#*");\r
+ libmakefile.writeLine("#*");\r
+ libmakefile.writeLine("#*******************************************************************************");\r
+ libmakefile.writeLine("#");\r
+ libmakefile.writeLine("");\r
+ libmakefile.writeLine("#");\r
+ libmakefile.writeLine("# Macro definitions referenced below");\r
+ libmakefile.writeLine("#");\r
+ libmakefile.writeLine("empty =");\r
+ libmakefile.writeLine("space =$(empty) $(empty)");\r
+ \r
+ if ((targetname.name == "A15F") || (targetname.name == "A9F") || (targetname.name == "A8F"))\r
+ {\r
+ \r
+ if(stringname.match("gnu.targets"))\r
+ {\r
+ libmakefile.writeLine("CC = $("+tooldir+")/bin/$("+cmdprefix+")gcc");\r
+ libmakefile.writeLine("AC = $("+tooldir+")/bin/$("+cmdprefix+")as"); \r
+ libmakefile.writeLine("ARIN = $("+tooldir+")/bin/$("+cmdprefix+")ar"); \r
+ libmakefile.writeLine("LD = $("+tooldir+")/bin/$("+cmdprefix+")gcc"); \r
+ }\r
+ else\r
+ {\r
+ print("Error: Non-GNU targets are not currently supported ");\r
+ java.lang.System.exit(1);\r
+\r
+ }\r
+ \r
+ libmakefile.writeLine("INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\\$(space),$(INCDIR)))) -I$("+tooldir+")/include");\r
+ libmakefile.writeLine("OBJEXT = o"+targetname.suffix); \r
+ libmakefile.writeLine("AOBJEXT = s"+targetname.suffix); \r
+ if (useProfiling == true){\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts+" -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM");\r
+ }else{\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts);\r
+ }\r
+ libmakefile.writeLine("ASFLAGS_INTERNAL = " +targetname.asmOpts.prefix+" "+targetname.asm.opts);\r
+ libmakefile.writeLine("ARFLAGS_INTERNAL = " +targetname.ar.opts);\r
+ libmakefile.writeLine("LNKFLAGS_INTERNAL = " +targetname.lnk.opts);\r
+ libmakefile.writeLine("INTERNALDEFS = -MD -MF $@.dep");\r
+ libmakefile.writeLine("INTERNALLINKDEFS = -o $@ -m $@.map"); /* TBD */\r
+ libmakefile.writeLine("OBJDIR = ./obj/obj_" +targetname.suffix +"/" + device.toString() + "/" + targetDir +"/obj" + "/" + objExtDir + benchSuffix); \r
+ \r
+ }\r
+ else\r
+ {\r
+ \r
+ if(stringname.match("ti.targets"))\r
+ {\r
+\r
+ var rtslibtemp = targetname.lnkOpts.suffix.toString().split("/");\r
+ var rtslib;\r
+ for(n=0;n<rtslibtemp.length;n++)\r
+ {\r
+ if(rtslibtemp[n].match(".lib"))\r
+ { \r
+ rtslib=rtslibtemp[n];\r
+ }\r
+ }\r
+\r
+ libmakefile.writeLine("CC = $("+tooldir+")/bin/"+targetname.cc.cmd);\r
+ libmakefile.writeLine("AC = $("+tooldir+")/bin/"+targetname.asm.cmd); \r
+ libmakefile.writeLine("ARIN = $("+tooldir+")/bin/"+targetname.ar.cmd); \r
+ libmakefile.writeLine("LD = $("+tooldir+")/bin/"+targetname.lnk.cmd); \r
+ libmakefile.writeLine("RTSLIB = -l $("+tooldir+")/lib/"+rtslib); \r
+ }\r
+ else\r
+ {\r
+ print("Error: Non-TI targets are not currently supported ");\r
+ java.lang.System.exit(1);\r
+\r
+ }\r
+ \r
+ libmakefile.writeLine("INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\\$(space),$(INCDIR)))) -I$("+tooldir+")/include");\r
+ libmakefile.writeLine("OBJEXT = o"+targetname.suffix); \r
+ libmakefile.writeLine("AOBJEXT = s"+targetname.suffix); \r
+ if (useProfiling == true){\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts+" --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM");\r
+ }else{\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts);\r
+ }\r
+ libmakefile.writeLine("ASFLAGS_INTERNAL = " +targetname.asmOpts.prefix+" "+targetname.asm.opts);\r
+ libmakefile.writeLine("ARFLAGS_INTERNAL = " +targetname.ar.opts);\r
+ libmakefile.writeLine("LNKFLAGS_INTERNAL = " +targetname.lnk.opts);\r
+ /* libmakefile.writeLine("INTERNALDEFS = -D"+stringname.replace(/\./g,"_")+" -Dxdc_target_types__=ti/targets/std.h -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep");*/\r
+ libmakefile.writeLine("INTERNALDEFS = -D"+stringname.replace(/\./g,"_")+" -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep");\r
+ libmakefile.writeLine("INTERNALLINKDEFS = -o $@ -m $@.map");\r
+ libmakefile.writeLine("OBJDIR = ./obj/obj_" +targetname.suffix +"/" + device.toString() + "/" + targetDir +"/obj" + "/" + objExtDir + benchSuffix); \r
+ }\r
+ \r
+ return libmakefile;\r
+\r
+}\r
+\r
+function makeAddObjects(srcString, makefilename, srcfiles, flags,fileExt, targetName, objDir)\r
+{\r
+ var sourcestring = (srcString + fileExt).toString().toUpperCase();\r
+ var compileflagstring = sourcestring + "FLAGS";\r
+ var objectliststring = sourcestring + "OBJS";\r
+ /* List all the source files */\r
+ makefilename.writeLine("\n#List the "+srcString+" Files"); \r
+ makefilename.writeLine(sourcestring + "= \\");\r
+ for(var i=0;i<srcfiles.length-1;i++)\r
+ {\r
+ makefilename.writeLine(" "+srcfiles[i]+"\\");\r
+ }\r
+ makefilename.writeLine(" "+srcfiles[i]+"\n");\r
+ \r
+ /* Flags for the source files */\r
+ makefilename.writeLine("# FLAGS for the "+srcString+" Files"); \r
+ var compileflags="";\r
+ if(fileExt == "asm" && flags.aopts != undefined)\r
+ {\r
+ compileflags+=" "+flags.aopts;\r
+ }\r
+ else if((fileExt == "c" || fileExt == "sa")&& flags.copts != undefined)\r
+ {\r
+ compileflags+=" "+flags.copts;\r
+ } \r
+\r
+ if(flags.incs != undefined)\r
+ {\r
+ compileflags+=" "+flags.incs;\r
+ }\r
+\r
+\r
+ makefilename.writeLine(compileflagstring+" = "+compileflags +" \n"); \r
+ makefilename.writeLine("# Make Rule for the "+srcString+" Files"); \r
+ \r
+ makefilename.writeLine(objectliststring +" = $(patsubst %."+fileExt+", "+objDir+"/%.$(OBJEXT), $(" + sourcestring + "))"); \r
+ makefilename.writeLine("\n$("+objectliststring+"): "+objDir+"/%.$(OBJEXT): %."+fileExt); \r
+ if(fileExt == "c")\r
+ { \r
+ makefilename.writeLine("\t-@echo cl"+targetName.suffix +" $< ..."); \r
+ }\r
+ else\r
+ {\r
+ makefilename.writeLine("\t-@echo asm"+targetName.suffix +" $< ..."); \r
+ }\r
+ makefilename.writeLine("\tif [ ! -d $(@D) ]; then $(MKDIR) $(@D) ; fi;"); \r
+ \r
+ if(fileExt == "c")\r
+ {\r
+ if ((targetName.name == "A15F") || (targetName.name == "A9F") || (targetName.name == "A8F"))\r
+ {\r
+ makefilename.writeLine("\t$(RM) $@.dep");\r
+ makefilename.writeLine("\t$(CC) $(CFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) $< -o $@");\r
+ /* \r
+ TBD\r
+ */\r
+ }\r
+ else\r
+ {\r
+ makefilename.writeLine("\t$(RM) $@.dep");\r
+ makefilename.writeLine("\t$(CC) $(CFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fc $< ");\r
+ makefilename.writeLine("\t-@$(CP) $@.dep $@.pp; \\");\r
+ makefilename.writeLine(" $(SED) -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\\\$$//' \\");\r
+ makefilename.writeLine(" -e '/^$$/ d' -e 's/$$/ :/' < $@.pp >> $@.dep; \\");\r
+ makefilename.writeLine(" $(RM) $@.pp ");\r
+ }\r
+ }\r
+ else if(fileExt == "asm")\r
+ {\r
+ makefilename.writeLine("\t$(AC) $(ASFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fa $< ");\r
+ }\r
+ else if(fileExt == "sa")\r
+ {\r
+ makefilename.writeLine("\t$(AC) $(ASFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) $< ");\r
+ }\r
+ \r
+ makefilename.writeLine("\n#Create Empty rule for dependency");\r
+ makefilename.writeLine("$("+objectliststring+"):"+makefilename.$private.fd);\r
+ makefilename.writeLine(makefilename.$private.fd+":");\r
+ makefilename.writeLine("\n#Include Depedency for "+srcString+" Files");\r
+ makefilename.writeLine("ifneq (clean,$(MAKECMDGOALS))");\r
+ makefilename.writeLine(" -include $("+objectliststring+":%.$(OBJEXT)=%.$(OBJEXT).dep)");\r
+ makefilename.writeLine("endif");\r
+ \r
+}\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : buildLibrary\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * Utility function which will build a specific library\r
+ **************************************************************************/\r
+var makefilelocal;\r
+function buildLibrary (socName, isDmaSoc, isSoc, libOptions, libName, target, libFiles, useProfiling) \r
+{\r
+ var targetDir;\r
+ var objExtDir;\r
+ \r
+ if (useProfiling == true)\r
+ {\r
+ libName += ".profiling"\r
+ }\r
+\r
+ if (target.name == "A15F")\r
+ {\r
+ targetDir = "a15/release";\r
+ }\r
+ else if (target.name == "A9F")\r
+ {\r
+ targetDir = "a9/release";\r
+ }\r
+ else if (target.name == "ARM9")\r
+ {\r
+ targetDir = "arm9/release";\r
+ }\r
+ else if (target.name == "A8F")\r
+ {\r
+ targetDir = "a8/release";\r
+ }\r
+ else if (target.name == "C674")\r
+ {\r
+ targetDir = "c674/release";\r
+ }\r
+ else if (target.name == "M4")\r
+ {\r
+ targetDir = "m4/release";\r
+ }\r
+ else\r
+ {\r
+ targetDir = "c66/release";\r
+ }\r
+ \r
+ /* Derive the operating system and soc names */\r
+ if (isSoc == "true") {\r
+ var libNameExp = libName;\r
+ targetDir = socName+"/"+targetDir;\r
+ objExtDir = "soc";\r
+ }\r
+ else {\r
+ var libNameExp = libName;\r
+ objExtDir = "all";\r
+ }\r
+\r
+ var lldFullLibraryPath = "./lib/" + targetDir +"/" + libNameExp;\r
+ var lldFullBuildPath = "./build/" + targetDir +"/" + libNameExp;\r
+ var lldFullLibraryPathMake = "$(LIBDIR)/" + targetDir +"/" + libNameExp;\r
+\r
+ /* Create Main make file in the root of package folder */\r
+ makefilelocal = createMake(makefilelocal);\r
+\r
+ /* Write the rule to make library in main makefile */\r
+ lib = lldFullBuildPath+".a"+target.suffix;\r
+ libMake = lldFullLibraryPathMake+".a"+target.suffix;\r
+ var objectPath= "./package/"+lldFullBuildPath;\r
+ \r
+ makefilelocal.writeLine("\n\n# Make rule to create "+libMake+" library");\r
+ makefilelocal.writeLine(".libraries: "+ libMake);\r
+ makefilelocal.writeLine(libMake+": FORCE\n\t$(MAKE) -f "+lib+".mk $@"); \r
+\r
+ /* Create Library make file in the lib folder */\r
+ var makefilelib= createLibMake(socName, objExtDir, lib+".mk",target,objectPath,useProfiling); \r
+\r
+ /* Rule to clean library in main makefile */\r
+ makefilelocal.writeLine("# Rule to clean "+libMake+" library"); \r
+ makefilelocal.writeLine("clean ::\n\t$(RM) "+ libMake); \r
+ librule="\n\n"+libMake+" :";\r
+\r
+ /* Add files to be compiled */\r
+ /* Separate out the C and assembly files */\r
+ var cfiles= new Array();\r
+ var afiles= new Array();\r
+ var safiles= new Array();\r
+ for each(var srcFile in libFiles)\r
+ {\r
+ var srcFile=String(srcFile);\r
+ var dot = srcFile.lastIndexOf(".");\r
+ var extension = srcFile.substr(dot,srcFile.length); \r
+ if(extension == ".c")\r
+ {\r
+ cfiles.push(srcFile);\r
+ }\r
+ else if(extension == ".sa")\r
+ {\r
+ safiles.push(srcFile);\r
+ }\r
+ else if(extension == ".asm")\r
+ {\r
+ afiles.push(srcFile);\r
+ }\r
+ else\r
+ {\r
+ print("ERROR: Unsupported file extension");\r
+ java.lang.System.exit(1);\r
+ }\r
+ }\r
+ if(cfiles.length > 0)\r
+ { \r
+ makeAddObjects("COMMONSRC",makefilelib,cfiles,libOptions,"c",target, "$(OBJDIR)");\r
+ librule += " $(COMMONSRCCOBJS)"; \r
+ }\r
+ if(afiles.length > 0)\r
+ { \r
+ makeAddObjects("COMMONSRC",makefilelib,afiles,libOptions,"asm",target, "$(OBJDIR)");\r
+ librule += " $(COMMONSRCASMOBJS)"; \r
+ }\r
+ if(safiles.length > 0)\r
+ { \r
+ makeAddObjects("COMMONSRC",makefilelib,safiles,libOptions,"sa",target, "$(OBJDIR)");\r
+ librule += " $(COMMONSRCSAOBJS)"; \r
+ }\r
+\r
+ makefilelib.writeLine(librule);\r
+ makefilelib.writeLine("\t@echo archiving $? into $@ ...");\r
+ makefilelib.writeLine("\tif [ ! -d $(LIBDIR)/"+targetDir+" ]; then $(MKDIR) $(LIBDIR)/"+targetDir+" ; fi;"); \r
+ makefilelib.writeLine("\t$(ARIN) $(ARFLAGS_INTERNAL) $@ $?");\r
+ makefilelib.close(); \r
+\r
+ /* Create the Epilogue; which executes after all the builds are completed. \r
+ * This is used to generate the benchmark information for the built library. \r
+ * Also add the benchmarking information file to the package. */\r
+ /* Put the temp file in object directory since javascript doesn't have a built in tmpname, \r
+ * and don't want --jobs=# with # > 1 to result in collisions */\r
+ var libFullName = lldFullLibraryPath + ".a" + target.suffix;\r
+ var tempFile = libFullName + ".xml";\r
+ Pkg.makeEpilogue += ".libraries: " + libFullName + "_size.txt\n";\r
+ Pkg.makeEpilogue += libFullName + "_size.txt: " + libFullName + "\n";\r
+ if ( java.lang.String(target.name).contains('66') )\r
+ { \r
+ Pkg.makeEpilogue += "\n\t $(C6X_GEN_INSTALL_PATH)/bin/ofd6x -x " + libFullName + " > " + tempFile;\r
+ Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt";\r
+ Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n";\r
+ } \r
+ else if (target.name == "M4")\r
+ {\r
+ Pkg.makeEpilogue += "\n\t $(TOOLCHAIN_PATH_M4)/bin/armofd -x " + libFullName + " > " + tempFile;\r
+ Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt";\r
+ Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n";\r
+ }\r
+ else\r
+ {\r
+ Pkg.makeEpilogue += "\n\t $(TOOLCHAIN_PATH_A15)/bin/$(CROSS_TOOL_PRFX)size " + libFullName + " > " + libFullName + "_size.txt";\r
+ } \r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix + "_size.txt";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullBuildPath + ".a" + target.suffix + ".mk";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix;\r
+\r
+ /* We need to clean after ourselves; extend the 'clean' target to take care of this. */\r
+ Pkg.makeEpilogue += "\nclean::\n";\r
+ Pkg.makeEpilogue += "\t$(RM) " + lldFullBuildPath + ".a" + target.suffix + "_size.txt\n"; \r
+ Pkg.makeEpilogue += "\t$(RMDIR) " + "$(LIBDIR)/" + targetDir + "/ \n\n";\r
+\r
+ return lib;\r
+}\r
+\r
+\r
+\r
diff --git a/build/makefile.mk b/build/makefile.mk
--- /dev/null
+++ b/build/makefile.mk
@@ -0,0 +1,83 @@
+#
+# Copyright (c) 2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+
+MODULE_NAME = iolink
+ifeq ($(ICSS0_FW), yes)
+ MODULE_NAME = iolink_icss0
+endif
+
+include $(PDK_IOLINK_COMP_PATH)/src/src_files_common.mk
+
+ifeq ($(SOC),$(filter $(SOC), am437x))
+SRCDIR += soc/$(SOC)
+INCDIR += soc
+# Common source files across all platforms and cores
+SRCS_COMMON += IOLINK_soc.c
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk bios xdc
+
+ifeq ($(SOC),$(filter $(SOC), am437x))
+PACKAGE_SRCS_COMMON += soc/$(SOC) soc/IOLINK_soc.h
+endif
+
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+
+# For all FW supporting devices source files in library and package
+ifeq ($(SOC),$(filter $(SOC), am437x))
+ SRCDIR += src/v0
+ INCDIR += src/v0
+ SRCS_COMMON += IOLINK_v0.c
+ PACKAGE_SRCS_COMMON += src/v0 soc/IOLINK_v0.h
+ CFLAGS_LOCAL_COMMON += -DPRU_ICSS_FW
+endif
+
+ifeq ($(SOC),$(filter $(SOC), am437x))
+ ifeq ($(ICSS0_FW), yes)
+ # For ICSS0
+ CFLAGS_LOCAL_COMMON += -DAM437X_ICSS0
+ endif
+endif
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
diff --git a/build/makefile_icss_iolink.mk b/build/makefile_icss_iolink.mk
--- /dev/null
@@ -0,0 +1,65 @@
+# Copyright (c) 2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+
+MODULE_NAME = icss_iolink
+
+#SRCDIR += src/ $(PDK_CSL_COMP_PATH)/ $(PDK_INSTALL_PATH)/
+SRCDIR += src/
+#INCDIR += src/ $(PDK_CSL_COMP_PATH)/ $(PDK_INSTALL_PATH)/
+
+# Common source files across all platforms and cores
+SRCS_ASM_COMMON += iolink.asm
+
+#LNKFLAGS_LOCAL_COMMON = --entry_point=main
+
+LNKCMD_FILE = $($(MODULE_NAME)_PATH)/src/am437x_pru.cmd
+
+PACKAGE_SRCS_COMMON += src/ build/makefile_icss_iolink.mk
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES =
+
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -DPRU
+CFLAGS_LOCAL_COMMON += --define=am4379 --define=icss1 --define=pru0
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
+
diff --git a/build/makefile_indp.mk b/build/makefile_indp.mk
--- /dev/null
+++ b/build/makefile_indp.mk
@@ -0,0 +1,53 @@
+#
+# Copyright (c) 2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+
+MODULE_NAME = iolink_indp
+
+include $(PDK_IOLINK_COMP_PATH)/src/src_files_common.mk
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk
+
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
diff --git a/build/makefile_profile.mk b/build/makefile_profile.mk
--- /dev/null
@@ -0,0 +1,79 @@
+#
+# Copyright (c) 2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+
+MODULE_NAME = iolink_profile
+
+include $(PDK_IOLINK_COMP_PATH)/src/src_files_common.mk
+
+ifeq ($(SOC),$(filter $(SOC), am437x))
+SRCDIR += soc/$(SOC)
+INCDIR += soc
+# Common source files across all platforms and cores
+SRCS_COMMON += IOLINK_soc.c
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk
+
+ifeq ($(SOC),$(filter $(SOC), am437x))
+PACKAGE_SRCS_COMMON += soc/$(SOC) soc/IOLINK_soc.h
+endif
+
+ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
+ ifeq ($(CORE),$(filter $(CORE), mpu1_0 a15_0 a9host a8host))
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
+ else
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
+ endif
+endif
+
+# For all FW supporting devices source files in library and package
+ifeq ($(SOC),$(filter $(SOC), am437x))
+ SRCDIR += src/v0
+ INCDIR += src/v0
+ SRCS_COMMON += IOLINK_v0.c
+ PACKAGE_SRCS_COMMON += src/v0 soc/IOLINK_v0.h
+ CFLAGS_LOCAL_COMMON += -DPRU_ICSS_FW
+endif
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
diff --git a/build/makefile_profile_indp.mk b/build/makefile_profile_indp.mk
--- /dev/null
@@ -0,0 +1,59 @@
+#
+# Copyright (c) 2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+
+MODULE_NAME = iolink_profile_indp
+
+include $(PDK_IOLINK_COMP_PATH)/src/src_files_common.mk
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk
+
+ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
+ ifeq ($(CORE),$(filter $(CORE), mpu1_0 a15_0 a9host a8host))
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
+ else
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
+ endif
+endif
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
diff --git a/config.bld b/config.bld
--- /dev/null
+++ b/config.bld
@@ -0,0 +1,367 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the iolink Driver
+ ******************************************************************************
+ * FILE NAME: config.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build configuration script for the iolink driver
+ * and is responsible for configuration of the paths for the various
+ * tools required to build the driver.
+ *
+ * Copyright (C) 2014-2016, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Get the Tools Base directory from the Environment Variable. */
+var c66ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var c674ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var m4ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_M4");
+var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15");
+var a9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A9");
+var arm9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_ARM9");
+var a8ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A8");
+
+/* Get the extended debug flags for C66x,
+ * did not change the name for backwards compatibilty */
+var extDbgFlags = java.lang.System.getenv("EXTDBGFLAGS");
+
+/* Get the extended debug flags for A15 */
+var extDbgFlags_a15 = java.lang.System.getenv("EXTDBGFLAGS_A15");
+
+/* Get the extended debug flags for A8 */
+var extDbgFlags_a8 = java.lang.System.getenv("EXTDBGFLAGS_A8");
+
+/* Get the extended debug flags for A9 */
+var extDbgFlags_a9 = java.lang.System.getenv("EXTDBGFLAGS_A9");
+
+/* Get the extended debug flags for ARM9 */
+var extDbgFlags_arm9 = java.lang.System.getenv("EXTDBGFLAGS_ARM9");
+
+/* Get the extended debug flags for M4 */
+var extDbgFlags_m4 = java.lang.System.getenv("EXTDBGFLAGS_M4");
+/* Get the base directory for the iolink Socket Driver Package */
+var driverPath = new java.io.File(".//").getPath();
+
+/* Include Path */
+var lldIncludePath = " -I" + driverPath + "/src" + " -I" + driverPath;
+
+/* Configure the iolink Socket Release Version Information */
+/* 3 steps: remove SPACE and TAB, convert to string and split to make array */
+var driverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+/* Print the Compiler Options */
+var pOpts = 1;
+
+/* C66 ELF compiler configuration for Little Endian Mode. */
+var C66LE = xdc.useModule('ti.targets.elf.C66');
+C66LE.rootDir = c66ToolsBaseDir;
+C66LE.ccOpts.prefix = "-mo -o3 -q -k -eo.o";
+if(extDbgFlags)
+ C66LE.ccOpts.prefix = C66LE.ccOpts.prefix + " " + extDbgFlags;
+
+/* C67 ELF compiler configuration for Little Endian Mode. */
+var C674LE = xdc.useModule('ti.targets.elf.C67');
+C674LE.rootDir = c66ToolsBaseDir;
+C674LE.ccOpts.prefix = "-mo -o3 -q -k -eo.o";
+if(extDbgFlags)
+ C67LE.ccOpts.prefix = C67LE.ccOpts.prefix + " " + extDbgFlags;
+
+/* C66 ELF compiler configuration for Big Endian Mode. */
+var C66BE = xdc.useModule('ti.targets.elf.C66_big_endian');
+C66BE.rootDir = c66ToolsBaseDir;
+C66BE.ccOpts.prefix = "-mo -o3 -q -k -eo.o -DBIGENDIAN";
+if(extDbgFlags)
+ C66BE.ccOpts.prefix = C66BE.ccOpts.prefix + " " + extDbgFlags;
+
+/* C674 ELF compiler configuration for Little Endian Mode. */
+var C674LE = xdc.useModule('ti.targets.elf.C674');
+C674LE.rootDir = c674ToolsBaseDir;
+C674LE.asmOpts.prefix = "--strip_coff_underscore";
+C674LE.ccOpts.prefix = "--strip_coff_underscore -mo -o3 -q -k -eo.o " + "-D" + cslPartNumber;
+if(extDbgFlags)
+ C674LE.ccOpts.prefix = C674LE.ccOpts.prefix + " " + extDbgFlags
+
+/* ARMv7 A15 compiler configuration */
+var A15LE = xdc.useModule('gnu.targets.arm.A15F');
+A15LE.rootDir = a15ToolsBaseDir;
+A15LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a15 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a15)
+ A15LE.ccOpts.prefix = A15LE.ccOpts.prefix + " " + extDbgFlags_a15;
+
+/* ARMv7 A9 compiler configuration */
+var A9LE = xdc.useModule('gnu.targets.arm.A9F');
+A9LE.rootDir = a9ToolsBaseDir;
+A9LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a9 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a9)
+ A9LE.ccOpts.prefix = A9LE.ccOpts.prefix + " " + extDbgFlags_a9;
+
+/* ARMv5 ARM9 compiler configuration */
+var ARM9LE = xdc.useModule('ti.targets.arm.elf.Arm9');
+ARM9LE.rootDir = arm9ToolsBaseDir;
+ARM9LE.ccOpts.prefix = "-mno-unaligned-access -c -marm -DDRA7xx -Dxdc_target_types__=gnu/targets/arm/std.h -Dxdc_target_name__=Arm9 -gstrict-dwarf -Wall -D__ARMv5 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_arm9)
+ ARM9LE.ccOpts.prefix = ARM9LE.ccOpts.prefix + " " + extDbgFlags_arm9;
+
+/* ARMv7 A8 compiler configuration */
+var A8LE = xdc.useModule('gnu.targets.arm.A8F');
+A8LE.rootDir = a8ToolsBaseDir;
+A8LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a8 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a8)
+ A8LE.ccOpts.prefix = A8LE.ccOpts.prefix + " " + extDbgFlags_a8;
+
+/* M4 ELF compiler configuration for Little Endian Mode. */
+var M4LE = xdc.useModule('ti.targets.arm.elf.M4');
+M4LE.rootDir = m4ToolsBaseDir;
+M4LE.ccOpts.prefix = "-o4 -qq -pdsw255 -DMAKEFILE_BUILD";
+if(extDbgFlags_m4)
+ M4LE.ccOpts.prefix = M4LE.ccOpts.prefix + " " + extDbgFlags_m4;
+
+/* soc name (am?) is inserted between first an second element of this
+ list to construct device file name for each device */
+var deviceConstruct = [ "soc/", "/IOLINK_soc.c" ];
+
+/* Create the SoC List */
+var socs = {
+ /* device independent libraries */
+ all :
+ {
+ /* Build this library */
+ build: "true",
+ /* SoC lib enabled */
+ socDevLib: "false",
+ /* Library options */
+ copts: "",
+ /* target lists, kept blank now, would be updated based on argument lists */
+ targets: []
+ },
+ am335x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am335x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM335x",
+ /* target list */
+ targets: [ A8LE ]
+ },
+ am437x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am437x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM437x",
+ /* target list */
+ targets: [ A9LE ]
+ },
+ am572x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am572x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM572x",
+ /* target list */
+ targets: [ C66LE, M4LE, A15LE]
+ },
+ am574x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am574x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM574x",
+ /* target list */
+ targets: [ C66LE, M4LE, A15LE]
+ },
+ dra75x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains dra75x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_DRA75x",
+ /* target list */
+ targets: [ C66LE, M4LE, A15LE]
+ },
+ am571x :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains am571x */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_AM571x",
+ /* target list */
+ targets: [ C66LE, M4LE, A15LE]
+ },
+ k2h :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains k2h */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_K2H",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE]
+ },
+ k2k :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains k2k */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_K2H",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE]
+ },
+ k2e :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains k2e */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_K2E",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE]
+ },
+ k2l :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains k2l */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_K2L",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE]
+ },
+ k2g :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains k2g */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_K2G",
+ /* target list */
+ targets: [ C66LE, C66BE, A15LE]
+ },
+ omapl137 :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains omapl137 */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_OMAPL137",
+ /* target list */
+ targets: [ C674LE, ARM9LE]
+ },
+ omapl138 :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains omapl138 */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_OMAPL138",
+ /* target list */
+ targets: [ C674LE, ARM9LE]
+ },
+ c6678 :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains c6678 */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_C6678",
+ /* target list */
+ targets: [ C66LE, C66BE]
+ },
+ c6657 :
+ {
+ /* this variable would be reinitialized to true, if XDCARGS contains c6657 */
+ build: "false",
+ /* SoC lib enabled */
+ socDevLib: "true",
+ /* Library options */
+ copts: " -DSOC_C6657",
+ /* target list */
+ targets: [ C66LE, C66BE]
+ }
+};
+
+/**************************************************************************
+ * FUNCTION NAME : merge
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to merge two arrarys
+ **************************************************************************/
+function merge() {
+ var args = arguments;
+ var hash = {};
+ var arr = [];
+ for (var i = 0; i < args.length; i++) {
+ for (var j = 0; j < args[i].length; j++) {
+ if (hash[args[i][j]] !== true) {
+ arr[arr.length] = args[i][j];
+ hash[args[i][j]] = true;
+ }
+ }
+ }
+ return arr;
+}
+
+/* Grab input from XDCARGS */
+var buildArguments = [];
+
+/* Construct the build arguments */
+for (var tmp=0; arguments[tmp] != undefined; tmp++)
+{
+
+ /* If no arguments are provided, override for building all */
+ if ( ( arguments.length == 1) && (arguments[tmp].equals("./config.bld")) )
+ buildArguments[buildArguments.length++] = "all";
+ else
+ buildArguments[buildArguments.length++] = arguments[tmp];
+}
+
+/* Build targets on this build */
+var build_targets = [];
+var soc_names = Object.keys(socs);
+
+for (var i=0; i < buildArguments.length; i++ ) {
+ /* Build it for all targets */
+ if (buildArguments[i] == "all") {
+ for (var j = 0; j < soc_names.length; j++) {
+ build_targets = merge (build_targets.slice(0), socs[soc_names[j]].targets.slice(0));
+ /* Set build to "true" for that SoC */
+ socs[soc_names[j]].build = "true";
+ }
+ }
+ else {
+ /* Skip the first argument, which is ./config.bld to get to next SoCs */
+ if (i == 0) continue;
+ /* Set that build to true if it is found in supported build socs */
+ for (j = 0; j < soc_names.length; j++) {
+ if (buildArguments[i] == soc_names[j]) {
+ socs[buildArguments[i]].build = "true";
+ build_targets = merge (build_targets.slice(0), socs[buildArguments[i]].targets.slice(0));
+ break;
+ }
+ }
+ }
+}
+
+/* Update the Build target generated list */
+socs["all"].targets = build_targets;
+Build.targets = build_targets;
diff --git a/config_mk.bld b/config_mk.bld
--- /dev/null
+++ b/config_mk.bld
@@ -0,0 +1,43 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the iolink Driver
+ ******************************************************************************
+ * FILE NAME: config_mk.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build configuration script for the iolink driver
+ * and is responsible for configuration of the paths for the various
+ * tools required to build the driver.
+ *
+ * Copyright (C) 2014-2016, Texas Instruments, Inc.
+ *****************************************************************************/
+/* Get the Tools Base directory from the Environment Variable. */
+var c66ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var c674ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var m4ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_M4");
+var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15");
+var a9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A9");
+var arm9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_ARM9");
+var a8ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A8");
+
+/* Get the base directory for the iolink Socket Driver Package */
+var driverPath = new java.io.File(".//").getPath();
+
+/* Include Path */
+var lldIncludePath = " -I" + driverPath + "/src" + " -I" + driverPath;
+
+/* Configure the iolink Socket Release Version Information */
+/* 3 steps: remove SPACE and TAB, convert to string and split to make array */
+var driverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+/* Do not Print the Compiler Options */
+var pOpts = 0;
+
+/* List of all devices that needs to be build via XDC
+ * As the build happens through makefile, there is nothing to build via XDC
+ * using the below for packaging infrastructure
+ */
+var socs = [];
+var devices = [];
+var build_devices = [];
+Build.targets = []
+
diff --git a/docs/IOLINK_LLD_SoftwareManifest.html b/docs/IOLINK_LLD_SoftwareManifest.html
--- /dev/null
@@ -0,0 +1,328 @@
+<!--\r\r
+Texas Instruments Manifest Format 2.0\r\r
+-->\r\r
+\r\r
+<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r\r
+<html>\r\r
+\r\r
+<head>\r\r
+<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />\r\r
+<!-- @Start Style -->\r\r
+<!-- Default style in case someone doesnt have Internet Access -->\r\r
+<style type="text/css" id="internalStyle">\r\r
+ body, div, p {\r\r
+ font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\r\r
+ font-size: 13px;\r\r
+ line-height: 1.3;\r\r
+ }\r\r
+ body {\r\r
+ margin: 20px; \r\r
+ }\r\r
+ h1 {\r\r
+ font-size: 150%;\r\r
+ }\r\r
+ h2 {\r\r
+ font-size: 120%;\r\r
+ }\r\r
+ h3 {\r\r
+ font-size: 100%;\r\r
+ }\r\r
+ img {\r\r
+ border: 0px;\r\r
+ vertical-align: middle;\r\r
+ }\r\r
+ table, th, td, tr {\r\r
+ border: 1px solid black; \r\r
+ font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\r\r
+ font-size: 13px;\r\r
+ line-height: 1.3;\r\r
+ empty-cells: show; \r\r
+ padding: 5px;\r\r
+ }\r\r
+ table {\r\r
+ border-collapse: collapse; \r\r
+ width: 100%;\r\r
+ }\r\r
+ tr {\r\r
+ page-break-inside: avoid;\r\r
+ }\r\r
+ #TIlogoLeft {\r\r
+ background-color: black; \r\r
+ padding: 0;\r\r
+ width: 20%;\r\r
+ }\r\r
+ #TIlogoRight {\r\r
+ background-color: red; \r\r
+ padding: 0;\r\r
+ }\r\r
+ #ProductName {\r\r
+ text-align: center;\r\r
+ }\r\r
+ #ReleaseDate {\r\r
+ text-align: center;\r\r
+ }\r\r
+ .LogoSection {\r\r
+ margin: 0;\r\r
+ padding: 0;\r\r
+ }\r\r
+ .HeaderSection {\r\r
+ margin: 25px 0 25px 0;\r\r
+ padding: 0;\r\r
+ }\r\r
+ .LegendSection {\r\r
+ margin: 25px 0 25px 0;\r\r
+ }\r\r
+ .ExportSection {\r\r
+ margin: 25px 0 25px 0;\r\r
+ }\r\r
+ .DisclaimerSection {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+ .CreditSection {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+ .LicenseSection {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+ .ManifestTable {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+</style> \r\r
+<!-- Override style from TI if they have Internet Access -->\r\r
+<link type="text/css" rel="stylesheet" href="timanifeststyle.css">\r\r
+<!-- @End Style -->\r\r
+<title>Texas Instruments Manifest</title>\r\r
+</head>\r\r
+\r\r
+<body><!-- Logo display, will need to fix up the URLs, this is just for testing.. Image alternate display not wporking well yet -->\r\r
+<div class="LogoSection">\r\r
+<table>\r\r
+ <tbody>\r\r
+ <tr>\r\r
+ <td id="TIlogoLeft">\r\r
+ <a href="http://www.ti.com/">\r\r
+ <!-- img src="tilogo.gif" alt="Texas Instruments Incorporated" -->\r\r
+ <img alt="" src="data:image/gif;base64,R0lGODlh3gA2AKIAAAAAAP///7u7u29vbz8/PwYGBujo6BgYGCH5BAAAAAAALAAAAADeADYAAAP/CLrc/jDKSau9OOvNu/9gKI5kaZ5oqq5s675wLM90bd94ru987//AoHBILBqPyKRyyWw6n9CodHorDALYLIHKJVqz2q44eAUHtoDB4DBu48rgLQErcNtnX7NhMDcICIB3gix5ZmtqAAZZew8EAo+QkQIDNVZqiIM1cHGKZ4YPAmaiAWw0c1gFmZqjB3SbZ6kNe6WhsAeOlDV0qjSFAXUAp7lwuREFtVsFgMvLB7fNAM+BCs+lDLd8BNYOuxfV22PL0RiWlwO1u3kDqejAEsjR6GB86FsHoYwA6gxWnVgGEegUuIelWJk6jswAGlXQ36J1xBSoQwfulIEDr/6l+VeK/+AehrAGOHRnAWRBbbWegckXAV6wk4AeRQtDQBEaBYsYlMl2hUCsBt0iKgilT9EfAlfO7SmzdKkrkQUT/fqZSECqLCSlntH375IAA1tqGUilLIBSNVnU+NmJNBRVChlF1QwAdlRWBy5P3QymwCLBYhs73cTHYBq3X33nDQ2wcWuBgef0FRD4GK3jU3VCZZUJAIw1OGg0P+4bFiubOWoOsEP1+KvZn3wurDbZ6lfcuw3yYkFjRSeYzRe7ARAbW0K3PmGIMi0OFDG1Mmha+RnufAHn3xL9ha6uTZ/rXagZ1GKAtTsHeWb+FEQvHILuX4+mLzj2j2r4TrFesTwMbE5Cuv8JzbTSGuRV1xgfUJFC3WbA0JWFalcItpgf8YU2yT/qATaedent5cBb8zk0DzIitgfKbonRFV9Wp2xl3UXq5Ccibp05598BnRigiAIJmrZAexkJQIuBwzX4CB3SQbeYQkPVAUco63DI2HzsAdYAiAvEZdYlaVQ5wXs3+bQAjovEUoBRR9LVAFLaPXCcY/KMqVRasQB5kiJgLcYgTkJiuCWKC2ZpIY/z/LRhYefkBAGW1HTyRy2UjObLHxSAOZ948EUVGCSC3SLZbB7iZKOLc2GRRgMH/VhdHnJwFCgD8iEGx0VKvpqbO+hoaCppEg3UiTES1CTkhNaQ+Qs4LQGql07/lET4mIQ6SvTSVGZ9Bmhz/bkYzK+PFKtpje6wumRm1wrLZzSdQASoZvyswdmSuk7p616HfkjBTxZBQucFgqXCFKdn1NpiUlQJhs8kteBWG0AbATbXS2tBlaeoVkmJRova4KkGPmhMFdiSYmq8cbTRYhrlkiHaNufJ9mIgVqEXnAOJM5JE4sgjudQ8bF82x+cKBP4Iiedecyjgx2/WtMNjjhcL9h+S4xq9RYJgsbeeUbmdrPTSQbPccsyijEXOfI8xyuinVJH1wdkS/MQ2Bc5Iq08DyHYwGglvPyCilbz0fa8GLV7r9+Btb7CJ14Qnzg8HpdKoOOF5Py752JNXvrblNphzEHnmnF/a+ecTbA465qKPXnnppkuOeuqKr8465K+z7nrsfc9Ouyq23z5I7rrfwXvvbhSQAAA7" />\r\r
+ </a>\r\r
+ </td>\r\r
+ <td id="TILogoRight">\r\r
+ <!-- img src="titagline.gif" alt="Technology for Innovators(tm)"-->\r\r
+ <img alt="" src="data:image/gif;base64,R0lGODlhOgEaALMAAP8AAP////92dv+3t/+Njf/W1v/t7f8hIf/19f+jo//Hx/8/P/9cXP/j4//6+v/+/iH5BAAAAAAALAAAAAA6ARoAAAT/EMhJq7046827/2AojmRpnmiqrmzrvnAsz3Rt33iu73zv/8CgcEgsGo/IpHLJbDqft0NDMCBQodis1jcADBKE7nYcCpjPgU5AQBKkVYOHAeRudqtXsh60/vRHdSoBBCGBNAkLe4o4f2psgG8pjR6GM5OLmDB/DA0GBoQADAgICRIBBQUOYgwGCg2kEgudBgUHAIGcBg0MsZ0NCnMGYgsBtqEGAbCynrW3AQONgcIFBgiErK6wAAfUtLbCscWiowoAyLDczLZu0AIJCAYOoJn0G38ObAwPEvLEts/O1vUhsA8AAjGonEmA9W6hGAVpEjiQoKBAhT8HJSRkVyEQQAAJ//a5YeMPQIFyACqCnJjSIgFCB4oB+HOSokWOAB6wIWCxnk8MfYh5QsYg5sVHfQLVMSqhztJIxWIaC6QzJy8KfZgqrNT0zR+nUNl8fSMvZ6IDwJCJRfoI7IR4Cub9nDsha6RwR02xUZpGq1utUWUq9FKgYV6/abgOHjt45tquEgY0SDDHoJg+fxhXolKNrmfH/EoR5EdAKmjQfB1qvPmGIQIJ3g4gC2egVF7LqxtP8Ng2cViTKFUCIGbNFKEEmB/VbDlYdqLRn+du8oTg6jjbmfe+CbTM2+BcuySgbQVtQoOCt7s3U8wbsqGs3ZppZLnylwFe8Uql825ogANPckUnYDoOCogxQGXADajggjcw4AA8DSSyTQASMmjhhTQscBWGHHbo4YcghijiiCSWaOKJKKao4oostugiFBEAADs=" />\r\r
+ </td>\r\r
+ </tr>\r\r
+ </tbody>\r\r
+</table>\r\r
+</div><div class="HeaderSection">\r\r
+<h1 id="ProductName">\r\r
+<!-- @Start Product -->\r\r
+I2C LLD Manifest\r\r
+<!-- @End Product -->\r\r
+</h1>\r\r
+\r\r
+<h2 id="ReleaseDate">\r\r
+<!-- @Start Date -->\r\r
+02-25-2016\r\r
+<!-- @End Date -->\r\r
+</h2>\r\r
+\r\r
+\r\r
+<h2 id="SRASID">\r\r
+<!-- @Start Date -->\r\r
+Manifest ID - SRAS00002585\r\r
+<!-- @End Date -->\r\r
+</h2>\r\r
+</div><div class="LegendSection">\r\r
+<h2>Legend</h2>\r\r
+<p>(explanation of the fields in the Manifest Table below)</p>\r\r
+<table>\r\r
+<tbody>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Software Name </b>\r\r
+</td>\r\r
+<td>\r\r
+The name of the application or file\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Version</b>\r\r
+</td>\r\r
+<td>\r\r
+Version of the application or file\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>License Type</b>\r\r
+</td>\r\r
+<td>\r\r
+Type of license(s) under which TI will be providing\r\r
+software to the licensee (e.g. BSD-3-Clause, GPL-2.0, TI TSPA License, TI\r\r
+Commercial License). The license could be under Commercial terms or Open Source. See Open Source Reference License Disclaimer in\r\r
+the Disclaimers Section. Whenever possible, TI will use an <a href="http://spdx.org/licenses/"> SPDX Short Identifier </a> for an Open Source\r\r
+License. TI Commercial license terms are not usually included in the manifest and are conveyed through a variety \r\r
+of means such as a clickwrap license upon install, \r\r
+a signed license agreement and so forth.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Location</b>\r\r
+</td>\r\r
+<td>\r\r
+The directory name and path on the media or a specific file where the Software is located. Typically fully qualified path names \r\r
+are not used and instead the relevant top level directory of the application is given. \r\r
+A notation often used in the manifests is [as installed]/directory/*. Note that the asterisk implies that all\r\r
+files under that directory are licensed as the License Type field denotes. Any exceptions to this will \r\r
+generally be denoted as [as installed]/directory/* except as noted below which means as shown in subsequent rows of \r\r
+the manifest.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Delivered As</b>\r\r
+</td>\r\r
+<td>\r\r
+This field will either be “Source”, “Binary” or “Source\r\r
+and Binary” and is the primary form the content of the Software is delivered\r\r
+in. If the Software is delivered in an archive format, this field\r\r
+applies to the contents of the archive. If the word Limited is used\r\r
+with Source, as in “Limited Source” or “Limited Source and Binary” then\r\r
+only portions of the Source for the application are provided.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Modified by TI</b>\r\r
+</td>\r\r
+<td>\r\r
+This field will either be “Yes” or “No”. A “Yes” means\r\r
+TI has made changes to the Software. A “No” means TI has not made any\r\r
+changes. Note: This field is not applicable for Software “Obtained\r\r
+from” TI.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Obtained from</b>\r\r
+</td>\r\r
+<td>\r\r
+This field specifies from where or from whom TI obtained\r\r
+the Software. It may be a URL to an Open Source site, a 3<sup>rd</sup>\r\r
+party licensor, or TI. See Links Disclaimer in the Disclaimers\r\r
+Section.\r\r
+</td>\r\r
+</tr>\r\r
+</tbody>\r\r
+</table>\r\r
+</div><div class="DisclaimerSection">\r\r
+<h2>Disclaimers</h2>\r\r
+<h3>Export Control Classification Number (ECCN)</h3>\r\r
+<p>Any use of ECCNs listed in the Manifest is at the user’s risk\r\r
+and without recourse to TI. Your\r\r
+company, as the exporter of record, is responsible for determining the\r\r
+correct classification of any item at\r\r
+the time of export. Any export classification by TI of Software is for\r\r
+TI’s internal use only and shall not be construed as a representation\r\r
+or warranty\r\r
+regarding the proper export classification for such Software or whether\r\r
+an export\r\r
+license or other documentation is required for exporting such Software</p>\r\r
+<h3>Links in the Manifest</h3>\r\r
+<p>Any\r\r
+links appearing on this Manifest\r\r
+(for example in the “Obtained from” field) were verified at the time\r\r
+the Manifest was created. TI makes no guarantee that any listed links\r\r
+will\r\r
+remain active in the future.</p>\r\r
+<h3>Open Source License References</h3>\r\r
+<p>Your company is responsible for confirming the\r\r
+applicable license terms for any open source Software\r\r
+listed in this Manifest that was not “Obtained from” TI. Any open\r\r
+source license\r\r
+specified in this Manifest for Software that was\r\r
+not “Obtained from” TI is for TI’s internal use only and shall not be\r\r
+construed as a representation or warranty regarding the proper open\r\r
+source license terms\r\r
+for such Software.</p>\r\r
+</div><div class="ExportSection">\r\r
+<h2>Export Information</h2>\r\r
+<p>ECCN for Software included in this release:</p>\r\r
+Publicly Available - Open Source or TI TSPA License\r\r
+</div><div class="ManifestTable">\r\r
+<!-- h2>Manifest Table</h2 -->\r\r
+ \r
+ <table> \r
+ <tbody> \r
+ \r
+ <h2> \r
+ I2C LLD Manifest Table \r
+ </h2> \r
+ \r
+ \r
+ <p> \r
+ \r
+ See the Legend above for a description of these columns. \r
+ \r
+ </p> \r
+ \r
+ <table id="targetpackages" name="targetpackages"> \r
+ <thead> \r
+ <tr> \r
+ <td><b>Software Name</b></td> \r
+ <td><b>Version</b></td> \r
+ <td><b>License Type</b></td> \r
+ <td><b>Delivered As</b></td> \r
+ <td><b>Modified by TI</b></td> \r
+ <td></td> \r
+ <td></td> \r
+ </tr> \r
+ </thead> \r
+ \r
+ \r
+ <tbody> \r
+ <tr> \r
+ <td id="name" name="name" rowspan="2"> \r
+ I2C LLD \r
+ </td> \r
+ <td id="version" name="version" rowspan="2"> \r
+ 01.00.00 \r
+ </td> \r
+ <td id="license" name="license" rowspan="2"> \r
+ BSD-3-Clause \r
+ </td> \r
+ <td id="delivered" name="delivered" rowspan="2"> \r
+ Source and Binary \r
+ </td> \r
+ <td id="modified" name="modified" rowspan="2"> \r
+ N/A \r
+ </td> \r
+ <td><b>Location</b></td> \r
+ <td id="location" name="location"> \r
+ packages/ti/drv/i2c \r
+ </td> \r
+ </tr> \r
+ <tr> \r
+ <td><b>Obtained from</b></td> \r
+ <td id="obtained" name="obtained"> \r
+ Texas Instruments Incorporated \r
+ </td> \r
+ </tr> \r
+ \r
+ </tbody> \r
+ </table> \r
+ \r
+ </p> \r
+ </p> \r
+ <p> \r
+\r\r
+</div><div class="CreditSection">\r\r
+<h2>Credits</h2>\r\r
+<BR> <BR><BR><BR><BR>\r\r
+</div><div class="LicenseSection">\r\r
+<h2>Licenses</h2>\r\r
+<BR><h3><b> I2C LLD Licenses </b></h3><BR> <BR><BR><BR>/* Copyright (c) 2013 Texas Instruments Inc - http://www.ti.com */<BR><BR>/*<BR>*Â Redistribution and use in source and binary forms, with or without<BR>*Â modification, are permitted provided that the following conditions<BR>*Â are met:<BR>*<BR>*Â Â Â Redistributions of source code must retain the above copyright<BR>*Â Â Â notice, this list of conditions and the following disclaimer.<BR>*<BR>*Â Â Â Redistributions in binary form must reproduce the above copyright<BR>*Â Â Â notice, this list of conditions and the following disclaimer in the<BR>*Â Â Â documentation and/or other materials provided with the<BR>*Â Â Â distribution.<BR>*<BR>*Â Â Â Neither the name of Texas Instruments Incorporated nor the names of<BR>*Â Â Â its contributors may be used to endorse or promote products derived<BR>*Â Â Â from this software without specific prior written permission.<BR>*<BR>*Â THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS<BR>*Â "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT<BR>*Â LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR<BR>*Â A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT<BR>*Â OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,<BR>*Â SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT<BR>*Â LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,<BR>*Â DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY<BR>*Â THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT<BR>*Â (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE<BR>*Â OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.<BR>*<BR>*/<BR><BR><BR>\r\r
+</div>\r\r
+\r\r
+</body></html>
\ No newline at end of file
diff --git a/docs/Module.xs b/docs/Module.xs
--- /dev/null
+++ b/docs/Module.xs
@@ -0,0 +1,61 @@
+/******************************************************************************\r
+ * FILE PURPOSE: IOLINK Driver DOCS Module specification file.\r
+ ******************************************************************************\r
+ * FILE NAME: module.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the module specification for the IOLINK Driver Documentation .\r
+ *\r
+ * Copyright (C) 2019, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Load the library utility. */\r
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : modBuild\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to build the LLD documentation and add it to the\r
+ * package.\r
+ **************************************************************************/\r
+function modBuild() \r
+{\r
+ /* Create the actual PROLOGUE Section for the Documentation.*/\r
+ Pkg.makePrologue += "release: iolink_document_generation\n";\r
+ Pkg.makePrologue += "iolink_document_generation:\n";\r
+ Pkg.makePrologue += "\t @echo ----------------------------\n";\r
+ Pkg.makePrologue += "\t @echo Generating IOLINK Driver Documentation\n";\r
+ Pkg.makePrologue += "\t doxygen docs/Doxyfile\n";\r
+ Pkg.makePrologue += "\t @echo IOLINK Driver Documentation Generated \n";\r
+ Pkg.makePrologue += "\t @echo ----------------------------\n";\r
+\r
+ /* Add the documentation file to the package. */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tifooter.htm";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tiheader.htm";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tilogo.gif";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/titagline.gif";\r
+\r
+\r
+ /* Add the IOLINK Software Manifest to the package */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/IOLINK_LLD_SoftwareManifest.html";\r
+\r
+ /* Add the HTML documentation to the package */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/doxygen";\r
+\r
+ /* Add the release notes to the package */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/ReleaseNotes_IOLINK_LLD.pdf";\r
+\r
+ /* Generate the ECLIPSE Plugin Generation: Only for SETUP Releases. */\r
+ if (driverInstallType == "SETUP")\r
+ {\r
+ Pkg.makePrologue += "all: eclipse_plugin_generation\n";\r
+ Pkg.makePrologue += "eclipse_plugin_generation:\n";\r
+ Pkg.makePrologue += "\t @echo ----------------------------\n";\r
+ Pkg.makePrologue += "\t @echo IOLINK Eclipse Plugin Generation\n";\r
+ Pkg.makePrologue += "\t xs xdc.tools.eclipsePluginGen -o . -x ./eclipseDocs/sample.xml -c ./eclipseDocs/toc_cdoc_sample.xml\n";\r
+ Pkg.makePrologue += "\t @echo IOLINK Eclipse Plugin Generated \n";\r
+ Pkg.makePrologue += "\t @echo ----------------------------\n";\r
+ }\r
+}\r
+\r
diff --git a/docs/ReleaseNotes_IOLINK_LLD.doc b/docs/ReleaseNotes_IOLINK_LLD.doc
new file mode 100755 (executable)
index 0000000..b8b1b88
Binary files /dev/null and b/docs/ReleaseNotes_IOLINK_LLD.doc differ
index 0000000..b8b1b88
Binary files /dev/null and b/docs/ReleaseNotes_IOLINK_LLD.doc differ
diff --git a/docs/ReleaseNotes_IOLINK_LLD.pdf b/docs/ReleaseNotes_IOLINK_LLD.pdf
new file mode 100755 (executable)
index 0000000..d11864d
Binary files /dev/null and b/docs/ReleaseNotes_IOLINK_LLD.pdf differ
index 0000000..d11864d
Binary files /dev/null and b/docs/ReleaseNotes_IOLINK_LLD.pdf differ
diff --git a/docs/doxyfile.xdt b/docs/doxyfile.xdt
--- /dev/null
+++ b/docs/doxyfile.xdt
@@ -0,0 +1,302 @@
+%%{\r
+/*!\r
+ * This template implements the Doxyfile\r
+ */ \r
+ /* Versioning */\r
+ var ver = this;\r
+ var packageVersion = ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3];\r
+\r
+%%}\r
+\r
+# Doxyfile 1.5.6\r
+\r
+#---------------------------------------------------------------------------\r
+# Project related configuration options\r
+#---------------------------------------------------------------------------\r
+DOXYFILE_ENCODING = UTF-8\r
+PROJECT_NAME = "IOLINK Low Level Driver"\r
+PROJECT_NUMBER = `packageVersion`\r
+OUTPUT_DIRECTORY = ./docs/doxygen\r
+CREATE_SUBDIRS = NO\r
+OUTPUT_LANGUAGE = English\r
+BRIEF_MEMBER_DESC = YES\r
+REPEAT_BRIEF = YES\r
+ABBREVIATE_BRIEF = "The $name class" \\r
+ "The $name widget" \\r
+ "The $name file" \\r
+ is \\r
+ provides \\r
+ specifies \\r
+ contains \\r
+ represents \\r
+ a \\r
+ an \\r
+ the\r
+ALWAYS_DETAILED_SEC = NO\r
+INLINE_INHERITED_MEMB = NO\r
+FULL_PATH_NAMES = NO\r
+STRIP_FROM_PATH = \r
+STRIP_FROM_INC_PATH = \r
+SHORT_NAMES = NO\r
+JAVADOC_AUTOBRIEF = NO\r
+QT_AUTOBRIEF = NO\r
+MULTILINE_CPP_IS_BRIEF = NO\r
+DETAILS_AT_TOP = NO\r
+INHERIT_DOCS = YES\r
+SEPARATE_MEMBER_PAGES = NO\r
+TAB_SIZE = 8\r
+ALIASES = \r
+OPTIMIZE_OUTPUT_FOR_C = YES\r
+OPTIMIZE_OUTPUT_JAVA = NO\r
+OPTIMIZE_FOR_FORTRAN = NO\r
+OPTIMIZE_OUTPUT_VHDL = NO\r
+BUILTIN_STL_SUPPORT = NO\r
+CPP_CLI_SUPPORT = NO\r
+SIP_SUPPORT = NO\r
+IDL_PROPERTY_SUPPORT = YES\r
+DISTRIBUTE_GROUP_DOC = NO\r
+SUBGROUPING = YES\r
+TYPEDEF_HIDES_STRUCT = NO\r
+#---------------------------------------------------------------------------\r
+# Build related configuration options\r
+#---------------------------------------------------------------------------\r
+EXTRACT_ALL = NO\r
+EXTRACT_PRIVATE = NO\r
+EXTRACT_STATIC = YES\r
+EXTRACT_LOCAL_CLASSES = YES\r
+EXTRACT_LOCAL_METHODS = NO\r
+EXTRACT_ANON_NSPACES = NO\r
+HIDE_UNDOC_MEMBERS = YES\r
+HIDE_UNDOC_CLASSES = YES\r
+HIDE_FRIEND_COMPOUNDS = NO\r
+HIDE_IN_BODY_DOCS = NO\r
+INTERNAL_DOCS = NO\r
+CASE_SENSE_NAMES = NO\r
+HIDE_SCOPE_NAMES = NO\r
+SHOW_INCLUDE_FILES = YES\r
+INLINE_INFO = YES\r
+SORT_MEMBER_DOCS = YES\r
+SORT_BRIEF_DOCS = NO\r
+SORT_GROUP_NAMES = NO\r
+SORT_BY_SCOPE_NAME = NO\r
+GENERATE_TODOLIST = YES\r
+GENERATE_TESTLIST = YES\r
+GENERATE_BUGLIST = YES\r
+GENERATE_DEPRECATEDLIST= YES\r
+ENABLED_SECTIONS = \r
+MAX_INITIALIZER_LINES = 30\r
+SHOW_USED_FILES = YES\r
+SHOW_DIRECTORIES = NO\r
+SHOW_FILES = YES\r
+SHOW_NAMESPACES = YES\r
+FILE_VERSION_FILTER = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to warning and progress messages\r
+#---------------------------------------------------------------------------\r
+QUIET = NO\r
+WARNINGS = YES\r
+WARN_IF_UNDOCUMENTED = YES\r
+WARN_IF_DOC_ERROR = YES\r
+WARN_NO_PARAMDOC = NO\r
+WARN_FORMAT = "$file:$line: $text"\r
+WARN_LOGFILE = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to the input files\r
+#---------------------------------------------------------------------------\r
+INPUT = \r
+INPUT_ENCODING = UTF-8\r
+FILE_PATTERNS = *.c \\r
+ *.cc \\r
+ *.cxx \\r
+ *.cpp \\r
+ *.c++ \\r
+ *.d \\r
+ *.java \\r
+ *.ii \\r
+ *.ixx \\r
+ *.ipp \\r
+ *.i++ \\r
+ *.inl \\r
+ *.h \\r
+ *.hh \\r
+ *.hxx \\r
+ *.hpp \\r
+ *.h++ \\r
+ *.idl \\r
+ *.odl \\r
+ *.cs \\r
+ *.php \\r
+ *.php3 \\r
+ *.inc \\r
+ *.m \\r
+ *.mm \\r
+ *.dox \\r
+ *.py \\r
+ *.f90 \\r
+ *.f \\r
+ *.vhd \\r
+ *.vhdl\r
+RECURSIVE = YES\r
+EXCLUDE = YES \\r
+ ./example \\r
+ ./test \\r
+ ./package \\r
+ ./packages\r
+EXCLUDE_SYMLINKS = NO\r
+EXCLUDE_PATTERNS = cslr_*.h\r
+EXCLUDE_SYMBOLS = \r
+EXAMPLE_PATH = \r
+EXAMPLE_PATTERNS = *\r
+EXAMPLE_RECURSIVE = NO\r
+IMAGE_PATH = \r
+INPUT_FILTER = \r
+FILTER_PATTERNS = \r
+FILTER_SOURCE_FILES = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to source browsing\r
+#---------------------------------------------------------------------------\r
+SOURCE_BROWSER = NO\r
+INLINE_SOURCES = NO\r
+STRIP_CODE_COMMENTS = YES\r
+REFERENCED_BY_RELATION = NO\r
+REFERENCES_RELATION = NO\r
+REFERENCES_LINK_SOURCE = YES\r
+USE_HTAGS = NO\r
+VERBATIM_HEADERS = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the alphabetical class index\r
+#---------------------------------------------------------------------------\r
+ALPHABETICAL_INDEX = NO\r
+COLS_IN_ALPHA_INDEX = 5\r
+IGNORE_PREFIX = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to the HTML output\r
+#---------------------------------------------------------------------------\r
+GENERATE_HTML = YES\r
+HTML_OUTPUT = html\r
+HTML_FILE_EXTENSION = .html\r
+HTML_HEADER = ./docs/tiheader.htm\r
+HTML_FOOTER = ./docs/tifooter.htm\r
+HTML_STYLESHEET = \r
+HTML_ALIGN_MEMBERS = YES\r
+GENERATE_HTMLHELP = YES\r
+GENERATE_DOCSET = NO\r
+DOCSET_FEEDNAME = "Doxygen generated docs"\r
+DOCSET_BUNDLE_ID = org.doxygen.Project\r
+HTML_DYNAMIC_SECTIONS = NO\r
+CHM_FILE = ..\..\iolinklldDocs.chm\r
+HHC_LOCATION = hhc.exe\r
+GENERATE_CHI = NO\r
+CHM_INDEX_ENCODING = \r
+BINARY_TOC = NO\r
+TOC_EXPAND = NO\r
+DISABLE_INDEX = NO\r
+ENUM_VALUES_PER_LINE = 4\r
+GENERATE_TREEVIEW = NONE\r
+TREEVIEW_WIDTH = 250\r
+FORMULA_FONTSIZE = 10\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the LaTeX output\r
+#---------------------------------------------------------------------------\r
+GENERATE_LATEX = NO\r
+LATEX_OUTPUT = latex\r
+LATEX_CMD_NAME = latex\r
+MAKEINDEX_CMD_NAME = makeindex\r
+COMPACT_LATEX = NO\r
+PAPER_TYPE = a4wide\r
+EXTRA_PACKAGES = \r
+LATEX_HEADER = \r
+PDF_HYPERLINKS = YES\r
+USE_PDFLATEX = YES\r
+LATEX_BATCHMODE = NO\r
+LATEX_HIDE_INDICES = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the RTF output\r
+#---------------------------------------------------------------------------\r
+GENERATE_RTF = NO\r
+RTF_OUTPUT = rtf\r
+COMPACT_RTF = NO\r
+RTF_HYPERLINKS = NO\r
+RTF_STYLESHEET_FILE = \r
+RTF_EXTENSIONS_FILE = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to the man page output\r
+#---------------------------------------------------------------------------\r
+GENERATE_MAN = NO\r
+MAN_OUTPUT = man\r
+MAN_EXTENSION = .3\r
+MAN_LINKS = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the XML output\r
+#---------------------------------------------------------------------------\r
+GENERATE_XML = NO\r
+XML_OUTPUT = xml\r
+XML_SCHEMA = \r
+XML_DTD = \r
+XML_PROGRAMLISTING = YES\r
+#---------------------------------------------------------------------------\r
+# configuration options for the AutoGen Definitions output\r
+#---------------------------------------------------------------------------\r
+GENERATE_AUTOGEN_DEF = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the Perl module output\r
+#---------------------------------------------------------------------------\r
+GENERATE_PERLMOD = NO\r
+PERLMOD_LATEX = NO\r
+PERLMOD_PRETTY = YES\r
+PERLMOD_MAKEVAR_PREFIX = \r
+#---------------------------------------------------------------------------\r
+# Configuration options related to the preprocessor \r
+#---------------------------------------------------------------------------\r
+ENABLE_PREPROCESSING = YES\r
+MACRO_EXPANSION = NO\r
+EXPAND_ONLY_PREDEF = NO\r
+SEARCH_INCLUDES = YES\r
+INCLUDE_PATH = \r
+INCLUDE_FILE_PATTERNS = \r
+PREDEFINED = \r
+EXPAND_AS_DEFINED = \r
+SKIP_FUNCTION_MACROS = YES\r
+#---------------------------------------------------------------------------\r
+# Configuration::additions related to external references \r
+#---------------------------------------------------------------------------\r
+TAGFILES = \r
+GENERATE_TAGFILE = \r
+ALLEXTERNALS = NO\r
+EXTERNAL_GROUPS = YES\r
+PERL_PATH = /usr/bin/perl\r
+#---------------------------------------------------------------------------\r
+# Configuration options related to the dot tool \r
+#---------------------------------------------------------------------------\r
+CLASS_DIAGRAMS = NO\r
+MSCGEN_PATH = \r
+HIDE_UNDOC_RELATIONS = YES\r
+HAVE_DOT = NO\r
+DOT_FONTNAME = FreeSans\r
+DOT_FONTPATH = \r
+CLASS_GRAPH = YES\r
+COLLABORATION_GRAPH = YES\r
+GROUP_GRAPHS = YES\r
+UML_LOOK = NO\r
+TEMPLATE_RELATIONS = NO\r
+INCLUDE_GRAPH = YES\r
+INCLUDED_BY_GRAPH = YES\r
+CALL_GRAPH = NO\r
+CALLER_GRAPH = NO\r
+GRAPHICAL_HIERARCHY = YES\r
+DIRECTORY_GRAPH = YES\r
+DOT_IMAGE_FORMAT = png\r
+DOT_PATH = \r
+DOTFILE_DIRS = \r
+DOT_GRAPH_MAX_NODES = 50\r
+MAX_DOT_GRAPH_DEPTH = 1000\r
+DOT_TRANSPARENT = YES\r
+DOT_MULTI_TARGETS = NO\r
+GENERATE_LEGEND = YES\r
+DOT_CLEANUP = YES\r
+#---------------------------------------------------------------------------\r
+# Configuration::additions related to the search engine \r
+#---------------------------------------------------------------------------\r
+SEARCHENGINE = NO\r
+\r
+\r
diff --git a/docs/tifooter.htm b/docs/tifooter.htm
--- /dev/null
+++ b/docs/tifooter.htm
@@ -0,0 +1,4 @@
+<hr size="1"><small>\r
+Copyright $year, Texas Instruments Incorporated</small>\r
+</body>\r
+</html>\r
diff --git a/docs/tiheader.htm b/docs/tiheader.htm
--- /dev/null
+++ b/docs/tiheader.htm
@@ -0,0 +1,12 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">\r
+<title>$title</title>\r
+<link href="$relpath$doxygen.css" rel="stylesheet" type="text/css">\r
+<link href="$relpath$tabs.css" rel="stylesheet" type="text/css">\r
+</head><body>\r
+<table width=100%>\r
+<tr>\r
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../../tilogo.gif"></a></td>\r
+ <td bgcolor="red"><img src="../../titagline.gif"></td>\r
+</tr>\r
+</table>\r
diff --git a/docs/tilogo.gif b/docs/tilogo.gif
new file mode 100755 (executable)
index 0000000..f2fab2d
Binary files /dev/null and b/docs/tilogo.gif differ
index 0000000..f2fab2d
Binary files /dev/null and b/docs/tilogo.gif differ
diff --git a/docs/titagline.gif b/docs/titagline.gif
new file mode 100755 (executable)
index 0000000..743a024
Binary files /dev/null and b/docs/titagline.gif differ
index 0000000..743a024
Binary files /dev/null and b/docs/titagline.gif differ
diff --git a/firmware/Module.xs b/firmware/Module.xs
--- /dev/null
+++ b/firmware/Module.xs
@@ -0,0 +1,64 @@
+/******************************************************************************\r
+ * FILE PURPOSE: IOLINK Firmware Source specification file.\r
+ ******************************************************************************\r
+ * FILE NAME: module.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the module specification for the IOLINK Driver\r
+ *\r
+ * Copyright (C) 2019 Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Load the library utility. */\r
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : modBuild\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to build the IOLINK LLD Driver and to add the core\r
+ * driver files to the package. \r
+ **************************************************************************/\r
+function modBuild() \r
+{\r
+ /* Add all the .h files to the release package. */\r
+ var fwFiles = libUtility.listAllFiles (".h");\r
+ for (var k = 0 ; k < fwFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = fwFiles[k];\r
+ \r
+ fwFiles = libUtility.listAllFiles (".c"); \r
+ for (var k = 0 ; k < fwFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = fwFiles[k];\r
+ \r
+ /* Add all the .mk files to the release package. */\r
+ var mkFiles = libUtility.listAllFiles (".mk", "firmware", true);\r
+ for (var k = 0 ; k < mkFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k];\r
+\r
+ /* Add all the .cmd files to the release package. */\r
+ var fwFiles = libUtility.listAllFiles (".cmd", "firmware", true);\r
+ for (var k = 0 ; k < fwFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = fwFiles[k];\r
+ \r
+ /* Add all the .asm files to the release package. */\r
+ var fwFiles = libUtility.listAllFiles (".asm", "firmware", true);\r
+ for (var k = 0 ; k < fwFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = fwFiles[k];\r
+ \r
+ /* Add all the .inc files to the release package. */\r
+ var fwFiles = libUtility.listAllFiles (".inc", "firmware", true);\r
+ for (var k = 0 ; k < fwFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = fwFiles[k];\r
+\r
+ /* Add all the .bin files to the release package. */\r
+ var fwFiles = libUtility.listAllFiles (".bin", "firmware", true);\r
+ for (var k = 0 ; k < fwFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = fwFiles[k];\r
+\r
+ /* Add all the .pdf files to the release package. */\r
+ var fwFiles = libUtility.listAllFiles (".pdf", "firmware", true);\r
+ for (var k = 0 ; k < fwFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = fwFiles[k];\r
+ \r
+}\r
+\r
diff --git a/firmware/icss_iolink/src/am437x_pru.cmd b/firmware/icss_iolink/src/am437x_pru.cmd
--- /dev/null
@@ -0,0 +1,94 @@
+/****************************************************************************/
+/* AM437x_PRU_SS1.cmd */
+/* Copyright (c) 2015 Texas Instruments Incorporated */
+/* */
+/* Description: This file is a linker command file that can be used for */
+/* linking PRU programs built with the C compiler and */
+/* the resulting .out file on an AM437x device. */
+/****************************************************************************/
+
+/****************************************************************************/
+//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+//WARNING:
+//This code was modified for use with the PRU ICSS0 peripheral
+//Do not use this code for PRU ICSS1 development
+//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+/****************************************************************************/
+
+-cr /* Link using C conventions */
+
+/* Specify the System Memory Map */
+MEMORY
+{
+ PAGE 0:
+ PRU_IMEM : org = 0x00000000 len = 0x00001000 /* 4kB PRU-ICSS1 Instruction RAM */
+
+ PAGE 1:
+
+ /* RAM */
+
+ PRU_DMEM_0_1 : org = 0x00000000 len = 0x00001000 CREGISTER=24 /* 4kB PRU Data RAM 0_1 */
+ PRU_DMEM_1_0 : org = 0x00002000 len = 0x00001000 CREGISTER=25 /* 4kB PRU Data RAM 1_0 */
+
+ PAGE 2:
+
+ DDR : org = 0x80000000 len = 0x00000100 CREGISTER=31
+ L3OCMC : org = 0x40000000 len = 0x00010000 CREGISTER=30
+
+
+ /* Peripherals */
+
+ PRU_CFG : org = 0x00026000 len = 0x00000120 CREGISTER=4
+ PRU_ECAP : org = 0x00030000 len = 0x00000060 CREGISTER=3
+ PRU_IEP : org = 0x0002E000 len = 0x0000031C CREGISTER=26
+ PRU_INTC : org = 0x00020000 len = 0x00001504 CREGISTER=0
+ PRU_UART : org = 0x00028000 len = 0x00000038 CREGISTER=7
+
+ DCAN0 : org = 0x481CC000 len = 0x000001E8 CREGISTER=14
+ DCAN1 : org = 0x481D0000 len = 0x000001E8 CREGISTER=15
+ DMTIMER2 : org = 0x48040000 len = 0x0000005C CREGISTER=1
+ PWMSS0 : org = 0x48300000 len = 0x000002C4 CREGISTER=18
+ PWMSS1 : org = 0x48302000 len = 0x000002C4 CREGISTER=19
+ PWMSS2 : org = 0x48304000 len = 0x000002C4 CREGISTER=20
+ GEMAC : org = 0x4A100000 len = 0x0000128C CREGISTER=9
+ I2C1 : org = 0x4802A000 len = 0x000000D8 CREGISTER=2
+ I2C2 : org = 0x4819C000 len = 0x000000D8 CREGISTER=17
+ MBX0 : org = 0x480C8000 len = 0x00000140 CREGISTER=22
+ MCASP0_DMA : org = 0x46000000 len = 0x00000100 CREGISTER=8
+ MCSPI0 : org = 0x48030000 len = 0x000001A4 CREGISTER=6
+ MCSPI1 : org = 0x481A0000 len = 0x000001A4 CREGISTER=16
+ MMCSD0 : org = 0x48060000 len = 0x00000300 CREGISTER=5
+ SPINLOCK : org = 0x480CA000 len = 0x00000880 CREGISTER=23
+ TPCC : org = 0x49000000 len = 0x00001098 CREGISTER=29
+ UART1 : org = 0x48022000 len = 0x00000088 CREGISTER=11
+ UART2 : org = 0x48024000 len = 0x00000088 CREGISTER=12
+
+ RSVD10 : org = 0x48318000 len = 0x00000100 CREGISTER=10
+ RSVD13 : org = 0x48310000 len = 0x00000100 CREGISTER=13
+ RSVD21 : org = 0x00032400 len = 0x00000100 CREGISTER=21
+ RSVD27 : org = 0x00032000 len = 0x00000100 CREGISTER=27
+
+}
+
+/* Specify the sections allocation into memory */
+SECTIONS {
+
+/* Forces _c_int00 to the start of PRU IRAM. Not necessary when */
+/* loading an ELF file, but useful when loading a binary */
+
+ .text:main > 0x00
+ //.text:_c_int00* > 0x0, PAGE 0
+ .text > PRU_IMEM, PAGE 0
+ .stack > PRU_DMEM_0_1, PAGE 1
+ .bss > PRU_DMEM_0_1, PAGE 1
+ .cio > PRU_DMEM_0_1, PAGE 1
+ .data > PRU_DMEM_0_1, PAGE 1
+ .switch > PRU_DMEM_0_1, PAGE 1
+ .sysmem > PRU_DMEM_0_1, PAGE 1
+ .cinit > PRU_DMEM_0_1, PAGE 1
+ .rodata > PRU_DMEM_0_1, PAGE 1
+ .rofardata > PRU_DMEM_0_1, PAGE 1
+ .farbss > PRU_DMEM_0_1, PAGE 1
+ .fardata > PRU_DMEM_0_1, PAGE 1
+ .resource_table > PRU_DMEM_0_1, PAGE 1
+}
diff --git a/firmware/icss_iolink/src/include/am437x/pru_cfg.h b/firmware/icss_iolink/src/include/am437x/pru_cfg.h
--- /dev/null
@@ -0,0 +1,498 @@
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRU_CFG_H_
+#define _PRU_CFG_H_
+
+/* PRU CFG register set */
+typedef struct {
+
+ /* PRU_CFG_REVID register bit field */
+ union {
+ volatile uint32_t REVID;
+
+ volatile struct {
+ uint32_t REVID : 32; // 31:0
+ } REVID_bit;
+ }; // 0x0
+
+ /* PRU_CFG_SYSCFG register bit field */
+ union {
+ volatile uint32_t SYSCFG;
+
+ volatile struct {
+ uint32_t IDLE_MODE : 2; // 1:0
+ uint32_t STANDBY_MODE : 2; // 3:2
+ uint32_t STANDBY_INIT : 1; // 4
+ uint32_t SUB_MWAIT : 1; // 5
+ uint32_t rsvd6 : 26; // 31:6
+ } SYSCFG_bit;
+ }; // 0x4
+
+ /* PRU_CFG_GPCFG0 register bit field */
+ union {
+ volatile uint32_t GPCFG0;
+
+ volatile struct {
+ uint32_t PRU0_GPI_MODE : 2; // 1:0
+ uint32_t PRU0_GPI_CLK_MODE : 1; // 2
+ uint32_t PRU0_GPI_DIV0 : 5; // 7:3
+ uint32_t PRU0_GPI_DIV1 : 5; // 12:8
+ uint32_t PRU0_GPI_SB : 1; // 13
+ uint32_t PRU0_GPO_MODE : 1; // 14
+ uint32_t PRU0_GPO_DIV0 : 5; // 19:15
+ uint32_t PRU0_GPO_DIV1 : 5; // 24:20
+ uint32_t PRU0_GPO_SH_SEL : 1; // 25
+ uint32_t PR1_PRU0_GP_MUX_SEL : 2; // 27:26
+ uint32_t rsvd28 : 4; // 31:28
+ } GPCFG0_bit;
+ }; // 0x8
+
+ /* PRU_CFG_GPCFG1 register bit field */
+ union {
+ volatile uint32_t GPCFG1;
+
+ volatile struct {
+ uint32_t PRU1_GPI_MODE : 2; // 1:0
+ uint32_t PRU1_GPI_CLK_MODE : 1; // 2
+ uint32_t PRU1_GPI_DIV0 : 5; // 7:3
+ uint32_t PRU1_GPI_DIV1 : 5; // 12:8
+ uint32_t PRU1_GPI_SB : 1; // 13
+ uint32_t PRU1_GPO_MODE : 1; // 14
+ uint32_t PRU1_GPO_DIV0 : 5; // 19:15
+ uint32_t PRU1_GPO_DIV1 : 5; // 24:20
+ uint32_t PRU1_GPO_SH_SEL : 1; // 25
+ uint32_t PR1_PRU1_GP_MUX_SEL : 2; // 27:26
+ uint32_t rsvd28 : 4; // 31:28
+ } GPCFG1_bit;
+ }; // 0xc
+
+ /* PRU_CFG_CGR register bit field */
+ union {
+ volatile uint32_t CGR;
+
+ volatile struct {
+ uint32_t PRU0_CLK_STOP_REQ : 1; // 0
+ uint32_t PRU0_CLK_STOP_ACK : 1; // 1
+ uint32_t PRU0_CLK_EN : 1; // 2
+ uint32_t PRU1_CLK_STOP_REQ : 1; // 3
+ uint32_t PRU1_CLK_STOP_ACK : 1; // 4
+ uint32_t PRU1_CLK_EN : 1; // 5
+ uint32_t INTC_CLK_STOP_REQ : 1; // 6
+ uint32_t INTC_CLK_STOP_ACK : 1; // 7
+ uint32_t INTC_CLK_EN : 1; // 8
+ uint32_t UART_CLK_STOP_REQ : 1; // 9
+ uint32_t UART_CLK_STOP_ACK : 1; // 10
+ uint32_t UART_CLK_EN : 1; // 11
+ uint32_t ECAP_CLK_STOP_REQ : 1; // 12
+ uint32_t ECAP_CLK_STOP_ACK : 1; // 13
+ uint32_t ECAP_CLK_EN : 1; // 14
+ uint32_t IEP_CLK_STOP_REQ : 1; // 15
+ uint32_t IEP_CLK_STOP_ACK : 1; // 16
+ uint32_t IEP_CLK_EN : 1; // 17
+ uint32_t rsvd18 : 14; // 31:18
+ } CGR_bit;
+ }; // 0x10
+
+ /* PRU_CFG_ISRP register bit field */
+ union {
+ volatile uint32_t ISRP;
+
+ volatile struct {
+ uint32_t PRU0_IMEM_PE_RAW : 4; // 3:0
+ uint32_t PRU0_DMEM_PE_RAW : 4; // 7:4
+ uint32_t PRU1_IMEM_PE_RAW : 4; // 11:8
+ uint32_t PRU1_DMEM_PE_RAW : 4; // 15:12
+ uint32_t RAM_PE_RAW : 4; // 19:16
+ uint32_t rsvd20 : 12; // 31:20
+ } ISRP_bit;
+ }; // 0x14
+
+ /* PRU_CFG_ISP register bit field */
+ union {
+ volatile uint32_t ISP;
+
+ volatile struct {
+ uint32_t PRU0_IMEM_PE : 4; // 3:0
+ uint32_t PRU0_DMEM_PE : 4; // 7:4
+ uint32_t PRU1_IMEM_PE : 4; // 11:8
+ uint32_t PRU1_DMEM_PE : 4; // 15:12
+ uint32_t RAM_PE : 4; // 19:16
+ uint32_t rsvd20 : 12; // 31:20
+ } ISP_bit;
+ }; // 0x18
+
+ /* PRU_CFG_IESP register bit field */
+ union {
+ volatile uint32_t IESP;
+
+ volatile struct {
+ uint32_t PRU0_IMEM_PE_SET : 4; // 3:0
+ uint32_t PRU0_DMEM_PE_SET : 4; // 7:4
+ uint32_t PRU1_IMEM_PE_SET : 4; // 11:8
+ uint32_t PRU1_DMEM_PE_SET : 4; // 15:12
+ uint32_t RAM_PE_SET : 4; // 19:16
+ uint32_t rsvd20 : 12; // 31:20
+ } IESP_bit;
+ }; // 0x1c
+
+ /* PRU_CFG_IECP register bit field */
+ union {
+ volatile uint32_t IECP;
+
+ volatile struct {
+ uint32_t PRU0_IMEM_PE_CLR : 4; // 3:0
+ uint32_t PRU0_DMEM_PE_CLR : 4; // 7:4
+ uint32_t PRU1_IMEM_PE_CLR : 4; // 11:8
+ uint32_t PRU1_DMEM_PE_CLR : 4; // 15:12
+ uint32_t rsvd16 : 16; // 31:16
+ } IECP_bit;
+ }; // 0x20
+
+ uint8_t rsvd24[4]; // 0x24 - 0x27
+
+ /* PRU_CFG_PMAO register bit field */
+ union {
+ volatile uint32_t PMAO;
+
+ volatile struct {
+ uint32_t PMAO_PRU0 : 1; // 0
+ uint32_t PMAO_PRU1 : 1; // 1
+ uint32_t rsvd2 : 30; // 31:2
+ } PMAO_bit;
+ }; // 0x28
+
+ uint8_t rsvd2c[4]; // 0x2c - 0x2f
+
+ /* PRU_CFG_IEPCLK register bit field */
+ union {
+ volatile uint32_t IEPCLK;
+
+ volatile struct {
+ uint32_t OCP_EN : 1; // 0
+ uint32_t rsvd1 : 31; // 31:1
+ } IEPCLK_bit;
+ }; // 0x30
+
+ /* PRU_CFG_SPP register bit field */
+ union {
+ volatile uint32_t SPP;
+
+ volatile struct {
+ uint32_t PRU1_PAD_HP_EN : 1; // 0
+ uint32_t XFR_SHIFT_EN : 1; // 1
+ uint32_t rsvd2 : 30; // 31:2
+ } SPP_bit;
+ }; // 0x34
+
+ uint8_t rsvd38[8]; // 0x38 - 0x3f
+
+ /* PRU_CFG_PIN_MX register bit field */
+ union {
+ volatile uint32_t PIN_MX;
+
+ volatile struct {
+ uint32_t PIN_MUX_SEL : 8; // 7:0
+ uint32_t PWM0_REMAP_EN : 1; // 8
+ uint32_t PWM3_REMAP_EN : 1; // 9
+ uint32_t rsvd10 : 22; // 31:10
+ } PIN_MX_bit;
+ }; // 0x40
+
+ uint8_t rsvd44[4]; // 0x44 - 0x47
+
+ volatile struct {
+ union {
+ volatile uint32_t CLKSEL;
+
+ volatile struct {
+ unsigned CLK_SEL : 2; //1:0
+ unsigned CLK_INV : 1; //2
+ unsigned rsvd3 : 1; //3
+ unsigned ACC2_SEL : 1; //4
+ unsigned rsvd5 : 27; //31:5
+ } CLKSEL_bit;
+ };
+ union {
+ volatile uint32_t SS;
+
+ volatile struct {
+ unsigned SAMPLE_SIZE : 8; //7:0
+ unsigned rsvd8 : 16; //31:8
+ } SS_bit;
+ };
+ } SD_PRU0[9];
+
+ volatile struct {
+ union {
+ volatile uint32_t CLKSEL;
+
+ volatile struct {
+ unsigned CLK_SEL : 2; //1:0
+ unsigned CLK_INV : 1; //2
+ unsigned ACC2_SEL : 1; //3
+ unsigned rsvd4 : 28; //31:4
+ } CLKSEL_bit;
+ };
+ union {
+ volatile uint32_t SS;
+
+ volatile struct {
+ unsigned SAMPLE_SIZE : 8; //7:0
+ unsigned rsvd8 : 16; //31:8
+ } SS_bit;
+ };
+ } SD_PRU1[9];
+
+ uint8_t rsvddc[4]; // 0xdc - 0xdf
+
+ /* PRU_CFG_ED_PRU0_RXCFG register bit field */
+ union {
+ volatile uint32_t ED_PRU0_RXCFG;
+
+ volatile struct {
+ uint32_t RX_SAMPLE_SIZE : 3; // 2:0
+ uint32_t rsvd3 : 1; //3
+ uint32_t RX_CLK_SEL : 1; //4
+ uint32_t rsvd5 : 10; //14:5
+ uint32_t RX_DIV_FACTOR_FRAC : 1; //15
+ uint32_t RX_DIV_FACTOR : 16; //31:16
+ } ED_PRU0_RXCFG_bit;
+ }; // 0xe0
+
+ /* PRU_CFG_ED_PRU0_TXCFG register bit field */
+ union {
+ volatile uint32_t ED_PRU0_TXCFG;
+
+ volatile struct {
+ uint32_t rsvd0 : 4; // 3:0
+ uint32_t TX_CLK_SEL : 1; // 4
+ uint32_t TX_BUSY0 : 1; // 5
+ uint32_t TX_BUSY1 : 1; // 6
+ uint32_t TX_BUSY2 : 1; // 7
+ uint32_t PRU0_ENDAT0_CLK : 1; // 8
+ uint32_t PRU0_ENDAT1_CLK : 1; // 9
+ uint32_t PRU0_ENDAT2_CLK : 1; // 10
+ uint32_t rsvd11 : 4; // 14:11
+ uint32_t TX_DIV_FACTOR_FRAC : 1; // 15
+ uint32_t TX_DIV_FACTOR : 16; // 31:16
+ } ED_PRU0_TXCFG_bit;
+ }; // 0xe4
+
+ /* PRU_CFG_ED_PRU0_CFG0_0 register bit field */
+ union {
+ volatile uint32_t ED_PRU0_CFG0_0;
+
+ volatile struct {
+ uint32_t TX_WIRE_DLY : 11; // 10:0
+ uint32_t TX_FRAME_SIZE : 5; // 15:11
+ uint32_t RX_FRAME_SIZE : 12; // 27-16
+ uint32_t PRU0_ED0_RX_SNOOP : 1; // 28
+ uint32_t ED_CLK_OUT_OVERRIDE_EN : 1; // 29
+ uint32_t PRU0_ED0_CLK : 1; // 30
+ uint32_t TX_FIFO_SWAP_BITS : 1; // 31
+ } ED_PRU0_CFG0_0_bit;
+ }; // 0xe8
+
+ /* PRU_CFG_ED_PRU0_CFG1_0 register bit field */
+ union {
+ volatile uint32_t ED_PRU0_CFG1_0;
+
+ volatile struct {
+ uint32_t TST_DELAY_COUNTER : 16; // 15:0
+ uint32_t RX_EN_COUNTER : 16; // 31:16
+ } ED_PRU0_CFG1_0_bit;
+ }; // 0xec
+
+ /* PRU_CFG_ED_PRU0_CFG0_1 register bit field */
+ union {
+ volatile uint32_t ED_PRU0_CFG0_1;
+
+ volatile struct {
+ uint32_t TX_WIRE_DLY : 11; // 10:0
+ uint32_t TX_FRAME_SIZE : 5; // 15:11
+ uint32_t RX_FRAME_SIZE : 12; // 27-16
+ uint32_t PRU0_ED1_RX_SNOOP : 1; // 28
+ uint32_t ED_CLK_OUT_OVERRIDE_EN : 1; // 29
+ uint32_t PRU0_ED1_CLK : 1; // 30
+ uint32_t TX_FIFO_SWAP_BITS : 1; // 31
+ } ED_PRU0_CFG0_1_bit;
+ }; // 0xf0
+
+ /* PRU_CFG_ED_PRU0_CFG1_1 register bit field */
+ union {
+ volatile uint32_t ED_PRU0_CFG1_1;
+
+ volatile struct {
+ uint32_t TST_DELAY_COUNTER : 16; // 15:0
+ uint32_t RX_EN_COUNTER : 16; // 31:16
+ } ED_PRU0_CFG1_1_bit;
+ }; // 0xf4
+
+ /* PRU_CFG_ED_PRU0_CFG0_2 register bit field */
+ union {
+ volatile uint32_t ED_PRU0_CFG0_2;
+
+ volatile struct {
+ uint32_t TX_WIRE_DLY : 11; // 10:0
+ uint32_t TX_FRAME_SIZE : 5; // 15:11
+ uint32_t RX_FRAME_SIZE : 12; // 27-16
+ uint32_t PRU0_ED2_RX_SNOOP : 1; // 28
+ uint32_t ED_CLK_OUT_OVERRIDE_EN : 1; // 29
+ uint32_t PRU0_ED2_CLK : 1; // 30
+ uint32_t TX_FIFO_SWAP_BITS : 1; // 31
+ } ED_PRU0_CFG0_2_bit;
+ }; // 0xf8
+
+ /* PRU_CFG_ED_PRU0_CFG1_2 register bit field */
+ union {
+ volatile uint32_t ED_PRU0_CFG1_2;
+
+ volatile struct {
+ uint32_t TST_DELAY_COUNTER : 16; // 15:0
+ uint32_t RX_EN_COUNTER : 16; // 31:16
+ } ED_PRU0_CFG1_2_bit;
+ }; // 0xfc
+
+ /* PRU_CFG_ED_PRU1_RXCFG register bit field */
+ union {
+ volatile uint32_t ED_PRU1_RXCFG;
+
+ volatile struct {
+ uint32_t RX_SAMPLE_SIZE : 3; // 2:0
+ uint32_t RX_CLK_SEL : 1; //3
+ uint32_t RX_DIV_FACTOR_FRAC : 1; //4
+ uint32_t RX_DIV_FACTOR : 16; //20:5
+ uint32_t rsvd21 : 11; //31:21
+ } ED_PRU1_RXCFG_bit;
+ }; // 0x100
+
+ /* PRU_CFG_ED_PRU1_TXCFG register bit field */
+ union {
+ volatile uint32_t ED_PRU1_TXCFG;
+
+ volatile struct {
+ uint32_t TX_CLK_SEL : 1; // 0
+ uint32_t TX_BUSY0 : 1; // 1
+ uint32_t TX_BUSY1 : 1; // 2
+ uint32_t TX_BUSY2 : 1; // 3
+ uint32_t PRU1_ENDAT0_CLK : 1; // 4
+ uint32_t PRU1_ENDAT1_CLK : 1; // 5
+ uint32_t PRU1_ENDAT2_CLK : 1; // 6
+ uint32_t TX_DIV_FACTOR_FRAC : 1; // 7
+ uint32_t TX_DIV_FACTOR : 16; // 23:8
+ uint32_t rsvd24 : 8; // 31:24
+ } ED_PRU1_TXCFG_bit;
+ }; // 0x104
+
+ /* PRU_CFG_ED_PRU1_CFG0_0 register bit field */
+ union {
+ volatile uint32_t ED_PRU1_CFG0_0;
+
+ volatile struct {
+ uint32_t TX_WIRE_DLY : 11; // 10:0
+ uint32_t TX_FRAME_SIZE : 5; // 15:11
+ uint32_t RX_FRAME_SIZE : 12; // 27-16
+ uint32_t PRU1_ED0_RX_SNOOP : 1; // 28
+ uint32_t ED_CLK_OUT_OVERRIDE_EN : 1; // 29
+ uint32_t PRU1_ED0_CLK : 1; // 30
+ uint32_t TX_FIFO_SWAP_BITS : 1; // 31
+ } ED_PRU1_CFG0_0_bit;
+ }; // 0x108
+
+ /* PRU_CFG_ED_PRU1_CFG1_0 register bit field */
+ union {
+ volatile uint32_t ED_PRU1_CFG1_0;
+
+ volatile struct {
+ uint32_t TST_DELAY_COUNTER : 16; // 15:0
+ uint32_t RX_EN_COUNTER : 16; // 31:16
+ } ED_PRU1_CFG1_0_bit;
+ }; // 0x10c
+
+ /* PRU_CFG_ED_PRU1_CFG0_1 register bit field */
+ union {
+ volatile uint32_t ED_PRU1_CFG0_1;
+
+ volatile struct {
+ uint32_t TX_WIRE_DLY : 11; // 10:0
+ uint32_t TX_FRAME_SIZE : 5; // 15:11
+ uint32_t RX_FRAME_SIZE : 12; // 27-16
+ uint32_t PRU1_ED1_RX_SNOOP : 1; // 28
+ uint32_t ED_CLK_OUT_OVERRIDE_EN : 1; // 29
+ uint32_t PRU1_ED1_CLK : 1; // 30
+ uint32_t TX_FIFO_SWAP_BITS : 1; // 31
+ } ED_PRU1_CFG0_1_bit;
+ }; // 0x110
+
+ /* PRU_CFG_ED_PRU1_CFG1_1 register bit field */
+ union {
+ volatile uint32_t ED_PRU1_CFG1_1;
+
+ volatile struct {
+ uint32_t TST_DELAY_COUNTER : 16; // 15:0
+ uint32_t RX_EN_COUNTER : 16; // 31:16
+ } ED_PRU1_CFG1_1_bit;
+ }; // 0x114
+
+ /* PRU_CFG_ED_PRU1_CFG0_2 register bit field */
+ union {
+ volatile uint32_t ED_PRU1_CFG0_2;
+
+ volatile struct {
+ uint32_t TX_WIRE_DLY : 11; // 10:0
+ uint32_t TX_FRAME_SIZE : 5; // 15:11
+ uint32_t RX_FRAME_SIZE : 12; // 27-16
+ uint32_t PRU1_ED2_RX_SNOOP : 1; // 28
+ uint32_t ED_CLK_OUT_OVERRIDE_EN : 1; // 29
+ uint32_t PRU1_ED2_CLK : 1; // 30
+ uint32_t TX_FIFO_SWAP_BITS : 1; // 31
+ } ED_PRU1_CFG0_2_bit;
+ }; // 0x118
+
+ /* PRU_CFG_ED_PRU1_CFG1_2 register bit field */
+ union {
+ volatile uint32_t ED_PRU1_CFG1_2;
+
+ volatile struct {
+ uint32_t TST_DELAY_COUNTER : 16; // 15:0
+ uint32_t RX_EN_COUNTER : 16; // 31:16
+ } ED_PRU1_CFG1_2_bit;
+ }; // 0x11c
+
+} pruCfg;
+
+volatile __far pruCfg CT_CFG __attribute__((cregister("PRU_CFG", near), peripheral));
+
+#endif /* _PRU_CFG_H_ */
+
diff --git a/firmware/icss_iolink/src/include/am437x/pru_ctrl.h b/firmware/icss_iolink/src/include/am437x/pru_ctrl.h
--- /dev/null
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRU_CTRL_H_
+#define _PRU_CTRL_H_
+
+/* PRU CTRL register set */
+typedef struct {
+
+ /* PRU_CTRL_CTRL register bit field */
+ union {
+ volatile uint32_t CTRL;
+
+ volatile struct {
+ uint32_t SOFT_RST_N : 1; // 0
+ uint32_t ENABLE : 1; // 1
+ uint32_t SLEEPING : 1; // 2
+ uint32_t COUNTER_ENABLE : 1; // 3
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t SINGLE_STEP : 1; // 8
+ uint32_t rsvd9 : 6; // 14:9
+ uint32_t RUNSTATE : 1; // 15
+ uint32_t PCOUNTER_RST_VAL : 16; // 31:16
+ } CTRL_bit;
+ }; // 0x0
+
+ /* PRU_CTRL_STS register bit field */
+ union {
+ volatile uint32_t STS;
+
+ volatile struct {
+ uint32_t PCOUNTER : 16; // 15:0
+ uint32_t rsvd16 : 16; // 31:16
+ } STS_bit;
+ }; // 0x4
+
+ /* PRU_CTRL_WAKEUP_EN register bit field */
+ union {
+ volatile uint32_t WAKEUP_EN;
+
+ volatile struct {
+ uint32_t BITWISE_ENABLES : 32; // 31:0
+ } WAKEUP_EN_bit;
+ }; // 0x8
+
+ /* PRU_CTRL_CYCLE register bit field */
+ union {
+ volatile uint32_t CYCLE;
+
+ volatile struct {
+ uint32_t CYCLECOUNT : 32; // 31:0
+ } CYCLE_bit;
+ }; // 0xc
+
+ /* PRU_CTRL_STALL register bit field */
+ union {
+ volatile uint32_t STALL;
+
+ volatile struct {
+ uint32_t STALLCOUNT : 32; // 31:0
+ } STALL_bit;
+ }; // 0x10
+
+ uint8_t rsvd14[12]; // 0x14 - 0x1f
+
+ /* PRU_CTRL_CTBIR0 register bit field */
+ union {
+ volatile uint32_t CTBIR0;
+
+ volatile struct {
+ uint32_t C24_BLK_INDEX : 8; // 7:0
+ uint32_t rsvd8 : 8; // 15:8
+ uint32_t C25_BLK_INDEX : 8; // 23:16
+ uint32_t rsvd24 : 8; // 31:24
+ } CTBIR0_bit;
+ }; // 0x20
+
+ /* PRU_CTRL_CTBIR1 register bit field */
+ union {
+ volatile uint32_t CTBIR1;
+
+ volatile struct {
+ uint32_t C26_BLK_INDEX : 8; // 7:0
+ uint32_t rsvd8 : 8; // 15:8
+ uint32_t C27_BLK_INDEX : 8; // 23:16
+ uint32_t rsvd24 : 8; // 31:24
+ } CTBIR1_bit;
+ }; // 0x24
+
+ /* PRU_CTRL_CTPPR0 register bit field */
+ union {
+ volatile uint32_t CTPPR0;
+
+ volatile struct {
+ uint32_t C28_POINTER : 16; // 15:0
+ uint32_t C29_POINTER : 16; // 31:16
+ } CTPPR0_bit;
+ }; // 0x28
+
+ /* PRU_CTRL_CTPPR1 register bit field */
+ union {
+ volatile uint32_t CTPPR1;
+
+ volatile struct {
+ uint32_t C30_POINTER : 16; // 15:0
+ uint32_t C31_POINTER : 16; // 31:16
+ } CTPPR1_bit;
+ }; // 0x2c
+
+} pruCtrl;
+
+/* Definition of control register structures. */
+#define PRU0_CTRL (*((volatile pruCtrl*)0x22000))
+#define PRU1_CTRL (*((volatile pruCtrl*)0x24000))
+
+#endif /* _PRU_CTRL_H_ */
+
diff --git a/firmware/icss_iolink/src/include/am437x/pru_ecap.h b/firmware/icss_iolink/src/include/am437x/pru_ecap.h
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRU_ECAP_H_
+#define _PRU_ECAP_H_
+
+/* PRU ECAP register set */
+typedef struct {
+
+ /* PRU_ECAP_TSCTR register bit field */
+ union {
+ volatile uint32_t TSCTR;
+
+ volatile struct {
+ uint32_t TSCTR : 32; // 31:0
+ } TSCTR_bit;
+ }; // 0x0
+
+ /* PRU_ECAP_CTRPHS register bit field */
+ union {
+ volatile uint32_t CTRPHS;
+
+ volatile struct {
+ uint32_t CTRPHS : 32; // 31:0
+ } CTRPHS_bit;
+ }; // 0x4
+
+ /* PRU_ECAP_CAP1 register bit field */
+ union {
+ volatile uint32_t CAP1;
+
+ volatile struct {
+ uint32_t CAP1 : 32; // 31:0
+ } CAP1_bit;
+ }; // 0x8
+
+ /* PRU_ECAP_CAP2 register bit field */
+ union {
+ volatile uint32_t CAP2;
+
+ volatile struct {
+ uint32_t CAP2 : 32; // 31:0
+ } CAP2_bit;
+ }; // 0xc
+
+ /* PRU_ECAP_CAP3 register bit field */
+ union {
+ volatile uint32_t CAP3;
+
+ volatile struct {
+ uint32_t CAP3 : 32; // 31:0
+ } CAP3_bit;
+ }; // 0x10
+
+ /* PRU_ECAP_CAP4 register bit field */
+ union {
+ volatile uint32_t CAP4;
+
+ volatile struct {
+ uint32_t CAP4 : 32; // 31:0
+ } CAP4_bit;
+ }; // 0x14
+
+ uint8_t rsvd18[16]; // 0x18 - 0x27
+
+ /* PRU_ECAP_ECCTL1 register bit field */
+ volatile uint16_t ECCTL1; // 0x28
+
+ /* PRU_ECAP_ECCTL2 register bit field */
+ volatile uint16_t ECCTL2; // 0x2a
+
+ /* PRU_ECAP_ECEINT register bit field */
+ volatile uint16_t ECEINT; // 0x2c
+
+ /* PRU_ECAP_ECFLG register bit field */
+ volatile uint16_t ECFLG; // 0x2e
+
+ /* PRU_ECAP_ECCLR register bit field */
+ volatile uint16_t ECCLR; // 0x30
+
+ /* PRU_ECAP_ECFRC register bit field */
+ volatile uint16_t ECFRC; // 0x32
+
+ uint8_t rsvd34[40]; // 0x34 - 0x5b
+
+ /* PRU_ECAP_REVID register bit field */
+ union {
+ volatile uint32_t REVID;
+
+ volatile struct {
+ uint32_t REV : 32; // 31:0
+ } REVID_bit;
+ }; // 0x5c
+
+} pruEcap;
+
+volatile __far pruEcap CT_ECAP __attribute__((cregister("PRU_ECAP", near), peripheral));
+
+#endif /* _PRU_ECAP_H_ */
+
diff --git a/firmware/icss_iolink/src/include/am437x/pru_iep.h b/firmware/icss_iolink/src/include/am437x/pru_iep.h
--- /dev/null
@@ -0,0 +1,343 @@
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRU_IEP_H_
+#define _PRU_IEP_H_
+
+/* PRU IEP register set */
+typedef struct {
+
+ /* PRU_IEP_TMR_GLB_CFG register bit field */
+ union {
+ volatile uint32_t TMR_GLB_CFG;
+
+ volatile struct {
+ uint32_t CNT_ENABLE : 1; // 0
+ uint32_t rsvd1 : 3; // 3:1
+ uint32_t DEFAULT_INC : 4; // 7:4
+ uint32_t CMP_INC : 12; // 19:8
+ uint32_t rsvd20 : 12; // 31:20
+ } TMR_GLB_CFG_bit;
+ }; // 0x0
+
+ /* PRU_IEP_TMR_GLB_STS register bit field */
+ union {
+ volatile uint32_t TMR_GLB_STS;
+
+ volatile struct {
+ uint32_t CNT_OVF : 1; // 0
+ uint32_t rsvd1 : 31; // 31:1
+ } TMR_GLB_STS_bit;
+ }; // 0x4
+
+ /* PRU_IEP_TMR_COMPEN register bit field */
+ union {
+ volatile uint32_t TMR_COMPEN;
+
+ volatile struct {
+ uint32_t COMPEN_CNT : 24; // 23:0
+ uint32_t rsvd24 : 8; // 31:24
+ } TMR_COMPEN_bit;
+ }; // 0x8
+
+ /* PRU_IEP_TMR_CNT register bit field */
+ union {
+ volatile uint32_t TMR_CNT;
+
+ volatile struct {
+ uint32_t COUNT : 32; // 31:0
+ } TMR_CNT_bit;
+ }; // 0xc
+
+ uint8_t rsvd10[48]; // 0x10 - 0x3f
+
+ /* PRU_IEP_TMR_CMP_CFG register bit field */
+ union {
+ volatile uint32_t TMR_CMP_CFG;
+
+ volatile struct {
+ uint32_t CMP0_RST_CNT_EN : 1; // 0
+ uint32_t CMP_EN : 8; // 8:1
+ uint32_t rsvd9 : 23; // 31:9
+ } TMR_CMP_CFG_bit;
+ }; // 0x40
+
+ /* PRU_IEP_TMR_CMP_STS register bit field */
+ union {
+ volatile uint32_t TMR_CMP_STS;
+
+ volatile struct {
+ uint32_t CMP_HIT : 8; // 7:0
+ uint32_t rsvd8 : 24; // 31:8
+ } TMR_CMP_STS_bit;
+ }; // 0x44
+
+ /* PRU_IEP_TMR_CMP0 register bit field */
+ union {
+ volatile uint32_t TMR_CMP0;
+
+ volatile struct {
+ uint32_t CMP0 : 32; // 31:0
+ } TMR_CMP0_bit;
+ }; // 0x48
+
+ /* PRU_IEP_TMR_CMP1 register bit field */
+ union {
+ volatile uint32_t TMR_CMP1;
+
+ volatile struct {
+ uint32_t CMP1 : 32; // 31:0
+ } TMR_CMP1_bit;
+ }; // 0x4c
+
+ /* PRU_IEP_TMR_CMP2 register bit field */
+ union {
+ volatile uint32_t TMR_CMP2;
+
+ volatile struct {
+ uint32_t CMP2 : 32; // 31:0
+ } TMR_CMP2_bit;
+ }; // 0x50
+
+ /* PRU_IEP_TMR_CMP3 register bit field */
+ union {
+ volatile uint32_t TMR_CMP3;
+
+ volatile struct {
+ uint32_t CMP3 : 32; // 31:0
+ } TMR_CMP3_bit;
+ }; // 0x54
+
+ /* PRU_IEP_TMR_CMP4 register bit field */
+ union {
+ volatile uint32_t TMR_CMP4;
+
+ volatile struct {
+ uint32_t CMP4 : 32; // 31:0
+ } TMR_CMP4_bit;
+ }; // 0x58
+
+ /* PRU_IEP_TMR_CMP5 register bit field */
+ union {
+ volatile uint32_t TMR_CMP5;
+
+ volatile struct {
+ uint32_t CMP5 : 32; // 31:0
+ } TMR_CMP5_bit;
+ }; // 0x5c
+
+ /* PRU_IEP_TMR_CMP6 register bit field */
+ union {
+ volatile uint32_t TMR_CMP6;
+
+ volatile struct {
+ uint32_t CMP6 : 32; // 31:0
+ } TMR_CMP6_bit;
+ }; // 0x60
+
+ /* PRU_IEP_TMR_CMP7 register bit field */
+ union {
+ volatile uint32_t TMR_CMP7;
+
+ volatile struct {
+ uint32_t CMP7 : 32; // 31:0
+ } TMR_CMP7_bit;
+ }; // 0x64
+
+ uint8_t rsvd68[32]; // 0x68 - 0x87
+
+ /* PRU_IEP_TMR_CMP8 register bit field */
+ union {
+ volatile uint32_t TMR_CMP8;
+
+ volatile struct {
+ uint32_t CMP8 : 32; // 31:0
+ } TMR_CMP8_bit;
+ }; // 0x88
+
+ /* PRU_IEP_TMR_CMP9 register bit field */
+ union {
+ volatile uint32_t TMR_CMP9;
+
+ volatile struct {
+ uint32_t CMP9 : 32; // 31:0
+ } TMR_CMP9_bit;
+ }; // 0x8c
+
+ /* PRU_IEP_TMR_CMP10 register bit field */
+ union {
+ volatile uint32_t TMR_CMP10;
+
+ volatile struct {
+ uint32_t CMP10 : 32; // 31:0
+ } TMR_CMP10_bit;
+ }; // 0x90
+
+ /* PRU_IEP_TMR_CMP11 register bit field */
+ union {
+ volatile uint32_t TMR_CMP11;
+
+ volatile struct {
+ uint32_t CMP11 : 32; // 31:0
+ } TMR_CMP11_bit;
+ }; // 0x94
+
+ /* PRU_IEP_TMR_CMP12 register bit field */
+ union {
+ volatile uint32_t TMR_CMP12;
+
+ volatile struct {
+ uint32_t CMP12 : 32; // 31:0
+ } TMR_CMP12_bit;
+ }; // 0x98
+
+ /* PRU_IEP_TMR_CMP13 register bit field */
+ union {
+ volatile uint32_t TMR_CMP13;
+
+ volatile struct {
+ uint32_t CMP13 : 32; // 31:0
+ } TMR_CMP13_bit;
+ }; // 0x9c
+
+ /* PRU_IEP_TMR_CMP14 register bit field */
+ union {
+ volatile uint32_t TMR_CMP14;
+
+ volatile struct {
+ uint32_t CMP14 : 32; // 31:0
+ } TMR_CMP14_bit;
+ }; // 0xa0
+
+ /* PRU_IEP_TMR_CMP15 register bit field */
+ union {
+ volatile uint32_t TMR_CMP15;
+
+ volatile struct {
+ uint32_t CMP15 : 32; // 31:0
+ } TMR_CMP15_bit;
+ }; // 0xa4
+
+ /* PRU_IEP_TMR_CNT_RST register bit field */
+ union {
+ volatile uint32_t TMR_CNT_RST;
+
+ volatile struct {
+ uint32_t RESET_VAL : 32; // 31:0
+ } TMR_CNT_RST_bit;
+ }; // 0xa8
+
+ /* PRU_IEP_TMR_PWM register bit field */
+ union {
+ volatile uint32_t TMR_PWM;
+
+ volatile struct {
+ uint32_t PWM0_RST_CNT_EN : 1; // 0
+ uint32_t PWM0_HIT : 1; // 1
+ uint32_t PWM3_RST_CNT_EN : 1; // 2
+ uint32_t PWM3_HIT : 1; // 3
+ uint32_t rsvd4 : 28; // 31:4
+ } TMR_PWM_bit;
+ }; // 0xac
+
+ uint8_t rsvdb0[592]; // 0xb0 - 0x2ff
+
+ /* PRU_IEP_TMR_DIGIO_CTRL register bit field */
+ union {
+ volatile uint32_t TMR_DIGIO_CTRL;
+
+ volatile struct {
+ uint32_t OUTVALID_POL : 1; // 0
+ uint32_t rsvd1 : 1; // 1
+ uint32_t BIDI_MODE : 1; // 2
+ uint32_t rsvd3 : 1; // 3
+ uint32_t IN_MODE : 2; // 5:4
+ uint32_t rsvd6 : 26; // 31:6
+ } TMR_DIGIO_CTRL_bit;
+ }; // 0x300
+
+ uint8_t rsvd304[4]; // 0x304 - 0x307
+
+ /* PRU_IEP_TMR_DIGIO_DATA_IN register bit field */
+ union {
+ volatile uint32_t TMR_DIGIO_DATA_IN;
+
+ volatile struct {
+ uint32_t DATA_IN : 32; // 31:0
+ } TMR_DIGIO_DATA_IN_bit;
+ }; // 0x308
+
+ /* PRU_IEP_TMR_DIGIO_DATA_IN_RAW register bit field */
+ union {
+ volatile uint32_t TMR_DIGIO_DATA_IN_RAW;
+
+ volatile struct {
+ uint32_t DATA_IN_RAW : 32; // 31:0
+ } TMR_DIGIO_DATA_IN_RAW_bit;
+ }; // 0x30c
+
+ /* PRU_IEP_TMR_DIGIO_DATA_OUT register bit field */
+ union {
+ volatile uint32_t TMR_DIGIO_DATA_OUT;
+
+ volatile struct {
+ uint32_t DATA_OUT : 32; // 31:0
+ } TMR_DIGIO_DATA_OUT_bit;
+ }; // 0x310
+
+ /* PRU_IEP_TMR_DIGIO_DATA_OUT_EN register bit field */
+ union {
+ volatile uint32_t TMR_DIGIO_DATA_OUT_EN;
+
+ volatile struct {
+ uint32_t DATA_OUT_EN : 32; // 31:0
+ } TMR_DIGIO_DATA_OUT_EN_bit;
+ }; // 0x314
+
+ /* PRU_IEP_TMR_DIGIO_EXP register bit field */
+ union {
+ volatile uint32_t TMR_DIGIO_EXP;
+
+ volatile struct {
+ uint32_t SW_DATA_OUT_UPDATE : 1; // 0
+ uint32_t OUTVALID_OVR_EN : 1; // 1
+ uint32_t rsvd2 : 30; // 31:2
+ } TMR_DIGIO_EXP_bit;
+ }; // 0x318
+
+} pruIep;
+
+volatile __far pruIep CT_IEP __attribute__((cregister("PRU_IEP", far), peripheral));
+
+#endif /* _PRU_IEP_H_ */
+
diff --git a/firmware/icss_iolink/src/include/am437x/pru_intc.h b/firmware/icss_iolink/src/include/am437x/pru_intc.h
--- /dev/null
@@ -0,0 +1,831 @@
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRU_INTC_H_
+#define _PRU_INTC_H_
+
+/* PRU INTC register set */
+typedef struct {
+
+ /* PRU_INTC_REVID register bit field */
+ union {
+ volatile uint32_t REVID;
+
+ volatile struct {
+ uint32_t REV_MINOR : 6; // 5:0
+ uint32_t REV_CUSTOM : 2; // 7:6
+ uint32_t REV_MAJOR : 3; // 10:8
+ uint32_t REV_RTL : 5; // 15:11
+ uint32_t REV_MODULE : 12; // 27:16
+ uint32_t rsvd28 : 2; // 29:28
+ uint32_t REV_SCHEME : 2; // 31:30
+ } REVID_bit;
+ }; // 0x0
+
+ /* PRU_INTC_CR register bit field */
+ union {
+ volatile uint32_t CR;
+
+ volatile struct {
+ uint32_t rsvd0 : 2; // 1:0
+ uint32_t NEST_MODE : 2; // 3:2
+ uint32_t rsvd4 : 28; // 31:4
+ } CR_bit;
+ }; // 0x4
+
+ uint8_t rsvd8[8]; // 0x8 - 0xf
+
+ /* PRU_INTC_GER register bit field */
+ union {
+ volatile uint32_t GER;
+
+ volatile struct {
+ uint32_t ENABLE_HINT_ANY : 1; // 0
+ uint32_t rsvd1 : 31; // 31:1
+ } GER_bit;
+ }; // 0x10
+
+ uint8_t rsvd14[8]; // 0x14 - 0x1b
+
+ /* PRU_INTC_GNLR register bit field */
+ union {
+ volatile uint32_t GNLR;
+
+ volatile struct {
+ uint32_t GLB_NEST_LEVEL : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } GNLR_bit;
+ }; // 0x1c
+
+ /* PRU_INTC_SISR register bit field */
+ union {
+ volatile uint32_t SISR;
+
+ volatile struct {
+ uint32_t STATUS_SET_INDEX : 10; // 9:0
+ uint32_t rsvd10 : 22; // 31:10
+ } SISR_bit;
+ }; // 0x20
+
+ /* PRU_INTC_SICR register bit field */
+ union {
+ volatile uint32_t SICR;
+
+ volatile struct {
+ uint32_t STATUS_CLR_INDEX : 10; // 9:0
+ uint32_t rsvd10 : 22; // 31:10
+ } SICR_bit;
+ }; // 0x24
+
+ /* PRU_INTC_EISR register bit field */
+ union {
+ volatile uint32_t EISR;
+
+ volatile struct {
+ uint32_t ENABLE_SET_INDEX : 10; // 9:0
+ uint32_t rsvd10 : 22; // 31:10
+ } EISR_bit;
+ }; // 0x28
+
+ /* PRU_INTC_EICR register bit field */
+ union {
+ volatile uint32_t EICR;
+
+ volatile struct {
+ uint32_t ENABLE_CLR_INDEX : 10; // 9:0
+ uint32_t rsvd10 : 22; // 31:10
+ } EICR_bit;
+ }; // 0x2c
+
+ uint8_t rsvd30[4]; // 0x30 - 0x33
+
+ /* PRU_INTC_HIEISR register bit field */
+ union {
+ volatile uint32_t HIEISR;
+
+ volatile struct {
+ uint32_t HINT_ENABLE_SET_INDEX : 4; // 3:0
+ uint32_t rsvd4 : 28; // 31:4
+ } HIEISR_bit;
+ }; // 0x34
+
+ /* PRU_INTC_HIDISR register bit field */
+ union {
+ volatile uint32_t HIDISR;
+
+ volatile struct {
+ uint32_t HINT_ENABLE_CLR_INDEX : 4; // 3:0
+ uint32_t rsvd4 : 28; // 31:4
+ } HIDISR_bit;
+ }; // 0x38
+
+ uint8_t rsvd3c[68]; // 0x3c - 0x7f
+
+ /* PRU_INTC_GPIR register bit field */
+ union {
+ volatile uint32_t GPIR;
+
+ volatile struct {
+ uint32_t GLB_PRI_INTR : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t GLB_NONE : 1; // 31
+ } GPIR_bit;
+ }; // 0x80
+
+ uint8_t rsvd84[380]; // 0x84 - 0x1ff
+
+ /* PRU_INTC_SRSR0 register bit field */
+ union {
+ volatile uint32_t SRSR0;
+
+ volatile struct {
+ uint32_t RAW_STATUS_31_0 : 32; // 31:0
+ } SRSR0_bit;
+ }; // 0x200
+
+ /* PRU_INTC_SRSR1 register bit field */
+ union {
+ volatile uint32_t SRSR1;
+
+ volatile struct {
+ uint32_t RAW_STATUS_63_32 : 32; // 31:0
+ } SRSR1_bit;
+ }; // 0x204
+
+ uint8_t rsvd208[120]; // 0x208 - 0x27f
+
+ /* PRU_INTC_SECR0 register bit field */
+ union {
+ volatile uint32_t SECR0;
+
+ volatile struct {
+ uint32_t ENA_STATUS_31_0 : 32; // 31:0
+ } SECR0_bit;
+ }; // 0x280
+
+ /* PRU_INTC_SECR1 register bit field */
+ union {
+ volatile uint32_t SECR1;
+
+ volatile struct {
+ uint32_t ENA_STATUS_63_32 : 32; // 31:0
+ } SECR1_bit;
+ }; // 0x284
+
+ uint8_t rsvd288[120]; // 0x288 - 0x2ff
+
+ /* PRU_INTC_ESR0 register bit field */
+ union {
+ volatile uint32_t ESR0;
+
+ volatile struct {
+ uint32_t ENABLE_SET_31_0 : 32; // 31:0
+ } ESR0_bit;
+ }; // 0x300
+
+ /* PRU_INTC_ERS1 register bit field */
+ union {
+ volatile uint32_t ERS1;
+
+ volatile struct {
+ uint32_t ENABLE_SET_63_32 : 32; // 31:0
+ } ERS1_bit;
+ }; // 0x304
+
+ uint8_t rsvd308[120]; // 0x308 - 0x37f
+
+ /* PRU_INTC_ECR0 register bit field */
+ union {
+ volatile uint32_t ECR0;
+
+ volatile struct {
+ uint32_t ENABLE_CLR_31_0 : 32; // 31:0
+ } ECR0_bit;
+ }; // 0x380
+
+ /* PRU_INTC_ECR1 register bit field */
+ union {
+ volatile uint32_t ECR1;
+
+ volatile struct {
+ uint32_t ENABLE_CLR_63_32 : 32; // 31:0
+ } ECR1_bit;
+ }; // 0x384
+
+ uint8_t rsvd388[120]; // 0x388 - 0x3ff
+
+ /* PRU_INTC_CMR0 register bit field */
+ union {
+ volatile uint32_t CMR0;
+
+ volatile struct {
+ uint32_t CH_MAP_0 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_1 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_2 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_3 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR0_bit;
+ }; // 0x400
+
+ /* PRU_INTC_CMR1 register bit field */
+ union {
+ volatile uint32_t CMR1;
+
+ volatile struct {
+ uint32_t CH_MAP_4 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_5 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_6 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_7 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR1_bit;
+ }; // 0x404
+
+ /* PRU_INTC_CMR2 register bit field */
+ union {
+ volatile uint32_t CMR2;
+
+ volatile struct {
+ uint32_t CH_MAP_8 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_9 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_10 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_11 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR2_bit;
+ }; // 0x408
+
+ /* PRU_INTC_CMR3 register bit field */
+ union {
+ volatile uint32_t CMR3;
+
+ volatile struct {
+ uint32_t CH_MAP_12 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_13 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_14 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_15 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR3_bit;
+ }; // 0x40c
+
+ /* PRU_INTC_CMR4 register bit field */
+ union {
+ volatile uint32_t CMR4;
+
+ volatile struct {
+ uint32_t CH_MAP_16 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_17 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_18 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_19 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR4_bit;
+ }; // 0x410
+
+ /* PRU_INTC_CMR5 register bit field */
+ union {
+ volatile uint32_t CMR5;
+
+ volatile struct {
+ uint32_t CH_MAP_20 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_21 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_22 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_23 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR5_bit;
+ }; // 0x414
+
+ /* PRU_INTC_CMR6 register bit field */
+ union {
+ volatile uint32_t CMR6;
+
+ volatile struct {
+ uint32_t CH_MAP_24 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_25 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_26 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_27 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR6_bit;
+ }; // 0x418
+
+ /* PRU_INTC_CMR7 register bit field */
+ union {
+ volatile uint32_t CMR7;
+
+ volatile struct {
+ uint32_t CH_MAP_28 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_29 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_30 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_31 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR7_bit;
+ }; // 0x41c
+
+ /* PRU_INTC_CMR8 register bit field */
+ union {
+ volatile uint32_t CMR8;
+
+ volatile struct {
+ uint32_t CH_MAP_32 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_33 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_34 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_35 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR8_bit;
+ }; // 0x420
+
+ /* PRU_INTC_CMR9 register bit field */
+ union {
+ volatile uint32_t CMR9;
+
+ volatile struct {
+ uint32_t CH_MAP_36 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_37 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_38 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_39 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR9_bit;
+ }; // 0x424
+
+ /* PRU_INTC_CMR10 register bit field */
+ union {
+ volatile uint32_t CMR10;
+
+ volatile struct {
+ uint32_t CH_MAP_40 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_41 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_42 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_43 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR10_bit;
+ }; // 0x428
+
+ /* PRU_INTC_CMR11 register bit field */
+ union {
+ volatile uint32_t CMR11;
+
+ volatile struct {
+ uint32_t CH_MAP_44 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_45 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_46 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_47 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR11_bit;
+ }; // 0x42c
+
+ /* PRU_INTC_CMR12 register bit field */
+ union {
+ volatile uint32_t CMR12;
+
+ volatile struct {
+ uint32_t CH_MAP_48 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_49 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_50 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_51 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR12_bit;
+ }; // 0x430
+
+ /* PRU_INTC_CMR13 register bit field */
+ union {
+ volatile uint32_t CMR13;
+
+ volatile struct {
+ uint32_t CH_MAP_52 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_53 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_54 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_55 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR13_bit;
+ }; // 0x434
+
+ /* PRU_INTC_CMR14 register bit field */
+ union {
+ volatile uint32_t CMR14;
+
+ volatile struct {
+ uint32_t CH_MAP_56 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_57 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_58 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_59 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR14_bit;
+ }; // 0x438
+
+ /* PRU_INTC_CMR15 register bit field */
+ union {
+ volatile uint32_t CMR15;
+
+ volatile struct {
+ uint32_t CH_MAP_60 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t CH_MAP_61 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t CH_MAP_62 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t CH_MAP_63 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } CMR15_bit;
+ }; // 0x43c
+
+ uint8_t rsvd440[960]; // 0x440 - 0x7ff
+
+ /* PRU_INTC_HMR0 register bit field */
+ union {
+ volatile uint32_t HMR0;
+
+ volatile struct {
+ uint32_t HINT_MAP_0 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t HINT_MAP_1 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t HINT_MAP_2 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t HINT_MAP_3 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } HMR0_bit;
+ }; // 0x800
+
+ /* PRU_INTC_HMR1 register bit field */
+ union {
+ volatile uint32_t HMR1;
+
+ volatile struct {
+ uint32_t HINT_MAP_4 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t HINT_MAP_5 : 4; // 11:8
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t HINT_MAP_6 : 4; // 19:16
+ uint32_t rsvd20 : 4; // 23:20
+ uint32_t HINT_MAP_7 : 4; // 27:24
+ uint32_t rsvd28 : 4; // 31:28
+ } HMR1_bit;
+ }; // 0x804
+
+ /* PRU_INTC_HMR2 register bit field */
+ union {
+ volatile uint32_t HMR2;
+
+ volatile struct {
+ uint32_t HINT_MAP_8 : 4; // 3:0
+ uint32_t rsvd4 : 4; // 7:4
+ uint32_t HINT_MAP_9 : 4; // 11:8
+ uint32_t rsvd12 : 20; // 31:12
+ } HMR2_bit;
+ }; // 0x808
+
+ uint8_t rsvd80c[244]; // 0x80c - 0x8ff
+
+ /* PRU_INTC_HIPIR0 register bit field */
+ union {
+ volatile uint32_t HIPIR0;
+
+ volatile struct {
+ uint32_t PRI_HINT_0 : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t NONE_HINT_0 : 1; // 31
+ } HIPIR0_bit;
+ }; // 0x900
+
+ /* PRU_INTC_HIPIR1 register bit field */
+ union {
+ volatile uint32_t HIPIR1;
+
+ volatile struct {
+ uint32_t PRI_HINT_1 : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t NONE_HINT_1 : 1; // 31
+ } HIPIR1_bit;
+ }; // 0x904
+
+ /* PRU_INTC_HIPIR2 register bit field */
+ union {
+ volatile uint32_t HIPIR2;
+
+ volatile struct {
+ uint32_t PRI_HINT_2 : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t NONE_HINT_2 : 1; // 31
+ } HIPIR2_bit;
+ }; // 0x908
+
+ /* PRU_INTC_HIPIR3 register bit field */
+ union {
+ volatile uint32_t HIPIR3;
+
+ volatile struct {
+ uint32_t PRI_HINT_3 : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t NONE_HINT_3 : 1; // 31
+ } HIPIR3_bit;
+ }; // 0x90c
+
+ /* PRU_INTC_HIPIR4 register bit field */
+ union {
+ volatile uint32_t HIPIR4;
+
+ volatile struct {
+ uint32_t PRI_HINT_4 : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t NONE_HINT_4 : 1; // 31
+ } HIPIR4_bit;
+ }; // 0x910
+
+ /* PRU_INTC_HIPIR5 register bit field */
+ union {
+ volatile uint32_t HIPIR5;
+
+ volatile struct {
+ uint32_t PRI_HINT_5 : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t NONE_HINT_5 : 1; // 31
+ } HIPIR5_bit;
+ }; // 0x914
+
+ /* PRU_INTC_HIPIR6 register bit field */
+ union {
+ volatile uint32_t HIPIR6;
+
+ volatile struct {
+ uint32_t PRI_HINT_6 : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t NONE_HINT_6 : 1; // 31
+ } HIPIR6_bit;
+ }; // 0x918
+
+ /* PRU_INTC_HIPIR7 register bit field */
+ union {
+ volatile uint32_t HIPIR7;
+
+ volatile struct {
+ uint32_t PRI_HINT_7 : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t NONE_HINT_7 : 1; // 31
+ } HIPIR7_bit;
+ }; // 0x91c
+
+ /* PRU_INTC_HIPIR8 register bit field */
+ union {
+ volatile uint32_t HIPIR8;
+
+ volatile struct {
+ uint32_t PRI_HINT_8 : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t NONE_HINT_8 : 1; // 31
+ } HIPIR8_bit;
+ }; // 0x920
+
+ /* PRU_INTC_HIPIR9 register bit field */
+ union {
+ volatile uint32_t HIPIR9;
+
+ volatile struct {
+ uint32_t PRI_HINT_9 : 10; // 9:0
+ uint32_t rsvd10 : 21; // 30:10
+ uint32_t NONE_HINT_9 : 1; // 31
+ } HIPIR9_bit;
+ }; // 0x924
+
+ uint8_t rsvd928[984]; // 0x928 - 0xcff
+
+ /* PRU_INTC_SIPR0 register bit field */
+ union {
+ volatile uint32_t SIPR0;
+
+ volatile struct {
+ uint32_t POLARITY_31_0 : 32; // 31:0
+ } SIPR0_bit;
+ }; // 0xd00
+
+ /* PRU_INTC_SIPR1 register bit field */
+ union {
+ volatile uint32_t SIPR1;
+
+ volatile struct {
+ uint32_t POLARITY_63_32 : 32; // 31:0
+ } SIPR1_bit;
+ }; // 0xd04
+
+ uint8_t rsvdd08[120]; // 0xd08 - 0xd7f
+
+ /* PRU_INTC_SITR0 register bit field */
+ union {
+ volatile uint32_t SITR0;
+
+ volatile struct {
+ uint32_t TYPE_31_0 : 32; // 31:0
+ } SITR0_bit;
+ }; // 0xd80
+
+ /* PRU_INTC_SITR1 register bit field */
+ union {
+ volatile uint32_t SITR1;
+
+ volatile struct {
+ uint32_t TYPE_63_32 : 32; // 31:0
+ } SITR1_bit;
+ }; // 0xd84
+
+ uint8_t rsvdd88[888]; // 0xd88 - 0x10ff
+
+ /* PRU_INTC_HINLR0 register bit field */
+ union {
+ volatile uint32_t HINLR0;
+
+ volatile struct {
+ uint32_t NEST_HINT_0 : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } HINLR0_bit;
+ }; // 0x1100
+
+ /* PRU_INTC_HINLR1 register bit field */
+ union {
+ volatile uint32_t HINLR1;
+
+ volatile struct {
+ uint32_t NEST_HINT_1 : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } HINLR1_bit;
+ }; // 0x1104
+
+ /* PRU_INTC_HINLR2 register bit field */
+ union {
+ volatile uint32_t HINLR2;
+
+ volatile struct {
+ uint32_t NEST_HINT_2 : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } HINLR2_bit;
+ }; // 0x1108
+
+ /* PRU_INTC_HINLR3 register bit field */
+ union {
+ volatile uint32_t HINLR3;
+
+ volatile struct {
+ uint32_t NEST_HINT_3 : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } HINLR3_bit;
+ }; // 0x110c
+
+ /* PRU_INTC_HINLR4 register bit field */
+ union {
+ volatile uint32_t HINLR4;
+
+ volatile struct {
+ uint32_t NEST_HINT_4 : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } HINLR4_bit;
+ }; // 0x1110
+
+ /* PRU_INTC_HINLR5 register bit field */
+ union {
+ volatile uint32_t HINLR5;
+
+ volatile struct {
+ uint32_t NEST_HINT_5 : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } HINLR5_bit;
+ }; // 0x1114
+
+ /* PRU_INTC_HINLR6 register bit field */
+ union {
+ volatile uint32_t HINLR6;
+
+ volatile struct {
+ uint32_t NEST_HINT_6 : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } HINLR6_bit;
+ }; // 0x1118
+
+ /* PRU_INTC_HINLR7 register bit field */
+ union {
+ volatile uint32_t HINLR7;
+
+ volatile struct {
+ uint32_t NEST_HINT_7 : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } HINLR7_bit;
+ }; // 0x111c
+
+ /* PRU_INTC_HINLR8 register bit field */
+ union {
+ volatile uint32_t HINLR8;
+
+ volatile struct {
+ uint32_t NEST_HINT_8 : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } HINLR8_bit;
+ }; // 0x1120
+
+ /* PRU_INTC_HINLR9 register bit field */
+ union {
+ volatile uint32_t HINLR9;
+
+ volatile struct {
+ uint32_t NEST_HINT_9 : 9; // 8:0
+ uint32_t rsvd9 : 22; // 30:9
+ uint32_t AUTO_OVERRIDE : 1; // 31
+ } HINLR9_bit;
+ }; // 0x1124
+
+ uint8_t rsvd1128[984]; // 0x1128 - 0x14ff
+
+ /* PRU_INTC_HIER register bit field */
+ union {
+ volatile uint32_t HIER;
+
+ volatile struct {
+ uint32_t ENABLE_HINT : 10; // 9:0
+ uint32_t rsvd10 : 22; // 31:10
+ } HIER_bit;
+ }; // 0x1500
+
+} pruIntc;
+
+volatile __far pruIntc CT_INTC __attribute__((cregister("PRU_INTC", far), peripheral));
+
+#endif /* _PRU_INTC_H_ */
+
diff --git a/firmware/icss_iolink/src/include/am437x/pru_uart.h b/firmware/icss_iolink/src/include/am437x/pru_uart.h
--- /dev/null
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRU_UART_H_
+#define _PRU_UART_H_
+
+/* UART Register set */
+typedef struct {
+
+ /*
+ * RBR and THR register pair
+ * This is a unique register pair in that RBR and THR
+ * share the same address. RBR is read-only while THR is
+ * write-only.
+ *
+ * Additionally, RBR and THR share an address with DLL. To
+ * read/write RBR/THR write 0 to the DLAB bit in the LCR
+ * register. To modify DLL write a 1.
+ *
+ * DLL also has a dedicated
+ * address which does not require toggling the DLAB bit.
+ */
+ union {
+ /* PRU_UART_RBR register bit field */
+ union {
+ volatile uint32_t RBR;
+
+ volatile struct {
+ unsigned DATA : 8; // 7:0
+ unsigned rsvd8 : 24; // 31:8
+ } RBR_bit;
+ };
+
+ /* PRU_UART_THR register bit field */
+ union {
+ volatile uint32_t THR;
+
+ volatile struct {
+ unsigned DATA : 8; // 7:0
+ unsigned rsvd8 : 24; // 31:8
+ } THR_bit;
+ };
+ }; // 0x0
+
+
+ /* PRU_UART_IER register bit field */
+ /*
+ * IER shares an address with DLH. To modify IER write 0
+ * to the DLAB bit in the LCR register. To modify DLH write a 1.
+ *
+ * DLH also has a dedicated address which does not require
+ * toggling the DLAB bit.
+ */
+ union {
+ volatile uint32_t IER;
+
+ volatile struct {
+ unsigned ERBI : 1; // 0
+ unsigned ETBEI : 1; // 1
+ unsigned ELSI : 1; // 2
+ unsigned EDSSI : 1; // 3
+ unsigned rsvd4 : 28; // 31:4
+ } IER_bit;
+ }; // 0x4
+
+
+ /*
+ * IIR and FCR register pair
+ * This is a unique register pair in that IIR and FCR
+ * share the same address. IIR is read-only while FCR is
+ * write-only.
+ */
+ union {
+ /* PRU_UART_IIR register bit field */
+ union {
+ volatile uint32_t IIR;
+
+ volatile struct {
+ unsigned IPEND : 1; // 0
+ unsigned INTID : 3; // 3:1
+ unsigned rsvd4 : 2; // 5:4
+ unsigned FIFOEN : 2; // 7:6
+ unsigned rsvd8 : 24; // 31:8
+ } IIR_bit;
+ };
+
+ /* PRU_UART_FCR register bit field */
+ union {
+ volatile uint32_t FCR;
+
+ volatile struct {
+ unsigned FIFOEN : 1; // 0
+ unsigned RXCLR : 1; // 1
+ unsigned TXCLR : 1; // 2
+ unsigned DMAMODE1 : 1; // 3
+ unsigned rsvd4 : 2; // 5:4
+ unsigned RXFIFTL : 2; // 7:6
+ unsigned rsvd8 : 24; // 31:8
+ } FCR_bit;
+ };
+ }; // 0x8
+
+
+ /* PRU_UART_LCR register bit field */
+ union {
+ volatile uint32_t LCR;
+
+ volatile struct {
+ unsigned WLS : 2; // 1:0
+ unsigned STB : 1; // 2
+ unsigned PEN : 1; // 3
+ unsigned EPS : 1; // 4
+ unsigned SP : 1; // 5
+ unsigned BC : 1; // 6
+ unsigned DLAB : 1; // 7
+ unsigned rsvd8 : 24; // 31:8
+ } LCR_bit;
+ }; // 0xC
+
+
+ /* PRU_UART_MCR register bit field */
+ union {
+ volatile uint32_t MCR;
+
+ volatile struct {
+ unsigned rsvd0 : 1; // 0
+ unsigned RTS : 1; // 1
+ unsigned OUT1 : 1; // 2
+ unsigned OUT2 : 1; // 3
+ unsigned LOOP : 1; // 4
+ unsigned AFE : 1; // 5
+ unsigned rsvd8 : 26; // 31:6
+ } MCR_bit;
+ }; // 0x10
+
+
+ /* PRU_UART_LSR register bit field */
+ union {
+ volatile uint32_t LSR;
+
+ volatile struct {
+ unsigned DR : 1; // 0
+ unsigned OE : 1; // 1
+ unsigned PE : 1; // 2
+ unsigned FE : 1; // 3
+ unsigned BI : 1; // 4
+ unsigned THRE : 1; // 5
+ unsigned TEMT : 1; // 6
+ unsigned RXFIFOE : 1; // 7
+ unsigned rsvd8 : 24; // 31:8
+ } LSR_bit;
+ }; // 0x14
+
+
+ /* PRU_UART_MSR register bit field */
+ union {
+ volatile uint32_t MSR;
+
+ volatile struct {
+ unsigned DCTS : 1; // 0
+ unsigned DDSR : 1; // 1
+ unsigned TERI : 1; // 2
+ unsigned DCD : 1; // 3
+ unsigned CTS : 1; // 4
+ unsigned DSR : 1; // 5
+ unsigned RI : 1; // 6
+ unsigned CD : 1; // 7
+ unsigned rsvd8 : 24; // 31:8
+ } MSR_bit;
+ }; // 0x18
+
+
+ /* PRU_UART_SCR register bit field */
+ union {
+ volatile uint32_t SCR;
+
+ volatile struct {
+ unsigned SCR : 8; // 7:0
+ unsigned rsvd8 : 24; // 31:8
+ } SCR_bit;
+ }; // 0x1C
+
+
+ /* PRU_UART_DLL register bit field */
+ union {
+ volatile uint32_t DLL;
+
+ volatile struct {
+ unsigned DLL : 8; // 7:0
+ unsigned rsvd8 : 24; // 31:8
+ } DLL_bit;
+ }; // 0x20
+
+
+ /* PRU_UART_DLH register bit field */
+ union {
+ volatile uint32_t DLH;
+
+ volatile struct {
+ unsigned DLH : 8; // 7:0
+ unsigned rsvd8 : 24; // 31:8
+ } DLH_bit;
+ }; // 0x24
+
+
+ /* PRU_UART_REVID1 register bit field */
+ union {
+ volatile uint32_t REVID1;
+
+ volatile struct {
+ unsigned REVID1 : 32; // 31:0
+ } REVID1_bit;
+ }; // 0x28
+
+
+ /* PRU_UART_REVID2 register bit field */
+ union {
+ volatile uint32_t REVID2;
+
+ volatile struct {
+ unsigned REVID2 : 8; // 7:0
+ unsigned rsvd8 : 24; // 31:8
+ } REVID2_bit;
+ }; // 0x2C
+
+
+ /* PRU_UART_PWREMU_MGMT register bit field */
+ union {
+ volatile uint32_t PWREMU_MGMT;
+
+ volatile struct {
+ unsigned FREE : 1; // 0
+ unsigned rsvd1 : 12; // 12:1
+ unsigned URRST : 1; // 13
+ unsigned UTRST : 1; // 14
+ unsigned rsvd15 : 17; // 31:15
+ } PWREMU_MGMT_bit;
+ }; // 0x30
+
+
+ /* PRU_UART_MDR register bit field */
+ union {
+ volatile uint32_t MDR;
+
+ volatile struct {
+ unsigned OSM_SEL : 1; // 0
+ unsigned rsvd1 : 31; // 31:1
+ } MDR_bit;
+ }; // 0x34
+
+} pruUart;
+
+volatile __far pruUart CT_UART __attribute__((cregister("PRU_UART", near), peripheral));
+
+#endif /* _PRU_UART_H_ */
diff --git a/firmware/icss_iolink/src/include/am437x/sys_adc0TscSs.h b/firmware/icss_iolink/src/include/am437x/sys_adc0TscSs.h
--- /dev/null
@@ -0,0 +1,995 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SYS_ADC0_H_
+#define _SYS_ADC0_H_
+
+/* SYS ADC0 register set */
+typedef struct {
+
+ /* SYS_ADC0_REVISION register bit field */
+ union {
+ volatile uint32_t REVISION;
+
+ volatile struct {
+ uint32_t Y_MINOR : 6; // 5:0
+ uint32_t CUSTOM : 2; // 7:6
+ uint32_t X_MAJOR : 3; // 10:8
+ uint32_t R_RTL : 5; // 15:11
+ uint32_t FUNC : 12; // 27:16
+ uint32_t rsvd28 : 2; // 29:28
+ uint32_t SCHEME : 2; // 31:30
+ } REVISION_bit;
+ }; // 0x0
+
+ uint8_t rsvd4[12]; // 0x4 - 0xf
+
+ /* SYS_ADC0_SYSCONFIG register bit field */
+ union {
+ volatile uint32_t SYSCONFIG;
+
+ volatile struct {
+ uint32_t rsvd0 : 2; // 1:0
+ uint32_t IDLEMODE : 2; // 3:2
+ uint32_t rsvd4 : 28; // 31:4
+ } SYSCONFIG_bit;
+ }; // 0x10
+
+ uint8_t rsvd14[16]; // 0x14 - 0x23
+
+ /* SYS_ADC0_IRQSTS_RAW register bit field */
+ union {
+ volatile uint32_t IRQSTS_RAW;
+
+ volatile struct {
+ uint32_t HW_PEN_EVENT_ASYNCHRONOUS : 1; // 0
+ uint32_t END_OF_SEQUENCE : 1; // 1
+ uint32_t FIFO0_THRESHOLD : 1; // 2
+ uint32_t FIFO0_OVERRUN : 1; // 3
+ uint32_t FIFO0_UNDERFLOW : 1; // 4
+ uint32_t FIFO1_THRESHOLD : 1; // 5
+ uint32_t FIFO1_OVERRUN : 1; // 6
+ uint32_t FIFO1_UNDERFLOW : 1; // 7
+ uint32_t OUT_OF_RANGE : 1; // 8
+ uint32_t PEN_UP_EVENT : 1; // 9
+ uint32_t PEN_IRQ_SYNCHRONIZED : 1; // 10
+ uint32_t rsvd11 : 21; // 31:11
+ } IRQSTS_RAW_bit;
+ }; // 0x24
+
+ /* SYS_ADC0_IRQSTS register bit field */
+ union {
+ volatile uint32_t IRQSTS;
+
+ volatile struct {
+ uint32_t HW_PEN_EVENT_ASYNCHRONOUS : 1; // 0
+ uint32_t END_OF_SEQUENCE : 1; // 1
+ uint32_t FIFO0_THRESHOLD : 1; // 2
+ uint32_t FIFO0_OVERRUN : 1; // 3
+ uint32_t FIFO0_UNDERFLOW : 1; // 4
+ uint32_t FIFO1_THRESHOLD : 1; // 5
+ uint32_t FIFO1_OVERRUN : 1; // 6
+ uint32_t FIFO1_UNDERFLOW : 1; // 7
+ uint32_t OUT_OF_RANGE : 1; // 8
+ uint32_t PEN_UP_EVENT : 1; // 9
+ uint32_t HW_PEN_EVENT_SYNCHRONOUS : 1; // 10
+ uint32_t rsvd11 : 21; // 31:11
+ } IRQSTS_bit;
+ }; // 0x28
+
+ /* SYS_ADC0_IRQEN_SET register bit field */
+ union {
+ volatile uint32_t IRQEN_SET;
+
+ volatile struct {
+ uint32_t HW_PEN_EVENT_ASYNCHRONOUS : 1; // 0
+ uint32_t END_OF_SEQUENCE : 1; // 1
+ uint32_t FIFO0_THRESHOLD : 1; // 2
+ uint32_t FIFO0_OVERRUN : 1; // 3
+ uint32_t FIFO0_UNDERFLOW : 1; // 4
+ uint32_t FIFO1_THRESHOLD : 1; // 5
+ uint32_t FIFO1_OVERRUN : 1; // 6
+ uint32_t FIFO1_UNDERFLOW : 1; // 7
+ uint32_t OUT_OF_RANGE : 1; // 8
+ uint32_t PEN_UP_EVENT : 1; // 9
+ uint32_t HW_PEN_EVENT_SYNCHRONOUS : 1; // 10
+ uint32_t rsvd11 : 21; // 31:11
+ } IRQEN_SET_bit;
+ }; // 0x2c
+
+ /* SYS_ADC0_IRQEN_CLR register bit field */
+ union {
+ volatile uint32_t IRQEN_CLR;
+
+ volatile struct {
+ uint32_t HW_PEN_EVENT_ASYNCHRONOUS : 1; // 0
+ uint32_t END_OF_SEQUENCE : 1; // 1
+ uint32_t FIFO0_THRESHOLD : 1; // 2
+ uint32_t FIFO0_OVERRUN : 1; // 3
+ uint32_t FIFO0_UNDERFLOW : 1; // 4
+ uint32_t FIFO1_THRESHOLD : 1; // 5
+ uint32_t FIFO1_OVERRUN : 1; // 6
+ uint32_t FIFO1_UNDERFLOW : 1; // 7
+ uint32_t OUT_OF_RANGE : 1; // 8
+ uint32_t PEN_UP_EVENT : 1; // 9
+ uint32_t HW_PEN_EVENT_SYNCHRONOUS : 1; // 10
+ uint32_t rsvd11 : 21; // 31:11
+ } IRQEN_CLR_bit;
+ }; // 0x30
+
+ /* SYS_ADC0_IRQWAKEUP register bit field */
+ union {
+ volatile uint32_t IRQWAKEUP;
+
+ volatile struct {
+ uint32_t WAKEEN0 : 1; // 0
+ uint32_t rsvd1 : 31; // 31:1
+ } IRQWAKEUP_bit;
+ }; // 0x34
+
+ /* SYS_ADC0_DMAEN_SET register bit field */
+ union {
+ volatile uint32_t DMAEN_SET;
+
+ volatile struct {
+ uint32_t ENABLE_0 : 1; // 0
+ uint32_t ENABLE_1 : 1; // 1
+ uint32_t rsvd2 : 30; // 31:2
+ } DMAEN_SET_bit;
+ }; // 0x38
+
+ /* SYS_ADC0_DMAEN_CLR register bit field */
+ union {
+ volatile uint32_t DMAEN_CLR;
+
+ volatile struct {
+ uint32_t ENABLE_0 : 1; // 0
+ uint32_t ENABLE_1 : 1; // 1
+ uint32_t rsvd2 : 30; // 31:2
+ } DMAEN_CLR_bit;
+ }; // 0x3c
+
+ /* SYS_ADC0_CTRL register bit field */
+ union {
+ volatile uint32_t CTRL;
+
+ volatile struct {
+ uint32_t ENABLE : 1; // 0
+ uint32_t STEP_ID_TAG : 1; // 1
+ uint32_t STEPCONFIG_WRITEPROTECT_N_ACTIVE_LOW : 1; // 2
+ uint32_t ADC_BIAS_SELECT : 1; // 3
+ uint32_t POWER_DOWN : 1; // 4
+ uint32_t AFE_PEN_CTRL : 2; // 6:5
+ uint32_t TOUCH_SCREEN_ENABLE : 1; // 7
+ uint32_t HW_EVENT_MAPPING : 1; // 8
+ uint32_t HW_PREEMPT : 1; // 9
+ uint32_t rsvd10 : 22; // 31:10
+ } CTRL_bit;
+ }; // 0x40
+
+ /* SYS_ADC0_ADCSTAT register bit field */
+ union {
+ volatile uint32_t ADCSTAT;
+
+ volatile struct {
+ uint32_t STEP_ID : 5; // 4:0
+ uint32_t FSM_BUSY : 1; // 5
+ uint32_t PEN_IRQ0 : 1; // 6
+ uint32_t PEN_IRQ1 : 1; // 7
+ uint32_t rsvd8 : 24; // 31:8
+ } ADCSTAT_bit;
+ }; // 0x44
+
+ /* SYS_ADC0_ADCRANGE register bit field */
+ union {
+ volatile uint32_t ADCRANGE;
+
+ volatile struct {
+ uint32_t LOW_RANGE_DATA : 12; // 11:0
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t HIGH_RANGE_DATA : 12; // 27:16
+ uint32_t rsvd28 : 4; // 31:28
+ } ADCRANGE_bit;
+ }; // 0x48
+
+ /* SYS_ADC0_ADC_CLKDIV register bit field */
+ union {
+ volatile uint32_t ADC_CLKDIV;
+
+ volatile struct {
+ uint32_t ADC_CLKDIV : 16; // 15:0
+ uint32_t rsvd16 : 16; // 31:16
+ } ADC_CLKDIV_bit;
+ }; // 0x4c
+
+ /* SYS_ADC0_ADC_MISC register bit field */
+ union {
+ volatile uint32_t ADC_MISC;
+
+ volatile struct {
+ uint32_t AFE_SPARE_INPUT : 4; // 3:0
+ uint32_t AFE_SPARE_OUTPUT : 4; // 7:4
+ uint32_t rsvd8 : 24; // 31:8
+ } ADC_MISC_bit;
+ }; // 0x50
+
+ /* SYS_ADC0_STEPEN register bit field */
+ union {
+ volatile uint32_t STEPEN;
+
+ volatile struct {
+ uint32_t TS_CHARGE : 1; // 0
+ uint32_t STEP1 : 1; // 1
+ uint32_t STEP2 : 1; // 2
+ uint32_t STEP3 : 1; // 3
+ uint32_t STEP4 : 1; // 4
+ uint32_t STEP5 : 1; // 5
+ uint32_t STEP6 : 1; // 6
+ uint32_t STEP7 : 1; // 7
+ uint32_t STEP8 : 1; // 8
+ uint32_t STEP9 : 1; // 9
+ uint32_t STEP10 : 1; // 10
+ uint32_t STEP11 : 1; // 11
+ uint32_t STEP12 : 1; // 12
+ uint32_t STEP13 : 1; // 13
+ uint32_t STEP14 : 1; // 14
+ uint32_t STEP15 : 1; // 15
+ uint32_t STEP16 : 1; // 16
+ uint32_t rsvd17 : 15; // 31:17
+ } STEPEN_bit;
+ }; // 0x54
+
+ /* SYS_ADC0_IDLECONFIG register bit field */
+ union {
+ volatile uint32_t IDLECONFIG;
+
+ volatile struct {
+ uint32_t rsvd0 : 5; // 4:0
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW__SWC : 1; // 6
+ uint32_t YPPSW__SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t rsvd26 : 6; // 31:26
+ } IDLECONFIG_bit;
+ }; // 0x58
+
+ /* SYS_ADC0_TS_CHARGE_STEPCONFIG register bit field */
+ union {
+ volatile uint32_t TS_CHARGE_STEPCONFIG;
+
+ volatile struct {
+ uint32_t rsvd0 : 5; // 4:0
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW__SWC : 1; // 6
+ uint32_t YPPSW__SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t rsvd26 : 6; // 31:26
+ } TS_CHARGE_STEPCONFIG_bit;
+ }; // 0x5c
+
+ /* SYS_ADC0_TS_CHARGE_DELAY register bit field */
+ union {
+ volatile uint32_t TS_CHARGE_DELAY;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 14; // 31:18
+ } TS_CHARGE_DELAY_bit;
+ }; // 0x60
+
+ /* SYS_ADC0_STEPCONFIG0 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG0;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG0_bit;
+ }; // 0x64
+
+ /* SYS_ADC0_STEPDELAY0 register bit field */
+ union {
+ volatile uint32_t STEPDELAY0;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY0_bit;
+ }; // 0x68
+
+ /* SYS_ADC0_STEPCONFIG1 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG1;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG1_bit;
+ }; // 0x6c
+
+ /* SYS_ADC0_STEPDELAY1 register bit field */
+ union {
+ volatile uint32_t STEPDELAY1;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY1_bit;
+ }; // 0x70
+
+ /* SYS_ADC0_STEPCONFIG2 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG2;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG2_bit;
+ }; // 0x74
+
+ /* SYS_ADC0_STEPDELAY2 register bit field */
+ union {
+ volatile uint32_t STEPDELAY2;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY2_bit;
+ }; // 0x78
+
+ /* SYS_ADC0_STEPCONFIG3 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG3;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG3_bit;
+ }; // 0x7c
+
+ /* SYS_ADC0_STEPDELAY3 register bit field */
+ union {
+ volatile uint32_t STEPDELAY3;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY3_bit;
+ }; // 0x80
+
+ /* SYS_ADC0_STEPCONFIG4 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG4;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG4_bit;
+ }; // 0x84
+
+ /* SYS_ADC0_STEPDELAY4 register bit field */
+ union {
+ volatile uint32_t STEPDELAY4;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY4_bit;
+ }; // 0x88
+
+ /* SYS_ADC0_STEPCONFIG5 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG5;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG5_bit;
+ }; // 0x8c
+
+ /* SYS_ADC0_STEPDELAY5 register bit field */
+ union {
+ volatile uint32_t STEPDELAY5;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY5_bit;
+ }; // 0x90
+
+ /* SYS_ADC0_STEPCONFIG6 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG6;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG6_bit;
+ }; // 0x94
+
+ /* SYS_ADC0_STEPDELAY6 register bit field */
+ union {
+ volatile uint32_t STEPDELAY6;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY6_bit;
+ }; // 0x98
+
+ /* SYS_ADC0_STEPCONFIG7 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG7;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG7_bit;
+ }; // 0x9c
+
+ /* SYS_ADC0_STEPDELAY7 register bit field */
+ union {
+ volatile uint32_t STEPDELAY7;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY7_bit;
+ }; // 0xa0
+
+ /* SYS_ADC0_STEPCONFIG8 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG8;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG8_bit;
+ }; // 0xa4
+
+ /* SYS_ADC0_STEPDELAY8 register bit field */
+ union {
+ volatile uint32_t STEPDELAY8;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY8_bit;
+ }; // 0xa8
+
+ /* SYS_ADC0_STEPCONFIG9 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG9;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG9_bit;
+ }; // 0xac
+
+ /* SYS_ADC0_STEPDELAY9 register bit field */
+ union {
+ volatile uint32_t STEPDELAY9;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY9_bit;
+ }; // 0xb0
+
+ /* SYS_ADC0_STEPCONFIG10 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG10;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG10_bit;
+ }; // 0xb4
+
+ /* SYS_ADC0_STEPDELAY10 register bit field */
+ union {
+ volatile uint32_t STEPDELAY10;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY10_bit;
+ }; // 0xb8
+
+ /* SYS_ADC0_STEPCONFIG11 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG11;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG11_bit;
+ }; // 0xbc
+
+ /* SYS_ADC0_STEPDELAY11 register bit field */
+ union {
+ volatile uint32_t STEPDELAY11;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY11_bit;
+ }; // 0xc0
+
+ /* SYS_ADC0_STEPCONFIG12 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG12;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG12_bit;
+ }; // 0xc4
+
+ /* SYS_ADC0_STEPDELAY12 register bit field */
+ union {
+ volatile uint32_t STEPDELAY12;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY12_bit;
+ }; // 0xc8
+
+ /* SYS_ADC0_STEPCONFIG13 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG13;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG13_bit;
+ }; // 0xcc
+
+ /* SYS_ADC0_STEPDELAY13 register bit field */
+ union {
+ volatile uint32_t STEPDELAY13;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY13_bit;
+ }; // 0xd0
+
+ /* SYS_ADC0_STEPCONFIG14 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG14;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG14_bit;
+ }; // 0xd4
+
+ /* SYS_ADC0_STEPDELAY14 register bit field */
+ union {
+ volatile uint32_t STEPDELAY14;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY14_bit;
+ }; // 0xd8
+
+ /* SYS_ADC0_STEPCONFIG15 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG15;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t XPPSW_SWC : 1; // 5
+ uint32_t XNNSW_SWC : 1; // 6
+ uint32_t YPPSW_SWC : 1; // 7
+ uint32_t YNNSW_SWC : 1; // 8
+ uint32_t XNPSW_SWC : 1; // 9
+ uint32_t YPNSW_SWC : 1; // 10
+ uint32_t WPNSW_SWC : 1; // 11
+ uint32_t SEL_RFP__SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM__SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK : 1; // 27
+ uint32_t rsvd28 : 4; // 31:28
+ } STEPCONFIG15_bit;
+ }; // 0xdc
+
+ /* SYS_ADC0_STEPDELAY15 register bit field */
+ union {
+ volatile uint32_t STEPDELAY15;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY15_bit;
+ }; // 0xe0
+
+ /* SYS_ADC0_FIFOCOUNT0 register bit field */
+ union {
+ volatile uint32_t FIFOCOUNT0;
+
+ volatile struct {
+ uint32_t WORDS_IN_FIFO0 : 7; // 6:0
+ uint32_t rsvd7 : 25; // 31:7
+ } FIFOCOUNT0_bit;
+ }; // 0xe4
+
+ /* SYS_ADC0_FIFOTHR0 register bit field */
+ union {
+ volatile uint32_t FIFOTHR0;
+
+ volatile struct {
+ uint32_t FIFO0_THRESHOLD_LEVEL : 6; // 5:0
+ uint32_t rsvd6 : 26; // 31:6
+ } FIFOTHR0_bit;
+ }; // 0xe8
+
+ /* SYS_ADC0_DMAREQ0 register bit field */
+ union {
+ volatile uint32_t DMAREQ0;
+
+ volatile struct {
+ uint32_t DMA_REQUEST_LEVEL : 6; // 5:0
+ uint32_t rsvd6 : 26; // 31:6
+ } DMAREQ0_bit;
+ }; // 0xec
+
+ /* SYS_ADC0_FIFOCOUNT1 register bit field */
+ union {
+ volatile uint32_t FIFOCOUNT1;
+
+ volatile struct {
+ uint32_t WORDS_IN_FIFO0 : 7; // 6:0
+ uint32_t rsvd7 : 25; // 31:7
+ } FIFOCOUNT1_bit;
+ }; // 0xf0
+
+ /* SYS_ADC0_FIFOTHR1 register bit field */
+ union {
+ volatile uint32_t FIFOTHR1;
+
+ volatile struct {
+ uint32_t FIFO0_THRESHOLD_LEVEL : 6; // 5:0
+ uint32_t rsvd6 : 26; // 31:6
+ } FIFOTHR1_bit;
+ }; // 0xf4
+
+ /* SYS_ADC0_DMAREQ1 register bit field */
+ union {
+ volatile uint32_t DMAREQ1;
+
+ volatile struct {
+ uint32_t DMA_REQUEST_LEVEL : 6; // 5:0
+ uint32_t rsvd6 : 26; // 31:6
+ } DMAREQ1_bit;
+ }; // 0xf8
+
+ uint8_t rsvdfc[4]; // 0xfc - 0xff
+
+ /* SYS_ADC0_FIFO0DATA register bit field */
+ union {
+ volatile uint32_t FIFO0DATA;
+
+ volatile struct {
+ uint32_t ADCDATA : 12; // 11:0
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t ADCCHNLID : 4; // 19:16
+ uint32_t rsvd20 : 12; // 31:20
+ } FIFO0DATA_bit;
+ }; // 0x100
+
+ uint8_t rsvd104[252]; // 0x104 - 0x1ff
+
+ /* SYS_ADC0_FIFO1DATA register bit field */
+ union {
+ volatile uint32_t FIFO1DATA;
+
+ volatile struct {
+ uint32_t ADCDATA : 12; // 11:0
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t ADCCHNLID : 4; // 19:16
+ uint32_t rsvd20 : 12; // 31:20
+ } FIFO1DATA_bit;
+ }; // 0x200
+
+} sysAdc0TscSs;
+
+/* Definition of ADC0 register structures. */
+#define ADC0_TSC_SS (*((volatile sysAdc0TscSs*)0x44E0D000))
+
+#endif /* _SYS_ADC0_H_ */
diff --git a/firmware/icss_iolink/src/include/am437x/sys_adc1MagSs.h b/firmware/icss_iolink/src/include/am437x/sys_adc1MagSs.h
--- /dev/null
@@ -0,0 +1,931 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SYS_ADC1_H_
+#define _SYS_ADC1_H_
+
+/* SYS ADC1 register set */
+typedef struct {
+
+ /* SYS_ADC1_REVISION register bit field */
+ union {
+ volatile uint32_t REVISION;
+
+ volatile struct {
+ uint32_t Y_MINOR : 6; // 5:0
+ uint32_t CUSTOM : 2; // 7:6
+ uint32_t X_MAJOR : 3; // 10:8
+ uint32_t R_RTL : 5; // 15:11
+ uint32_t FUNC : 12; // 27:16
+ uint32_t rsvd28 : 2; // 29:28
+ uint32_t SCHEME : 2; // 31:30
+ } REVISION_bit;
+ }; // 0x0
+
+ uint8_t rsvd4[12]; // 0x4 - 0xf
+
+ /* SYS_ADC1_SYSCONFIG register bit field */
+ union {
+ volatile uint32_t SYSCONFIG;
+
+ volatile struct {
+ uint32_t rsvd0 : 2; // 1:0
+ uint32_t IDLEMODE : 2; // 3:2
+ uint32_t rsvd4 : 28; // 31:4
+ } SYSCONFIG_bit;
+ }; // 0x10
+
+ uint8_t rsvd14[16]; // 0x14 - 0x23
+
+ /* SYS_ADC1_IRQSTS_RAW register bit field */
+ union {
+ volatile uint32_t IRQSTS_RAW;
+
+ volatile struct {
+ uint32_t rsvd0 : 1; // 0
+ uint32_t END_OF_SEQUENCE : 1; // 1
+ uint32_t FIFO0_THRESHOLD : 1; // 2
+ uint32_t FIFO0_OVERRUN : 1; // 3
+ uint32_t FIFO0_UNDERFLOW : 1; // 4
+ uint32_t FIFO1_THRESHOLD : 1; // 5
+ uint32_t FIFO1_OVERRUN : 1; // 6
+ uint32_t FIFO1_UNDERFLOW : 1; // 7
+ uint32_t OUT_OF_RANGE : 1; // 8
+ uint32_t START_OF_SWIPE : 1; // 9
+ uint32_t rsvd10 : 22; // 31:10
+ } IRQSTS_RAW_bit;
+ }; // 0x24
+
+ /* SYS_ADC1_IRQSTS register bit field */
+ union {
+ volatile uint32_t IRQSTS;
+
+ volatile struct {
+ uint32_t rsvd0 : 1; // 0
+ uint32_t END_OF_SEQUENCE : 1; // 1
+ uint32_t FIFO0_THRESHOLD : 1; // 2
+ uint32_t FIFO0_OVERRUN : 1; // 3
+ uint32_t FIFO0_UNDERFLOW : 1; // 4
+ uint32_t FIFO1_THRESHOLD : 1; // 5
+ uint32_t FIFO1_OVERRUN : 1; // 6
+ uint32_t FIFO1_UNDERFLOW : 1; // 7
+ uint32_t OUT_OF_RANGE : 1; // 8
+ uint32_t START_OF_SWIPE : 1; // 9
+ uint32_t rsvd10 : 22; // 31:10
+ } IRQSTS_bit;
+ }; // 0x28
+
+ /* SYS_ADC1_IRQEN_SET register bit field */
+ union {
+ volatile uint32_t IRQEN_SET;
+
+ volatile struct {
+ uint32_t rsvd0 : 1; // 0
+ uint32_t END_OF_SEQUENCE : 1; // 1
+ uint32_t FIFO0_THRESHOLD : 1; // 2
+ uint32_t FIFO0_OVERRUN : 1; // 3
+ uint32_t FIFO0_UNDERFLOW : 1; // 4
+ uint32_t FIFO1_THRESHOLD : 1; // 5
+ uint32_t FIFO1_OVERRUN : 1; // 6
+ uint32_t FIFO1_UNDERFLOW : 1; // 7
+ uint32_t OUT_OF_RANGE : 1; // 8
+ uint32_t START_OF_SWIPE : 1; // 9
+ uint32_t rsvd10 : 22; // 31:10
+ } IRQEN_SET_bit;
+ }; // 0x2c
+
+ /* SYS_ADC1_IRQEN_CLR register bit field */
+ union {
+ volatile uint32_t IRQEN_CLR;
+
+ volatile struct {
+ uint32_t rsvd0 : 1; // 0
+ uint32_t END_OF_SEQUENCE : 1; // 1
+ uint32_t FIFO0_THRESHOLD : 1; // 2
+ uint32_t FIFO0_OVERRUN : 1; // 3
+ uint32_t FIFO0_UNDERFLOW : 1; // 4
+ uint32_t FIFO1_THRESHOLD : 1; // 5
+ uint32_t FIFO1_OVERRUN : 1; // 6
+ uint32_t FIFO1_UNDERFLOW : 1; // 7
+ uint32_t OUT_OF_RANGE : 1; // 8
+ uint32_t START_OF_SWIPE : 1; // 9
+ uint32_t rsvd10 : 22; // 31:10
+ } IRQEN_CLR_bit;
+ }; // 0x30
+
+ uint8_t rsvd34[4]; // 0x34 - 0x37
+
+ /* SYS_ADC1_DMAEN_SET register bit field */
+ union {
+ volatile uint32_t DMAEN_SET;
+
+ volatile struct {
+ uint32_t ENABLE0 : 1; // 0
+ uint32_t ENABLE1 : 1; // 1
+ uint32_t rsvd2 : 30; // 31:2
+ } DMAEN_SET_bit;
+ }; // 0x38
+
+ /* SYS_ADC1_DMAEN_CLR register bit field */
+ union {
+ volatile uint32_t DMAEN_CLR;
+
+ volatile struct {
+ uint32_t ENABLE0 : 1; // 0
+ uint32_t ENABLE1 : 1; // 1
+ uint32_t rsvd2 : 30; // 31:2
+ } DMAEN_CLR_bit;
+ }; // 0x3c
+
+ /* SYS_ADC1_CTRL register bit field */
+ union {
+ volatile uint32_t CTRL;
+
+ volatile struct {
+ uint32_t ADC1_ENABLE : 1; // 0
+ uint32_t STEP_ID_TAG : 1; // 1
+ uint32_t SIMULTANEOUS_CONTROL : 1; // 2
+ uint32_t rsvd3 : 1; // 3
+ uint32_t ADC_POWER_DOWN : 1; // 4
+ uint32_t PREAMP_PD : 1; // 5
+ uint32_t PREAMP_BYPASS : 1; // 6
+ uint32_t rsvd7 : 1; // 7
+ uint32_t HW_EVENT_MAPPING : 1; // 8
+ uint32_t rsvd9 : 23; // 31:9
+ } CTRL_bit;
+ }; // 0x40
+
+ /* SYS_ADC1_ADCSTAT register bit field */
+ union {
+ volatile uint32_t ADCSTAT;
+
+ volatile struct {
+ uint32_t STEP_ID : 5; // 4:0
+ uint32_t FSM_BUSY : 1; // 5
+ uint32_t rsvd6 : 26; // 31:6
+ } ADCSTAT_bit;
+ }; // 0x44
+
+ /* SYS_ADC1_ADCRANGE register bit field */
+ union {
+ volatile uint32_t ADCRANGE;
+
+ volatile struct {
+ uint32_t THRESHOLD_LOW_RANGE_DATA : 12; // 11:0
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t THRESHOLD_HIGH_RANGE_DATA : 12; // 27:16
+ uint32_t rsvd28 : 4; // 31:28
+ } ADCRANGE_bit;
+ }; // 0x48
+
+ /* SYS_ADC1_CLKDIV register bit field */
+ union {
+ volatile uint32_t CLKDIV;
+
+ volatile struct {
+ uint32_t ADC_CLKDIV : 16; // 15:0
+ uint32_t rsvd16 : 16; // 31:16
+ } CLKDIV_bit;
+ }; // 0x4c
+
+ uint8_t rsvd50[4]; // 0x50 - 0x53
+
+ /* SYS_ADC1_STEPEN register bit field */
+ union {
+ volatile uint32_t STEPEN;
+
+ volatile struct {
+ uint32_t rsvd0 : 1; // 0
+ uint32_t STEP1 : 1; // 1
+ uint32_t STEP2 : 1; // 2
+ uint32_t STEP3 : 1; // 3
+ uint32_t STEP4 : 1; // 4
+ uint32_t STEP5 : 1; // 5
+ uint32_t STEP6 : 1; // 6
+ uint32_t STEP7 : 1; // 7
+ uint32_t STEP8 : 1; // 8
+ uint32_t STEP9 : 1; // 9
+ uint32_t STEP10 : 1; // 10
+ uint32_t STEP11 : 1; // 11
+ uint32_t STEP12 : 1; // 12
+ uint32_t STEP13 : 1; // 13
+ uint32_t STEP14 : 1; // 14
+ uint32_t STEP15 : 1; // 15
+ uint32_t STEP16 : 1; // 16
+ uint32_t rsvd17 : 15; // 31:17
+ } STEPEN_bit;
+ }; // 0x54
+
+ /* SYS_ADC1_IDLECONFIG register bit field */
+ union {
+ volatile uint32_t IDLECONFIG;
+
+ volatile struct {
+ uint32_t rsvd0 : 5; // 4:0
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t rsvd11 : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t rsvd26 : 2; // 27:26
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t rsvd30 : 2; // 31:30
+ } IDLECONFIG_bit;
+ }; // 0x58
+
+ /* SYS_ADC1_SWIPE_COMPARE_REG1_2 register bit field */
+ union {
+ volatile uint32_t SWIPE_COMPARE_REG1_2;
+
+ volatile struct {
+ uint32_t THRESHOLD_DATA2 : 12; // 11:0
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t THRESHOLD_DATA1 : 12; // 27:16
+ uint32_t rsvd28 : 4; // 31:28
+ } SWIPE_COMPARE_REG1_2_bit;
+ }; // 0x5c
+
+ /* SYS_ADC1_SWIPE_COMPARE_REG3_4 register bit field */
+ union {
+ volatile uint32_t SWIPE_COMPARE_REG3_4;
+
+ volatile struct {
+ uint32_t THRESHOLD_DATA4 : 12; // 11:0
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t THRESHOLD_DATA3 : 12; // 27:16
+ uint32_t rsvd28 : 4; // 31:28
+ } SWIPE_COMPARE_REG3_4_bit;
+ }; // 0x60
+
+ /* SYS_ADC1_STEPCONFIG1 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG1;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG1_bit;
+ }; // 0x64
+
+ /* SYS_ADC1_STEPDELAY1 register bit field */
+ union {
+ volatile uint32_t STEPDELAY1;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY1_bit;
+ }; // 0x68
+
+ /* SYS_ADC1_STEPCONFIG2 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG2;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG2_bit;
+ }; // 0x6c
+
+ /* SYS_ADC1_STEPDELAY2 register bit field */
+ union {
+ volatile uint32_t STEPDELAY2;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY2_bit;
+ }; // 0x70
+
+ /* SYS_ADC1_STEPCONFIG3 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG3;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG3_bit;
+ }; // 0x74
+
+ /* SYS_ADC1_STEPDELAY3 register bit field */
+ union {
+ volatile uint32_t STEPDELAY3;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY3_bit;
+ }; // 0x78
+
+ /* SYS_ADC1_STEPCONFIG4 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG4;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG4_bit;
+ }; // 0x7c
+
+ /* SYS_ADC1_STEPDELAY4 register bit field */
+ union {
+ volatile uint32_t STEPDELAY4;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY4_bit;
+ }; // 0x80
+
+ /* SYS_ADC1_STEPCONFIG5 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG5;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG5_bit;
+ }; // 0x84
+
+ /* SYS_ADC1_STEPDELAY5 register bit field */
+ union {
+ volatile uint32_t STEPDELAY5;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY5_bit;
+ }; // 0x88
+
+ /* SYS_ADC1_STEPCONFIG6 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG6;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG6_bit;
+ }; // 0x8c
+
+ /* SYS_ADC1_STEPDELAY6 register bit field */
+ union {
+ volatile uint32_t STEPDELAY6;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY6_bit;
+ }; // 0x90
+
+ /* SYS_ADC1_STEPCONFIG7 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG7;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG7_bit;
+ }; // 0x94
+
+ /* SYS_ADC1_STEPDELAY7 register bit field */
+ union {
+ volatile uint32_t STEPDELAY7;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY7_bit;
+ }; // 0x98
+
+ /* SYS_ADC1_STEPCONFIG8 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG8;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG8_bit;
+ }; // 0x9c
+
+ /* SYS_ADC1_STEPDELAY8 register bit field */
+ union {
+ volatile uint32_t STEPDELAY8;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY8_bit;
+ }; // 0xa0
+
+ /* SYS_ADC1_STEPCONFIG9 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG9;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG9_bit;
+ }; // 0xa4
+
+ /* SYS_ADC1_STEPDELAY9 register bit field */
+ union {
+ volatile uint32_t STEPDELAY9;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY9_bit;
+ }; // 0xa8
+
+ /* SYS_ADC1_STEPCONFIG10 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG10;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG10_bit;
+ }; // 0xac
+
+ /* SYS_ADC1_STEPDELAY10 register bit field */
+ union {
+ volatile uint32_t STEPDELAY10;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY10_bit;
+ }; // 0xb0
+
+ /* SYS_ADC1_STEPCONFIG11 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG11;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG11_bit;
+ }; // 0xb4
+
+ /* SYS_ADC1_STEPDELAY11 register bit field */
+ union {
+ volatile uint32_t STEPDELAY11;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY11_bit;
+ }; // 0xb8
+
+ /* SYS_ADC1_STEPCONFIG12 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG12;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG12_bit;
+ }; // 0xbc
+
+ /* SYS_ADC1_STEPDELAY12 register bit field */
+ union {
+ volatile uint32_t STEPDELAY12;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY12_bit;
+ }; // 0xc0
+
+ /* SYS_ADC1_STEPCONFIG13 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG13;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG13_bit;
+ }; // 0xc4
+
+ /* SYS_ADC1_STEPDELAY13 register bit field */
+ union {
+ volatile uint32_t STEPDELAY13;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY13_bit;
+ }; // 0xc8
+
+ /* SYS_ADC1_STEPCONFIG14 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG14;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG14_bit;
+ }; // 0xcc
+
+ /* SYS_ADC1_STEPDELAY14 register bit field */
+ union {
+ volatile uint32_t STEPDELAY14;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY14_bit;
+ }; // 0xd0
+
+ /* SYS_ADC1_STEPCONFIG15 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG15;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG15_bit;
+ }; // 0xd4
+
+ /* SYS_ADC1_STEPDELAY15 register bit field */
+ union {
+ volatile uint32_t STEPDELAY15;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY15_bit;
+ }; // 0xd8
+
+ /* SYS_ADC1_STEPCONFIG16 register bit field */
+ union {
+ volatile uint32_t STEPCONFIG16;
+
+ volatile struct {
+ uint32_t MODE : 2; // 1:0
+ uint32_t AVERAGING : 3; // 4:2
+ uint32_t GAIN_CONTROL1 : 2; // 6:5
+ uint32_t GAIN_CONTROL2 : 2; // 8:7
+ uint32_t GAIN_CONTROL3 : 2; // 10:9
+ uint32_t SWIPE_THRESHOLD_COMPARE_FEATURE : 1; // 11
+ uint32_t SEL_RFP_SWC_2_0 : 3; // 14:12
+ uint32_t SEL_INM_SWM_3_0 : 4; // 18:15
+ uint32_t SEL_INP_SWC_3_0 : 4; // 22:19
+ uint32_t SEL_RFM_SWC_1_0 : 2; // 24:23
+ uint32_t DIFF_CNTRL : 1; // 25
+ uint32_t FIFO_SELECT : 1; // 26
+ uint32_t RANGE_CHECK_INTERRUPT : 1; // 27
+ uint32_t GAIN_CONTROL4 : 2; // 29:28
+ uint32_t SWIPE_THRESHOLD_REGISTER_POINTER : 2; // 31:30
+ } STEPCONFIG16_bit;
+ }; // 0xdc
+
+ /* SYS_ADC1_STEPDELAY16 register bit field */
+ union {
+ volatile uint32_t STEPDELAY16;
+
+ volatile struct {
+ uint32_t OPENDELAY : 18; // 17:0
+ uint32_t rsvd18 : 6; // 23:18
+ uint32_t SAMPLEDELAY : 8; // 31:24
+ } STEPDELAY16_bit;
+ }; // 0xe0
+
+ /* SYS_ADC1_FIFO0COUNT register bit field */
+ union {
+ volatile uint32_t FIFO0COUNT;
+
+ volatile struct {
+ uint32_t WORDS_IN_FIFO0 : 7; // 6:0
+ uint32_t rsvd7 : 25; // 31:7
+ } FIFO0COUNT_bit;
+ }; // 0xe4
+
+ /* SYS_ADC1_FIFO0THR register bit field */
+ union {
+ volatile uint32_t FIFO0THR;
+
+ volatile struct {
+ uint32_t FIFO0_THRESHOLD_LEVEL : 6; // 5:0
+ uint32_t rsvd6 : 26; // 31:6
+ } FIFO0THR_bit;
+ }; // 0xe8
+
+ /* SYS_ADC1_DMA0REQ register bit field */
+ union {
+ volatile uint32_t DMA0REQ;
+
+ volatile struct {
+ uint32_t DMA_REQUEST_LEVEL : 6; // 5:0
+ uint32_t rsvd6 : 26; // 31:6
+ } DMA0REQ_bit;
+ }; // 0xec
+
+ /* SYS_ADC1_FIFO1COUNT register bit field */
+ union {
+ volatile uint32_t FIFO1COUNT;
+
+ volatile struct {
+ uint32_t WORDS_IN_FIFO1 : 7; // 6:0
+ uint32_t rsvd7 : 25; // 31:7
+ } FIFO1COUNT_bit;
+ }; // 0xf0
+
+ /* SYS_ADC1_FIFO1THR register bit field */
+ union {
+ volatile uint32_t FIFO1THR;
+
+ volatile struct {
+ uint32_t FIFO1_THRESHOLD_LEVEL : 6; // 5:0
+ uint32_t rsvd6 : 26; // 31:6
+ } FIFO1THR_bit;
+ }; // 0xf4
+
+ /* SYS_ADC1_DMA1REQ register bit field */
+ union {
+ volatile uint32_t DMA1REQ;
+
+ volatile struct {
+ uint32_t DMA_REQUEST_LEVEL : 6; // 5:0
+ uint32_t rsvd6 : 26; // 31:6
+ } DMA1REQ_bit;
+ }; // 0xf8
+
+ uint8_t rsvdfc[4]; // 0xfc - 0xff
+
+ /* SYS_ADC1_FIFO0DATA register bit field */
+ union {
+ volatile uint32_t FIFO0DATA;
+
+ volatile struct {
+ uint32_t ADCDATA : 12; // 11:0
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t ADCCHNLID : 4; // 19:16
+ uint32_t rsvd20 : 12; // 31:20
+ } FIFO0DATA_bit;
+ }; // 0x100
+
+ uint8_t rsvd104[252]; // 0x104 - 0x1ff
+
+ /* SYS_ADC1_FIFO1DATA register bit field */
+ union {
+ volatile uint32_t FIFO1DATA;
+
+ volatile struct {
+ uint32_t ADCDATA : 12; // 11:0
+ uint32_t rsvd12 : 4; // 15:12
+ uint32_t ADCCHNLID : 4; // 19:16
+ uint32_t rsvd20 : 12; // 31:20
+ } FIFO1DATA_bit;
+ }; // 0x200
+
+} sysAdc1MagSs;
+
+/* Definition of ADC1 register structures. */
+#define ADC1_MAG_SS (*((volatile sysAdc1MagSs*)0x4834C000))
+
+#endif /* _SYS_ADC1_H_ */
diff --git a/firmware/icss_iolink/src/include/am437x/sys_mailbox.h b/firmware/icss_iolink/src/include/am437x/sys_mailbox.h
--- /dev/null
@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SYS_MAILBOX_H_
+#define _SYS_MAILBOX_H_
+
+/* SYS_MAILBOX register set */
+typedef struct {
+
+ /* SYS_MAILBOX_REVISION register bit field */
+ union {
+ volatile uint32_t REVISION;
+
+ volatile struct {
+ unsigned MINOR : 6; //5:0
+ unsigned CUSTOM : 2; //7:6
+ unsigned MAJOR : 3; //10:8
+ unsigned RTL : 5; //15:11
+ unsigned FUNC : 12; //27:16
+ unsigned rsvd28 : 2; //29:28
+ unsigned SCHEME : 2; //31:30
+ } REVISION_bit;
+ }; // 0x0
+
+ uint32_t rsvd4[3]; // 0x4 - 0xC
+
+ /* SYS_MAILBOX_SYSCONFIG register bit field */
+ union {
+ volatile uint32_t SYSCONFIG;
+
+ volatile struct {
+ unsigned SOFTRESET : 1; //0
+ unsigned rsvd : 1; //1
+ unsigned SLIDLEMODE : 2; //3:2
+ unsigned rsvd1 : 28; //31:4
+ } SYSCONFIG_bit;
+ }; // 0x10
+
+ uint32_t rsvd14[11]; // 0x14 - 0x3C
+
+ /* SYS_MAILBOX_MESSAGE register bit fields */
+ union {
+ volatile uint32_t MESSAGE[8];
+
+ volatile struct {
+ unsigned MESSAGE : 32; //31:0
+ } MESSAGE_bit[8];
+ }; // 0x40-0x5C
+
+ uint32_t rsvd60[8]; // 0x60 - 0x7C
+
+ /* SYS_MAILBOX_FIFOSTATUS register bit fields */
+ union {
+ volatile uint32_t FIFOSTATUS[8];
+
+ volatile struct {
+ unsigned FIFOFULL : 1; //0
+ unsigned rsvd : 31; //31:1
+ } FIFOSTATUS_bit[8];
+ }; // 0x80-0x9C
+
+ uint32_t rsvdA0[8]; // 0xA0 - 0xBC
+
+ /* SYS_MAILBOX_MSGSTATUS register bit fields */
+ union {
+ volatile uint32_t MSGSTATUS[8];
+
+ volatile struct {
+ unsigned NBOFMSG : 3; //2:0
+ unsigned rsvd : 29; //31:3
+ } MSGSTATUS_bit[8];
+ }; // 0xC0-DC
+
+ uint32_t rsvdE0[8]; // 0xE0 - 0xFC
+
+ volatile struct {
+ union {
+ volatile uint32_t STATUS_RAW;
+
+ volatile struct {
+ unsigned NEWMSGSTATUSMB0 : 1; //0
+ unsigned NOTFULLSTATUSMB0 : 1; //1
+ unsigned NEWMSGSTATUSMB1 : 1; //2
+ unsigned NOTFULLSTATUSMB1 : 1; //3
+ unsigned NEWMSGSTATUSMB2 : 1; //4
+ unsigned NOTFULLSTATUSMB2 : 1; //5
+ unsigned NEWMSGSTATUSMB3 : 1; //6
+ unsigned NOTFULLSTATUSMB3 : 1; //7
+ unsigned NEWMSGSTATUSMB4 : 1; //8
+ unsigned NOTFULLSTATUSMB4 : 1; //9
+ unsigned NEWMSGSTATUSMB5 : 1; //10
+ unsigned NOTFULLSTATUSMB5 : 1; //11
+ unsigned NEWMSGSTATUSMB6 : 1; //12
+ unsigned NOTFULLSTATUSMB6 : 1; //13
+ unsigned NEWMSGSTATUSMB7 : 1; //14
+ unsigned NOTFULLSTATUSMB7 : 1; //15
+ unsigned rsvd : 16; //31:16
+ } STATUS_RAW_bit;
+ };
+ union {
+ volatile uint32_t STATUS_CLR;
+
+ volatile struct {
+ unsigned NEWMSGSTATUSMB0 : 1; //0
+ unsigned NOTFULLSTATUSMB0 : 1; //1
+ unsigned NEWMSGSTATUSMB1 : 1; //2
+ unsigned NOTFULLSTATUSMB1 : 1; //3
+ unsigned NEWMSGSTATUSMB2 : 1; //4
+ unsigned NOTFULLSTATUSMB2 : 1; //5
+ unsigned NEWMSGSTATUSMB3 : 1; //6
+ unsigned NOTFULLSTATUSMB3 : 1; //7
+ unsigned NEWMSGSTATUSMB4 : 1; //8
+ unsigned NOTFULLSTATUSMB4 : 1; //9
+ unsigned NEWMSGSTATUSMB5 : 1; //10
+ unsigned NOTFULLSTATUSMB5 : 1; //11
+ unsigned NEWMSGSTATUSMB6 : 1; //12
+ unsigned NOTFULLSTATUSMB6 : 1; //13
+ unsigned NEWMSGSTATUSMB7 : 1; //14
+ unsigned NOTFULLSTATUSMB7 : 1; //15
+ unsigned rsvd : 16; //31:16
+ } STATUS_CLR_bit;
+ };
+ union {
+ volatile uint32_t ENABLE_SET;
+
+ volatile struct {
+ unsigned NEWMSGSTATUSMB0 : 1; //0
+ unsigned NOTFULLSTATUSMB0 : 1; //1
+ unsigned NEWMSGSTATUSMB1 : 1; //2
+ unsigned NOTFULLSTATUSMB1 : 1; //3
+ unsigned NEWMSGSTATUSMB2 : 1; //4
+ unsigned NOTFULLSTATUSMB2 : 1; //5
+ unsigned NEWMSGSTATUSMB3 : 1; //6
+ unsigned NOTFULLSTATUSMB3 : 1; //7
+ unsigned NEWMSGSTATUSMB4 : 1; //8
+ unsigned NOTFULLSTATUSMB4 : 1; //9
+ unsigned NEWMSGSTATUSMB5 : 1; //10
+ unsigned NOTFULLSTATUSMB5 : 1; //11
+ unsigned NEWMSGSTATUSMB6 : 1; //12
+ unsigned NOTFULLSTATUSMB6 : 1; //13
+ unsigned NEWMSGSTATUSMB7 : 1; //14
+ unsigned NOTFULLSTATUSMB7 : 1; //15
+ unsigned rsvd : 16; //31:16
+ } ENABLE_SET_bit;
+ };
+ union {
+ volatile uint32_t ENABLE_CLR;
+
+ volatile struct {
+ unsigned NEWMSGSTATUSMB0 : 1; //0
+ unsigned NOTFULLSTATUSMB0 : 1; //1
+ unsigned NEWMSGSTATUSMB1 : 1; //2
+ unsigned NOTFULLSTATUSMB1 : 1; //3
+ unsigned NEWMSGSTATUSMB2 : 1; //4
+ unsigned NOTFULLSTATUSMB2 : 1; //5
+ unsigned NEWMSGSTATUSMB3 : 1; //6
+ unsigned NOTFULLSTATUSMB3 : 1; //7
+ unsigned NEWMSGSTATUSMB4 : 1; //8
+ unsigned NOTFULLSTATUSMB4 : 1; //9
+ unsigned NEWMSGSTATUSMB5 : 1; //10
+ unsigned NOTFULLSTATUSMB5 : 1; //11
+ unsigned NEWMSGSTATUSMB6 : 1; //12
+ unsigned NOTFULLSTATUSMB6 : 1; //13
+ unsigned NEWMSGSTATUSMB7 : 1; //14
+ unsigned NOTFULLSTATUSMB7 : 1; //15
+ unsigned rsvd : 16; //31:16
+ } ENABLE_CLR_bit;
+ };
+ } IRQ[4];
+
+} sysMailbox;
+
+volatile __far sysMailbox CT_MBX __attribute__((cregister("MBX0", far), peripheral));
+
+#endif /* _SYS_MAILBOX_H_ */
diff --git a/firmware/icss_iolink/src/include/am437x/sys_mcspi.h b/firmware/icss_iolink/src/include/am437x/sys_mcspi.h
--- /dev/null
@@ -0,0 +1,560 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SYS_MCSPI_H_
+#define _SYS_MCSPI_H_
+
+/* SYS MCSPI register set */
+typedef struct {
+
+ /* SYS_MCSPI_HL_REV register bit field */
+ union {
+ volatile uint32_t HL_REV;
+
+ volatile struct {
+ uint32_t Y_MINOR : 6; // 5:0
+ uint32_t CUSTOM : 2; // 7:6
+ uint32_t X_MAJOR : 3; // 10:8
+ uint32_t R_RTL : 5; // 15:11
+ uint32_t FUNC : 12; // 27:16
+ uint32_t rsvd28 : 2; // 29:28
+ uint32_t SCHEME : 2; // 31:30
+ } HL_REV_bit;
+ }; // 0x0
+
+ /* SYS_MCSPI_HL_HWINFO register bit field */
+ union {
+ volatile uint32_t HL_HWINFO;
+
+ volatile struct {
+ uint32_t USEFIFO : 1; // 0
+ uint32_t FFNBYTE : 5; // 5:1
+ uint32_t RETMODE : 1; // 6
+ uint32_t rsvd7 : 25; // 31:7
+ } HL_HWINFO_bit;
+ }; // 0x4
+
+ uint8_t rsvd8[8]; // 0x8 - 0xf
+
+ /* SYS_MCSPI_HL_SYSCONFIG register bit field */
+ union {
+ volatile uint32_t HL_SYSCONFIG;
+
+ volatile struct {
+ uint32_t SOFTRESET : 1; // 0
+ uint32_t FREEEMU : 1; // 1
+ uint32_t IDLEMODE : 2; // 3:2
+ uint32_t rsvd4 : 28; // 31:4
+ } HL_SYSCONFIG_bit;
+ }; // 0x10
+
+ uint8_t rsvd14[236]; // 0x14 - 0xff
+
+ /* SYS_MCSPI_REVISION register bit field */
+ union {
+ volatile uint32_t REVISION;
+
+ volatile struct {
+ uint32_t REV : 8; // 7:0
+ uint32_t rsvd8 : 24; // 31:8
+ } REVISION_bit;
+ }; // 0x100
+
+ uint8_t rsvd104[12]; // 0x104 - 0x10f
+
+ /* SYS_MCSPI_SYSCONFIG register bit field */
+ union {
+ volatile uint32_t SYSCONFIG;
+
+ volatile struct {
+ uint32_t AUTOIDLE : 1; // 0
+ uint32_t SOFTRESET : 1; // 1
+ uint32_t ENAWAKEUP : 1; // 2
+ uint32_t SIDLEMODE : 2; // 4:3
+ uint32_t rsvd5 : 3; // 7:5
+ uint32_t CLOCKACTIVITY : 2; // 9:8
+ uint32_t rsvd10 : 22; // 31:10
+ } SYSCONFIG_bit;
+ }; // 0x110
+
+ /* SYS_MCSPI_SYSSTS register bit field */
+ union {
+ volatile uint32_t SYSSTS;
+
+ volatile struct {
+ uint32_t RESETDONE : 1; // 0
+ uint32_t rsvd1 : 31; // 31:1
+ } SYSSTS_bit;
+ }; // 0x114
+
+ /* SYS_MCSPI_IRQSTS register bit field */
+ union {
+ volatile uint32_t IRQSTS;
+
+ volatile struct {
+ uint32_t TX0_EMPTY : 1; // 0
+ uint32_t TX0_UNDERFLOW : 1; // 1
+ uint32_t RX0_FULL : 1; // 2
+ uint32_t RX0_OVERFLOW : 1; // 3
+ uint32_t TX1_EMPTY : 1; // 4
+ uint32_t TX1_UNDERFLOW : 1; // 5
+ uint32_t RX1_FULL : 1; // 6
+ uint32_t rsvd7 : 1; // 7
+ uint32_t TX2_EMPTY : 1; // 8
+ uint32_t TX2_UNDERFLOW : 1; // 9
+ uint32_t RX2_FULL : 1; // 10
+ uint32_t rsvd11 : 1; // 11
+ uint32_t TX3_EMPTY : 1; // 12
+ uint32_t TX3_UNDERFLOW : 1; // 13
+ uint32_t RX3_FULL : 1; // 14
+ uint32_t rsvd15 : 1; // 15
+ uint32_t WKS : 1; // 16
+ uint32_t EOW : 1; // 17
+ uint32_t rsvd18 : 14; // 31:18
+ } IRQSTS_bit;
+ }; // 0x118
+
+ /* SYS_MCSPI_IRQEN register bit field */
+ union {
+ volatile uint32_t IRQEN;
+
+ volatile struct {
+ uint32_t TX0_EMPTY_ENABLE : 1; // 0
+ uint32_t TX0_UNDERFLOW_ENABLE : 1; // 1
+ uint32_t RX0_FULL_ENABLE : 1; // 2
+ uint32_t RX0_OVERFLOW_ENABLE : 1; // 3
+ uint32_t TX1_EMPTY_ENABLE : 1; // 4
+ uint32_t TX1_UNDERFLOW_ENABLE : 1; // 5
+ uint32_t RX1_FULL_ENABLE : 1; // 6
+ uint32_t rsvd7 : 1; // 7
+ uint32_t TX2_EMPTY_ENABLE : 1; // 8
+ uint32_t TX2_UNDERFLOW_ENABLE : 1; // 9
+ uint32_t RX2_FULL_ENABLE : 1; // 10
+ uint32_t rsvd11 : 1; // 11
+ uint32_t TX3_EMPTY_ENABLE : 1; // 12
+ uint32_t TX3_UNDERFLOW_ENABLE : 1; // 13
+ uint32_t RX3_FULL_ENABLE : 1; // 14
+ uint32_t rsvd15 : 1; // 15
+ uint32_t WKE : 1; // 16
+ uint32_t EOW_ENABLE : 1; // 17
+ uint32_t rsvd18 : 14; // 31:18
+ } IRQEN_bit;
+ }; // 0x11c
+
+ /* SYS_MCSPI_WAKEUPEN register bit field */
+ union {
+ volatile uint32_t WAKEUPEN;
+
+ volatile struct {
+ uint32_t WKEN : 1; // 0
+ uint32_t rsvd1 : 31; // 31:1
+ } WAKEUPEN_bit;
+ }; // 0x120
+
+ /* SYS_MCSPI_SYST register bit field */
+ union {
+ volatile uint32_t SYST;
+
+ volatile struct {
+ uint32_t SPIEN_0 : 1; // 0
+ uint32_t SPIEN_1 : 1; // 1
+ uint32_t SPIEN_2 : 1; // 2
+ uint32_t SPIEN_3 : 1; // 3
+ uint32_t SPIDAT_0 : 1; // 4
+ uint32_t SPIDAT_1 : 1; // 5
+ uint32_t SPICLK : 1; // 6
+ uint32_t WAKD : 1; // 7
+ uint32_t SPIDATDIR0 : 1; // 8
+ uint32_t SPIDATDIR1 : 1; // 9
+ uint32_t SPIENDIR : 1; // 10
+ uint32_t SSB : 1; // 11
+ uint32_t rsvd12 : 20; // 31:12
+ } SYST_bit;
+ }; // 0x124
+
+ /* SYS_MCSPI_MODULCTRL register bit field */
+ union {
+ volatile uint32_t MODULCTRL;
+
+ volatile struct {
+ uint32_t SINGLE : 1; // 0
+ uint32_t PIN34 : 1; // 1
+ uint32_t MS : 1; // 2
+ uint32_t SYSTEM_TEST : 1; // 3
+ uint32_t INITDLY : 3; // 6:4
+ uint32_t MOA : 1; // 7
+ uint32_t FDAA : 1; // 8
+ uint32_t rsvd9 : 23; // 31:9
+ } MODULCTRL_bit;
+ }; // 0x128
+
+ /* SYS_MCSPI_CH0CONF register bit field */
+ union {
+ volatile uint32_t CH0CONF;
+
+ volatile struct {
+ uint32_t PHA : 1; // 0
+ uint32_t POL : 1; // 1
+ uint32_t CLKD : 4; // 5:2
+ uint32_t EPOL : 1; // 6
+ uint32_t WL : 5; // 11:7
+ uint32_t TRM : 2; // 13:12
+ uint32_t DMAW : 1; // 14
+ uint32_t DMAR : 1; // 15
+ uint32_t DPE0 : 1; // 16
+ uint32_t DPE1 : 1; // 17
+ uint32_t IS : 1; // 18
+ uint32_t TURBO : 1; // 19
+ uint32_t FORCE : 1; // 20
+ uint32_t SPIENSLV : 2; // 22:21
+ uint32_t SBE : 1; // 23
+ uint32_t SBPOL : 1; // 24
+ uint32_t TCS0 : 2; // 26:25
+ uint32_t FFEW : 1; // 27
+ uint32_t FFER : 1; // 28
+ uint32_t CLKG : 1; // 29
+ uint32_t rsvd30 : 2; // 31:30
+ } CH0CONF_bit;
+ }; // 0x12c
+
+ /* SYS_MCSPI_CH0STAT register bit field */
+ union {
+ volatile uint32_t CH0STAT;
+
+ volatile struct {
+ uint32_t RXS : 1; // 0
+ uint32_t TXS : 1; // 1
+ uint32_t EOT : 1; // 2
+ uint32_t TXFFE : 1; // 3
+ uint32_t TXFFF : 1; // 4
+ uint32_t RXFFE : 1; // 5
+ uint32_t RXFFF : 1; // 6
+ uint32_t rsvd7 : 25; // 31:7
+ } CH0STAT_bit;
+ }; // 0x130
+
+ /* SYS_MCSPI_CH0CTRL register bit field */
+ union {
+ volatile uint32_t CH0CTRL;
+
+ volatile struct {
+ uint32_t EN : 1; // 0
+ uint32_t rsvd1 : 7; // 7:1
+ uint32_t EXTCLK : 8; // 15:8
+ uint32_t rsvd16 : 16; // 31:16
+ } CH0CTRL_bit;
+ }; // 0x134
+
+ /* SYS_MCSPI_TX0 register bit field */
+ union {
+ volatile uint32_t TX0;
+
+ volatile struct {
+ uint32_t TDATA : 32; // 31:0
+ } TX0_bit;
+ }; // 0x138
+
+ /* SYS_MCSPI_RX0 register bit field */
+ union {
+ volatile uint32_t RX0;
+
+ volatile struct {
+ uint32_t RDATA : 32; // 31:0
+ } RX0_bit;
+ }; // 0x13c
+
+ /* SYS_MCSPI_CH1CONF register bit field */
+ union {
+ volatile uint32_t CH1CONF;
+
+ volatile struct {
+ uint32_t PHA : 1; // 0
+ uint32_t POL : 1; // 1
+ uint32_t CLKD : 4; // 5:2
+ uint32_t EPOL : 1; // 6
+ uint32_t WL : 5; // 11:7
+ uint32_t TRM : 2; // 13:12
+ uint32_t DMAW : 1; // 14
+ uint32_t DMAR : 1; // 15
+ uint32_t DPE0 : 1; // 16
+ uint32_t DPE1 : 1; // 17
+ uint32_t IS : 1; // 18
+ uint32_t TURBO : 1; // 19
+ uint32_t FORCE : 1; // 20
+ uint32_t rsvd21 : 2; // 22:21
+ uint32_t SBE : 1; // 23
+ uint32_t SBPOL : 1; // 24
+ uint32_t TCS1 : 2; // 26:25
+ uint32_t FFEW : 1; // 27
+ uint32_t FFER : 1; // 28
+ uint32_t CLKG : 1; // 29
+ uint32_t rsvd30 : 2; // 31:30
+ } CH1CONF_bit;
+ }; // 0x140
+
+ /* SYS_MCSPI_CH1STAT register bit field */
+ union {
+ volatile uint32_t CH1STAT;
+
+ volatile struct {
+ uint32_t RXS : 1; // 0
+ uint32_t TXS : 1; // 1
+ uint32_t EOT : 1; // 2
+ uint32_t TXFFE : 1; // 3
+ uint32_t TXFFF : 1; // 4
+ uint32_t RXFFE : 1; // 5
+ uint32_t RXFFF : 1; // 6
+ uint32_t rsvd7 : 25; // 31:7
+ } CH1STAT_bit;
+ }; // 0x144
+
+ /* SYS_MCSPI_CH1CTRL register bit field */
+ union {
+ volatile uint32_t CH1CTRL;
+
+ volatile struct {
+ uint32_t EN : 1; // 0
+ uint32_t rsvd1 : 7; // 7:1
+ uint32_t EXTCLK : 8; // 15:8
+ uint32_t rsvd16 : 16; // 31:16
+ } CH1CTRL_bit;
+ }; // 0x148
+
+ /* SYS_MCSPI_TX1 register bit field */
+ union {
+ volatile uint32_t TX1;
+
+ volatile struct {
+ uint32_t TDATA : 32; // 31:0
+ } TX1_bit;
+ }; // 0x14c
+
+ /* SYS_MCSPI_RX1 register bit field */
+ union {
+ volatile uint32_t RX1;
+
+ volatile struct {
+ uint32_t RDATA : 32; // 31:0
+ } RX1_bit;
+ }; // 0x150
+
+ /* SYS_MCSPI_CH2CONF register bit field */
+ union {
+ volatile uint32_t CH2CONF;
+
+ volatile struct {
+ uint32_t PHA : 1; // 0
+ uint32_t POL : 1; // 1
+ uint32_t CLKD : 4; // 5:2
+ uint32_t EPOL : 1; // 6
+ uint32_t WL : 5; // 11:7
+ uint32_t TRM : 2; // 13:12
+ uint32_t DMAW : 1; // 14
+ uint32_t DMAR : 1; // 15
+ uint32_t DPE0 : 1; // 16
+ uint32_t DPE1 : 1; // 17
+ uint32_t IS : 1; // 18
+ uint32_t TURBO : 1; // 19
+ uint32_t FORCE : 1; // 20
+ uint32_t rsvd21 : 2; // 22:21
+ uint32_t SBE : 1; // 23
+ uint32_t SBPOL : 1; // 24
+ uint32_t TCS2 : 2; // 26:25
+ uint32_t FFEW : 1; // 27
+ uint32_t FFER : 1; // 28
+ uint32_t CLKG : 1; // 29
+ uint32_t rsvd30 : 2; // 31:30
+ } CH2CONF_bit;
+ }; // 0x154
+
+ /* SYS_MCSPI_CH2STAT register bit field */
+ union {
+ volatile uint32_t CH2STAT;
+
+ volatile struct {
+ uint32_t RXS : 1; // 0
+ uint32_t TXS : 1; // 1
+ uint32_t EOT : 1; // 2
+ uint32_t TXFFE : 1; // 3
+ uint32_t TXFFF : 1; // 4
+ uint32_t RXFFE : 1; // 5
+ uint32_t RXFFF : 1; // 6
+ uint32_t rsvd7 : 25; // 31:7
+ } CH2STAT_bit;
+ }; // 0x158
+
+ /* SYS_MCSPI_CH2CTRL register bit field */
+ union {
+ volatile uint32_t CH2CTRL;
+
+ volatile struct {
+ uint32_t EN : 1; // 0
+ uint32_t rsvd1 : 7; // 7:1
+ uint32_t EXTCLK : 8; // 15:8
+ uint32_t rsvd16 : 16; // 31:16
+ } CH2CTRL_bit;
+ }; // 0x15c
+
+ /* SYS_MCSPI_TX2 register bit field */
+ union {
+ volatile uint32_t TX2;
+
+ volatile struct {
+ uint32_t TDATA : 32; // 31:0
+ } TX2_bit;
+ }; // 0x160
+
+ /* SYS_MCSPI_RX2 register bit field */
+ union {
+ volatile uint32_t RX2;
+
+ volatile struct {
+ uint32_t RDATA : 32; // 31:0
+ } RX2_bit;
+ }; // 0x164
+
+ /* SYS_MCSPI_CH3CONF register bit field */
+ union {
+ volatile uint32_t CH3CONF;
+
+ volatile struct {
+ uint32_t PHA : 1; // 0
+ uint32_t POL : 1; // 1
+ uint32_t CLKD : 4; // 5:2
+ uint32_t EPOL : 1; // 6
+ uint32_t WL : 5; // 11:7
+ uint32_t TRM : 2; // 13:12
+ uint32_t DMAW : 1; // 14
+ uint32_t DMAR : 1; // 15
+ uint32_t DPE0 : 1; // 16
+ uint32_t DPE1 : 1; // 17
+ uint32_t IS : 1; // 18
+ uint32_t TURBO : 1; // 19
+ uint32_t FORCE : 1; // 20
+ uint32_t rsvd21 : 2; // 22:21
+ uint32_t SBE : 1; // 23
+ uint32_t SBPOL : 1; // 24
+ uint32_t TCS3 : 2; // 26:25
+ uint32_t FFEW : 1; // 27
+ uint32_t FFER : 1; // 28
+ uint32_t CLKG : 1; // 29
+ uint32_t rsvd30 : 2; // 31:30
+ } CH3CONF_bit;
+ }; // 0x168
+
+ /* SYS_MCSPI_CH3STAT register bit field */
+ union {
+ volatile uint32_t CH3STAT;
+
+ volatile struct {
+ uint32_t RXS : 1; // 0
+ uint32_t TXS : 1; // 1
+ uint32_t EOT : 1; // 2
+ uint32_t TXFFE : 1; // 3
+ uint32_t TXFFF : 1; // 4
+ uint32_t RXFFE : 1; // 5
+ uint32_t RXFFF : 1; // 6
+ uint32_t rsvd7 : 25; // 31:7
+ } CH3STAT_bit;
+ }; // 0x16c
+
+ /* SYS_MCSPI_CH3CTRL register bit field */
+ union {
+ volatile uint32_t CH3CTRL;
+
+ volatile struct {
+ uint32_t EN : 1; // 0
+ uint32_t rsvd1 : 7; // 7:1
+ uint32_t EXTCLK : 8; // 15:8
+ uint32_t rsvd16 : 16; // 31:16
+ } CH3CTRL_bit;
+ }; // 0x170
+
+ /* SYS_MCSPI_TX3 register bit field */
+ union {
+ volatile uint32_t TX3;
+
+ volatile struct {
+ uint32_t TDATA : 32; // 31:0
+ } TX3_bit;
+ }; // 0x174
+
+ /* SYS_MCSPI_RX3 register bit field */
+ union {
+ volatile uint32_t RX3;
+
+ volatile struct {
+ uint32_t RDATA : 32; // 31:0
+ } RX3_bit;
+ }; // 0x178
+
+ /* SYS_MCSPI_XFERLEVEL register bit field */
+ union {
+ volatile uint32_t XFERLEVEL;
+
+ volatile struct {
+ uint32_t AEL : 8; // 7:0
+ uint32_t AFL : 8; // 15:8
+ uint32_t WCNT : 16; // 31:16
+ } XFERLEVEL_bit;
+ }; // 0x17c
+
+ /* SYS_MCSPI_DAFTX register bit field */
+ union {
+ volatile uint32_t DAFTX;
+
+ volatile struct {
+ uint32_t DAFTDATA : 32; // 31:0
+ } DAFTX_bit;
+ }; // 0x180
+
+ uint8_t rsvd184[28]; // 0x184 - 0x19f
+
+ /* SYS_MCSPI_DAFRX register bit field */
+ union {
+ volatile uint32_t DAFRX;
+
+ volatile struct {
+ uint32_t DAFRDATA : 32; // 31:0
+ } DAFRX_bit;
+ }; // 0x1a0
+
+} sysMcspi;
+
+volatile __far sysMcspi CT_MCSPI0 __attribute__((cregister("MCSPI0", far), peripheral));
+volatile __far sysMcspi CT_MCSPI1 __attribute__((cregister("MCSPI1", far), peripheral));
+#define MCSPI2 (*((volatile sysMcspi*)0x481A2000))
+#define MCSPI3 (*((volatile sysMcspi*)0x481A4000))
+#define MCSPI4 (*((volatile sysMcspi*)0x48345000))
+
+#endif /* _SYS_MCSPI_H_ */
diff --git a/firmware/icss_iolink/src/include/am437x/sys_pwmss.h b/firmware/icss_iolink/src/include/am437x/sys_pwmss.h
--- /dev/null
@@ -0,0 +1,445 @@
+/*
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SYS_PWMSS_H_
+#define _SYS_PWMSS_H_
+
+/* SYS_PWMSS register set */
+typedef struct {
+
+ /***************************/
+ /* PWM Subsystem Registers */
+ /***************************/
+ /* SYS_PWMSS_IDVER register bit field */
+ union {
+ volatile uint32_t IDVER;
+
+ volatile struct {
+ unsigned Y_MINOR : 6; //5:0
+ unsigned CUSTOM : 2; //7:6
+ unsigned X_MAJOR : 3; //10:8
+ unsigned R_RTL : 5; //15:11
+ unsigned FUNC : 12; //27:16
+ unsigned rsvd28 : 2; //29:28
+ unsigned SCHEME : 2; //31:30
+ } IDVER_bit;
+ }; // 0x0
+
+ /* SYS_PWMSS_SYSCONFIG register bit field */
+ union {
+ volatile uint32_t SYSCONFIG;
+
+ volatile struct {
+ unsigned SOFTRESET : 1; //0
+ unsigned FREEEMU : 1; //1
+ unsigned IDLEMODE : 2; //3:2
+ unsigned STANDBYMODE : 2; //5:4
+ unsigned rsvd6 : 26; //31:6
+ } SYSCONFIG_bit;
+ }; // 0x4
+
+ /* SYS_PWMSS_CLKCONFIG register bit field */
+ union {
+ volatile uint32_t CLKCONFIG;
+
+ volatile struct {
+ unsigned ECAPCLK_EN : 1; //0
+ unsigned ECAPCLKSTOP_REQ : 1; //1
+ unsigned rsvd2 : 2; //3:2
+ unsigned EQEPCLK_EN : 1; //4
+ unsigned EQEPCLKSTOP_REQ : 1; //5
+ unsigned rsvd6 : 2; //7:6
+ unsigned EPWMCLK_EN : 1; //8
+ unsigned EPWMCLKSTOP_REQ : 1; //9
+ unsigned rsvd10 : 22; //31:10
+ } CLKCONFIG_bit;
+ }; // 0x8
+
+ /* SYS_PWMSS_CLKSTATUS register bit field */
+ union {
+ volatile uint32_t CLKSTATUS;
+
+ volatile struct {
+ unsigned ECAPCLK_EN_ACK : 1; //0
+ unsigned ECAPCLKSTOP_ACK : 1; //1
+ unsigned rsvd2 : 2; //3:2
+ unsigned EQEPCLK_EN_ACK : 1; //4
+ unsigned EQEPCLKSTOP_ACK : 1; //5
+ unsigned rsvd6 : 2; //7:6
+ unsigned EPWMCLK_EN_ACK : 1; //8
+ unsigned EPWMCLKSTOP_ACK : 1; //9
+ unsigned rsvd10 : 22; //31:10
+ } CLKSTATUS_bit;
+ }; // 0xC
+
+ uint32_t rsvd10[60]; // 0x10 - 0xFC
+
+ /*************************/
+ /* eCAP Module Registers */
+ /*************************/
+ /* SYS_PWMSS_ECAP_TSCTR register bit field */
+ union {
+ volatile uint32_t ECAP_TSCTR;
+
+ volatile struct {
+ unsigned TSCTR : 32; //31:0
+ } ECAP_TSCTR_bit;
+ }; // 0x100
+
+ /* SYS_PWMSS_ECAP_CTRPHS register bit field */
+ union {
+ volatile uint32_t ECAP_CTRPHS;
+
+ volatile struct {
+ unsigned CTRPHS : 32; //31:0
+ } ECAP_CTRPHS_bit;
+ }; // 0x104
+
+ /* SYS_PWMSS_ECAP_CAP1 register bit field */
+ union {
+ volatile uint32_t ECAP_CAP1;
+
+ volatile struct {
+ unsigned CAP1 : 32; //31:0
+ } ECAP_CAP1_bit;
+ }; // 0x108
+
+ /* SYS_PWMSS_ECAP_CAP2 register bit field */
+ union {
+ volatile uint32_t ECAP_CAP2;
+
+ volatile struct {
+ unsigned CAP2 : 32; //31:0
+ } ECAP_CAP2_bit;
+ }; // 0x10C
+
+ /* SYS_PWMSS_ECAP_CAP3 register bit field */
+ union {
+ volatile uint32_t ECAP_CAP3;
+
+ volatile struct {
+ unsigned CAP3 : 32; //31:0
+ } ECAP_CAP3_bit;
+ }; // 0x110
+
+ /* SYS_PWMSS_ECAP_CAP4 register bit field */
+ union {
+ volatile uint32_t ECAP_CAP4;
+
+ volatile struct {
+ unsigned CAP4 : 32; //31:0
+ } ECAP_CAP4_bit;
+ }; // 0x114
+
+ uint32_t rsvd118[4]; // 0x118 - 0x124
+
+ /* SYS_PWMSS_ECAP_ECCTL1 register bit field */
+ volatile uint16_t ECAP_ECCTL1; // 0x128
+
+ /* SYS_PWMSS_ECAP_ECCTL2 register bit field */
+ volatile uint16_t ECAP_ECCTL2; // 0x12A
+
+ /* SYS_PWMSS_ECAP_ECEINT register bit field */
+ volatile uint16_t ECAP_ECEINT; // 0x12C
+
+ /* SYS_PWMSS_ECAP_ECFLG register bit field */
+ volatile uint16_t ECAP_ECFLG; // 0x12E
+
+ /* SYS_PWMSS_ECAP_ECCLR register bit field */
+ volatile uint16_t ECAP_ECCLR; // 0x130
+
+ /* SYS_PWMSS_ECAP_ECFRC register bit field */
+ volatile uint16_t ECAP_ECFRC; // 0x132
+
+ uint32_t rsvd134[10]; // 0x134 - 0x158
+
+ /* SYS_PWMSS_ECAP_REVID register bit field */
+ union {
+ volatile uint32_t ECAP_REVID;
+
+ volatile struct {
+ unsigned REV : 32; //31:0
+ } ECAP_REVID_bit;
+ }; // 0x15C
+
+ uint32_t rsvd160[8]; // 0x160 - 0x17C
+
+ /*************************/
+ /* eQEP Module Registers */
+ /*************************/
+ /* SYS_PWMSS_EQEP_QPOSCNT register bit field */
+ union {
+ volatile uint32_t EQEP_QPOSCNT;
+
+ volatile struct {
+ unsigned QPOSCNT : 32; //31:0
+ } EQEP_QPOSCNT_bit;
+ }; // 0x180
+
+ /* SYS_PWMSS_EQEP_QPOSINIT register bit field */
+ union {
+ volatile uint32_t EQEP_QPOSINIT;
+
+ volatile struct {
+ unsigned QPOSINIT : 32; //31:0
+ } EQEP_QPOSINIT_bit;
+ }; // 0x184
+
+ /* SYS_PWMSS_EQEP_QPOSMAX register bit field */
+ union {
+ volatile uint32_t EQEP_QPOSMAX;
+
+ volatile struct {
+ unsigned QPOSMAX : 32; //31:0
+ } EQEP_QPOSMAX_bit;
+ }; // 0x188
+
+ /* SYS_PWMSS_EQEP_QPOSCMP register bit field */
+ union {
+ volatile uint32_t EQEP_QPOSCMP;
+
+ volatile struct {
+ unsigned QPOSCMP : 32; //31:0
+ } EQEP_QPOSCMP_bit;
+ }; // 0x18C
+
+ /* SYS_PWMSS_EQEP_QPOSILAT register bit field */
+ union {
+ volatile uint32_t EQEP_QPOSILAT;
+
+ volatile struct {
+ unsigned QPOSILAT : 32; //31:0
+ } EQEP_QPOSILAT_bit;
+ }; // 0x190
+
+ /* SYS_PWMSS_EQEP_QPOSSLAT register bit field */
+ union {
+ volatile uint32_t EQEP_QPOSSLAT;
+
+ volatile struct {
+ unsigned QPOSSLAT : 32; //31:0
+ } EQEP_QPOSSLAT_bit;
+ }; // 0x194
+
+ /* SYS_PWMSS_EQEP_QPOSLAT register bit field */
+ union {
+ volatile uint32_t EQEP_QPOSLAT;
+
+ volatile struct {
+ unsigned QPOSLAT : 32; //31:0
+ } EQEP_QPOSLAT_bit;
+ }; // 0x198
+
+ /* SYS_PWMSS_EQEP_QUTMR register bit field */
+ union {
+ volatile uint32_t EQEP_QUTMR;
+
+ volatile struct {
+ unsigned QUTMR : 32; //31:0
+ } EQEP_QUTMR_bit;
+ }; // 0x19C
+
+ /* SYS_PWMSS_EQEP_QUPRD register bit field */
+ union {
+ volatile uint32_t EQEP_QUPRD;
+
+ volatile struct {
+ unsigned QUPRD : 32; //31:0
+ } EQEP_QUPRD_bit;
+ }; // 0x1A0
+
+ /* SYS_PWMSS_EQEP_QWDTMR register bit field */
+ volatile uint16_t EQEP_QWDTMR; // 0x1A4
+
+ /* SYS_PWMSS_EQEP_QWDPRD register bit field */
+ volatile uint16_t EQEP_QWDPRD; // 0x1A6
+
+ /* SYS_PWMSS_EQEP_QDECCTL register bit field */
+ volatile uint16_t EQEP_QDECCTL; // 0x1A8
+
+ /* SYS_PWMSS_EQEP_QEPCTL register bit field */
+ volatile uint16_t EQEP_QEPCTL; // 0x1AA
+
+ /* SYS_PWMSS_EQEP_QCAPCTL register bit field */
+ volatile uint16_t EQEP_QCAPCTL; // 0x1AC
+
+ /* SYS_PWMSS_EQEP_QPOSCTL register bit field */
+ volatile uint16_t EQEP_QPOSCTL; // 0x1AE
+
+ /* SYS_PWMSS_EQEP_QEINT register bit field */
+ volatile uint16_t EQEP_QEINT; // 0x1B0
+
+ /* SYS_PWMSS_EQEP_QFLG register bit field */
+ volatile uint16_t EQEP_QFLG; // 0x1B2
+
+ /* SYS_PWMSS_EQEP_QCLR register bit field */
+ volatile uint16_t EQEP_QCLR; // 0x1B4
+
+ /* SYS_PWMSS_EQEP_QFRC register bit field */
+ volatile uint16_t EQEP_QFRC; // 0x1B6
+
+ /* SYS_PWMSS_EQEP_QEPSTS register bit field */
+ volatile uint16_t EQEP_QEPSTS; // 0x1B8
+
+ /* SYS_PWMSS_EQEP_QCTMR register bit field */
+ volatile uint16_t EQEP_QCTMR; // 0x1BA
+
+ /* SYS_PWMSS_EQEP_QCPRD register bit field */
+ volatile uint16_t EQEP_QCPRD; // 0x1BC
+
+ /* SYS_PWMSS_EQEP_QCTMRLAT register bit field */
+ volatile uint16_t EQEP_QCTMRLAT; // 0x1BE
+
+ /* SYS_PWMSS_EQEP_QCPRDLAT register bit field */
+ volatile uint16_t EQEP_QCPRDLAT; // 0x1C0
+
+ uint16_t rsvd1C2[1]; // 0x1C2 - 0x1C3
+ uint32_t rsvd1C4[6]; // 0x1C4 - 0x1D8
+
+ /* SYS_PWMSS_EQEP_REVID register bit field */
+ union {
+ volatile uint32_t EQEP_REVID;
+
+ volatile struct {
+ unsigned REVID : 32; //31:0
+ } EQEP_REVID_bit;
+ }; // 0x1DC
+
+ uint32_t rsvd1E0[8]; // 0x1E0 - 0x1FC
+
+ /*************************/
+ /* ePWM Module Registers */
+ /*************************/
+ /* SYS_PWMSS_EPWM_TBCTL register bit field */
+ volatile uint16_t EPWM_TBCTL; // 0x200
+
+ /* SYS_PWMSS_EPWM_TBSTS register bit field */
+ volatile uint16_t EPWM_TBSTS; // 0x202
+
+ /* SYS_PWMSS_EPWM_TBPHSHR register bit field */
+ volatile uint16_t EPWM_TBPHSHR; // 0x204
+
+ /* SYS_PWMSS_EPWM_TBPHS register bit field */
+ volatile uint16_t EPWM_TBPHS; // 0x206
+
+ /* SYS_PWMSS_EPWM_TBCNT register bit field */
+ volatile uint16_t EPWM_TBCNT; // 0x208
+
+ /* SYS_PWMSS_EPWM_TBPRD register bit field */
+ volatile uint16_t EPWM_TBPRD; // 0x20A
+
+ uint16_t rsvd20C[1]; // 0x20C - 0x20D
+
+ /* SYS_PWMSS_EPWM_CMPCTL register bit field */
+ volatile uint16_t EPWM_CMPCTL; // 0x20E
+
+ /* SYS_PWMSS_EPWM_CMPAHR register bit field */
+ volatile uint16_t EPWM_CMPAHR; // 0x210
+
+ /* SYS_PWMSS_EPWM_CMPA register bit field */
+ volatile uint16_t EPWM_CMPA; // 0x212
+
+ /* SYS_PWMSS_EPWM_CMPB register bit field */
+ volatile uint16_t EPWM_CMPB; // 0x214
+
+ /* SYS_PWMSS_EPWM_AQCTLA register bit field */
+ volatile uint16_t EPWM_AQCTLA; // 0x216
+
+ /* SYS_PWMSS_EPWM_AQCTLB register bit field */
+ volatile uint16_t EPWM_AQCTLB; // 0x218
+
+ /* SYS_PWMSS_EPWM_AQSFRC register bit field */
+ volatile uint16_t EPWM_AQSFRC; // 0x21A
+
+ /* SYS_PWMSS_EPWM_AQCSFRC register bit field */
+ volatile uint16_t EPWM_AQCSFRC; // 0x21C
+
+ /* SYS_PWMSS_EPWM_DBCTL register bit field */
+ volatile uint16_t EPWM_DBCTL; // 0x21E
+
+ /* SYS_PWMSS_EPWM_DBRED register bit field */
+ volatile uint16_t EPWM_DBRED; // 0x220
+
+ /* SYS_PWMSS_EPWM_DBFED register bit field */
+ volatile uint16_t EPWM_DBFED; // 0x222
+
+ /* SYS_PWMSS_EPWM_TZSEL register bit field */
+ volatile uint16_t EPWM_TZSEL; // 0x224
+
+ uint16_t rsvd226[1]; // 0x226 - 0x227
+
+ /* SYS_PWMSS_EPWM_TZCTL register bit field */
+ volatile uint16_t EPWM_TZCTL; // 0x228
+
+ /* SYS_PWMSS_EPWM_TZEINT register bit field */
+ volatile uint16_t EPWM_TZEINT; // 0x22A
+
+ /* SYS_PWMSS_EPWM_TZFLG register bit field */
+ volatile uint16_t EPWM_TZFLG; // 0x22C
+
+ /* SYS_PWMSS_EPWM_TZCLR register bit field */
+ volatile uint16_t EPWM_TZCLR; // 0x22E
+
+ /* SYS_PWMSS_EPWM_TZFRC register bit field */
+ volatile uint16_t EPWM_TZFRC; // 0x230
+
+ /* SYS_PWMSS_EPWM_ETSEL register bit field */
+ volatile uint16_t EPWM_ETSEL; // 0x232
+
+ /* SYS_PWMSS_EPWM_ETPS register bit field */
+ volatile uint16_t EPWM_ETPS; // 0x234
+
+ /* SYS_PWMSS_EPWM_ETFLG register bit field */
+ volatile uint16_t EPWM_ETFLG; // 0x236
+
+ /* SYS_PWMSS_EPWM_ETCLR register bit field */
+ volatile uint16_t EPWM_ETCLR; // 0x238
+
+ /* SYS_PWMSS_EPWM_ETFRC register bit field */
+ volatile uint16_t EPWM_ETFRC; // 0x23A
+
+ /* SYS_PWMSS_EPWM_PCCTL register bit field */
+ volatile uint16_t EPWM_PCCTL; // 0x23C
+
+ uint16_t rsvd23E[1]; // 0x23E - 0x23F
+
+ /* SYS_PWMSS_EPWM_HRCTL register bit field */
+ volatile uint16_t EPWM_HRCTL; // 0x240
+
+} sysPwmss;
+
+volatile __far sysPwmss PWMSS0 __attribute__((cregister("PWMSS0", far), peripheral));
+volatile __far sysPwmss PWMSS1 __attribute__((cregister("PWMSS1", far), peripheral));
+volatile __far sysPwmss PWMSS2 __attribute__((cregister("PWMSS2", far), peripheral));
+
+#endif /* _SYS_PWMSS_H_ */
diff --git a/firmware/icss_iolink/src/include/io_link_master/defines.inc b/firmware/icss_iolink/src/include/io_link_master/defines.inc
--- /dev/null
@@ -0,0 +1,86 @@
+; Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; file: defines.inc
+;
+; brief: PRU IO-Link master defines
+
+;defines.inc
+;PRU IO-Link Master
+;ICSS0 PRU0
+;v0.1
+
+ ;hard coded timings
+ .asg "5", t2_time ;hard coded t2 time (Tbit)
+
+ ;status codes
+ .asg "0x0", status_idle
+ .asg "0x1", status_complete
+
+ ;State machine encoding
+ .asg "0x0", idle
+ .asg "0x1", idle_startpulse
+ .asg "0x2", idle_startpulseCount
+ .asg "0x3", idle_startpulseFin
+ .asg "0x4", rx_idle
+ .asg "0x5", rx_get
+ .asg "0x6", tx_setup
+ .asg "0x7", tx_start
+ .asg "0x8", tx_nxtMsg
+ .asg "0x9", tx_transmit
+ .asg "0xA", tx_complete
+ .asg "0xB", final
+
+ ;RX and TX pin definition
+ ;GPI / GPO pins of the PRU (R30)
+ ;these pins are much faster as GPIO pins and can be written in a single PRU cycle
+ .asg "0", rx0_pin ;N24 J16 Pin 31
+ .asg "1", rx1_pin ;N22 J16 Pin 33
+ .asg "2", rx2_pin ;H23 J16 Pin 35
+ .asg "3", rx3_pin ;M24 J16 Pin 32
+ .asg "4", rx4_pin ;L23 J16 Pin 34
+ .asg "5", rx5_pin ;K23 J16 Pin 36
+ .asg "6", rx6_pin ;M25 J16 Pin 52
+ .asg "7", rx7_pin ;L24 J16 Pin 54
+
+ .asg "8", tx0_pin ;B1 J16 Pin 56
+ .asg "9", tx1_pin ;B2 J16 Pin 37
+ .asg "10", tx2_pin ;C2 J16 Pin 38
+ .asg "11", tx3_pin ;C1 J16 Pin 58
+ .asg "19", tx4_pin ;bluewire Pin 5
+ .asg "12", tx5_pin ;bluewire Pin 53
+ .asg "13", tx6_pin ;bluewire Pin 55
+ .asg "18", tx7_pin ;bluewire Pin 57
+
+;macro used to precisely wait for (P1 > 1) cycles
+nopx .macro P1
+ loop endloop?, P1 - 1
+ NOP
+endloop?:
+ .endm
diff --git a/firmware/icss_iolink/src/include/io_link_master/memory_map.inc b/firmware/icss_iolink/src/include/io_link_master/memory_map.inc
--- /dev/null
@@ -0,0 +1,137 @@
+; Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; file: memory_map.inc
+;
+; brief: PRU IO-Link master memory map
+
+;memory_map.inc
+;PRU IO-Link Master
+;ICSS0 PRU0
+;v0.1
+
+;adresses of data sections in RAM
+
+;instance specific memory
+globalSts .set 0x0000 ;reserved
+globalCtrl .set 0x0001 ;bit 0: needs to be set to start a new transmission on any port
+maxResponseTime .set 0x0002 ;sets the maximum response time of all channels and needs to be set before PRU startup
+firmwareRev .set 0x0003 ;reserved
+
+;channel specific control and indication registers
+ctrlCh0 .set 0x0004 ;32 bit for control
+
+;control register description:
+;bit 0: set to start a new transmission cycle
+;bit 1: transmit buffer selector (0 = transmit buffer 0; 1 = transmit buffer 1)
+;bit 2: set this bit and bit 0 to transmit a start pulse
+
+statusCh0 .set 0x0008 ;16 bit for status
+
+;status register description:
+;bit 0: indicates a completed transmission cycle (has to be reset by the driver)
+
+errorCh0 .set 0x000A ;16 bit for error
+
+;error register description:
+;bit 0: rx_length error
+;bit 7: parity error
+
+ctrlCh1 .set 0x000C
+statusCh1 .set 0x0010
+errorCh1 .set 0x0012
+
+ctrlCh2 .set 0x0014
+statusCh2 .set 0x0018
+errorCh2 .set 0x001A
+
+ctrlCh3 .set 0x001C
+statusCh3 .set 0x0020
+errorCh3 .set 0x0022
+
+ctrlCh4 .set 0x0024
+statusCh4 .set 0x0028
+errorCh4 .set 0x002A
+
+ctrlCh5 .set 0x002C
+statusCh5 .set 0x0030
+errorCh5 .set 0x0032
+
+ctrlCh6 .set 0x0034
+statusCh6 .set 0x0038
+errorCh6 .set 0x003A
+
+ctrlCh7 .set 0x003C
+statusCh7 .set 0x0040
+errorCh7 .set 0x0042
+
+;transmit and receive buffers
+;rx buffer length = 128 bytes
+
+receivebfrCh0 .set 0x0100
+receivebfrCh1 .set 0x0180
+receivebfrCh2 .set 0x0200
+receivebfrCh3 .set 0x0280
+receivebfrCh4 .set 0x0300
+receivebfrCh5 .set 0x0380
+receivebfrCh6 .set 0x0400
+receivebfrCh7 .set 0x0480
+
+;the transmit buffer is twice as large as the receive buffer
+;you can use it as a double send buffer by setting the buffer select bit
+;tx buffer length = 256 bytes (or 128 bytes per sub-buffer)
+
+transmitbfrCh0 .set 0x0500
+transmitbfrCh1 .set 0x0600
+transmitbfrCh2 .set 0x0700
+transmitbfrCh3 .set 0x0800
+transmitbfrCh4 .set 0x0900
+transmitbfrCh5 .set 0x0A00
+transmitbfrCh6 .set 0x0B00
+transmitbfrCh7 .set 0x0C00
+
+;channel specific RAM
+
+channel0mem .set 0x0D00
+channel1mem .set 0x0D10
+channel2mem .set 0x0D20
+channel3mem .set 0x0D30
+channel4mem .set 0x0D40
+channel5mem .set 0x0D50
+channel6mem .set 0x0D60
+channel7mem .set 0x0D70
+
+;LUT's
+
+sampleratelut .set 0x0E00
+startbitfilter .set 0x0F00
+
+;LUT's in the other PRU's memory
+averagingfilter .set 0x2E00
+paritylut .set 0x2F00
diff --git a/firmware/icss_iolink/src/include/io_link_master/register_map.inc b/firmware/icss_iolink/src/include/io_link_master/register_map.inc
--- /dev/null
@@ -0,0 +1,120 @@
+; Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; file: register_map.inc
+;
+; brief: PRU IO-Link master register map
+
+;register_map.inc
+;PRU IO-Link Master
+;ICSS0 PRU0
+;v0.1
+
+ .asg "R0", gp_r0 ;general purpose register
+ .asg "R1", gp_r1 ;general purpose register
+ .asg "R2", gp_r2 ;general purpose register
+ .asg "R3", gp_r3 ;general purpose register
+
+ .asg "R4", sample_r0
+ .asg "R5", sample_r1
+ .asg "R6", sample_r2
+ .asg "R7", sample_r3
+ .asg "R4.w0", sample0 ;2 bytes of raw samples (CH0)
+ .asg "R4.w2", sample1 ;2 bytes of raw samples (CH1)
+ .asg "R5.w0", sample2 ;2 bytes of raw samples (CH2)
+ .asg "R5.w2", sample3 ;2 bytes of raw samples (CH3)
+ .asg "R6.w0", sample4 ;2 bytes of raw samples (CH4)
+ .asg "R6.w2", sample5 ;2 bytes of raw samples (CH5)
+ .asg "R7.w0", sample6 ;2 bytes of raw samples (CH6)
+ .asg "R7.w2", sample7 ;2 bytes of raw samples (CH7)
+
+ .asg "R8", count_r0
+ .asg "R9", count_r1
+ .asg "R8.b0", count0 ;count of received samples since start bit det. (CH0)
+ .asg "R8.b1", count1 ;count of received samples since start bit det. (CH0)
+ .asg "R8.b2", count2 ;count of received samples since start bit det. (CH0)
+ .asg "R8.b3", count3 ;count of received samples since start bit det. (CH0)
+ .asg "R9.b0", count4 ;count of received samples since start bit det. (CH0)
+ .asg "R9.b1", count5 ;count of received samples since start bit det. (CH0)
+ .asg "R9.b2", count6 ;count of received samples since start bit det. (CH0)
+ .asg "R9.b3", count7 ;count of received samples since start bit det. (CH0)
+
+ ;Baud rate setting encoding:
+ ;COM3: 0x3
+ ;COM2: 0x2
+ ;COM1: 0x1
+ ;other values will cause the channels sampler and state machine to halt
+
+ .asg "R10", baud_r0
+ .asg "R11", baud_r1
+ .asg "R10.b0", baud0 ;baud rate setting register (CH0)
+ .asg "R10.b1", baud1 ;baud rate setting register (CH0)
+ .asg "R10.b2", baud2 ;baud rate setting register (CH0)
+ .asg "R10.b3", baud3 ;baud rate setting register (CH0)
+ .asg "R11.b0", baud4 ;baud rate setting register (CH0)
+ .asg "R11.b1", baud5 ;baud rate setting register (CH0)
+ .asg "R11.b2", baud6 ;baud rate setting register (CH0)
+ .asg "R11.b3", baud7 ;baud rate setting register (CH0)
+
+ .asg "R12.b0", state ;state of CH0
+ .asg "R12.b1", idle_count ;count of Tbit waiting for a startbit (CH0)
+ .asg "R12.b2", error ;error register (CH0)
+ .asg "R12.b3", samplepoint ;samplepoint (within sample register) (CH0)
+ .asg "R13.b0", databuffer ;1 byte uart frame buffer (CH0)
+ .asg "R13.b1", bfr_ptr ;points to the next position in the tx or rx buffer (RAM) (CH0)
+ .asg "R13.b2", bfr_length ;length of valid data in buffer (tx or rx) (CH0)
+ .asg "R13.b3", txPin ;pru txPin nr.
+ .asg "R14", txEnAdr ;txEn gpio address of the active port
+ .asg "R15", txEnPin ;txEn Pin of the active port
+
+ .asg "R16.b0", loopcounter ;counts the nr. of loops (oversampling period) for variable baudrate sampling
+ .asg "R16.b1", substate ;used by the chsel state machine (encodes the active chanel)
+ .asg "R16.b2", nxtSymbolFlag ;8 symbol flags (1 bit per channel) to signal that another 8 samples (1 symbol) have been received
+
+ .asg "R17", ch0MemAdr ;channel 0 memory base adr
+ .asg "R18.w0", ch0RxBufferAdr ;channel 0 rx buffer base adr
+ .asg "R18.w2", ch0TxBufferAdr ;channel 0 tx buffer base adr
+ .asg "R19", activeChMemAdr ;active channel memory adr
+
+ .asg "R20.w0", gpioSetRegOfs ;register offset of the gpio set register
+ .asg "R20.w2", gpioClrRegOfs ;register offset of the gpio clr register
+
+ .asg "R21.b0", taReg ;holds ta and is loaded once at startup (this value can be set once at every PRU startup)
+ .asg "R21.b1", t2Reg ;holds t2 and is loaded once at startup (this value has to be set in code)
+ .asg "R21.b2", txBufferSel ;tx buffer offset register (selects txbuffer0 or txbuffer1)
+
+ .asg "R22", sampleratelut_adr ;stores a 32bit address for faster access with LBBO (used for LUT's)
+ .asg "R23", startbitfilter_adr ;stores a 32bit address for faster access with LBBO (used for LUT's)
+ .asg "R24", averagingfilter_adr ;stores a 32bit address for faster access with LBBO (used for LUT's)
+ .asg "R25", paritylut_adr ;stores a 32bit address for faster access with LBBO (used for LUT's)
+
+ .asg "R26", globalCtrlRegAdr ;globalCtrlRegAdr
+
+ .asg "R31", rxr ;receive pin register (r31 is mapped to the PRU's GPI pins)
+ .asg "R30", txr ;transmit pin register (r30 is mapped to the PRU's GPO pins)
diff --git a/firmware/icss_iolink/src/iolink.asm b/firmware/icss_iolink/src/iolink.asm
--- /dev/null
@@ -0,0 +1,788 @@
+; Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions
+; are met:
+;
+; Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+;
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the
+; distribution.
+;
+; Neither the name of Texas Instruments Incorporated nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+; file: main.asm
+;
+; brief: PRU IO-Link master assembly
+
+
+;main.asm
+;PRU IO-Link Master
+;ICSS0 PRU0
+;v0.1
+
+ .retain ; Required for building .out with assembly file
+ .retainrefs ; Required for building .out with assembly file
+
+ .include "./include/io_link_master/memory_map.inc"
+ .include "./include/io_link_master/register_map.inc"
+ .include "./include/io_link_master/defines.inc"
+
+ .global main
+ .sect ".text:main"
+
+;program entry point:
+
+main:
+ ;configuration goes here
+ zero &R0, 120 ;clear R0 to R29
+
+ ;load the configured maximum response time
+ ;NOTE: this will only be done once at PRU startup
+ ldi gp_r0, maxResponseTime
+ lbbo &taReg, gp_r0, 0, 1
+
+ ;set t2
+ ;NOTE: this value is hard coded (you can change it in the defines.inc file if needed)
+ ldi t2Reg, t2_time
+
+ ;preload frequently used LUT addresses into registers
+ ldi32 startbitfilter_adr, startbitfilter
+ ldi32 averagingfilter_adr, averagingfilter
+ ldi32 paritylut_adr, paritylut
+ ldi32 sampleratelut_adr, sampleratelut
+
+ ;preload frequently used address offsets and constants into registers
+ ldi ch0MemAdr, channel0mem
+ ldi ch0RxBufferAdr, receivebfrCh0
+ ldi ch0TxBufferAdr, transmitbfrCh0
+
+ ldi gpioSetRegOfs, 0x194
+ ldi gpioClrRegOfs, 0x190
+
+ ldi globalCtrlRegAdr, globalCtrl
+
+ ;set all tx pins to high (DQ line will be low)
+ ldi32 txr, 0xFFFFFFFF
+
+;IO-Link main software loop:
+
+run:
+
+sample:
+ ;use the samplerate LUT to load one byte of data encoding the baud rate selective sample points (uses loopcounter)
+ lbbo &gp_r1, sampleratelut_adr, loopcounter, 1
+ ;3 cycles
+
+sampleCh0:
+ ;check if bit nr. baud0 in gp_r1 (result of samplerate LUT) is set.
+ qbbc sampleCh0exit0, gp_r1.b0, baud0
+ ;bit nr. baud0 in gp_r1 (result of samplerate LUT) is set
+ ;shift sample0 to the left
+ lsl sample0, sample0, 1
+ ;check if rx0 is high
+ qbbc sampleCh0exit1, rxr, rx0_pin
+ ;rx0 is high
+ ;set the LSB of sample 0
+ set sample0, sample0, 0
+continue0:
+ ;count the sample count of channel 1 up
+ ADD count0, count0, 0x1
+ ;check if the first 3 bit of count0 are 0 (check if count0 % 8 == 0)
+ AND gp_r0, count0, 0x7
+ qbeq setflag0, gp_r0, 0
+ ;count0 % 8 =/= 0
+ ;don't set a flag and continue sampling with channel 2
+ jmp sampleCh1
+
+sampleCh0exit0:
+ ;bit nr. baud0 in gp_r1 (result of samplerate LUT) is not set
+ ;dont take a sample and jump to sampleCh1
+ nopx 6
+ jmp sampleCh1
+
+sampleCh0exit1:
+ ;rx0 is not high
+ ;dont set the LSB of sample0 and continue
+ jmp continue0
+
+setflag0:
+ ;count0 % 8 == 0
+ ;we have received a new octet of samples
+ ;set a flag and continue sampling with channel 2
+ set nxtSymbolFlag, nxtSymbolFlag, 0
+ ;8 cycles
+
+ ;this repeats for the next 7 channels:
+
+sampleCh1:
+ qbbc sampleCh1exit0, gp_r1.b0, baud1
+ lsl sample1, sample1, 1
+ qbbc sampleCh1exit1, rxr, rx1_pin
+ set sample1, sample1, 0
+continue1:
+ ADD count1, count1, 0x1
+ AND gp_r0, count1, 0x7
+ qbeq setflag1, gp_r0, 0
+ jmp sampleCh2
+
+sampleCh1exit0:
+ nopx 6
+ jmp sampleCh2
+
+sampleCh1exit1:
+ jmp continue1
+
+setflag1:
+ set nxtSymbolFlag, nxtSymbolFlag, 1
+ ;8 cycles
+
+sampleCh2:
+ qbbc sampleCh2exit0, gp_r1.b0, baud2
+ lsl sample2, sample2, 1
+ qbbc sampleCh2exit1, rxr, rx2_pin
+ set sample2, sample2, 0
+continue2:
+ ADD count2, count2, 0x1
+ AND gp_r0, count2, 0x7
+ qbeq setflag2, gp_r0, 0
+ jmp sampleCh3
+
+sampleCh2exit0:
+ nopx 6
+ jmp sampleCh3
+
+sampleCh2exit1:
+ jmp continue2
+
+setflag2:
+ set nxtSymbolFlag, nxtSymbolFlag, 2
+ ;8 cycles
+
+sampleCh3:
+ qbbc sampleCh3exit0, gp_r1.b0, baud3
+ lsl sample3, sample3, 1
+ qbbc sampleCh3exit1, rxr, rx3_pin
+ set sample3, sample3, 0
+continue3:
+ ADD count3, count3, 0x1
+ AND gp_r0, count3, 0x7
+ qbeq setflag3, gp_r0, 0
+ jmp sampleCh4
+
+sampleCh3exit0:
+ nopx 6
+ jmp sampleCh4
+
+sampleCh3exit1:
+ jmp continue3
+
+setflag3:
+ set nxtSymbolFlag, nxtSymbolFlag, 3
+ ;8 cycles
+
+sampleCh4:
+ qbbc sampleCh4exit0, gp_r1.b0, baud4
+ lsl sample4, sample4, 1
+ qbbc sampleCh4exit1, rxr, rx4_pin
+ set sample4, sample4, 0
+continue4:
+ ADD count4, count4, 0x1
+ AND gp_r0, count4, 0x7
+ qbeq setflag4, gp_r0, 0
+ jmp sampleCh5
+
+sampleCh4exit0:
+ nopx 6
+ jmp sampleCh5
+
+sampleCh4exit1:
+ jmp continue4
+
+setflag4:
+ set nxtSymbolFlag, nxtSymbolFlag, 4
+ ;8 cycles
+
+sampleCh5:
+ qbbc sampleCh5exit0, gp_r1.b0, baud5
+ lsl sample5, sample5, 1
+ qbbc sampleCh5exit1, rxr, rx5_pin
+ set sample5, sample5, 0
+continue5:
+ ADD count5, count5, 0x1
+ AND gp_r0, count5, 0x7
+ qbeq setflag5, gp_r0, 0
+ jmp sampleCh6
+
+sampleCh5exit0:
+ nopx 6
+ jmp sampleCh6
+
+sampleCh5exit1:
+ jmp continue5
+
+setflag5:
+ set nxtSymbolFlag, nxtSymbolFlag, 5
+ ;8 cycles
+
+sampleCh6:
+ qbbc sampleCh6exit0, gp_r1.b0, baud6
+ lsl sample6, sample6, 1
+ qbbc sampleCh6exit1, rxr, rx6_pin
+ set sample6, sample6, 0
+continue6:
+ ADD count6, count6, 0x1
+ AND gp_r0, count6, 0x7
+ qbeq setflag6, gp_r0, 0
+ jmp sampleCh7
+
+sampleCh6exit0:
+ nopx 6
+ jmp sampleCh7
+
+sampleCh6exit1:
+ jmp continue6
+
+setflag6:
+ set nxtSymbolFlag, nxtSymbolFlag, 6
+ ;8 cycles
+
+sampleCh7:
+ qbbc sampleCh7exit0, gp_r1.b0, baud7
+ lsl sample7, sample7, 1
+ qbbc sampleCh7exit1, rxr, rx7_pin
+ set sample7, sample7, 0
+continue7:
+ ADD count7, count7, 0x1
+ AND gp_r0, count7, 0x7
+ qbeq setflag7, gp_r0, 0
+ jmp samplefinish
+
+sampleCh7exit0:
+ nopx 6
+ jmp samplefinish
+
+sampleCh7exit1:
+ jmp continue7
+
+sampleCountUpFinish:
+ ;we have not reached the wraparound threshold yet
+ ;continue with the uart state machines
+ jmp uartmode
+
+setflag7:
+ set nxtSymbolFlag, nxtSymbolFlag, 7
+ ;8 cycles
+
+samplefinish:
+ ;we have finished sampling
+ ;count the loopcounter up
+ ADD loopcounter, loopcounter, 1
+ ;check if we have reached the wraparound threshold of loopcounter > 240
+ qbgt sampleCountUpFinish, loopcounter, 240
+ ;we have reached the wraparound threshold
+ ;reset the loopcounter to 0
+ ldi loopcounter, 0
+ ;3 cycles
+; 3 + 64 + 3 = 70 cycles for variable baudrate sampling
+
+;beginning of the UART state machines:
+uartmode:
+
+;state machine of channel 0
+transceiver:
+ lsl gp_r2, substate, 4 ;offset between channels is 16 bytes, calculate the memory offset for channel "substate"
+ ADD activeChMemAdr, ch0MemAdr, gp_r2 ;calculate the absolute memory adress by adding channel0's memory offset
+ lbbo &r12, activeChMemAdr, 0, 16 ;load the channels memory (6 cycles for 16 bytes, 2 cycles + 16/4 * 1 cycles)
+ ;check if the symbolFlag of channel 0 is set
+ qbbc flagClear ,nxtSymbolFlag, substate
+ ;9 cycles
+ ;the flag is set, we should process data now (rx or tx)
+ clr nxtSymbolFlag, nxtSymbolFlag, substate ;clear the flag
+ ;state decider:
+ qbeq startbitdet, state, rx_idle ;21 cycles left for startbitdet
+ qbeq samplesymbol, state, rx_get ;20
+ qbeq channelIdle, state, idle ;19
+ qbeq comFinal, state, final ;18
+ qbeq startpulse, state, idle_startpulse ;17
+ qbeq startpulseCount, state, idle_startpulseCount ;16
+ qbeq txSetup, state, tx_setup ;15
+ qbeq txStart, state, tx_start ;14
+ qbeq txNextMsg, state, tx_nxtMsg ;13
+ qbeq txStop, state, tx_complete ;12
+ qbeq txTx, state, tx_transmit ;11
+ qbeq startpulseClrTxEn, state, idle_startpulseFin ;10
+ nopx 9 ;should never be reached
+ jmp cyclefinish
+flagClear:
+ ;the flag is not set
+ ;we will process idle and startpulse functionality only
+ nopx 3
+ qbeq channelIdle, state, idle
+ qbeq comFinal, state, final
+ qbeq startpulse, state, idle_startpulse
+ qbeq startpulseCount, state, idle_startpulseCount
+ nopx 2
+ qbeq txStop, state, tx_complete
+ nopx 2
+ qbeq startpulseClrTxEn, state, idle_startpulseFin
+ nopx 9
+ jmp cyclefinish
+
+receivefxn:
+
+startbitdet:
+ lsl gp_r1.b0, substate, 1 ;sample register is 2 bytes wide so we have to multiply by 2
+ ADD gp_r1.b0, gp_r1.b0, &R4.b0 ;sample register file adr
+ mviw r0.w0, *r1.b0 ;load sample
+ ;use the predefined LUT to detect a startbit edge in the sample stream
+ ;the LUT will also return the position of the start bit
+ lbbo &gp_r2, startbitfilter_adr, gp_r0.b0, 1
+ qbne startbitdet_0, gp_r2.b0, 0
+ ;we have not detected a start bit. shift the bitstream by 4 and retry
+ lsr gp_r0, gp_r0, 4
+ lbbo &gp_r2, startbitfilter_adr, gp_r0.b0, 1
+ qbne startbitdet_1, gp_r2.b0, 0
+ ;there is no valid start bit edge in the bit stream
+ ;check if we have already received a byte
+ qbne checkt2, bfr_ptr, 0
+ ;we have not received any bytes yet
+ ;check if we have reached the maximum response time
+ ADD idle_count, idle_count, 1
+ qblt rxFinish, idle_count, taReg
+ ;threshold not reached, continue with startbitdet
+ nopx 5
+ jmp cyclefinish
+ ;21 cycles for startbit detection
+
+checkt2:
+ ;there are bytes in the buffer
+ ;we need to check the devices t2 time
+ ADD idle_count, idle_count, 1
+ qblt rxFinish, idle_count, t2Reg
+ ;threshold not reached, continue with startbitdet
+ nopx 5
+ jmp cyclefinish
+ ;8 cycles
+
+startbitdet_0:
+ ;we have detected a valid startbit pattern in the first 8 bit of the sample buffer
+ ;the next instructions will reset the count register of the active channel to 0
+ ADD gp_r1.b0, substate, &R8.b0
+ ldi gp_r0.b0, 0
+ mvib *r1.b0, gp_r0.b0
+ ;copy the samplepoint to the active channel's samplepoint register
+ mov samplepoint, gp_r2.b0
+ ;load the next state for this channel
+ ldi state, rx_get
+ nopx 8
+ jmp cyclefinish
+ ;14 cycles
+
+startbitdet_1:
+ ;we have a detected valid startbit pattern located between bit 4 and 11 of the sample buffer
+ ;copy the samplepoint to the active channel's samplepoint register
+ mov samplepoint, gp_r2.b0
+ ;the offset of 4 bit has to be added to the result
+ ADD samplepoint, samplepoint, 4
+ ;load the next state for this channel
+ ldi state, rx_get
+ ;the next instructions will try to move the samplepoint to the right re-calculation of the count register
+ qble adjustSamplePoint, samplepoint, 8
+ ;the next instructions will reset the count register of the active channel to 0
+ ADD gp_r1.b0, substate, &R8.b0
+ ldi gp_r0.b0, 0
+ mvib *r1.b0, gp_r0.b0
+ NOP
+ jmp cyclefinish
+ ;9 cycles
+
+adjustSamplePoint:
+ ;try to move the samplepoint to the right re-calculation of the count register
+ ;the next instructions will set the count register of the active channel to 8
+ ADD gp_r1.b0, substate, &R8.b0
+ ldi gp_r0.b0, 8
+ mvib *r1.b0, gp_r0.b0
+ ;decrease samplepoint by 8
+ SUB samplepoint, samplepoint, 8 ;decrease samplepoint by 8
+ jmp cyclefinish
+ ;5 cycles
+
+rxFinish:
+ ;we have reached the idlecount limit
+ ;the device has finished transmitting data
+ ;write reveived nr of bytes to memory and go to comFinal state
+ lsl gp_r3, substate, 7 ;multiply substate by 265 (offset between buffers)
+ ADD gp_r2, ch0RxBufferAdr, gp_r3 ;add the offset to the entry address
+ sbbo &bfr_ptr, gp_r2, 0, 1 ;write the rx length to the RAM
+ ldi state, final ;load next state
+ jmp cyclefinish
+ ;6 cycles
+
+samplesymbol:
+ lsl gp_r1.b0, substate, 1 ;sample register is 2 bytes wide so we have to multiply by 2
+ ADD gp_r1.b0, gp_r1.b0, &R4.b0 ;sample register file adr
+ mviw gp_r0.w0, *r1.b0 ;load sample
+
+ ;take the next 8 samples and filter them
+ ;this will decide if a '1' or '0' has been received
+ lsr gp_r0, gp_r0.w0, samplepoint
+ lbbo &gp_r0, averagingfilter_adr, gp_r0.b0, 1
+
+ ADD gp_r1.b0, substate, &R8.b0 ;count register file adr
+ mvib gp_r2.b0, *r1.b0 ;load count
+
+ ;check if we have received > 72 samples (9 symbols, position of parity bit)
+ qblt paritychk, gp_r2.b0, 72
+
+ ;it's not a parity bit
+ lsr databuffer, databuffer, 1 ;shift the databuffer to the right
+ OR databuffer, databuffer, gp_r0.b0 ;add the new bit of data as msb (buffer will fill from left to right)
+
+ qblt writeData, gp_r2.b0, 64 ;jump to writeData if we are done receiving data bits (8 x 8 samples)
+ nopx 6
+ jmp cyclefinish
+ ;20 cycles for symbol sampling
+
+writeData:
+ ;we have received a new octet of data
+ ;write it to the RAM
+ ADD bfr_ptr, bfr_ptr, 1
+ lsl gp_r2, substate, 7
+ ADD gp_r0, ch0RxBufferAdr, gp_r2
+ sbbo &databuffer, gp_r0, bfr_ptr, 1
+ NOP
+ jmp cyclefinish
+ ;7 cycles
+
+paritychk:
+ ;load the pre-calculated parity for the bit pattern in the databuffer
+ lbbo &gp_r2, paritylut_adr, databuffer, 1
+ ;compare the received parity bit with the calculated bit
+ XOR gp_r0, gp_r2.b0, gp_r0.b0
+ OR error, error, gp_r0
+ ;reset the idle_count to 0, to make it available for the next startbit detection
+ ldi idle_count, 0
+ ;load the next state for the active channel
+ ldi state, rx_idle
+ ;check for rxlength error (too many bytes received)
+ qblt rxlength_error, bfr_ptr, bfr_length
+ NOP
+ jmp cyclefinish
+ ;10 cycles for parity check
+
+rxlength_error:
+ set error, error, 0 ;set the rxlength error flag
+ jmp cyclefinish
+ ;2 cycles
+
+;tx functions
+transmitter:
+
+txSetup:
+ ;set txEnable pin
+ ADD gp_r0 ,txEnAdr ,gpioSetRegOfs
+ sbbo &txEnPin, gp_r0, 0, 4
+ ;reset bfr_ptr to 2 (0 and 1 are used for length information)
+ ldi bfr_ptr, 2
+ ;load the bfr_length byte from the transmit buffer
+ lsl gp_r2, substate, 8 ;shift the substate by 8 to calculate the memory offset of the channel
+ ADD gp_r2, ch0TxBufferAdr, gp_r2 ;add ch0's txbuffer address
+ lbbo &bfr_length, gp_r2, 0, 1 ;load the byte from DRAM
+ ;add 2 to bfr_length to compensate for the first 2 bytes
+ ADD bfr_length, bfr_length, 2
+ ;set the active channels state to tx_start
+ ldi state, tx_start
+ ;reset the channels error register
+ ldi error, 0x00
+ nopx 2
+ jmp cyclefinish
+ ;15 cycles
+
+txStart:
+ ;generate start bit
+ ;reset the channels count register to 0
+ ADD gp_r1.b0, substate, &R8.b0
+ ldi gp_r0.b0, 0
+ mvib *r1.b0, gp_r0.b0 ;set count to 0
+ ;clr the tx pin to transmit the start bit
+ clr txr, txr, txPin
+ ;set state to tx_transmit
+ ldi state, tx_transmit
+ ;reset the idle count to 0 (will be used in the rx state machine later)
+ ldi idle_count, 0
+ ;load the first byte of data from the txbuffer (RAM)
+ lsl gp_r2, substate, 8
+ ADD gp_r2, ch0TxBufferAdr, gp_r2
+ ;check if buffer0 or buffer1 is selected
+ qbbc txStartUseBfr0, txBufferSel, substate
+ ADD gp_r2, gp_r2, 0x80
+ lbbo &databuffer, gp_r2, bfr_ptr, 1
+ jmp cyclefinish
+ ;14 cycles
+
+txStartUseBfr0:
+ NOP
+ lbbo &databuffer, gp_r2, bfr_ptr, 1
+ jmp cyclefinish
+ ;5 cycles
+
+txNextMsg:
+ ;reset count to 0
+ ADD gp_r1.b0, substate, &R8.b0 ;count register file adr
+ ldi gp_r0.b0, 0
+ mvib *r1.b0, gp_r0.b0 ;set count to 0
+ ;set state to tx_transmit
+ ldi state, tx_transmit
+ ;clr the tx pin to transmit the start bit
+ clr txr, txr, txPin
+ ;load next byte from tx buffer (RAM)
+ lsl gp_r2, substate, 8
+ ADD gp_r2, ch0TxBufferAdr, gp_r2
+ ;tx buffer selection (0 or 1)
+ qbbc txNextMsgUseBfr0, txBufferSel, substate
+ ADD gp_r2, gp_r2, 0x80
+ lbbo &databuffer, gp_r2, bfr_ptr, 1
+ jmp cyclefinish
+ ;13 cycles
+
+txNextMsgUseBfr0:
+ NOP
+ lbbo &databuffer, gp_r2, bfr_ptr, 1
+ jmp cyclefinish
+ ;5 cycles
+
+txTx:
+ ;load the count register
+ ADD gp_r1.b0, substate, &R8.b0 ;count register file adr
+ mvib gp_r0.b0, *r1.b0 ;load count
+ ;check if we need to send a stopbit (count0 > 9 x 8 samples)
+ qblt generateStopbit, gp_r0.b0, 72
+ ;check if we need to send a paritybit (count0 > 8 x 8 samples)
+ qblt generateParitybit, gp_r0.b0, 64
+ ;divide count0 by 8 and subtract 1 for the start bit
+ lsr gp_r0, gp_r0.b0, 3
+ SUB gp_r0, gp_r0, 1
+ ;use the result to determine which bit needs to be transmitted next
+ ;this bit will be set or cleared
+ qbbs setTx, databuffer, gp_r0
+ clr txr, txr, txPin
+ nopx 2
+ jmp cyclefinish
+ ;11 cycles
+setTx:
+ set txr, txr, txPin
+ nopx 2
+ jmp cyclefinish
+ ;4 cycles
+
+generateParitybit:
+ ;calculate the parity using a LUT
+ lbbo &gp_r0, paritylut_adr, databuffer, 1
+ ;transmit the parity bit
+ qbbs setParity, gp_r0, 7
+ clr txr, txr, txPin
+ NOP
+ jmp cyclefinish
+ ;7 cycles
+setParity:
+ set txr, txr, txPin
+ NOP
+ jmp cyclefinish
+ ;3 cycles
+
+generateStopbit:
+ ;set the tx pin to transmit the stop bit
+ set txr, txr, txPin
+ ;count bfr_ptr up
+ ADD bfr_ptr, bfr_ptr, 1
+ ;check if we have transmitted all bytes in the tx buffer
+ qble txComplete, bfr_ptr, bfr_length
+ ;we still need to send a byte
+ ;set the channels state to tx_nxtMsg
+ ldi state, tx_nxtMsg
+ nopx 3
+ jmp cyclefinish
+ ;8 cycles
+
+txComplete:
+ ;we have sent all bytes in the buffer
+ ;set the channels state to tx_complete
+ ldi state, tx_complete
+ nopx 3
+ jmp cyclefinish
+ ;5 cycles
+
+txStop:
+ ;we have transmitted all bytes in the buffer
+ ;clr the txen pin
+ ADD gp_r0 ,txEnAdr ,gpioClrRegOfs
+ sbbo &txEnPin, gp_r0, 0, 4
+ ldi state, rx_idle ;set the state to rx_idle
+ ;load the rx bfr_length from RAM
+ lsl gp_r2, substate, 8
+ ADD gp_r2, ch0TxBufferAdr, gp_r2
+ lbbo &bfr_length, gp_r2, 1, 1
+ ;add 1 to the length (first field in the rx buffer is the nr. of received bytes in the buffer)
+ ADD bfr_length, bfr_length, 1
+ ;reset the bfr_ptr to 0
+ ldi bfr_ptr, 0
+ jmp cyclefinish
+ ;12 cycles
+
+;ARM communication will be handled in the idle state:
+channelIdle:
+ ;load configuration and baud rate from memory
+ ldi gp_r0, ctrlCh0
+ lsl gp_r2, substate, 3
+ ADD gp_r0, gp_r0, gp_r2
+ lbbo &gp_r2, gp_r0, 0, 2
+ ADD gp_r1.b0, substate, &R10.b0
+ mvib *R1.b0, gp_r2.b1
+ ;check global control
+ lbbo &gp_r3, globalCtrlRegAdr, 0, 1
+ AND gp_r3.b0, gp_r2.b0, gp_r3.b0
+ ;check if we need to start a commmunication cycle
+ qbbs beginDataExchange, gp_r3.b0, 0
+ ;the bit is not set, so we don't need to do anything
+ ;the channel will remain in idle state
+ nopx 5
+ jmp cyclefinish
+ ;19 cycles
+
+txBuffer0sel:
+ ;tx buffer 0 is selected (we dont need to set the bit in the txBufferSel register)
+ jmp checkBit;
+
+beginDataExchange:
+ ;reset the tx buffer select bit
+ clr txBufferSel, txBufferSel, substate
+ ;check if tx buffer 0 or tx buffer 1 is selected
+ qbbc txBuffer0sel, gp_r2.b0, 1
+ ;tx buffer 1 is selected (set the according bit in the txBufferSel register)
+ set txBufferSel, txBufferSel, substate
+checkBit:
+ ;check if the startpulse bit is set
+ qbbs beginStartPulse ,gp_r2.b0, 2
+ ;there are > 0 bytes in the tx buffer
+ ldi state, tx_setup ;set state to tx_setup
+ jmp cyclefinish
+ ;6 cycles
+
+;start pulse generator
+;will be triggered by transmitting an empty (txlength = 0) buffer of tx bytes
+beginStartPulse:
+ ;there are no bytes in the buffer
+ ldi state, idle_startpulse ;set state to idle_startpulse (generate a startpulse)
+ jmp cyclefinish
+ ;2 cycles
+
+startpulse:
+ ;check the voltage level on the dq line
+ lsl gp_r1.b0, substate, 1 ;sample register is 2 bytes wide so we have to multiply by 2
+ ADD gp_r1.b0, gp_r1.b0, &R4.b0 ;sample register file adr
+ mvib r0.b0, *r1.b0 ;load sample
+ lbbo &gp_r0, averagingfilter_adr, r0.b0, 1
+ ;reset bfr_length to 0 (temp. used to measure the pulsewidth)
+ ldi bfr_length, 0
+ ;set the txEn pin
+ ADD gp_r2 ,txEnAdr ,gpioSetRegOfs
+ sbbo &txEnPin, gp_r2, 0, 4
+ ;set state to idle_starpulseCount
+ ldi state, idle_startpulseCount
+ ;transmit a signal of oppposite voltage level
+ qbbc lowpulse, gp_r0, 7
+ clr txr, txr, txPin
+ nopx 3
+ jmp cyclefinish
+ ;17 cycles
+
+lowpulse:
+ set txr, txr, txPin
+ nopx 3
+ jmp cyclefinish
+ ;5 cycles
+
+startpulseCount:
+ ;measure the pulse width by using bfr_length as a counter
+ qblt startpulseFinish, bfr_length, 17
+ ;count bfr_length up
+ ADD bfr_length, bfr_length, 1
+ nopx 13
+ jmp cyclefinish
+ ;16 cycles
+
+startpulseFinish:
+ ;bfr_length has reached it's threshold
+ set txr, txr, txPin ;set the tx pin (this will set the dq line's voltage level to low)
+ ldi state, idle ;set the state to idle
+ ;reset the channels control byte
+ ldi gp_r0, ctrlCh0
+ lsl gp_r2, substate, 3
+ ADD gp_r0, gp_r0, gp_r2
+ ldi gp_r2, 0x00
+ sbbo &gp_r2, gp_r0, 0, 1
+ ldi state, idle_startpulseFin ;set state to startpulse fin
+ nopx 5
+ jmp cyclefinish
+ ;15 cycles
+
+startpulseClrTxEn:
+ ldi state, idle ;set state to idle
+ ; clear the channels TxEn pin
+ ADD gp_r0 ,txEnAdr ,gpioClrRegOfs
+ sbbo &txEnPin, gp_r0, 0, 4
+ nopx 5
+ jmp cyclefinish
+ ;10 cycles
+
+
+comFinal:
+ ;cleanup function for end of communication cycle
+ ldi gp_r0, ctrlCh0
+ lsl gp_r2, substate, 3
+ ADD gp_r0, gp_r0, gp_r2
+ ldi gp_r2, 0x00
+ sbbo &gp_r2, gp_r0, 0, 1 ;reset the control byte in RAM
+ ldi state, idle ;set state to idle
+ ldi gp_r0, statusCh0
+ lsl gp_r2, substate, 3
+ ADD gp_r0, gp_r0, gp_r2
+ ldi32 gp_r2, 0
+ ldi gp_r2.b0, status_complete
+ mov gp_r2.b2, error
+ sbbo &gp_r2, gp_r0, 0, 4 ;set the channels status register to complete
+ ldi R31.b0, ((1<<5) | 0x0) ;generate cycle complete interrupt
+ jmp cyclefinish
+ ;18 cycles
+
+ ;32 cycles for symbol processing
+
+cyclefinish:
+ sbbo &r12, activeChMemAdr, 0, 8 ;write channels memory (3 cycles for 8 bytes)
+ ;channel selector (Channels will be processed in a row while its necessary to sample every loop cycle)
+chselect:
+ qblt wraparound, substate, 6
+ ADD substate, substate, 1
+ jmp run
+wraparound:
+ ldi substate, 0
+ nopx 4 ;cycle compensation
+ jmp run
+ ;6.5 cycles on average
diff --git a/iolink_component.mk b/iolink_component.mk
--- /dev/null
+++ b/iolink_component.mk
@@ -0,0 +1,280 @@
+#
+# Copyright (c) 2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+# File: iolink_component.mk
+# This file is component include make file of IOLINK library.
+# List of variables set in this file and their purpose:
+# <mod>_RELPATH - This is the relative path of the module, typically from
+# top-level directory of the package
+# <mod>_PATH - This is the absolute path of the module. It derives from
+# absolute path of the top-level directory (set in env.mk)
+# and relative path set above
+# <mod>_INCLUDE - This is the path that has interface header files of the
+# module. This can be multiple directories (space separated)
+# <mod>_PKG_LIST - Names of the modules (and sub-modules) that are a part
+# part of this module, including itself.
+# <mod>_BOARD_DEPENDENCY - "yes": means the code for this module depends on
+# board and the compiled obj/lib has to be kept
+# under <board> directory
+# "no" or "" or if this variable is not defined: means
+# this module has no board dependent code and hence
+# the obj/libs are not kept under <board> dir.
+# <mod>_CORE_DEPENDENCY - "yes": means the code for this module depends on
+# core and the compiled obj/lib has to be kept
+# under <core> directory
+# "no" or "" or if this variable is not defined: means
+# this module has no core dependent code and hence
+# the obj/libs are not kept under <core> dir.
+# <mod>_APP_STAGE_FILES - List of source files that belongs to the module
+# <mod>, but that needs to be compiled at application
+# build stage (in the context of the app). This is
+# primarily for link time configurations or if the
+# source file is dependent on options/defines that are
+# application dependent. This can be left blank or
+# not defined at all, in which case, it means there
+# no source files in the module <mod> that are required
+# to be compiled in the application build stage.
+#
+ifeq ($(iolink_component_make_include), )
+
+drviolink_BOARDLIST = idkAM437x
+drviolink_SOCLIST = am437x
+drviolink_am437x_CORELIST = a9host pru_0 pru_1
+
+############################
+# iolink package
+# List of components included under iolink lib
+# The components included here are built and will be part of iolink lib
+############################
+iolink_LIB_LIST = iolink iolink_indp iolink_profile iolink_profile_indp
+drviolink_LIB_LIST = $(iolink_LIB_LIST)
+
+############################
+# iolink Firmwares
+# All the firmware mentioned in list are built when build target is called
+# List below all firmware for allowed values
+############################
+iolink_FIRM_LIST = icss_iolink
+drviolink_FIRM_LIST = $(iolink_FIRM_LIST)
+
+############################
+# iolink examples
+# List of examples under iolink
+# All the tests mentioned in list are built when test target is called
+# List below all examples for allowed values
+############################
+ifeq ($(CORE), a9host)
+ifneq ($(IOLINK_STACK_INSTALL_PATH), )
+iolink_EXAMPLE_LIST = IOLINK_IQ2Stack_TestApp
+endif
+drviolink_EXAMPLE_LIST = $(iolink_EXAMPLE_LIST)
+endif
+
+#
+# IOLINK Modules
+#
+
+# IOLINK LIB
+iolink_COMP_LIST = iolink
+iolink_RELPATH = ti/drv/iolink
+iolink_PATH = $(PDK_IOLINK_COMP_PATH)
+iolink_LIBNAME = ti.drv.iolink
+export iolink_LIBNAME
+iolink_LIBPATH = $(iolink_PATH)/lib
+export iolink_LIBPATH
+iolink_OBJPATH = $(iolink_RELPATH)/iolink
+export iolink_OBJPATH
+iolink_MAKEFILE = -f build/makefile.mk
+export iolink_MAKEFILE
+iolink_BOARD_DEPENDENCY = no
+iolink_CORE_DEPENDENCY = no
+iolink_SOC_DEPENDENCY = yes
+export iolink_COMP_LIST
+export iolink_BOARD_DEPENDENCY
+export iolink_CORE_DEPENDENCY
+export iolink_SOC_DEPENDENCY
+iolink_PKG_LIST = iolink
+export iolink_PKG_LIST
+iolink_INCLUDE = $(iolink_PATH)
+iolink_SOCLIST = $(drviolink_SOCLIST)
+export iolink_SOCLIST
+iolink_$(SOC)_CORELIST = $(drviolink_$(SOC)_CORELIST)
+export iolink_$(SOC)_CORELIST
+
+# IOLINK INDEPENDENT LIB
+iolink_indp_COMP_LIST = iolink_indp
+iolink_indp_RELPATH = ti/drv/iolink
+iolink_indp_PATH = $(PDK_IOLINK_COMP_PATH)
+iolink_indp_LIBNAME = ti.drv.iolink
+export iolink_indp_LIBNAME
+iolink_indp_LIBPATH = $(iolink_indp_PATH)/lib
+export iolink_indp_LIBPATH
+iolink_indp_OBJPATH = $(iolink_indp_RELPATH)/iolink_indp
+export iolink_indp_OBJPATH
+iolink_indp_MAKEFILE = -f build/makefile_indp.mk
+export iolink_indp_MAKEFILE
+iolink_indp_BOARD_DEPENDENCY = no
+iolink_indp_CORE_DEPENDENCY = no
+iolink_indp_SOC_DEPENDENCY = no
+export iolink_indp_COMP_LIST
+export iolink_indp_BOARD_DEPENDENCY
+export iolink_indp_CORE_DEPENDENCY
+export iolink_indp_SOC_DEPENDENCY
+iolink_indp_PKG_LIST = iolink_indp
+export iolink_indp_PKG_LIST
+iolink_indp_INCLUDE = $(iolink_indp_PATH)
+iolink_indp_SOCLIST = $(drviolink_SOCLIST)
+export iolink_indp_SOCLIST
+iolink_indp_$(SOC)_CORELIST = $(drviolink_$(SOC)_CORELIST)
+export iolink_indp_$(SOC)_CORELIST
+
+# IOLINK PROFILE LIB
+iolink_profile_COMP_LIST = iolink_profile
+iolink_profile_RELPATH = ti/drv/iolink
+iolink_profile_PATH = $(PDK_IOLINK_COMP_PATH)
+iolink_profile_LIBNAME = ti.drv.iolink.profiling
+export iolink_profile_LIBNAME
+iolink_profile_LIBPATH = $(iolink_profile_PATH)/lib
+export iolink_profile_LIBPATH
+iolink_profile_OBJPATH = $(iolink_profile_RELPATH)/iolink_profile
+export iolink_profile_OBJPATH
+iolink_profile_MAKEFILE = -f build/makefile_profile.mk
+export iolink_profile_MAKEFILE
+iolink_profile_BOARD_DEPENDENCY = no
+iolink_profile_CORE_DEPENDENCY = no
+iolink_profile_SOC_DEPENDENCY = yes
+export iolink_profile_COMP_LIST
+export iolink_profile_BOARD_DEPENDENCY
+export iolink_profile_CORE_DEPENDENCY
+export iolink_profile_SOC_DEPENDENCY
+iolink_profile_PKG_LIST = iolink_profile
+export iolink_profile_PKG_LIST
+iolink_profile_INCLUDE = $(iolink_profile_PATH)
+iolink_profile_SOCLIST = $(drviolink_SOCLIST)
+export iolink_profile_SOCLIST
+iolink_profile_$(SOC)_CORELIST = $(drviolink_$(SOC)_CORELIST)
+export iolink_profile_$(SOC)_CORELIST
+
+# IOLINK PROFILE INDEPENDENT LIB
+iolink_profile_indp_COMP_LIST = iolink_profile_indp
+iolink_profile_indp_RELPATH = ti/drv/iolink
+iolink_profile_indp_PATH = $(PDK_IOLINK_COMP_PATH)
+iolink_profile_indp_LIBNAME = ti.drv.iolink.profiling
+export iolink_profile_indp_LIBNAME
+iolink_profile_indp_LIBPATH = $(iolink_profile_indp_PATH)/lib
+export iolink_profile_indp_LIBPATH
+iolink_profile_indp_OBJPATH = $(iolink_profile_indp_RELPATH)/iolink_profile_indp
+export iolink_profile_indp_OBJPATH
+iolink_profile_indp_MAKEFILE = -f build/makefile_profile_indp.mk
+export iolink_profile_indp_MAKEFILE
+iolink_profile_indp_BOARD_DEPENDENCY = no
+iolink_profile_indp_CORE_DEPENDENCY = no
+iolink_profile_indp_SOC_DEPENDENCY = no
+export iolink_profile_indp_COMP_LIST
+export iolink_profile_indp_BOARD_DEPENDENCY
+export iolink_profile_indp_CORE_DEPENDENCY
+export iolink_profile_indp_SOC_DEPENDENCY
+iolink_profile_indp_PKG_LIST = iolink_profile_indp
+export iolink_profile_indp_PKG_LIST
+iolink_profile_indp_INCLUDE = $(iolink_profile_indp_PATH)
+iolink_profile_indp_SOCLIST = $(drviolink_SOCLIST)
+export iolink_profile_indp_SOCLIST
+iolink_profile_indp_$(SOC)_CORELIST = $(drviolink_$(SOC)_CORELIST)
+export iolink_profile_indp_$(SOC)_CORELIST
+
+#
+# IOLINK Firmwares
+#
+icss_iolink_COMP_LIST = icss_iolink
+# temporary fix for nightly build
+# icss_iolink_RELPATH = ti/drv/iolink/firmware/icss_iolink
+icss_iolink_RELPATH = icss_iolink
+icss_iolink_PATH = $(PDK_IOLINK_COMP_PATH)/firmware/icss_iolink
+icss_iolink_HEADERNAME = icss_iolink
+export icss_iolink_HEADERNAME
+icss_iolink_HEADERPATH = $(icss_iolink_PATH)/bin
+export icss_iolink_HEADERPATH
+icss_iolink_OBJPATH = $(icss_iolink_RELPATH)
+export icss_iolink_OBJPATH
+icss_iolink_MAKEFILE = -f ../../build/makefile_icss_iolink.mk
+export icss_iolink_MAKEFILE
+icss_iolink_BOARD_DEPENDENCY = no
+icss_iolink_CORE_DEPENDENCY = yes
+icss_iolink_SOC_DEPENDENCY = yes
+export icss_iolink_COMP_LIST
+export icss_iolink_BOARD_DEPENDENCY
+export icss_iolink_CORE_DEPENDENCY
+export icss_iolink_SOC_DEPENDENCY
+icss_iolink_PKG_LIST = icss_iolink
+export icss_iolink_PKG_LIST
+icss_iolink_INCLUDE = $(icss_iolink_PATH)
+icss_iolink_SOCLIST = am437x
+export icss_iolink_SOCLIST
+#icss_iolink_$(SOC)_CORELIST = $(drviolink_$(SOC)_CORELIST)
+icss_iolink_$(SOC)_CORELIST = pru_0
+export icss_iolink_$(SOC)_CORELIST
+
+#
+# IOLINK Examples
+#
+
+# IOLINK rtos test
+ifeq ($(CORE), a9host)
+IOLINK_IQ2Stack_TestApp_COMP_LIST = IOLINK_IQ2Stack_TestApp
+IOLINK_IQ2Stack_TestApp_RELPATH = $(PDK_IOLINK_COMP_PATH)/test/iq2_stack_test
+IOLINK_IQ2Stack_TestApp_PATH = $(PDK_IOLINK_COMP_PATH)/test/iq2_stack_test
+IOLINK_IQ2Stack_TestApp_BOARD_DEPENDENCY = yes
+IOLINK_IQ2Stack_TestApp_CORE_DEPENDENCY = no
+IOLINK_IQ2Stack_TestApp_MAKEFILE = -f makefile
+IOLINK_IQ2Stack_TestApp_XDC_CONFIGURO = yes
+export IOLINK_IQ2Stack_TestApp_COMP_LIST
+export IOLINK_IQ2Stack_TestApp_BOARD_DEPENDENCY
+export IOLINK_IQ2Stack_TestApp_CORE_DEPENDENCY
+export IOLINK_IQ2Stack_TestApp_XDC_CONFIGURO
+export IOLINK_IQ2Stack_TestApp_MAKEFILE
+IOLINK_IQ2Stack_TestApp_PKG_LIST = IOLINK_IQ2Stack_TestApp
+IOLINK_IQ2Stack_TestApp_INCLUDE = $(IOLINK_IQ2Stack_TestApp_PATH)
+IOLINK_IQ2Stack_TestApp_BOARDLIST = $(drviolink_BOARDLIST)
+export IOLINK_IQ2Stack_TestApp_BOARDLIST
+IOLINK_IQ2Stack_TestApp_$(SOC)_CORELIST = $(iolink_$(SOC)_CORELIST)
+export IOLINK_IQ2Stack_TestApp_$(SOC)_CORELIST
+endif
+
+export drviolink_LIB_LIST
+export drviolink_EXAMPLE_LIST
+export drviolink_FIRM_LIST
+export iolink_FIRM_LIST
+export iolink_LIB_LIST
+export iolink_EXAMPLE_LIST
+
+iolink_component_make_include := 1
+endif
diff --git a/makefile b/makefile
--- /dev/null
+++ b/makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (c) 2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+ifeq ($(RULES_MAKE), )
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+else
+include $(RULES_MAKE)
+endif
+
+COMP = drviolink
+
+lib_$(COMP)_BUILD_DEPENDENCY = soc
+
+$(COMP)_DOXYGEN_SUPPORT = yes
+
+include $(PDK_INSTALL_PATH)/ti/build/comp_top.mk
+
diff --git a/package.bld b/package.bld
--- /dev/null
+++ b/package.bld
@@ -0,0 +1,128 @@
+/******************************************************************************\r
+ * FILE PURPOSE: Build description for the iolink Driver\r
+ ******************************************************************************\r
+ * FILE NAME: package.bld\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the build specification and description for the iolink driver\r
+ * \r
+ * The file takes the following parameters from the command line through the\r
+ * XDCARGS variable.\r
+ * XDCARGS[0] = Driver Install Type \r
+ * Valid Values are "TAR" or "SETUP"\r
+ * DEFAULT is "SETUP"\r
+ *\r
+ * Example for a valid command:\r
+ * xdc XDCARGS="SETUP" release \r
+ *\r
+ * Copyright (C) 2018, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* List of all subdirectories that combine to make the iolink Socket Driver Package. */\r
+var subDirectories = [ "src", "docs", "soc", "test", "firmware" ];\r
+\r
+var driverInstallType;\r
+\r
+/* Determine if we need to create the InstallJammer Application or not? \r
+ * iolink LLD Deliverables be either of the following formats:\r
+ * - TAR Ball Package\r
+ * - Setup Executable \r
+ * DEFAULT is a SETUP Executable. */\r
+\r
+if ((arguments[0] != "TAR") && (arguments[0] != "SETUP"))\r
+ driverInstallType = "TAR";\r
+else\r
+ driverInstallType = arguments[0];\r
+\r
+/* Irrespective of the InstallType we always create a TAR Ball Package as a part\r
+ * of the RTSC Build. Here we determine the name of the TAR Ball Package\r
+ * Format is as follows:\r
+ * iolink_<version> */\r
+var iolinkRTSCFileName = "iolink" + "_" + \r
+ driverReleaseVersion[0] + "_" + driverReleaseVersion[1] + "_" + \r
+ driverReleaseVersion[2] + "_" + driverReleaseVersion[3];\r
+\r
+/******************************************************************\r
+ ************************ Release Banner **************************\r
+ ******************************************************************/\r
+\r
+print ("************* iolink Socket Driver Build Information *************");\r
+print ("iolink Socket Driver Install : " + driverInstallType);\r
+print ("iolink Socket Driver LLD Version : " + driverReleaseVersion);\r
+print ("RTSC File Name : " + iolinkRTSCFileName);\r
+print ("iolink Socket Driver LLD Path : " + driverPath);\r
+print ("C66 Tools Directory : " + c66ToolsBaseDir);\r
+print ("M4 Tools Directory : " + m4ToolsBaseDir);\r
+print ("A15 Tools Directory : " + a15ToolsBaseDir);\r
+if (pOpts == 1) \r
+{\r
+ print ("CC LE opts : " + C66LE.ccOpts.prefix);\r
+ print ("CC BE opts : " + C66BE.ccOpts.prefix);\r
+ print ("M4 LE opts : " + M4LE.ccOpts.prefix);\r
+ print ("A15 basic opts : " + A15LE.ccOpts.prefix);\r
+}\r
+print ("****************************************************************");\r
+\r
+/* Create the release package for the iolink LLD */\r
+Pkg.defaultRelease = Pkg.addRelease (iolinkRTSCFileName, {prefix: "./packages/"});\r
+\r
+/* Moving forward we need to set the Archiver of the package to be ZIP. This is currently\r
+ * not supported in the XDC tools being used. Currenly builds need to be done with the \r
+ * following options:-\r
+ * xdc MK_FIXLISTOPTS=-t release \r
+ * ZIP is a better option as it works natively with INSTALL Jammer and we can remove the\r
+ * uncompression into a temporary directory. XDC Tools with xdc-rXX support the ZIP archiver. */\r
+//Pkg.attrs = {archiver : "zip"};\r
+\r
+/* Cycle through all the sub-directories and build all the files */\r
+for (var i = 0; i < subDirectories.length; i++) \r
+{\r
+ /* Load the capsule in the sub directory. */\r
+ var caps = xdc.loadCapsule (subDirectories[i]+"/Module.xs");\r
+\r
+ print ("Building directory " + subDirectories[i]);\r
+\r
+ /* Build the capsule. */\r
+ caps.modBuild();\r
+\r
+ /* Package the module.xs files for building via package */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = subDirectories[i]+"/Module.xs";\r
+}\r
+\r
+/* Package the remaining files */\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "config.bld";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "config_mk.bld";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "package.bld";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "package.xdc";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "package.xs";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "Settings.xdc";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "Settings.xdc.xdt";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "IOLINK.h";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "IOLINKver.h";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "IOLINKver.h.xdt";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/Doxyfile";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/doxyfile.xdt";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/buildlib.xs";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "makefile";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/makefile.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/makefile_indp.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/makefile_profile_indp.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/makefile_profile.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/makefile_icss_iolink.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "src/src_files_common.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "iolink_component.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "./lib";\r
+\r
+/* Generate Users Manual Doxyfile */\r
+var tplt = xdc.loadTemplate("./docs/doxyfile.xdt");\r
+tplt.genFile("./docs/Doxyfile",driverReleaseVersion); \r
+\r
+/* Generate Settings.xdc */\r
+var tplt = xdc.loadTemplate("./Settings.xdc.xdt");\r
+tplt.genFile("./Settings.xdc",driverReleaseVersion); \r
+\r
+/* Generate paver.h */\r
+var tplt = xdc.loadTemplate("./IOLINKver.h.xdt");\r
+tplt.genFile("./IOLINKver.h",driverReleaseVersion); \r
+\r
+ \r
diff --git a/package.xdc b/package.xdc
--- /dev/null
+++ b/package.xdc
@@ -0,0 +1,16 @@
+/******************************************************************************\r
+ * FILE PURPOSE: Package specification file \r
+ ******************************************************************************\r
+ * FILE NAME: package.xdc\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the package specification for the iolink Driver\r
+ *\r
+ * Copyright (C) 2018, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+\r
+package ti.drv.iolink[1, 0, 0, 0] {\r
+ module Settings;\r
+}\r
+\r
diff --git a/package.xs b/package.xs
--- /dev/null
+++ b/package.xs
@@ -0,0 +1,138 @@
+/*\r
+ * ======== package.xs ========\r
+ *\r
+ */\r
+\r
+\r
+/*\r
+ * ======== Package.getLibs ========\r
+ * This function is called when a program's configuration files are\r
+ * being generated and it returns the name of a library appropriate\r
+ * for the program's configuration.\r
+ */\r
+\r
+function getLibs(prog)\r
+{\r
+ var suffix = prog.build.target.suffix;\r
+ var name = "";\r
+ var socType = this.Settings.socType;\r
+ var profilingTag = "";\r
+ var fwIcss0Tag = "";\r
+\r
+ socType = socType.toLowerCase();\r
+ /* Replace the last charecter in SoC am#### to am###x */\r
+ if (socType.substring(0, 2) == "am")\r
+ {\r
+ socType = socType.substring(0, socType.length - 1);\r
+ socType = socType.concat("x");\r
+ }\r
+ \r
+ if (this.Settings.enableProfiling == true)\r
+ {\r
+ profilingTag = ".profiling"\r
+ }\r
+ name = this.$name + profilingTag + ".a" + suffix;\r
+\r
+ if (this.Settings.fwIcss0 == true)\r
+ {\r
+ fwIcss0Tag = "_icss0"\r
+ }\r
+ name = this.$name + fwIcss0Tag + profilingTag + ".a" + suffix;\r
+ \r
+ /* Read LIBDIR variable */\r
+ var lib = java.lang.System.getenv("LIBDIR");\r
+\r
+ /* If NULL, default to "lib" folder */\r
+ if (lib == null)\r
+ {\r
+ lib = "./lib";\r
+ } else {\r
+ print ("\tSystem environment LIBDIR variable defined : " + lib);\r
+ }\r
+ \r
+ var socTypes = [ \r
+ 'am571x',\r
+ 'dra72x',\r
+ 'dra75x',\r
+ 'dra78x',\r
+ 'am572x',\r
+ 'am574x',\r
+ 'am335x',\r
+ 'am437x',\r
+ 'k2h',\r
+ 'k2k',\r
+ 'k2e',\r
+ 'k2l',\r
+ 'k2g',\r
+ 'omapl137',\r
+ 'omapl138',\r
+ 'c6678',\r
+ 'c6657',\r
+ 'c6747',\r
+ 'am65xx'\r
+ ];\r
+\r
+ /* Get the SOC */\r
+ for each (var soc in socTypes)\r
+ {\r
+ if (socType.equals(soc))\r
+ {\r
+ lib = lib + "/" + soc;\r
+ name = this.$name + fwIcss0Tag + profilingTag + ".a" + suffix;\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Get target folder, if applicable */\r
+ if ( java.lang.String(suffix).contains('66') )\r
+ lib = lib + "/c66";\r
+ else if (java.lang.String(suffix).contains('a15') )\r
+ lib = lib + "/a15";\r
+ else if (java.lang.String(suffix).contains('674') )\r
+ lib = lib + "/c674";\r
+ else if (java.lang.String(suffix).contains('m4') )\r
+ lib = lib + "/m4";\r
+ else if (java.lang.String(suffix).contains('a9') )\r
+ lib = lib + "/a9";\r
+ else if (java.lang.String(suffix).contains('e9') )\r
+ lib = lib + "/arm9";\r
+ else if (java.lang.String(suffix).contains('a8') )\r
+ lib = lib + "/a8"; \r
+ else if (java.lang.String(suffix).contains('a53'))\r
+ lib = lib + "/a53";\r
+ else if (java.lang.String(suffix).contains('r5f'))\r
+ lib = lib + "/r5f";\r
+ else\r
+ throw new Error("\tUnknown target for: " + this.packageBase + lib);\r
+\r
+ var libProfiles = ["debug", "release"];\r
+ /* get the configured library profile */\r
+ for each(var profile in libProfiles)\r
+ {\r
+ if (this.Settings.libProfile.equals(profile))\r
+ {\r
+ lib = lib + "/" + profile;\r
+ break;\r
+ }\r
+ } \r
+\r
+ /* Get library name with path */\r
+ lib = lib + "/" + name;\r
+ if (java.io.File(this.packageBase + lib).exists()) {\r
+ print ("\tLinking with library " + this.$name + ":" + lib);\r
+ return lib;\r
+ }\r
+\r
+ /* Could not find any library, throw exception */\r
+ throw new Error("\tLibrary not found: " + this.packageBase + lib);\r
+}\r
+\r
+/*\r
+ * ======== package.close ========\r
+ */\r
+function close()\r
+{ \r
+ if (xdc.om.$name != 'cfg') {\r
+ return;\r
+ }\r
+}\r
diff --git a/soc/IOLINK_soc.h b/soc/IOLINK_soc.h
--- /dev/null
+++ b/soc/IOLINK_soc.h
@@ -0,0 +1,46 @@
+/**
+ * @file IOLINK_soc.h
+ *
+ * @brief IOLINK SoC level driver
+ */
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if defined(SOC_AM437x) || defined(SOC_AM437X)
+#include <ti/drv/iolink/src/v0/IOLINK_v0.h>
+
+#define IOLINK_SWIP_MAX_CNT (1U)
+
+/* IOLINK SoC level API */
+extern int32_t IOLINK_socGetSwCfg(uint32_t index, IOLINK_v0_SwAttrs *cfg);
+extern int32_t IOLINK_socSetSwCfg(uint32_t index, const IOLINK_v0_SwAttrs *cfg);
+#endif
diff --git a/soc/Module.xs b/soc/Module.xs
--- /dev/null
+++ b/soc/Module.xs
@@ -0,0 +1,39 @@
+/******************************************************************************\r
+ * FILE PURPOSE: IOLINK LLD soc files.\r
+ ******************************************************************************\r
+ * FILE NAME: module.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the module specification for IOLINK LLD soc files.\r
+ *\r
+ * Copyright (C) 2019, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Load the library utility. */\r
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : modBuild\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to add all the source files in the soc \r
+ * directory into the package.\r
+ **************************************************************************/\r
+function modBuild() \r
+{\r
+ /* Add all the .c files to the release package. */\r
+ var configFiles = libUtility.listAllFiles (".c", "soc", true);\r
+ for (var k = 0 ; k < configFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k];\r
+\r
+ /* Add all the .h files to the release package. */\r
+ var configFiles = libUtility.listAllFiles (".h", "soc", true);\r
+ for (var k = 0 ; k < configFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k];\r
+\r
+ /* Add all the .mk files to the release package. */\r
+ var mkFiles = libUtility.listAllFiles (".mk", "soc", true);\r
+ for (var k = 0 ; k < mkFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k];\r
+\r
+}\r
diff --git a/soc/am437x/IOLINK_soc.c b/soc/am437x/IOLINK_soc.c
--- /dev/null
+++ b/soc/am437x/IOLINK_soc.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * \file IOLINK_soc.c
+ *
+ * \brief AM437x SoC specific IOLINK hardware attributes.
+ *
+ * This file contains the software attributes of IOLINK firmware IP, like
+ * base address, interrupt number etc.
+ */
+
+
+#include <stdint.h>
+#include <ti/drv/iolink/IOLINK.h>
+#include <ti/drv/iolink/soc/IOLINK_soc.h>
+#include <ti/starterware/include/hw/am437x.h>
+#include <ti/drv/pruss/soc/pruicss_v1.h>
+
+/* IOLINK Soft IP configuration structure */
+IOLINK_v0_SwAttrs iolinkInitCfg[IOLINK_SWIP_MAX_CNT] =
+{
+ {
+ /* version */
+ 0,
+ /* pruIcssConfig */
+ {
+ 1, /* icssNum, 1: ICSS0, 2: ICSS1 */
+ 0, /* pruNum */
+ PRU_ICSS_DATARAM(0), /* dataMem0 */
+ PRU_ICSS_DATARAM(1), /* dataMem1 */
+ PRU_ICSS_IRAM(0), /* instMem */
+ SOC_PRU_ICSS0_U_DATA_RAM0, /* dataMemBaseAddr */
+ SOC_PRU_ICSS0_U_INTC_REG /* intcBaseAddr */
+ },
+ /* cycleCounterIntConfig */
+ {
+ 191, /* coreIntNum */
+ 7, /* socEvId */
+ 1 /* intPrio */
+ },
+ /* adjustableTimerIntConfig */
+ {
+ 127, /* coreIntNum */
+ 7, /* socEvId */
+ 1 /* intPrio */
+ },
+ /* pruCompleteIntConfig */
+ {
+ 192, /* coreIntNum */
+ 16, /* socEvId */
+ 1 /* intPrio */
+ }
+ },
+};
+
+/* IOLINK objects */
+IOLINK_v0_Object iolinkObjects[IOLINK_SWIP_MAX_CNT];
+
+/* IOLINK configuration structure */
+IOLINK_config_list IOLINK_config =
+{
+ {
+ &IOLINK_v0_FxnTable,
+ &iolinkObjects[0],
+ &iolinkInitCfg[0]
+ }
+};
+
+/**
+ * \brief This API gets the IOLINK FW configuration
+ *
+ * \param index IOLINK instance index.
+ * \param cfg Pointer to IOLINK FW config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t IOLINK_socGetFwCfg(uint32_t index, IOLINK_v0_SwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < IOLINK_SWIP_MAX_CNT)
+ {
+ *cfg = iolinkInitCfg[index];
+ }
+ else
+ {
+ ret = (-((int32_t)1));
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API sets the IOLINK FW configuration
+ *
+ * \param index IOLINK instance index.
+ * \param cfg Pointer to IOLINK FW config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t IOLINK_socSetFwCfg(uint32_t index, const IOLINK_v0_SwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < IOLINK_SWIP_MAX_CNT)
+ {
+ iolinkInitCfg[index] = *cfg;
+ }
+ else
+ {
+ ret = (-((int32_t)1));
+ }
+
+ return ret;
+}
+
+void IOLINK_pruIcssPinMuxCfg(void)
+{
+ /* input configuration RX0 ... RX7 */
+ *((uint32_t *) 0x44E10990) = ((1<<18) | 0x6); /* enable GPI0 for PRU0-ICSS0; register mcasp0_aclkx; IDK Pin31 */
+ *((uint32_t *) 0x44E10994) = ((1<<18) | 0x6); /* enable GPI1 for PRU0-ICSS0; register mcasp0_fsx; IDK Pin33 */
+ *((uint32_t *) 0x44E10998) = ((1<<18) | 0x6); /* enable GPI2 for PRU0-ICSS0; register mcasp0_axr0; IDK Pin35 */
+ *((uint32_t *) 0x44E1099C) = ((1<<18) | 0x6); /* enable GPI3 for PRU0-ICSS0; register mcasp0_ahclkr; IDK Pin32 */
+ *((uint32_t *) 0x44E109A0) = ((1<<18) | 0x6); /* enable GPI4 for PRU0-ICSS0; register mcasp0_aclkr; IDK Pin34 */
+ *((uint32_t *) 0x44E109A4) = ((1<<18) | 0x6); /* enable GPI5 for PRU0-ICSS0; register mcasp0_fsr; IDK Pin36 */
+ *((uint32_t *) 0x44E109A8) = ((1<<18) | 0x6); /* enable GPI6 for PRU0-ICSS0; register mcasp0_axr1; IDK Pin52 */
+ *((uint32_t *) 0x44E109AC) = ((1<<18) | 0x6); /* enable GPI7 for PRU0-ICSS0; register mcasp0_ahclkx; IDK Pin54 */
+
+ /* output configuration TX0 ... TX7 */
+ *((uint32_t *) 0x44E108F0) = ((1<<16) | 0x5); /* enable GPO8 for PRU0-ICSS0; register mmc0_dat3; IDK Pin56 */
+ *((uint32_t *) 0x44E108F4) = ((1<<16) | 0x5); /* enable GPO9 for PRU0-ICSS0; register mmc0_dat2; IDK Pin57 */
+ *((uint32_t *) 0x44E108F8) = ((1<<16) | 0x5); /* enable GPO10 for PRU0-ICSS0; register mmc0_dat1; IDK Pin38 */
+ *((uint32_t *) 0x44E108FC) = ((1<<16) | 0x5); /* enable GPO11 for PRU0-ICSS0; register mmc0_dat0; IDK Pin58 */
+ *((uint32_t *) 0x44E10900) = ((1<<16) | 0x5); /* enable GPO12 for PRU0-ICSS0; register mmc0_clk; IDK Pin53 (bluewire) */
+ *((uint32_t *) 0x44E10904) = ((1<<16) | 0x5); /* enable GPO13 for PRU0-ICSS0; register mmc0_cmd; IDK Pin55 (bluewire) */
+ *((uint32_t *) 0x44E10A28) = ((1<<16) | 0x4); /* enable GPO18 for PRU0-ICSS0; register uart3_rxd; IDK Pin57 (bluewire) */
+ *((uint32_t *) 0x44E10A2C) = ((1<<16) | 0x4); /* enable GPO19 for PRU0-ICSS0; register uart3_txd; IDK Pin5 (bluewire) */
+
+ /* output configuration GPIO's for TX_EN function */
+ *((uint32_t *) (0x44DF8800 + 0x478)) = 0x2; /* Enable the GPIO1 module */
+ *((uint32_t *) (0x44DF8800 + 0x490)) = 0x2; /* Enable the GPIO4 module */
+ *((uint32_t *) (0x44DF8800 + 0x498)) = 0x2; /* Enable the GPIO5 module */
+
+ *((uint32_t *) 0x4804C134) &= ~((1<<8)); /* Enable the corresponding outputs of GPIO1 */
+ *((uint32_t *) 0x48320134) &= ~((1<<10) | (1<<12)); /* Enable the corresponding outputs of GPIO4 */
+ *((uint32_t *) 0x48322134) &= ~((1<<4) | (1<<6) | (1<<26) | (1<<23) | (1<<25)); /* Enable the corresponding outputs of GPIO5 */
+
+ *((uint32_t *) 0x4804C190) = ((1<<8)); /* Clear the corresponding outputs of GPIO1 */
+ *((uint32_t *) 0x48320190) = ((1<<10) | (1<<12)); /* Clear the corresponding outputs of GPIO4 */
+ *((uint32_t *) 0x48322190) = ((1<<4) | (1<<6) | (1<<26) | (1<<23) | (1<<25)); /* Clear the corresponding outputs of GPIO5 */
+
+ *((uint32_t *) 0x44E109D8) = ((1<<16) | 0x7); /* MUX GPIO4_10 to AC23, register cam1_vd; IDK Pin4 */
+ *((uint32_t *) 0x44E10A50) = ((1<<16) | 0x7); /* MUX GPIO5_4 to P25, register spi4_sclk; IDK Pin6 */
+ *((uint32_t *) 0x44E10A58) = ((1<<16) | 0x7); /* MUX GPIO5_6 to P24, register spi4_d1; IDK Pin8 */
+ *((uint32_t *) 0x44E1082C) = ((1<<16) | 0x9); /* MUX GPIO5_23 to D11, register spi4_d1; IDK Pin10 */
+ *((uint32_t *) 0x44E109E0) = ((1<<16) | 0x7); /* MUX GPIO4_12 to AC25, register cam1_field; IDK Pin12 */
+ *((uint32_t *) 0x44E10820) = ((1<<16) | 0x9); /* MUX GPIO5_26 to B10, register gpmc_ad8; IDK Pin14 */
+ *((uint32_t *) 0x44E10824) = ((1<<16) | 0x9); /* MUX GPIO5_25 to A10, register gpmc_ad9; IDK Pin16 */
+ *((uint32_t *) 0x44E10968) = ((1<<16) | 0x7); /* MUX GPIO1_8 to L25, register uart0_ctsn; IDK Pin18 */
+}
+
+/* TBD: need to check if can use timer apis in osal */
+void IOLINK_cTimerInit(void)
+{
+ /* Set the counters default increment value to 5 */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_IEP_REG + CSL_ICSSM_IEP_GLOBAL_CFG)) &= ~(CSL_ICSSM_IEP_GLOBAL_CFG_DEFAULT_INC_MASK);
+ *((uint32_t*) (SOC_PRU_ICSS0_U_IEP_REG + CSL_ICSSM_IEP_GLOBAL_CFG)) |= (0x5<<CSL_ICSSM_IEP_GLOBAL_CFG_DEFAULT_INC_SHIFT);
+ /* Clear the counter overflow status bits */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_IEP_REG + CSL_ICSSM_IEP_GLOBAL_STATUS)) = 0x1;
+ /* Enable compare register 0 and the counter reset on compare event */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_IEP_REG + CSL_ICSSM_IEP_CMP_CFG)) = 0x3;
+ /* Clear all compare match status bits */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_IEP_REG + CSL_ICSSM_IEP_CMP_STATUS)) = 0xFF;
+ /* Set the compare value to 100000 ns (100 us) */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_IEP_REG + CSL_ICSSM_IEP_CMP0)) = 100000;
+ /* Enable the IEP Timer of ICSS0 PRU0 */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_IEP_REG + CSL_ICSSM_IEP_GLOBAL_CFG)) |= 0x1;
+
+ /* ICSS0 INTC configuration */
+ /* Set the interrupt polarity of system event 7 to active high */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_SIPR0)) |= (1<<7);
+ /* Set the type of system event 7 to level or pulse interrupt */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_SITR0)) &= ~(1<<7);
+ /* map system event with index 7 to channel 2 */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_CMR1)) &= ~(CSL_ICSSM_INTC_CMR1_CH_MAP_7_MASK);
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_CMR1)) |= (0x2<<CSL_ICSSM_INTC_CMR1_CH_MAP_7_SHIFT);
+ /* map channel 2 to interrupt with index 2 */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_HMR0)) &= ~(CSL_ICSSM_INTC_HMR0_HINT_MAP_2_MASK);
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_HMR0)) |= (0x2<<CSL_ICSSM_INTC_HMR0_HINT_MAP_2_SHIFT);
+ /* clear the system event with index 7 (pr0_iep_tim_cap_cmp_pend) */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_SICR)) = 0x7;
+ /* enable the system event with index 7 (pr0_iep_tim_cap_cmp_pend) */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_EISR)) = 0x7;
+ /* enable host interrupt output with index 2 */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_HIEISR)) = 0x2;
+ /* globally enable all interrupts */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_GER)) = 0x1;
+}
+
+#define ADJUSTABLE_TIMER_ADR SOC_DMTIMER7_REG
+#define TIMER_CLKSEL_REG 0x18
+#define TIMER_CLKCTRL_REG 0x558
+void IOLINK_adjustableTimerInit(void)
+{
+ /* enable the timer 7 module */
+ *((uint32_t*) (SOC_CM_PER_REG + TIMER_CLKCTRL_REG)) = 0x2;
+ /* timer clock = M_OSC (24 MHz) */
+ *((uint32_t*) (SOC_CM_DPLL_REG + TIMER_CLKSEL_REG)) = 0x1;
+ /* clear pending compare match events */
+ *((uint32_t*) (ADJUSTABLE_TIMER_ADR + TIMER_IRQSTATUS)) |= (1<<TIMER_IRQSTATUS_MAT_IT_FLAG_SHIFT);
+ /* enable irq for compare match events */
+ *((uint32_t*) (ADJUSTABLE_TIMER_ADR + TIMER_IRQENABLE_SET)) |= (1<<TIMER_IRQENABLE_SET_MAT_EN_FLAG_SHIFT);
+ /* enable the compare mode */
+ *((uint32_t*) (ADJUSTABLE_TIMER_ADR + TIMER_TCLR)) |= (1<<TIMER_TCLR_CE_SHIFT);
+}
+
+void IOLINK_adjustableTimerStart(uint32_t compare)
+{
+ /* stop the timer */
+ *((uint32_t*) (ADJUSTABLE_TIMER_ADR + TIMER_TCLR)) &= ~((1<<TIMER_TCLR_ST_SHIFT));
+ /* clear pending compare match events */
+ *((uint32_t*) (ADJUSTABLE_TIMER_ADR + TIMER_IRQSTATUS)) |= (1<<TIMER_IRQSTATUS_MAT_IT_FLAG_SHIFT);
+ /* reset timer to 0 */
+ *((uint32_t*) (ADJUSTABLE_TIMER_ADR + TIMER_TCRR)) = 0;
+ /* set the compare value for this timer */
+ *((uint32_t*) (ADJUSTABLE_TIMER_ADR + TIMER_TMAR)) = compare;
+ /* set timer start bit */
+ *((uint32_t*) (ADJUSTABLE_TIMER_ADR + TIMER_TCLR)) |= (1<<TIMER_TCLR_ST_SHIFT);
+}
+
+void IOLINK_adjustableTimerStop(void)
+{
+ /* clear timer start bit */
+ *((uint32_t*) (ADJUSTABLE_TIMER_ADR + TIMER_TCLR)) &= ~(1<<TIMER_TCLR_ST_SHIFT);
+}
+
+void IOLINK_clearCycleTimerInt(void)
+{
+ /* Clear all compare match status bits */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_IEP_REG + CSL_ICSSM_IEP_CMP_STATUS)) = 0xFF;
+ /* clear the system event with index 7 (pr0_iep_tim_cap_cmp_pend) */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_SICR)) = 0x7;
+}
+
+void IOLINK_clearAdjTimerInt(void)
+{
+ /* clear pending compare match events */
+ *((uint32_t*) (ADJUSTABLE_TIMER_ADR + TIMER_IRQSTATUS)) |= (1<<TIMER_IRQSTATUS_MAT_IT_FLAG_SHIFT);
+}
+
+void IOLINK_clearPruCompInt(void)
+{
+ /* clear the system event with index 16 (pr0_iep_tim_cap_cmp_pend) */
+ *((uint32_t*) (SOC_PRU_ICSS0_U_INTC_REG + CSL_ICSSM_INTC_SICR)) = 16;
+}
+
+
diff --git a/src/IOLINK_drv.c b/src/IOLINK_drv.c
--- /dev/null
+++ b/src/IOLINK_drv.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * \file IOLINK_drv.c
+ *
+ * \brief IOLINK Driver high level APIs implementation.
+ *
+ * This file contains the driver APIs for IOLINK controller.
+ */
+
+
+#include <ti/drv/iolink/IOLINK.h>
+#include <ti/drv/iolink/src/IOLINK_osal.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+/* Externs */
+extern const IOLINK_config_list IOLINK_config;
+
+/* Used to check status and initialization */
+static int32_t IOLINK_count = (-((int32_t)1));
+
+/* Default IOLINK parameters structure */
+const IOLINK_Params IOLINK_defaultParams =
+{
+ 25U, /* tA */
+};
+
+/*
+ * ======== IOLINK_init ========
+ */
+void IOLINK_init(void)
+{
+ if (IOLINK_count == (-((int32_t)1)))
+ {
+ /* Call each driver's init function */
+ for (IOLINK_count = 0; IOLINK_config[IOLINK_count].fxnTablePtr != NULL; IOLINK_count++)
+ {
+ IOLINK_config[IOLINK_count].fxnTablePtr->initFxn((IOLINK_Handle)&(IOLINK_config[IOLINK_count]));
+ }
+ }
+}
+
+/*
+ * ======== IOLINK_open ========
+ */
+IOLINK_Handle IOLINK_open(uint32_t index, IOLINK_Params *params)
+{
+ IOLINK_Handle handle;
+
+ /* Get handle for this driver instance */
+ handle = (IOLINK_Handle)&(IOLINK_config[index]);
+
+ if (handle != NULL)
+ {
+ handle = handle->fxnTablePtr->openFxn(handle, params);
+ }
+
+ return (handle);
+}
+/*
+ * ======== IOLINK_close ========
+ */
+IOLINK_STATUS IOLINK_close(IOLINK_Handle handle)
+{
+ IOLINK_STATUS status;
+
+ if (handle == NULL)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ else
+ {
+ status = handle->fxnTablePtr->closeFxn(handle);
+ }
+
+ return (status);
+}
+
+/*
+ * ======== IOLINK_control ========
+ */
+IOLINK_STATUS IOLINK_control(IOLINK_Handle handle, uint32_t cmd, void *arg)
+{
+ IOLINK_STATUS status;
+
+ if (handle == NULL)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ else
+ {
+ status = handle->fxnTablePtr->controlFxn(handle, cmd, arg);
+ }
+
+ return (status);
+}
+
+/*
+ * ======== IOLINK_Params_init =======
+ */
+void IOLINK_Params_init(IOLINK_Params *params)
+{
+ *params = IOLINK_defaultParams;
+}
diff --git a/src/IOLINK_osal.h b/src/IOLINK_osal.h
--- /dev/null
+++ b/src/IOLINK_osal.h
@@ -0,0 +1,389 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file IOLINK_osal.h
+ *
+ * @brief
+ * This is the sample OS Adaptation layer which is used by the IOLINK
+ * driver. The OSAL layer can be ported in either of the following
+ * manners to a native OS:
+ *
+ * <b> Approach 1: </b>
+ * @n Use Prebuilt Libraries
+ * - Ensure that the provide an implementation of all
+ * Osal_XXX API for their native OS.
+ * - Link the prebuilt libraries with their application.
+ * - Refer to the "example" directory for an example of this
+ * @n <b> Pros: </b>
+ * - Customers can reuse prebuilt TI provided libraries
+ * @n <b> Cons: </b>
+ * - Level of indirection in the API to get to the actual OS call
+ *
+ * <b> Approach 2: </b>
+ * @n Rebuilt Library
+ * - Create a copy of this file and modify it to directly
+ * inline the native OS calls
+ * - Rebuild the IOLINK Driver library; ensure that the Include
+ * path points to the directory where the copy of this file
+ * has been provided.
+ * - Please refer to the "test" directory for an example of this
+ * @n <b> Pros: </b>
+ * - Optimizations can be done to remove the level of indirection
+ * @n <b> Cons: </b>
+ * - IOLINK Libraries need to be rebuilt by the customer.
+ *
+ */
+
+#ifndef IOLINK_OSAL_H
+#define IOLINK_OSAL_H
+
+/* include TI OSAL library interface header files */
+#include <ti/osal/osal.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief The macro is used by the IOLINK driver to create a semaphore for
+ * each IOLINK opened in blocking mode. Semaphores created should
+ * *initially* be created with a count of 0 i.e. unavailable.
+ *
+* @param count Initial count of the semaphore. For binary semaphores,
+ * only values of 0 or 1 are valid.
+ *
+ * @param params Pointer to the instance configuration parameters. NULL
+ * denotes to use the default parameters (SemOSAL default
+ * parameters as noted in ::SemOSAL_Params.
+ *
+ * @return A void* on success or a NULL on an error
+ */
+
+#define IOLINK_osalCreateBlockingLock(count,params) (SemaphoreP_create((count),(params)))
+
+/**
+ * @brief The macro is used by the IOLINK driver to delete a previously
+ * created semaphore. This is called when a IOLINK opened in blocking mode
+ * is being closed.
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void SemOSAL_delete(void* semHandle)
+ @endverbatim
+
+ * <b> Parameter </b>
+ * @n Semaphore Handle returned by the create semaphore
+ *
+ * <b> Return Value </b>
+ * @n Not Applicable
+ */
+#define IOLINK_osalDeleteBlockingLock(X) (SemaphoreP_delete(X))
+
+
+/*!
+ * @brief Initialize params structure to default values.
+ *
+ * The default parameters are:
+ * - mode: SemOSAL_Mode_COUNTING
+ * - name: NULL
+ *
+ * @param params Pointer to the instance configuration parameters.
+ */
+#define IOLINK_osalSemParamsInit(params) (SemaphoreP_Params_init(params))
+
+
+/**
+ * @brief The macro is used by the IOLINK driver to pend on a semaphore
+ * This is called when an application tries to receive data on a blocking
+ * when there is no data available. Since all semaphores are initially
+ * created to be unavailable; this will cause the application to block.
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void SemOSAL_pend(void* semHandle)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Semaphore Handle
+ *
+ * <b> Return Value </b>
+ * @n Not Applicable
+ */
+#define IOLINK_osalPendLock(X,Y) (SemaphoreP_pend((X),(Y)))
+
+/**
+ * @brief The macro is used by the IOLINK driver to post the semaphore
+ * The driver posts the semaphore once data is received on a specific
+ *
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void SemOSAL_post(void* semHandle)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Semaphore Handle
+ *
+ * <b> Return Value </b>
+ * @n Not Applicable
+ */
+#define IOLINK_osalPostLock(X) (SemaphoreP_post(X))
+
+/**
+ * @brief Function to disable interrupts to enter a critical region
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void HwiOSAL_enterCritical()
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Not Applicable
+ *
+ * <b> Return Value </b>
+ * @n Interrupt key
+ */
+#define IOLINK_osalHardwareIntDisable() (HwiP_disable())
+
+/**
+ * @brief Function to restore interrupts to exit a critical region
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void HwiOSAL_exitCritical(int key)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Interrupt key
+ *
+ * <b> Return Value </b>
+ * @n Not Applicable
+ */
+#define IOLINK_osalHardwareIntRestore(X) (HwiP_restore(X))
+
+/**
+ * @brief Function to deregister a interrupt
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ int HwiOSAL_deregisterInterrupt(void* hwiPtr)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Interrupt handler
+ *
+ * <b> Return Value </b>
+ * @n status of operation
+ */
+#define IOLINK_osalHardwareIntDestruct(X,Y) (Osal_DeleteInterrupt((X),(Y)))
+
+/**
+ * @brief Function to register an interrupt
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ HwiP_Handle HwiP_create(X, Y, Z);
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Interrupt number
+ *
+ * <b> Parameter </b>
+ * @n hwiFxn entry function of the hardware interrupt
+ *
+ * <b> Parameter </b>
+ * @n params argument passed into the entry function
+ *
+ * <b> Return Value </b>
+ * @n Interrupt handle
+ */
+#define IOLINK_osalRegisterInterrupt(X,Y) (Osal_RegisterInterrupt((X),(Y)))
+
+/**
+ * @brief Function to initialize hardware interrupt parameters.
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void HwiP_Params_init(HwiP_Params *params)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Parameters Pointer to the hardware interrupt's parameter structure.
+ *
+ */
+#define IOLINK_osalHwiParamsInit(X) (HwiP_Params_init(X))
+
+/**
+ * @brief Function to disable specific hardware interrupt
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void HwiOSAL_disableInterrupt(unsigned int intrNum)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Interrupt number
+ *
+ */
+#define IOLINK_osalHardwareIntrDisable(X,Y) (Osal_DisableInterrupt((X),(Y)))
+
+/**
+ * @brief Function to enable specific hardware interrupt
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void HwiOSAL_enableInterrupt(unsigned int intrNum)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Interrupt number
+ *
+ */
+#define IOLINK_osalHardwareIntrEnable(X,Y) (Osal_EnableInterrupt((X),(Y)))
+
+/**
+ * @brief Function to clear specific hardware interrupt
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void IOLINK_osalHardwareIntrClear(unsigned int intrNum)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Interrupt number
+ *
+ */
+#define IOLINK_osalHardwareIntrClear(X,Y) (Osal_ClearInterrupt((X),(Y)))
+
+/**
+ * @brief Function to initialize software interrupt parameters.
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ void SwiP_Params_init(SwiP_Params *params)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Parameters Pointer to the software interrupt's parameter structure.
+ *
+ */
+#define IOLINK_osalSwiParamsInit(X) (HwiP_Params_init(X))
+
+/**
+ * @brief Function to create a software interrupt
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ SwiP_Handle SwiP_create(X, Y);
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n swiFxn entry function of the software interrupt
+ *
+ * <b> Parameter </b>
+ * @n params argument passed into the entry function
+ *
+ * <b> Return Value </b>
+ * @n Software interrupt handle
+ */
+#define IOLINK_osalSwiCreate(X,Y) (SwiP_create((X),(Y)))
+
+/**
+ * @brief Function to destruct a software interrupt
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ int SwiP_delete(void* hwiPtr)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Software interrupt handler
+ *
+ * <b> Return Value </b>
+ * @n status of operation
+ */
+#define IOLINK_osalSoftwareIntDestruct(X) (SwiP_delete(X))
+
+/**
+ * @brief Function to post a software interrupt
+ *
+ * <b> Prototype: </b>
+ * The following is the C prototype for the expected OSAL API.
+ *
+ * @verbatim
+ int SwiP_delete(void* hwiPtr)
+ @endverbatim
+ *
+ * <b> Parameter </b>
+ * @n Software interrupt handler
+ *
+ * <b> Return Value </b>
+ * @n status of operation
+ */
+#define IOLINK_osalSoftwareIntPost(X) (SwiP_post(X))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IOLINK_OSAL_H__ */
+
diff --git a/src/Module.xs b/src/Module.xs
--- /dev/null
+++ b/src/Module.xs
@@ -0,0 +1,92 @@
+/******************************************************************************\r
+ * FILE PURPOSE: IOLINK Driver Source Module specification file.\r
+ ******************************************************************************\r
+ * FILE NAME: module.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the module specification for the IOLINK Driver\r
+ *\r
+ * Copyright (C) 2018 Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Load the library utility. */\r
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");\r
+\r
+/* List of all the IOLINK Driver Files */\r
+var IOLINKSockLibFiles = [\r
+ "src/IOLINK_drv.c",\r
+ "src/v0/IOLINK_v0.c",\r
+ \r
+];\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : modBuild\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to build the IOLINK LLD Driver and to add the core\r
+ * driver files to the package. \r
+ **************************************************************************/\r
+function modBuild() \r
+{\r
+ if (socs.length != 0)\r
+ {\r
+ /* Build the device independent libraries for all the targets specified. */\r
+ for (var targets=0; targets < socs["all"].targets.length; targets++)\r
+ {\r
+ var targetFiles = IOLINKSockLibFiles.slice(); /* make copy */\r
+ var libOptions = {\r
+ copts: socs["all"].copts,\r
+ incs: lldIncludePath, \r
+ };\r
+ libUtility.buildLibrary ("", "false", "false", libOptions, Pkg.name, socs["all"].targets[targets], targetFiles);\r
+ libUtility.buildLibrary ("", "false", "false", libOptions, Pkg.name, socs["all"].targets[targets], targetFiles, true);\r
+ }\r
+ \r
+ /* Build library targets for device dependent SoCs */\r
+ for (var soc=0; soc < soc_names.length; soc++) \r
+ {\r
+ var dev = socs[soc_names[soc]];\r
+ \r
+ /* do not proceed if this SoC is not configured to be built */\r
+ if (dev.build == "false")\r
+ continue;\r
+\r
+ if (dev.socDevLib == "true")\r
+ { \r
+ var targetFiles_soc = IOLINKSockLibFiles.slice(); /* make copy */\r
+ var soc_name = soc_names[soc];\r
+ if ( soc_name.equals("k2k") )\r
+ soc_name = "k2h";\r
+\r
+ targetFiles_soc.push (deviceConstruct[0]+soc_name+deviceConstruct[1]);\r
+ /* Build the libraries for all the targets specified. */\r
+ for (var targets=0; targets < dev.targets.length; targets++)\r
+ {\r
+ var libOptions = {\r
+ copts: dev.copts,\r
+ incs: lldIncludePath, \r
+ };\r
+ libUtility.buildLibrary (soc_names[soc], "false", "true", libOptions, Pkg.name, dev.targets[targets], targetFiles_soc);\r
+ libUtility.buildLibrary (soc_names[soc], "false", "true", libOptions, Pkg.name, dev.targets[targets], targetFiles_soc, true);\r
+ }\r
+ }\r
+ } \r
+ }\r
+\r
+ /* Add all the .c files to the release package. */\r
+ var testFiles = libUtility.listAllFiles (".c", "src", true);\r
+ for (var k = 0 ; k < testFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
+\r
+ /* Add all the .h files to the release package. */\r
+ var testFiles = libUtility.listAllFiles (".h", "src", true);\r
+ for (var k = 0 ; k < testFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
+\r
+ /* Add all the .mk files to the release package. */\r
+ var mkFiles = libUtility.listAllFiles (".mk", "src", true);\r
+ for (var k = 0 ; k < mkFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k];\r
+\r
+}\r
+\r
diff --git a/src/src_files_common.mk b/src/src_files_common.mk
--- /dev/null
+++ b/src/src_files_common.mk
@@ -0,0 +1,57 @@
+#
+# Copyright (c) 2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+
+PACKAGE_SRCS_COMMON = makefile IOLINK.h iolink_component.mk \
+ docs/IOLINK_LLD_SDS.pdf docs/IOLINK_LLD_SoftwareManifest.html \
+ docs/ReleaseNotes_IOLINK_LLD.pdf \
+ src/IOLINK_drv.c src/IOLINK_drv_log.h src/IOLINK_osal.h \
+ build/makefile.mk build/makefile_indp.mk build/makefile_profile_indp.mk \
+ build/makefile_profile.mk src/src_files_common.mk
+
+# The following v1 files are all that is shipped with TDA devices
+ SRCDIR = . src src/v1
+ INCDIR = . src src/v1
+ SRCS_COMMON += IOLINK_drv.c IOLINK_v0.c
+ PACKAGE_SRCS_COMMON += src/v1 soc/IOLINK_v0.h
+
+# For all non-TDA devices, component contains all source files in library and package
+ifneq ($(SOC),$(filter $(SOC), tda2xx tda2px dra75x tda2ex tda3xx dra78x))
+ SRCDIR += src/v0
+ INCDIR += src/v0
+ SRCS_COMMON += IOLINK_v0.c
+ PACKAGE_SRCS_COMMON += src/v0 soc/IOLINK_v0.h
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk
diff --git a/src/v0/IOLINK_fw_pru0.h b/src/v0/IOLINK_fw_pru0.h
--- /dev/null
+++ b/src/v0/IOLINK_fw_pru0.h
@@ -0,0 +1,426 @@
+/*
+ * IOLINK_fw_pru0.h
+ *
+ *
+ * Copyright (c) 2018 Texas Instruments Incorporated ALL RIGHTS RESERVED
+ *
+*/
+
+const unsigned int IO_LINK_FIRMWARE_PRU0[]= {
+0x2effbb80,
+0x240002e0,
+0xf1000015,
+0x24000535,
+0x240000d7,
+0x240f0097,
+0x240000d8,
+0x242e0098,
+0x240000d9,
+0x242f0099,
+0x240000d6,
+0x240e0096,
+0x240d00f1,
+0x24010092,
+0x240500d2,
+0x24019494,
+0x240190d4,
+0x240001fa,
+0x24ffffde,
+0x24ffff9e,
+0xf0101601,
+0xc80a0108,
+0x09018484,
+0xc900ff09,
+0x1f008484,
+0x01010808,
+0x110708e0,
+0x5100e006,
+0x21002200,
+0x31040002,
+0x10000000,
+0x21002200,
+0x21001900,
+0x1f005050,
+0xc82a0108,
+0x0901c4c4,
+0xc901ff09,
+0x1f00c4c4,
+0x01012828,
+0x110728e0,
+0x5100e006,
+0x21002f00,
+0x31040002,
+0x10000000,
+0x21002f00,
+0x21002600,
+0x1f015050,
+0xc84a0108,
+0x09018585,
+0xc902ff09,
+0x1f008585,
+0x01014848,
+0x110748e0,
+0x5100e006,
+0x21003c00,
+0x31040002,
+0x10000000,
+0x21003c00,
+0x21003300,
+0x1f025050,
+0xc86a0108,
+0x0901c5c5,
+0xc903ff09,
+0x1f00c5c5,
+0x01016868,
+0x110768e0,
+0x5100e006,
+0x21004900,
+0x31040002,
+0x10000000,
+0x21004900,
+0x21004000,
+0x1f035050,
+0xc80b0108,
+0x09018686,
+0xc904ff09,
+0x1f008686,
+0x01010909,
+0x110709e0,
+0x5100e006,
+0x21005600,
+0x31040002,
+0x10000000,
+0x21005600,
+0x21004d00,
+0x1f045050,
+0xc82b0108,
+0x0901c6c6,
+0xc905ff09,
+0x1f00c6c6,
+0x01012929,
+0x110729e0,
+0x5100e006,
+0x21006300,
+0x31040002,
+0x10000000,
+0x21006300,
+0x21005a00,
+0x1f055050,
+0xc84b0108,
+0x09018787,
+0xc906ff09,
+0x1f008787,
+0x01014949,
+0x110749e0,
+0x5100e006,
+0x21007000,
+0x31040002,
+0x10000000,
+0x21007000,
+0x21006700,
+0x1f065050,
+0xc86b0108,
+0x0901c7c7,
+0xc907ff09,
+0x1f00c7c7,
+0x01016969,
+0x110769e0,
+0x5100e007,
+0x21007e00,
+0x31040002,
+0x10000000,
+0x21007e00,
+0x21007400,
+0x21008100,
+0x1f075050,
+0x01011010,
+0x67f010fd,
+0x24000010,
+0x090430e2,
+0x00e2f1f3,
+0xf100f38c,
+0xc8305011,
+0x1c305050,
+0x51040c1e,
+0x51050c4b,
+0x51000cbc,
+0x510b0cf7,
+0x51010ccf,
+0x51020cdf,
+0x51060c64,
+0x51070c6f,
+0x51080c7d,
+0x510a0cac,
+0x51090c89,
+0x51030ce9,
+0x31070002,
+0x10000000,
+0x21019000,
+0x31010002,
+0x10000000,
+0x51000cad,
+0x510b0ce8,
+0x51010cc0,
+0x51020cd0,
+0x31000002,
+0x10000000,
+0x510a0c9e,
+0x31000002,
+0x10000000,
+0x51030cda,
+0x31070002,
+0x10000000,
+0x21019000,
+0x09013001,
+0x01100101,
+0x2c210180,
+0xf0001702,
+0x6900020f,
+0x0b04e0e0,
+0xf0001702,
+0x69000214,
+0x69002d06,
+0x01012c2c,
+0x48152c1f,
+0x31030002,
+0x10000000,
+0x21019000,
+0x01012c2c,
+0x48352c1a,
+0x31030002,
+0x10000000,
+0x21019000,
+0x01203001,
+0x24000000,
+0x2c800001,
+0x1002026c,
+0x2400050c,
+0x31060002,
+0x10000000,
+0x21019000,
+0x1002026c,
+0x01046c6c,
+0x2400050c,
+0x59086c06,
+0x01203001,
+0x24000000,
+0x2c800001,
+0x10000000,
+0x21019000,
+0x01203001,
+0x24000800,
+0x2c800001,
+0x05086c6c,
+0x21019000,
+0x090730e3,
+0x00e392e2,
+0xe100022d,
+0x24000b0c,
+0x21019000,
+0x09013001,
+0x01100101,
+0x2c210180,
+0x0a6c80e0,
+0xf0001800,
+0x01203001,
+0x2c200102,
+0x4948020d,
+0x0b010d0d,
+0x12000d0d,
+0x49400204,
+0x31040002,
+0x10000000,
+0x21019000,
+0x01012d2d,
+0x090730e2,
+0x00e292e0,
+0xe02d000d,
+0x10000000,
+0x21019000,
+0xf00d1902,
+0x140002e0,
+0x12e04c4c,
+0x2400002c,
+0x2400040c,
+0x484d2d03,
+0x10000000,
+0x21019000,
+0x1f004c4c,
+0x21019000,
+0x0094eee0,
+0xe100208f,
+0x2400022d,
+0x090830e2,
+0x00e2d2e2,
+0xf100024d,
+0x01024d4d,
+0x2400070c,
+0x2400004c,
+0x31000002,
+0x10000000,
+0x21019000,
+0x01203001,
+0x24000000,
+0x2c800001,
+0x1c6dfefe,
+0x2400090c,
+0x2400002c,
+0x090830e2,
+0x00e2d2e2,
+0xc8305504,
+0x0180e2e2,
+0xf02d020d,
+0x21019000,
+0x10000000,
+0xf02d020d,
+0x21019000,
+0x01203001,
+0x24000000,
+0x2c800001,
+0x2400090c,
+0x1c6dfefe,
+0x090830e2,
+0x00e2d2e2,
+0xc8305504,
+0x0180e2e2,
+0xf02d020d,
+0x21019000,
+0x10000000,
+0xf02d020d,
+0x21019000,
+0x01203001,
+0x2c200100,
+0x49480015,
+0x4940000c,
+0x0b0300e0,
+0x0501e0e0,
+0xd0e00d05,
+0x1c6dfefe,
+0x31000002,
+0x10000000,
+0x21019000,
+0x1e6dfefe,
+0x31000002,
+0x10000000,
+0x21019000,
+0xf00d1900,
+0xd107e004,
+0x1c6dfefe,
+0x10000000,
+0x21019000,
+0x1e6dfefe,
+0x10000000,
+0x21019000,
+0x1e6dfefe,
+0x01012d2d,
+0x584d2d05,
+0x2400080c,
+0x31010002,
+0x10000000,
+0x21019000,
+0x24000a0c,
+0x31010002,
+0x10000000,
+0x21019000,
+0x00d4eee0,
+0xe100208f,
+0x2400040c,
+0x090830e2,
+0x00e2d2e2,
+0xf101024d,
+0x01014d4d,
+0x2400002d,
+0x21019000,
+0x240004e0,
+0x090330e2,
+0x00e2e0e0,
+0xf1000082,
+0x01283001,
+0x2c802201,
+0xf1001a03,
+0x10030203,
+0xd1000305,
+0x31030002,
+0x10000000,
+0x21019000,
+0x21015400,
+0x1c305555,
+0xcf0102fe,
+0x1e305555,
+0xd1020203,
+0x2400060c,
+0x21019000,
+0x2400010c,
+0x21019000,
+0x09013001,
+0x01100101,
+0x2c200100,
+0xf0001800,
+0x2400004d,
+0x0094eee2,
+0xe100228f,
+0x2400020c,
+0xc907e005,
+0x1c6dfefe,
+0x31010002,
+0x10000000,
+0x21019000,
+0x1e6dfefe,
+0x31010002,
+0x10000000,
+0x21019000,
+0x49114d05,
+0x01014d4d,
+0x310b0002,
+0x10000000,
+0x21019000,
+0x1e6dfefe,
+0x2400000c,
+0x240004e0,
+0x090330e2,
+0x00e2e0e0,
+0x240000e2,
+0xe1000002,
+0x2400030c,
+0x31030002,
+0x10000000,
+0x21019000,
+0x2400000c,
+0x00d4eee0,
+0xe100208f,
+0x31030002,
+0x10000000,
+0x21019000,
+0x240004e0,
+0x090330e2,
+0x00e2e0e0,
+0x240000e2,
+0xe1000002,
+0x2400000c,
+0x240008e0,
+0x090330e2,
+0x00e2e0e0,
+0x240000c2,
+0x24000082,
+0x24000102,
+0x104c4c42,
+0xe1002082,
+0x2400201f,
+0x21019000,
+0xe100738c,
+0x49063003,
+0x01013030,
+0x21001400,
+0x24000030,
+0x31020002,
+0x10000000,
+0x21001400,
+0x240000c0,
+0x24000480,
+0x0504e0e2,
+0x230000c3,
+0x23019dc3,
+0x23019fc3,
+0x21019e00,
+0x10000000,
+0x20c30000 };
diff --git a/src/v0/IOLINK_memoryMap.h b/src/v0/IOLINK_memoryMap.h
--- /dev/null
@@ -0,0 +1,243 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** ============================================================================
+ * @file IOLINK_memoryMap.h
+ *
+ * @brief PRU IO-Link master memory map and initialization
+ * ============================================================================
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdint.h>
+
+#ifndef IOLINK_MEMORYMAP_H_
+#define IOLINK_MEMORYMAP_H_
+
+/* status definition */
+#define IOLINK_PRU_STATUS_IDLE (0x0U)
+#define IOLINK_PRU_STATUS_COMPLETE (0x1U)
+
+/* memory map */
+#define globalSts (0x0000U)
+#define globalCtrl (0x0001U)
+#define maxResponseTime (0x0002U)
+#define firmwareRev (0x0003U)
+
+#define status_idle (0x00U)
+#define status_complete (0x01U)
+
+#define ctrlCh0 (0x0004U) /* 32 bits */
+#define statusCh0 (0x0008U) /* 16 bits */
+#define errorCh0 (0x000AU) /* 16 bits */
+
+#define ctrlCh1 (0x000CU)
+#define statusCh1 (0x0010U)
+#define errorCh1 (0x0012U)
+
+#define ctrlCh2 (0x0014U)
+#define statusCh2 (0x0018U)
+#define errorCh2 (0x001AU)
+
+#define ctrlCh3 (0x001CU)
+#define statusCh3 (0x0020U)
+#define errorCh3 (0x0022U)
+
+#define ctrlCh4 (0x0024U)
+#define statusCh4 (0x0028U)
+#define errorCh4 (0x002AU)
+
+#define ctrlCh5 (0x002CU)
+#define statusCh5 (0x0030U)
+#define errorCh5 (0x0032U)
+
+#define ctrlCh6 (0x0034U)
+#define statusCh6 (0x0038U)
+#define errorCh6 (0x003AU)
+
+#define ctrlCh7 (0x003CU)
+#define statusCh7 (0x0040U)
+#define errorCh7 (0x0042U)
+
+#define PRU_CTRL_ADDR(x) (ctrlCh0 + (0x8U * (x)))
+#define PRU_STATUS_ADDR(x) (statusCh0 + (0x8U * (x)))
+
+#define receivebfrCh0 (0x0100U)
+#define receivebfrCh1 (0x0180U)
+#define receivebfrCh2 (0x0200U)
+#define receivebfrCh3 (0x0280U)
+#define receivebfrCh4 (0x0300U)
+#define receivebfrCh5 (0x0380U)
+#define receivebfrCh6 (0x0400U)
+#define receivebfrCh7 (0x0480U)
+
+#define PRU_RXBUF_ADDR(x) (receivebfrCh0 + (0x80U * (x)))
+
+#define transmitbfrCh0 (0x0500U)
+#define transmitbfrCh1 (0x0600U)
+#define transmitbfrCh2 (0x0700U)
+#define transmitbfrCh3 (0x0800U)
+#define transmitbfrCh4 (0x0900U)
+#define transmitbfrCh5 (0x0A00U)
+#define transmitbfrCh6 (0x0B00U)
+#define transmitbfrCh7 (0x0C00U)
+
+#define PRU_TXBUF_ADDR(x) (transmitbfrCh0 + (0x100U * (x)))
+
+#define channel0mem (0x0D00U)
+#define channel1mem (0x0D10U)
+#define channel2mem (0x0D20U)
+#define channel3mem (0x0D30U)
+#define channel4mem (0x0D40U)
+#define channel5mem (0x0D50U)
+#define channel6mem (0x0D60U)
+#define channel7mem (0x0D70U)
+
+/* LUT's of PRU 0 */
+#define pru0LutAdr (0x0E00U)
+#define sampleratelutAdr (0x0E00U)
+#define startbitfilterAdr (0x0F00U)
+/* LUT's of PRU 1 */
+#define pru1LutAdr (0x0E00U)
+#define averagingfilterAdr (0x0E00U)
+#define paritylutAdr (0x0F00U)
+
+
+/*
+ * PRU pin configuration
+ * The PRU uses GPI0 ... 7 for RX0 ... 7
+ * TX0 ... 7 can be bound to any of the remaining GPO's
+ */
+#define channel0TxPin (8U)
+#define channel1TxPin (9U)
+#define channel2TxPin (10U)
+#define channel3TxPin (11U)
+#define channel4TxPin (19U)
+#define channel5TxPin (12U)
+#define channel6TxPin (13U)
+#define channel7TxPin (18U)
+
+/*
+ * TxEn pin configuration
+ * You can use any of the available GPIO pins for the TX enable signal
+ */
+
+/* TX enable GPIO port hw address */
+#define channel0TxEnGpioAdr (0x48320000U)
+#define channel1TxEnGpioAdr (0x48322000U)
+#define channel2TxEnGpioAdr (0x48322000U)
+#define channel3TxEnGpioAdr (0x48322000U)
+#define channel4TxEnGpioAdr (0x48320000U)
+#define channel5TxEnGpioAdr (0x48322000U)
+#define channel6TxEnGpioAdr (0x48322000U)
+#define channel7TxEnGpioAdr (0x4804C000U)
+
+/* TX enable GPIO pin configuration */
+#define channel0TxEnGpioPin (1U << 10U)
+#define channel1TxEnGpioPin (1U << 4U)
+#define channel2TxEnGpioPin (1U << 6U)
+#define channel3TxEnGpioPin (1U << 23U)
+#define channel4TxEnGpioPin (1U << 12U)
+#define channel5TxEnGpioPin (1U << 26U)
+#define channel6TxEnGpioPin (1U << 25U)
+#define channel7TxEnGpioPin (1U << 8U)
+
+/* ========================================================================== */
+/* Local Variables */
+/* ========================================================================== */
+
+/*
+ * initialization values
+ * this section sets the PRU's look-up table entries
+ * each LUT is 256 bytes in size and can be exchanged for a more optimized version if necessary
+ */
+
+typedef struct lookUpTablesPRU0 lookUpTablesPRU0;
+typedef struct lookUpTablesPRU1 lookUpTablesPRU1;
+
+struct lookUpTablesPRU0
+{
+ uint8_t sampleratelut[256U];
+ uint8_t startbitfilterlut[256U];
+} __attribute__((packed));
+
+struct lookUpTablesPRU1
+{
+ uint8_t symbolfilterlut[256U];
+ uint8_t paritylut[256U];
+} __attribute__((packed));
+
+/* 8 bit look-up table initialization */
+lookUpTablesPRU0 initData0 =
+{
+ /*
+ * samplerate LUT
+ * This look-up table serves as a baud rate selection table
+ * It determined the sample rate of each channel for any of the 3 (or more) baud rates
+ * The PRU will check for a bit set on bit position x. If you enter 2 (COM2) in the PRU's baud rate register,
+ * it will only take a new sample if bit 2 is set in the LUT for a counter given offset.
+ */
+ .sampleratelut = {14,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,14,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,14,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,14,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,14,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8,8,8,14,8,8,8,8,8,12,8,8,8,8,8,12,8,8,8},
+
+ /*
+ * startbit LUT
+ * This look-up table indicates the position of a start bit edge in a given octet of bits.
+ * Zero means that there is no valid startbit in the bit stream.
+ */
+ .startbitfilterlut = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,3,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,6,6,6,6,0,0,0,0,0,0,0,0,0,0,0,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,4,4,0,0,0,0,0,3,0,0,0,2,0,0,0}
+};
+
+lookUpTablesPRU1 initData1 =
+{
+ /*
+ * symbolfilter LUT
+ * This look-up table is a simple averaging filter.
+ * NOTE: The signal level is indicated by bit 7 and not bit 0
+ */
+ .symbolfilterlut = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0x80,0,0,0,0,0,0,0,0x80,0,0,0,0x80,0,0x80,0x80,0x80,0,0,0,0,0,0,0,0x80,0,0,0,0x80,0,0x80,0x80,0x80,0,0,0,0x80,0,0x80,0x80,0x80,0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0,0,0,0,0,0,0,0x80,0,0,0,0x80,0,0x80,0x80,0x80,0,0,0,0x80,0,0x80,0x80,0x80,0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0,0,0,0x80,0,0x80,0x80,0x80,0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0,0,0,0,0,0,0,0x80,0,0,0,0x80,0,0x80,0x80,0x80,0,0,0,0x80,0,0x80,0x80,0x80,0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0,0,0,0x80,0,0x80,0x80,0x80,0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0,0,0,0x80,0,0x80,0x80,0x80,0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80},
+
+ /*
+ * parity LUT
+ * This look-up table calculates the parity of a given octet
+ * NOTE: The parity bit is indicated by bit 7 and not bit 0
+ */
+ .paritylut = {0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0,0x80,0x0,0x0,0x80,0x80,0x0,0x0,0x80,0x0,0x80,0x80,0x0}
+};
+
+
+uint32_t *memInitDataPRU0 = (uint32_t*)(&initData0);
+uint32_t *memInitDataPRU1 = (uint32_t*)(&initData1);
+
+#endif /* IOLINK_MEMORYMAP_H_ */
diff --git a/src/v0/IOLINK_v0.c b/src/v0/IOLINK_v0.c
--- /dev/null
+++ b/src/v0/IOLINK_v0.c
@@ -0,0 +1,1162 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * \file IOLINK_v0.c
+ *
+ * \brief PRU IO-Link FW specific IO-Link Master Driver.
+ *
+ * This file contains the driver APIs for IO-Link FW controller.
+ *
+ */
+
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/*#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/runtime/Error.h>
+#include <ti/sysbios/knl/Swi.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/knl/Semaphore.h>*/ /* TBD: call osal.h */
+
+#include <ti/drv/iolink/src/v0/IOLINK_v0.h>
+#include <ti/drv/iolink/src/v0/IOLINK_memoryMap.h>
+#include <ti/drv/iolink/src/v0/IOLINK_fw_pru0.h>
+
+#define IOLINK_v0 IO_LINK_FIRMWARE_PRU0
+
+/* ========================================================================== */
+/* External Variables */
+/* ========================================================================== */
+
+extern PRUICSS_Config pruss_config[2 + 1];
+
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+static void IOLINK_init_v0(IOLINK_Handle handle);
+static IOLINK_STATUS IOLINK_close_v0(IOLINK_Handle handle);
+static IOLINK_Handle IOLINK_open_v0(IOLINK_Handle handle, const IOLINK_Params *params);
+static IOLINK_STATUS IOLINK_control_v0(IOLINK_Handle handle, uint32_t cmd, void *arg);
+
+static IOLINK_STATUS IOLINK_pruInit(IOLINK_Handle handle);
+static void IOLINK_setCallbacks(IOLINK_Handle handle, IOLINK_v0_Callbacks *callbacks);
+static void IOLINK_enableChannels(IOLINK_Handle handle, bool enable);
+static void IOLINK_sendCommand(IOLINK_Handle handle, uint32_t channel, uint32_t cmd, uint32_t cmdArg);
+static void IOLINK_setBuffer(IOLINK_Handle handle, uint32_t channel, uint8_t txBufLen, uint8_t rxBufLen, uint8_t *txBuf, uint8_t *rxBuf);
+static void IOLINK_sendBuffer(IOLINK_Handle handle, uint32_t channel);
+static void IOLINK_start10msTimer(IOLINK_Handle handle, uint32_t channel);
+static void IOLINK_stop10msTimer(IOLINK_Handle handle, uint32_t channel);
+static void IOLINK_setCycleTimer(IOLINK_Handle handle, uint32_t channel, uint32_t delay);
+static void IOLINK_startCycleTimer(IOLINK_Handle handle, uint32_t channel);
+static void IOLINK_stopCycleTimer(IOLINK_Handle handle, uint32_t channel);
+static void IOLINK_startAdjustableTimer(IOLINK_Handle handle, uint32_t channel, uint8_t type, uint32_t compare);
+static void IOLINK_stopAdjustableTimer(IOLINK_Handle handle);
+
+static void IOLINK_cycleTickHwi(void *arg);
+static void IOLINK_adjustableTimerHwi(void *arg);
+static void IOLINK_pruCompleteHwi(void *arg);
+
+static void IOLINK_softwareTimerSwiFxn(void *arg0, void *arg1);
+static void IOLINK_cycleTimerSwiFxn(void *arg0, void *arg1);
+static void IOLINK_tRenTimerSwiFxn(void *arg0, void *arg1);
+static void IOLINK_tDmtTimerSwiFxn(void *arg0, void *arg1);
+static void IOLINK_pruCompleteSwiFxn(void *arg0, void *arg1);
+
+/* IOLINK function table for IOLINK master driver implementation */
+const IOLINK_FxnTable IOLINK_v0_FxnTable =
+{
+ &IOLINK_init_v0,
+ &IOLINK_open_v0,
+ &IOLINK_close_v0,
+ &IOLINK_control_v0
+};
+
+/*
+ * ======== IOLINK_init_v0 ========
+ */
+static void IOLINK_init_v0(IOLINK_Handle handle)
+{
+ if(handle != NULL)
+ {
+ /* Mark the object as available */
+ ((IOLINK_v0_Object *)(handle->object))->isOpen = (bool)false;
+ }
+ return;
+}
+
+/*
+ * ======== IOLINK_open_v0 ========
+ */
+static IOLINK_Handle IOLINK_open_v0(IOLINK_Handle handle, const IOLINK_Params *params)
+{
+ IOLINK_v0_SwAttrs const *swAttrs;
+ IOLINK_v0_Object *object;
+ PRUICSS_Handle pruIcssHandle;
+ OsalRegisterIntrParams_t interruptRegParams;
+ SwiP_Params swiParams;
+ IOLINK_PruIcssHwiAttrs *hwiAttrs;
+ uint32_t key;
+ IOLINK_STATUS status = IOLINK_STATUS_SUCCESS;
+ uint32_t i;
+
+ /* Input parameter validation */
+ if(handle != NULL)
+ {
+ /* Get the pointer to the object and swAttrs */
+ swAttrs = (IOLINK_v0_SwAttrs const *)handle->ipAttrs;
+ object = (IOLINK_v0_Object *)handle->object;
+
+ /* Determine if the device index was already opened */
+ key = IOLINK_osalHardwareIntDisable();
+ if(object->isOpen == true)
+ {
+ IOLINK_osalHardwareIntRestore(key);
+ handle = NULL;
+ }
+ else
+ {
+ /* Mark the handle as being used */
+ object->isOpen = (bool)true;
+ IOLINK_osalHardwareIntRestore(key);
+
+ /* IOLink Timer initialization */
+ for (i = 0; i < IOLINK_MAX_NUM_CHN; i++)
+ {
+ object->timerConfig.cycleTimer.enable[i] = false;
+ object->timerConfig.cycleTimer.timer[i] = 0;
+ object->timerConfig.swTimer.enable[i] = false;
+ }
+
+ object->timerConfig.swTimer.timer = 0;
+ object->timerConfig.swTimer.timerCnt = 0;
+ object->timerConfig.swTimer.timerDiv = 100U;
+
+
+ /* Store the IOLINK parameters */
+ if (params == NULL)
+ {
+ /* No params passed in, so use the defaults */
+ IOLINK_Params_init(&(object->iolinkParams));
+ }
+ else {
+ /* Copy the params contents */
+ object->iolinkParams = *params;
+ }
+
+ /* Initialize ICSS PRU */
+ pruIcssHandle = PRUICSS_create(pruss_config, swAttrs->pruIcssConfig.icssNum);
+ if (pruIcssHandle != NULL)
+ {
+ object->pruIcssHandle = pruIcssHandle;
+ PRUICSS_enableOCPMasterAccess(pruIcssHandle);
+ }
+ else
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Initialize timers */
+ IOLINK_cTimerInit();
+ IOLINK_adjustableTimerInit();
+ }
+
+ /* Register H/W interrupts */
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Register pruCompleteHwi */
+ Osal_RegisterInterrupt_initParams(&interruptRegParams);
+
+ /* Populate the interrupt parameters */
+ hwiAttrs = (IOLINK_PruIcssHwiAttrs *)&swAttrs->pruCompleteIntConfig;
+ interruptRegParams.corepacConfig.arg = (uintptr_t)handle;
+ interruptRegParams.corepacConfig.name = NULL;
+ interruptRegParams.corepacConfig.priority = hwiAttrs->intPriority;
+ interruptRegParams.corepacConfig.isrRoutine = (HwiP_Fxn)&IOLINK_pruCompleteHwi;
+ interruptRegParams.corepacConfig.corepacEventNum = hwiAttrs->socEvId;
+ interruptRegParams.corepacConfig.intVecNum = hwiAttrs->coreIntNum;
+ IOLINK_osalRegisterInterrupt(&interruptRegParams, &(object->pruCompleteHwi));
+ if(object->pruCompleteHwi == NULL)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Register cycleTickHwi */
+ hwiAttrs = (IOLINK_PruIcssHwiAttrs *)&swAttrs->cycleCounterIntConfig;
+ interruptRegParams.corepacConfig.priority = hwiAttrs->intPriority;
+ interruptRegParams.corepacConfig.isrRoutine = (HwiP_Fxn)&IOLINK_cycleTickHwi;
+ interruptRegParams.corepacConfig.corepacEventNum = hwiAttrs->socEvId;
+ interruptRegParams.corepacConfig.intVecNum = hwiAttrs->coreIntNum;
+ IOLINK_osalRegisterInterrupt(&interruptRegParams, &(object->cycleCounterHwi));
+ if(object->cycleCounterHwi == NULL)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Register adjustableTimerHwi */
+ hwiAttrs = (IOLINK_PruIcssHwiAttrs *)&swAttrs->adjustableTimerIntConfig;
+ interruptRegParams.corepacConfig.priority = hwiAttrs->intPriority;
+ interruptRegParams.corepacConfig.isrRoutine = (HwiP_Fxn)&IOLINK_adjustableTimerHwi;
+ interruptRegParams.corepacConfig.corepacEventNum = hwiAttrs->socEvId;
+ interruptRegParams.corepacConfig.intVecNum = hwiAttrs->coreIntNum;
+ IOLINK_osalRegisterInterrupt(&interruptRegParams, &(object->adjustableTimerHwi));
+ if(object->adjustableTimerHwi == NULL)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ }
+
+ /* Register S/W interrupts */
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Register softwareTimerSwi */
+ SwiP_Params_init(&swiParams);
+ swiParams.arg0 = (uintptr_t)handle;
+ swiParams.arg1 = (uintptr_t)0;
+ object->softwareTimerSwi = IOLINK_osalSwiCreate((SwiP_Fxn)&IOLINK_softwareTimerSwiFxn,
+ &swiParams);
+ if(object->softwareTimerSwi == NULL)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Register cycleTimerElapsedSwi */
+ for (i = 0; i < IOLINK_MAX_NUM_CHN; i++)
+ {
+ swiParams.arg1 = (uintptr_t)i;
+ object->cycleTimerElapsedSwi[i] = IOLINK_osalSwiCreate((SwiP_Fxn)&IOLINK_cycleTimerSwiFxn,
+ &swiParams);
+ if(object->cycleTimerElapsedSwi[i] == NULL)
+ {
+ status = IOLINK_STATUS_ERROR;
+ break;
+ }
+ }
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Register tDMTTimerSwi */
+ swiParams.arg1 = (uintptr_t)0;
+ object->tDMTTimerSwi = IOLINK_osalSwiCreate((SwiP_Fxn)&IOLINK_tDmtTimerSwiFxn,
+ &swiParams);
+ if(object->tDMTTimerSwi == NULL)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Register tRenTimerSwi */
+ object->tRenTimerSwi = IOLINK_osalSwiCreate((SwiP_Fxn)&IOLINK_tRenTimerSwiFxn,
+ &swiParams);
+ if(object->tRenTimerSwi == NULL)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Register pruCompleteSwi */
+ for (i = 0; i < IOLINK_MAX_NUM_CHN; i++)
+ {
+ swiParams.arg1 = (uintptr_t)i;
+ object->pruCompleteSwi[i] = IOLINK_osalSwiCreate((SwiP_Fxn)&IOLINK_pruCompleteSwiFxn,
+ &swiParams);
+ if(object->pruCompleteSwi[i] == NULL)
+ {
+ status = IOLINK_STATUS_ERROR;
+ break;
+ }
+ }
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ status = IOLINK_pruInit(handle);
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ IOLINK_enableChannels(handle, true);
+ }
+ }
+
+ if (status == IOLINK_STATUS_ERROR)
+ {
+ handle = NULL;
+ }
+ }
+ }
+
+ return (handle);
+}
+
+/*
+ * ======== IOLINK_close_v0 ========
+ */
+static IOLINK_STATUS IOLINK_close_v0(IOLINK_Handle handle)
+{
+ IOLINK_v0_SwAttrs const *swAttrs;
+ IOLINK_v0_Object *object;
+ IOLINK_STATUS status = IOLINK_STATUS_SUCCESS;
+ uint32_t i;
+
+ if(handle != NULL)
+ {
+ /* Get the pointer to the object and swAttrs */
+ swAttrs = (IOLINK_v0_SwAttrs const *)handle->ipAttrs;
+ object = (IOLINK_v0_Object *)handle->object;
+
+ /* De-register H/W interrupts */
+ if (object->adjustableTimerHwi != NULL)
+ {
+ IOLINK_osalHardwareIntDestruct(object->adjustableTimerHwi, swAttrs->adjustableTimerIntConfig.socEvId);
+ object->adjustableTimerHwi = NULL;
+ }
+
+ if (object->cycleCounterHwi != NULL)
+ {
+ IOLINK_osalHardwareIntDestruct(object->cycleCounterHwi, swAttrs->cycleCounterIntConfig.socEvId);
+ object->cycleCounterHwi = NULL;
+ }
+
+ if (object->pruCompleteHwi != NULL)
+ {
+ IOLINK_osalHardwareIntDestruct(object->pruCompleteHwi, swAttrs->pruCompleteIntConfig.socEvId);
+ object->pruCompleteHwi = NULL;
+ }
+
+ /* De-register S/W interrupts */
+ /* TBD: use osal swi APIs */
+ if (object->softwareTimerSwi != NULL)
+ {
+ IOLINK_osalSoftwareIntDestruct(object->softwareTimerSwi);
+ object->softwareTimerSwi = NULL;
+ }
+
+ if (object->tRenTimerSwi != NULL)
+ {
+ IOLINK_osalSoftwareIntDestruct(object->tRenTimerSwi);
+ object->tRenTimerSwi = NULL;
+ }
+
+ if (object->tDMTTimerSwi != NULL)
+ {
+ IOLINK_osalSoftwareIntDestruct(object->tDMTTimerSwi);
+ object->tDMTTimerSwi = NULL;
+ }
+
+ for (i = 0; i < IOLINK_MAX_NUM_CHN; i++)
+ {
+ if (object->cycleTimerElapsedSwi[i] != NULL)
+ {
+ IOLINK_osalSoftwareIntDestruct(object->cycleTimerElapsedSwi[i]);
+ object->cycleTimerElapsedSwi[i] = NULL;
+ }
+ if (object->pruCompleteSwi[i] != NULL)
+ {
+ IOLINK_osalSoftwareIntDestruct(object->pruCompleteSwi[i]);
+ object->pruCompleteSwi[i] = NULL;
+ }
+ }
+
+ IOLINK_enableChannels(handle, false);
+
+ /* Disable the PRU */
+ if (PRUICSS_pruDisable(object->pruIcssHandle, swAttrs->pruIcssConfig.pruNum) != 0)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+
+ object->pruIcssHandle = NULL;
+ object->isOpen = (bool)false;
+ }
+
+ return (status);
+}
+
+/*
+ * ======== IOLINK_control_v0 ========
+ */
+static IOLINK_STATUS IOLINK_control_v0(IOLINK_Handle handle, uint32_t cmd, void *arg)
+{
+ uint32_t *data = (uint32_t *)arg;
+ IOLINK_STATUS status = IOLINK_STATUS_SUCCESS;
+
+ /* Input parameter validation */
+ if(handle != NULL)
+ {
+ switch (cmd)
+ {
+ case IOLINK_CTRL_SEND_CMD:
+ {
+ IOLINK_sendCommand(handle, *data, *(data + 1U), *(data + 2U));
+ break;
+ }
+
+ case IOLINK_CTRL_SET_XFER_BUFFER:
+ {
+ IOLINK_setBuffer(handle, *data, (uint8_t)(*(data + 1U)), (uint8_t)(*(data + 2U)), (uint8_t *)(*(data + 3U)), (uint8_t *)(*(data + 4U)));
+ break;
+ }
+
+ case IOLINK_CTRL_START_XFER:
+ {
+ IOLINK_sendBuffer(handle, *data);
+ break;
+ }
+
+ case IOLINK_CTRL_START_TIMER:
+ {
+ if (*(data + 1U) == IOLINK_TIMER_TYPE_10MS)
+ {
+ IOLINK_start10msTimer(handle, *data);
+ }
+ else if (*(data + 1U) == IOLINK_TIMER_TYPE_CYCLE)
+ {
+ IOLINK_startCycleTimer(handle, *data);
+ }
+ else
+ {
+ IOLINK_startAdjustableTimer(handle, *data, *(data + 2U), *(data + 3U));
+ }
+ break;
+ }
+
+ case IOLINK_CTRL_STOP_TIMER:
+ {
+ if (*(data + 1U) == IOLINK_TIMER_TYPE_10MS)
+ {
+ IOLINK_stop10msTimer(handle, *data);
+ }
+ else if (*(data+1) == IOLINK_TIMER_TYPE_CYCLE)
+ {
+ IOLINK_stopCycleTimer(handle, *data);
+ }
+ else
+ {
+ IOLINK_stopAdjustableTimer(handle);
+ }
+ break;
+ }
+
+ case IOLINK_CTRL_SET_CYCLE_TIMER:
+ {
+ IOLINK_setCycleTimer(handle, *data, *(data + 1U));
+ break;
+ }
+
+ case IOLINK_CTRL_SET_CALLBACKS:
+ {
+ IOLINK_setCallbacks(handle, (IOLINK_v0_Callbacks *)data);
+ break;
+ }
+
+
+ default:
+ {
+ status = IOLINK_STATUS_ERROR;
+ break;
+ }
+ }
+ }
+ else
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+
+ return (status);
+}
+
+/*
+ * ======== IOLINK_pruInit ========
+ */
+static IOLINK_STATUS IOLINK_pruInit(IOLINK_Handle handle)
+{
+ IOLINK_v0_SwAttrs const *swAttrs;
+ IOLINK_v0_Object *object;
+ uint32_t i;
+ uint32_t baseAddr;
+ IOLINK_STATUS status = IOLINK_STATUS_SUCCESS;
+ //uint8_t global_cfg[4U] = {0, 0, 25U, 0}; /* globalSts, globalCtrl, maxResponseTime (Tbit), firmwareRev */
+ uint32_t global_cfg; /* firmwareRev */
+
+ /* Get the pointer to the object and swAttrs */
+ swAttrs = (IOLINK_v0_SwAttrs const *)handle->ipAttrs;
+ object = (IOLINK_v0_Object *)handle->object;
+
+ /* Disable the PRU */
+ if (PRUICSS_pruDisable(object->pruIcssHandle, swAttrs->pruIcssConfig.pruNum) != 0)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Reset the PRU */
+ if (PRUICSS_pruReset(object->pruIcssHandle, swAttrs->pruIcssConfig.pruNum) != 0)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ baseAddr = swAttrs->pruIcssConfig.dataMemBaseAddr;
+
+ /* PRU DRAM cleanup */
+ for(i = 0; i < 1024U; i++)
+ {
+ *((uint32_t*) (baseAddr + i * 4U)) = 0U;
+ }
+
+ /* Initialize the PRU's DRAM */
+ global_cfg = (0 << 0) | /* globalSts */
+ (0 << 8U) | /* globalCtrl */
+ (object->iolinkParams.tA << 16U) | /* maxResponseTime (Tbit) */
+ (swAttrs->version << 24U); /* firmwareRev */
+ *((uint32_t*) (baseAddr + globalSts)) = global_cfg;
+
+ /* Set the PRU's TX pins (GPO's) */
+ *((uint32_t*) (baseAddr + channel0mem + 4U)) = (channel0TxPin << 24U);
+ *((uint32_t*) (baseAddr + channel1mem + 4U)) = (channel1TxPin << 24U);
+ *((uint32_t*) (baseAddr + channel2mem + 4U)) = (channel2TxPin << 24U);
+ *((uint32_t*) (baseAddr + channel3mem + 4U)) = (channel3TxPin << 24U);
+ *((uint32_t*) (baseAddr + channel4mem + 4U)) = (channel4TxPin << 24U);
+ *((uint32_t*) (baseAddr + channel5mem + 4U)) = (channel5TxPin << 24U);
+ *((uint32_t*) (baseAddr + channel6mem + 4U)) = (channel6TxPin << 24U);
+ *((uint32_t*) (baseAddr + channel7mem + 4U)) = (channel7TxPin << 24U);
+
+ /* Set the PRU's TX Enable ports (GPIO's) */
+ *((uint32_t*) (baseAddr + channel0mem + 8U)) = channel0TxEnGpioAdr;
+ *((uint32_t*) (baseAddr + channel1mem + 8U)) = channel1TxEnGpioAdr;
+ *((uint32_t*) (baseAddr + channel2mem + 8U)) = channel2TxEnGpioAdr;
+ *((uint32_t*) (baseAddr + channel3mem + 8U)) = channel3TxEnGpioAdr;
+ *((uint32_t*) (baseAddr + channel4mem + 8U)) = channel4TxEnGpioAdr;
+ *((uint32_t*) (baseAddr + channel5mem + 8U)) = channel5TxEnGpioAdr;
+ *((uint32_t*) (baseAddr + channel6mem + 8U)) = channel6TxEnGpioAdr;
+ *((uint32_t*) (baseAddr + channel7mem + 8U)) = channel7TxEnGpioAdr;
+
+ /* Set the PRU's TX Enable pins (GPIO's) */
+ *((uint32_t*) (baseAddr + channel0mem + 12U)) = channel0TxEnGpioPin;
+ *((uint32_t*) (baseAddr + channel1mem + 12U)) = channel1TxEnGpioPin;
+ *((uint32_t*) (baseAddr + channel2mem + 12U)) = channel2TxEnGpioPin;
+ *((uint32_t*) (baseAddr + channel3mem + 12U)) = channel3TxEnGpioPin;
+ *((uint32_t*) (baseAddr + channel4mem + 12U)) = channel4TxEnGpioPin;
+ *((uint32_t*) (baseAddr + channel5mem + 12U)) = channel5TxEnGpioPin;
+ *((uint32_t*) (baseAddr + channel6mem + 12U)) = channel6TxEnGpioPin;
+ *((uint32_t*) (baseAddr + channel7mem + 12U)) = channel7TxEnGpioPin;
+
+ /* Initialize the PRU's pinmux */
+ IOLINK_pruIcssPinMuxCfg();
+
+ /* ICSS0 interrupt INTC configuration */
+ baseAddr = swAttrs->pruIcssConfig.intcBaseAddr;
+
+ /* Set the interrupt polarity of system event 16 to active high */
+ *((uint32_t*) (baseAddr + CSL_ICSSM_INTC_SIPR0)) |= (1<<16);
+ /* Set the type of system event 16 to level or pulse interrupt */
+ *((uint32_t*) (baseAddr + CSL_ICSSM_INTC_SITR0)) &= ~(1<<16);
+ /* map system event with index 16 to channel 3 */
+ *((uint32_t*) (baseAddr + CSL_ICSSM_INTC_CMR4)) &= ~(CSL_ICSSM_INTC_CMR4_CH_MAP_16_MASK);
+ *((uint32_t*) (baseAddr + CSL_ICSSM_INTC_CMR4)) |= (0x3<<CSL_ICSSM_INTC_CMR4_CH_MAP_16_SHIFT);
+ /* map channel 3 to interrupt with index 3 */
+ *((uint32_t*) (baseAddr + CSL_ICSSM_INTC_HMR0)) &= ~(CSL_ICSSM_INTC_HMR0_HINT_MAP_3_MASK);
+ *((uint32_t*) (baseAddr + CSL_ICSSM_INTC_HMR0)) |= (0x3<<CSL_ICSSM_INTC_HMR0_HINT_MAP_3_SHIFT);
+ /* clear the system event with index 16 (pr0_iep_tim_cap_cmp_pend) */
+ *((uint32_t*) (baseAddr + CSL_ICSSM_INTC_SICR)) = 16;
+ /* enable the system event with index 16 (pr0_iep_tim_cap_cmp_pend) */
+ *((uint32_t*) (baseAddr + CSL_ICSSM_INTC_EISR)) = 16;
+ /* enable host interrupt output with index 3 */
+ *((uint32_t*) (baseAddr + CSL_ICSSM_INTC_HIEISR)) = 0x3;
+ /* globally enable all interrupts */
+ *((uint32_t*) (baseAddr + CSL_ICSSM_INTC_GER)) = 0x1;
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* Write the DRAM and IRAM of PRU 0 */
+ if (PRUICSS_pruWriteMemory(object->pruIcssHandle,
+ swAttrs->pruIcssConfig.instMem,
+ 0,
+ (uint32_t *)IO_LINK_FIRMWARE_PRU0,
+ sizeof(IO_LINK_FIRMWARE_PRU0)) == 0)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /* load the LUT's into the PRU data memory */
+ if (PRUICSS_pruWriteMemory(object->pruIcssHandle,
+ swAttrs->pruIcssConfig.dataMem0,
+ pru0LutAdr,
+ memInitDataPRU0,
+ 1024U) == 0)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ /*
+ * load the LUT of the other PRU, initialization and
+ * loading of the other PRU's firmware could be done here
+ */
+ if (PRUICSS_pruWriteMemory(object->pruIcssHandle,
+ swAttrs->pruIcssConfig.dataMem1,
+ pru1LutAdr,
+ memInitDataPRU1,
+ 1024U) == 0)
+
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ }
+
+ if (status == IOLINK_STATUS_SUCCESS)
+ {
+ if (PRUICSS_pruEnable(object->pruIcssHandle, swAttrs->pruIcssConfig.pruNum) != 0)
+ {
+ status = IOLINK_STATUS_ERROR;
+ }
+ }
+ }
+
+ return (status);
+}
+
+/*
+ * ======== IOLINK_setCallbacks ========
+ */
+static void IOLINK_setCallbacks(IOLINK_Handle handle, IOLINK_v0_Callbacks *callbacks)
+{
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ object->callbacks = *callbacks;
+}
+
+/*
+ * ======== IOLINK_enableChannels ========
+ */
+static void IOLINK_enableChannels(IOLINK_Handle handle, bool enable)
+{
+ IOLINK_v0_SwAttrs const *swAttrs;
+ uint32_t baseAddr;
+
+ /* Get the pointer to the swAttrs */
+ swAttrs = (IOLINK_v0_SwAttrs const *)handle->ipAttrs;
+
+ baseAddr = swAttrs->pruIcssConfig.dataMemBaseAddr;
+
+ *((uint32_t*) (baseAddr)) &= ~(0xFFU << 8U);
+ *((uint32_t*) (baseAddr)) |= (((uint32_t)enable) << 8U);
+}
+
+/*
+ * ======== IOLINK_sendCommand ========
+ */
+static void IOLINK_sendCommand(IOLINK_Handle handle, uint32_t channel, uint32_t cmd, uint32_t cmdArg)
+{
+ IOLINK_v0_SwAttrs const *swAttrs;
+ uint32_t pruCtrlRegAddr;
+
+ /* Get the pointer to the swAttrs */
+ swAttrs = (IOLINK_v0_SwAttrs const *)handle->ipAttrs;
+
+ pruCtrlRegAddr = swAttrs->pruIcssConfig.dataMemBaseAddr + PRU_CTRL_ADDR(channel);
+
+ switch (cmd)
+ {
+ case IOLINK_COMMAND_STARTPULSE:
+ *((uint32_t *)(pruCtrlRegAddr)) |= (1U << 2U);
+ *((uint32_t *)(pruCtrlRegAddr)) |= 0x01U;
+ break;
+
+ case IOLINK_COMMAND_SETCOM:
+ *((uint32_t *)(pruCtrlRegAddr)) &= ~(0xFFU << 8U);
+ *((uint32_t *)(pruCtrlRegAddr)) |= (cmdArg << 8U);
+ break;
+
+ default:
+ break;
+ }
+
+ return;
+}
+
+/*
+ * ======== IOLINK_setBuffer ========
+ */
+static void IOLINK_setBuffer(IOLINK_Handle handle, uint32_t channel, uint8_t txBufLen, uint8_t rxBufLen, uint8_t *txBuf, uint8_t *rxBuf)
+{
+ IOLINK_v0_SwAttrs const *swAttrs;
+ IOLINK_v0_Object *object;
+ uint32_t pruTxBufAddr;
+ uint8_t newlen;
+ uint8_t tmp[128];
+ uint8_t i;
+ IOLINK_dataConverter convert;
+
+ /* Get the pointer to the object and swAttrs */
+ swAttrs = (IOLINK_v0_SwAttrs const *)handle->ipAttrs;
+ object = (IOLINK_v0_Object *)handle->object;
+
+ pruTxBufAddr = swAttrs->pruIcssConfig.dataMemBaseAddr + PRU_TXBUF_ADDR(channel);
+
+ object->rxBufConfig.rxBufAddr[channel] = rxBuf;
+ object->rxBufConfig.rxBufLen[channel] = (uint32_t)rxBufLen;
+
+ /*
+ * add the buffer length information bytes at the beginning and
+ * copy the new array of data to the PRU's TX buffer
+ */
+ if ((txBufLen + 2U) % 4U != 0)
+ {
+ newlen = ((txBufLen + 2U)/4U) * 4U + 4U;
+ }
+ else
+ {
+ newlen = (txBufLen + 2U);
+ }
+
+ tmp[0] = txBufLen;
+ tmp[1] = rxBufLen;
+
+ for(i = 0; i < txBufLen; i++)
+ {
+ tmp[i + 2U] = txBuf[i];
+ }
+
+ for (i = txBufLen; i < newlen; i++)
+ {
+ tmp[i + 2U] = 0;
+ }
+
+ {
+ convert.data8bit = tmp;
+
+ newlen = newlen/4U;
+
+ for(int i = 0; i < newlen; i ++)
+ {
+ *((uint32_t *)(pruTxBufAddr + (i * 4U))) = convert.data32bit[i];
+ }
+ }
+
+ return;
+}
+
+/*
+ * ======== IOLINK_sendBuffer ========
+ */
+static void IOLINK_sendBuffer(IOLINK_Handle handle, uint32_t channel)
+{
+ IOLINK_v0_SwAttrs const *swAttrs;
+ uint32_t pruCtrlRegAddr;
+
+ /* Get the pointer to the swAttrs */
+ swAttrs = (IOLINK_v0_SwAttrs const *)handle->ipAttrs;
+
+ pruCtrlRegAddr = swAttrs->pruIcssConfig.dataMemBaseAddr + PRU_CTRL_ADDR(channel);
+ *((uint32_t *)pruCtrlRegAddr) |= 0x1U;
+}
+
+/*
+ * ======== IOLINK_start10msTimer ========
+ */
+static void IOLINK_start10msTimer(IOLINK_Handle handle, uint32_t channel)
+{
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ object->timerConfig.swTimer.enable[channel] = true;
+ if (object->timerConfig.swTimer.timerCnt == 0)
+ {
+ object->timerConfig.swTimer.timer = 0;
+ }
+ object->timerConfig.swTimer.timerCnt++;
+}
+
+/*
+ * ======== IOLINK_stop10msTimer ========
+ */
+static void IOLINK_stop10msTimer(IOLINK_Handle handle, uint32_t channel)
+{
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ object->timerConfig.swTimer.enable[channel] = false;
+ object->timerConfig.swTimer.timerCnt--;
+}
+
+/*
+ * ======== IOLINK_setCycleTimer ========
+ */
+static void IOLINK_setCycleTimer(IOLINK_Handle handle, uint32_t channel, uint32_t delay)
+{
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ object->timerConfig.cycleTimer.delay[channel] = delay;
+}
+
+/*
+ * ======== IOLINK_startCycleTime ========
+ */
+static void IOLINK_startCycleTimer(IOLINK_Handle handle, uint32_t channel)
+{
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ object->timerConfig.cycleTimer.timer[channel] = 0;
+ object->timerConfig.cycleTimer.enable[channel] = true;
+}
+
+/*
+ * ======== IOLINK_stopCycleTimer ========
+ */
+void IOLINK_stopCycleTimer(IOLINK_Handle handle, uint32_t channel)
+{
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ object->timerConfig.cycleTimer.enable[channel] = false;
+}
+
+/*
+ * ======== IOLINK_startAdjustableTimer ========
+ */
+static void IOLINK_startAdjustableTimer(IOLINK_Handle handle, uint32_t channel, uint8_t type, uint32_t compare)
+{
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ object->timerConfig.adjTimer.timerType = type;
+ object->timerConfig.adjTimer.activeChannel = channel;
+ IOLINK_adjustableTimerStart(compare);
+}
+
+/*
+ * ======== IOLINK_stopAdjustableTimer ========
+ */
+static void IOLINK_stopAdjustableTimer(IOLINK_Handle handle)
+{
+ IOLINK_adjustableTimerStop();
+}
+
+/*
+ * ======== IOLINK_cycleTickHwi ========
+ *
+ * This hardware interrupt runs at 100 us per tick
+ * It is used to generate the clock for 8 independent software timers (cycle timer) and
+ * one 10 ms tick (slower software timers which are supported by the IO-Link master stack)
+ */
+static void IOLINK_cycleTickHwi(void *arg)
+{
+ IOLINK_Handle handle = (IOLINK_Handle)arg;
+ IOLINK_v0_Object *object;
+ uint32_t i;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ IOLINK_clearCycleTimerInt();
+
+ /* 100 us software timer for cycle time measurement */
+ for (i = 0; i < IOLINK_MAX_NUM_CHN; i++)
+ {
+ if (object->timerConfig.cycleTimer.enable[i] == true)
+ {
+ object->timerConfig.cycleTimer.timer[i]++;
+ if (object->timerConfig.cycleTimer.timer[i] >= object->timerConfig.cycleTimer.delay[i])
+ {
+ object->timerConfig.cycleTimer.enable[i] = false;
+ object->timerConfig.cycleTimer.timer[i] = 0;
+ IOLINK_osalSoftwareIntPost(object->cycleTimerElapsedSwi[i]);
+ }
+ }
+ }
+
+ if (object->timerConfig.swTimer.timerCnt > 0)
+ {
+ object->timerConfig.swTimer.timer++;
+
+ /* generate 10 ms tick for additional timers */
+ if (object->timerConfig.swTimer.timer >= object->timerConfig.swTimer.timerDiv)
+ {
+ object->timerConfig.swTimer.timer = 0;
+ IOLINK_osalSoftwareIntPost(object->softwareTimerSwi);
+ }
+ }
+}
+
+/*
+ * ======== IOLINK_adjustableTimerHwi ========
+ *
+ * This hardware interrupt is called by the adjustable timer after it has reached its compare threshold.
+ */
+static void IOLINK_adjustableTimerHwi(void *arg)
+{
+ IOLINK_Handle handle = (IOLINK_Handle)arg;
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ /* clear adjustable timer pending compare match events */
+ IOLINK_clearAdjTimerInt();
+
+ switch(object->timerConfig.adjTimer.timerType)
+ {
+ case IOLINK_TIMER_ADJ_TDMT:
+ IOLINK_osalSoftwareIntPost(object->tDMTTimerSwi);
+ break;
+
+ case IOLINK_TIMER_ADJ_TREN:
+ IOLINK_osalSoftwareIntPost(object->tRenTimerSwi);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*
+ * ======== IOLINK_pruCompleteHwi ========
+ *
+ * This hardware interrupt is called by the PRU after it has finished receiving data from the device
+ */
+static void IOLINK_pruCompleteHwi(void *arg)
+{
+ IOLINK_Handle handle = (IOLINK_Handle)arg;
+ IOLINK_v0_SwAttrs const *swAttrs;
+ IOLINK_v0_Object *object;
+ uint32_t baseAddr;
+ uint32_t i;
+
+ /* Get the pointer to the object and swAttrs */
+ swAttrs = (IOLINK_v0_SwAttrs const *)handle->ipAttrs;
+ object = (IOLINK_v0_Object *)handle->object;
+
+ IOLINK_clearPruCompInt();
+
+ /* check every channel for completion (status byte) */
+ baseAddr = swAttrs->pruIcssConfig.dataMemBaseAddr;
+ for (i = 0; i < IOLINK_MAX_NUM_CHN; i++)
+ {
+ if ((*((uint32_t*) (baseAddr + PRU_STATUS_ADDR(i))) & 0xFFFFU) == IOLINK_PRU_STATUS_COMPLETE)
+ {
+ /* reset the status byte and post a software interrupt */
+ *((uint32_t*) (baseAddr + PRU_STATUS_ADDR(i))) &= 0xFFFF0000U;
+ IOLINK_osalSoftwareIntPost(object->pruCompleteSwi[i]);
+ }
+ }
+}
+
+/*
+ * ======== IOLINK_softwareTimerSwiFxn ========
+ *
+ * This software interrupt can be used as a clock for more software timers,
+ * which should be provided by the stack (10 ms tick).
+ */
+static void IOLINK_softwareTimerSwiFxn(void *arg0, void *arg1)
+{
+ IOLINK_Handle handle = (IOLINK_Handle)arg0;
+ IOLINK_v0_Object *object;
+ uint32_t i;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ for(i = 0; i < IOLINK_MAX_NUM_CHN; i++)
+ {
+ if(object->timerConfig.swTimer.enable[i] == true)
+ {
+ object->callbacks.swTimerCallback(handle, i);
+ }
+ }
+}
+
+/*
+ * ======== IOLINK_cycleTimerSwiFxn ========
+ *
+ * This software interrupt is used to call a stack supplied callback function.
+ * arg1 indicates the dedicated channel number
+ */
+static void IOLINK_cycleTimerSwiFxn(void *arg0, void *arg1)
+{
+ IOLINK_Handle handle = (IOLINK_Handle)arg0;
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ object->callbacks.cycleTimerCallback(handle, (uint32_t)arg1);
+}
+
+/*
+ * ======== IOLINK_tRenTimerSwiFxn ========
+ *
+ * This software interrupt is used to call a stack supplied callback function.
+ * arg1 indicates the dedicated channel number
+ */
+static void IOLINK_tRenTimerSwiFxn(void *arg0, void *arg1)
+{
+ IOLINK_Handle handle = (IOLINK_Handle)arg0;
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ object->callbacks.adjTimerCallback(handle,
+ object->timerConfig.adjTimer.activeChannel,
+ IOLINK_TIMER_ADJ_TREN);
+}
+
+/*
+ * ======== IOLINK_tDmtTimerSwiFxn ========
+ *
+ * This software interrupt is used to call a stack supplied callback function.
+ * arg1 indicates the dedicated channel number
+ */
+static void IOLINK_tDmtTimerSwiFxn(void *arg0, void *arg1)
+{
+ IOLINK_Handle handle = (IOLINK_Handle)arg0;
+ IOLINK_v0_Object *object;
+
+ /* Get the pointer to the object */
+ object = (IOLINK_v0_Object *)handle->object;
+
+ object->callbacks.adjTimerCallback(handle,
+ object->timerConfig.adjTimer.activeChannel,
+ IOLINK_TIMER_ADJ_TDMT);
+}
+
+/*
+ * ======== IOLINK_pruCompleteSwiFxn ========
+ *
+ * This software interrupt is used to call a stack supplied callback function.
+ * arg1 indicates the dedicated channel number
+ *
+ * The PRU indicates the completion of a communication cycle by generating a hardware interrupt,
+ * which will then post the software interrupt with the dedicated channel number.
+ *
+ * This software interrupt will then read the PRU's buffer and copy it to the stack maintained
+ * memory address. It will also check for errors and call the stack supplied callback function.
+ */
+static void IOLINK_pruCompleteSwiFxn(void *arg0, void *arg1)
+{
+ IOLINK_Handle handle = (IOLINK_Handle)arg0;
+ IOLINK_v0_SwAttrs const *swAttrs;
+ IOLINK_v0_Object *object;
+ uint32_t baseAddr;
+ uint32_t chRxBuf;
+ uint32_t channel;
+ uint8_t *rxBuf;
+ uint8_t rxBuflen;
+ uint32_t tmp[64];
+ uint32_t i;
+ uint8_t receivedLen;
+ IOLINK_dataConverter convert;
+
+
+ /* Get the pointer to the object and swAttrs */
+ swAttrs = (IOLINK_v0_SwAttrs const *)handle->ipAttrs;
+ object = (IOLINK_v0_Object *)handle->object;
+
+ baseAddr = swAttrs->pruIcssConfig.dataMemBaseAddr;
+ channel = (uint32_t)arg1;
+ chRxBuf = baseAddr + PRU_RXBUF_ADDR(channel);
+
+ /* load received bytes into buffer */
+ rxBuf = object->rxBufConfig.rxBufAddr[channel];
+ rxBuflen = object->rxBufConfig.rxBufLen[channel];
+
+
+ for(i = 0; i < 64U; i++)
+ {
+ tmp[i] = *((uint32_t*) (chRxBuf + 4U * i));
+ }
+
+ convert.data32bit = tmp;
+
+ receivedLen = convert.data8bit[0];
+
+ for (i = 0; i < rxBuflen; i++)
+ {
+ rxBuf[i] = convert.data8bit[i+1];
+ }
+
+ /* check the PRU's error register and the received message length */
+ if((receivedLen != rxBuflen) || ((*((uint32_t*) (baseAddr + PRU_STATUS_ADDR(channel))) & 0xFFFF0000) != 0))
+ {
+ object->callbacks.xferErrRspCallback(handle, channel);
+ }
+ else
+ {
+ object->callbacks.xferRspCallback(handle, channel);
+ }
+}
+
+
diff --git a/src/v0/IOLINK_v0.h b/src/v0/IOLINK_v0.h
--- /dev/null
+++ b/src/v0/IOLINK_v0.h
@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** ============================================================================
+ * @file IOLINK_v0.h
+ *
+ * @brief IO-Link Master driver implementation for IO-Link PRU firmware.
+ *
+ * The IOLINK header file should be included in an application as follows:
+ * @code
+ * #include <ti/drv/iolink/IOLINK.h>
+ * #include <ti/drv/iolink/src/v0/IOLINK_v0.h>
+ * @endcode
+ *
+ * ============================================================================
+ */
+
+#ifndef IOLINK_V0_H
+#define IOLINK_V0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+#include <stdint.h>
+#include <ti/csl/src/ip/icss/V0/cslr_icssm_iep.h>
+#include <ti/csl/src/ip/icss/V0/cslr_icssm_intc.h>
+#include <ti/csl/src/ip/timer/V1/hw_timer.h>
+
+#include <ti/drv/iolink/IOLINK.h>
+#include <ti/drv/iolink/src/IOLINK_osal.h>
+#include <ti/drv/pruss/pruicss.h>
+
+/** ===========================================================================
+ *
+ * @defgroup IOLINK_V0_API IOLINK v0 driver API
+ * @ingroup IOLINK_V0_API
+ *
+ * ============================================================================
+ */
+/**
+@defgroup IOLINK_V0_DATASTRUCT IOLINK v0 driver Data Structures
+@ingroup IOLINK_V0_API
+*/
+/**
+@defgroup IOLINK_V0_FUNCTION IOLINK v0 driver Functions
+@ingroup IOLINK_V0_API
+*/
+/**
+@defgroup IOLINK_V0_ENUM IOLINK IOLINK v0 driver Enumerated Data Types
+@ingroup IOLINK_V0_API
+*/
+
+/** ===========================================================================
+ * @addtogroup IOLINK_V0_ENUM
+ @{
+ * ============================================================================
+ */
+
+/*!
+ * @brief Max number of channels per IO-Link instance
+ */
+#define IOLINK_MAX_NUM_CHN 8U
+
+/*!
+ * This command sets the stack callback functions to the driver.
+ * This command returns IOLINK_STATUS_SUCCESS if successful.
+ * Returns IOLINK_STATUS_ERROR otherwise.
+ * The arguments to this IOCTL is the uint32_t * of callback functions structure
+ */
+#define IOLINK_CTRL_SET_CALLBACKS (0U)
+
+/*!
+ * IOLINK control to send user specificed commands to the PRU. This IOCTL returns
+ * IOLINK_STATUS_SUCCESS if the command is sent successfully. Returns IOLINK_STATUS_ERROR
+ * otherwise.
+ * The argument to this IOCTL is the uint32_t * of the channel, command, commard arg
+ */
+#define IOLINK_CTRL_SEND_CMD (1U)
+
+/*!
+ * This command sets the TX/RX buffer for send/receive request.
+ * This command returns IOLINK_STATUS_SUCCESS if successful.
+ * Returns IOLINK_STATUS_ERROR otherwise.
+ * The arguments to this IOCTL is the uint32_t * of channel, txBufLen, rxBufLen, txBuf, rxBuf.
+ */
+#define IOLINK_CTRL_SET_XFER_BUFFER (2U)
+
+/*!
+ * This command starts a new TX/RX data cycle.
+ * This command returns IOLINK_STATUS_SUCCESS if successful.
+ * Returns IOLINK_STATUS_ERROR otherwise.
+ * The arguments to this IOCTL is the uint32_t * of channel
+ */
+#define IOLINK_CTRL_START_XFER (3U)
+
+/*!
+ * This command starts a timer.
+ * This command returns IOLINK_STATUS_SUCCESS if successful.
+ * Returns IOLINK_STATUS_ERROR otherwise.
+ * The arguments to this IOCTL is the uint32_t * of channel, timer type, delay type, delay.
+ */
+#define IOLINK_CTRL_START_TIMER (4U)
+
+/*!
+ * This command stops a timer.
+ * This command returns IOLINK_STATUS_SUCCESS if successful.
+ * Returns IOLINK_STATUS_ERROR otherwise.
+ * The arguments to this IOCTL is the uint32_t * of timer type.
+ */
+#define IOLINK_CTRL_STOP_TIMER (5U)
+
+/*!
+ * This command sets the delay time of a cycle timer.
+ * This command returns IOLINK_STATUS_SUCCESS if successful.
+ * Returns IOLINK_STATUS_ERROR otherwise.
+ * The arguments to this IOCTL is the uint32_t * of channel, timer delay
+ */
+#define IOLINK_CTRL_SET_CYCLE_TIMER (6U)
+
+/*!
+ * @brief IO-Link handle definitions
+ */
+#define IOLINK_HANDLE_COUNT (1U)
+#define IOLINK_HANDLE_ICSS0_PRU0 (0U)
+#define IOLINK_HANDLE_ICSS0_PRU1 (1U)
+#define IOLINK_HANDLE_ICSS1_PRU0 (2U)
+#define IOLINK_HANDLE_ICSS1_PRU1 (3U)
+
+/*!
+ * @brief IO-Link commands
+ */
+#define IOLINK_COMMAND_STARTPULSE (0U)
+#define IOLINK_COMMAND_SETCOM (1U)
+
+/*!
+ * @brief IO-Link timer types
+ */
+#define IOLINK_TIMER_TYPE_10MS (0U)
+#define IOLINK_TIMER_TYPE_ADJ (1U)
+#define IOLINK_TIMER_TYPE_CYCLE (2U)
+
+/*!
+ * @brief IO-Link adjuster timer types
+ */
+#define IOLINK_TIMER_ADJ_TREN (0U)
+#define IOLINK_TIMER_ADJ_TDMT (1U)
+
+/* @} */
+
+/**
+ * \addtogroup IOLINK_V0_DATASTRUCT
+ * @{
+ */
+
+/*!
+ * @brief union structure for 8-bit and 32-bit conversion
+ */
+typedef union IOLINK_dataConverter_s
+{
+ uint8_t *data8bit;
+ uint32_t *data32bit;
+} IOLINK_dataConverter;
+
+/*!
+ * @brief IO-Link PRU ICSS config data structure
+ */
+typedef struct IOLINK_PruIcssConfig_s
+{
+ /*! ICSS instance number (0 or 1) */
+ uint32_t icssNum;
+ /*! PRU instance number (0 or 1) */
+ uint32_t pruNum;
+ /*! PRU data memory 0 */
+ uint32_t dataMem0;
+ /*! PRU data memory 1 */
+ uint32_t dataMem1;
+ /*! PRU instruction memory */
+ uint32_t instMem;
+ /*! PRU data memory base address */
+ uint32_t dataMemBaseAddr;
+ /*! PRU intc base address */
+ uint32_t intcBaseAddr;
+
+} IOLINK_PruIcssConfig;
+
+/*!
+ * @brief IO-Link PRU ICSS HWI attributes
+ */
+typedef struct IOLINK_PruIcssHwiAttrs_s
+{
+ /*! SoC core interrupt number */
+ uint32_t coreIntNum;
+ /*! SoC event ID */
+ uint32_t socEvId;
+ /*! interrupt priority */
+ uint32_t intPriority;
+
+} IOLINK_PruIcssHwiAttrs;
+
+/*!
+ * @brief IOLINK_v0 PRU software IP attributes
+ */
+typedef struct IOLINK_v0_SwAttrs_s
+{
+ /*! ICSS PRU firmware version */
+ uint32_t version;
+ /*! ICSS PRU configuration */
+ IOLINK_PruIcssConfig pruIcssConfig;
+ /*! HWI config attrs of IO-Link cycle counter */
+ IOLINK_PruIcssHwiAttrs cycleCounterIntConfig;
+ /*! HWI config attrs of IO-Link adjustable timer */
+ IOLINK_PruIcssHwiAttrs adjustableTimerIntConfig;
+ /*! HWI config attrs of IO-Link PRU complete */
+ IOLINK_PruIcssHwiAttrs pruCompleteIntConfig;
+
+} IOLINK_v0_SwAttrs;
+
+/*!
+ * @brief IO-Link channel specific 100us cycle timer configuration
+ */
+typedef struct IOLINK_cycleTimerConfig_s
+{
+ bool enable[IOLINK_MAX_NUM_CHN];
+ uint32_t timer[IOLINK_MAX_NUM_CHN];
+ uint32_t delay[IOLINK_MAX_NUM_CHN];
+} IOLINK_cycleTimerConfig;
+
+/*!
+ * @brief IO-Link channel specific 10ms software timer configuration
+ */
+typedef struct IOLINK_swTimerConfig_s
+{
+ bool enable[IOLINK_MAX_NUM_CHN];
+ uint32_t timerCnt;
+ uint32_t timer;
+ uint32_t timerDiv;
+} IOLINK_swTimerConfig;
+
+/*!
+ * @brief IO-Link adjustable timer configuration
+ *
+ * Structure storing the high precision hardware timer configuration
+ * (used for start up sequence timings)
+ */
+typedef struct IOLINK_Adjustable_TimerConfig_s
+{
+ uint32_t timerType;
+ uint32_t activeChannel;
+} IOLINK_AdjTimerConfig;
+
+/*!
+ * @brief IO-Link channel specific timer configuration
+ */
+typedef struct IOLINK_TimerConfig_s
+{
+ IOLINK_cycleTimerConfig cycleTimer;
+ IOLINK_swTimerConfig swTimer;
+ IOLINK_AdjTimerConfig adjTimer;
+} IOLINK_TimerConfig;
+
+/*!
+ * @brief IO-Link channel specific receive buffer configuration
+ */
+typedef struct IOLINK_RxBufConfig_s
+{
+ uint8_t *rxBufAddr[IOLINK_MAX_NUM_CHN];
+ uint8_t rxBufLen[IOLINK_MAX_NUM_CHN];
+} IOLINK_RxBufConfig;
+
+/*!
+ * @brief The definition of a callback function for cycle timer
+ *
+ * @param IOLINK_Handle IO-Link handle #
+ *
+ * @param channel IO-Link channel #
+ *
+ */
+typedef void (*IOLINK_cycleTimerCallbackFxn)(IOLINK_Handle handle, uint32_t channel);
+
+/*!
+ * @brief The definition of a callback function for software timer
+ *
+ * @param IOLINK_Handle IO-Link handle #
+ *
+ * @param channel IO-Link channel #
+ *
+ */
+typedef void (*IOLINK_swTimerCallbackFxn)(IOLINK_Handle handle, uint32_t channel);
+
+/*!
+ * @brief The definition of a callback function for adjustable timer
+ *
+ * @param IOLINK_Handle IO-Link handle #
+ *
+ * @param channel IO-Link channel #
+ *
+ * @param uint32_t timer delay type
+ *
+ */
+typedef void (*IOLINK_adjTimerCallbackFxn)(IOLINK_Handle handle, uint32_t channel, uint32_t delayType);
+
+/*!
+ * @brief The definition of a callback function for data transfer
+ *
+ * @param IOLINK_Handle IO-Link handle #
+ *
+ * @param channel IO-Link channel #
+ *
+ */
+typedef void (*IOLINK_xferRspCallbackFxn)(IOLINK_Handle handle, uint32_t channel);
+
+/*!
+ * @brief The definition of a callback function for data transfer error
+ *
+ * @param IOLINK_Handle IO-Link handle #
+ *
+ * @param channel IO-Link channel #
+ *
+ */
+typedef void (*IOLINK_xferErrRspCallbackFxn)(IOLINK_Handle handle, uint32_t channel);
+
+/*!
+ * @brief IOLINK callback function pointers data structure
+ */
+typedef struct IOLINK_v0_Callbacks_s
+{
+ /*! cycle timer callback function pointer */
+ IOLINK_cycleTimerCallbackFxn cycleTimerCallback;
+ /*! 10 msec timer callbackFxn function pointer */
+ IOLINK_swTimerCallbackFxn swTimerCallback;
+ /*! adjustable timer callback function pointer */
+ IOLINK_adjTimerCallbackFxn adjTimerCallback;
+ /*! data transfer response callback function pointer */
+ IOLINK_xferRspCallbackFxn xferRspCallback;
+ /*! data transfer error response callback function pointer */
+ IOLINK_xferErrRspCallbackFxn xferErrRspCallback;
+
+} IOLINK_v0_Callbacks;
+
+/*!
+ * @brief IOLINK_v0 Object
+ *
+ * The application must not access any member variables of this structure!
+ */
+typedef struct IOLINK_v0_Object_s
+{
+ /*! ICSS PRU handle */
+ PRUICSS_Handle pruIcssHandle;
+ /*! Saved IO-Link params */
+ IOLINK_Params iolinkParams;
+
+ /*! Cycle timer h/w interrupt handler */
+ void *cycleCounterHwi;
+ /*! Adjustable timer h/w interrupt handler */
+ void *adjustableTimerHwi;
+ /*! PRU transfer complete h/w interrupt handler */
+ void *pruCompleteHwi;
+
+ /*! Software timer s/w interrupt handler */
+ void *softwareTimerSwi;
+ /*! Receive enable delay adjustable timer s/w interrupt handler */
+ void *tRenTimerSwi;
+ /*! Master message delay adjusable timer s/w interrupt handler */
+ void *tDMTTimerSwi;
+
+ /*! cycle timer timeout s/w interrupt handler */
+ void *cycleTimerElapsedSwi[IOLINK_MAX_NUM_CHN];
+ /*! PRU transfer complete s/w interrupt handler */
+ void *pruCompleteSwi[IOLINK_MAX_NUM_CHN];
+
+ /*! Timer configuration data */
+ IOLINK_TimerConfig timerConfig;
+ /*! RX buffer configuration data */
+ IOLINK_RxBufConfig rxBufConfig;
+
+ /*! callback function pointer data */
+ IOLINK_v0_Callbacks callbacks;
+
+ /*! flag to indicate PRU instance is open */
+ bool isOpen;
+
+} IOLINK_v0_Object, *IOLINK_v0_Handle;
+
+/* @} */
+
+/**
+ * \addtogroup IOLINK_V0_FUNCTION
+ * @{
+ */
+
+/* IOLINK function table pointer */
+extern const IOLINK_FxnTable IOLINK_v0_FxnTable;
+
+/* SoC specific functions */
+extern void IOLINK_pruIcssPinMuxCfg(void);
+
+/* TBD: need to move to osal */
+extern void IOLINK_cTimerInit(void);
+extern void IOLINK_adjustableTimerInit(void);
+extern void IOLINK_adjustableTimerStart(uint32_t compare);
+extern void IOLINK_adjustableTimerStop(void);
+extern void IOLINK_clearCycleTimerInt(void);
+extern void IOLINK_clearAdjTimerInt(void);
+extern void IOLINK_clearPruCompInt(void);
+
+extern void IOLINK_registerSwi(uintptr_t arg0, uintptr_t arg1, void *isrFnPtr, void *swi);
+extern void IOLINK_destructSwi(void *swi);
+extern void IOLINK_postSwi(void *swi);
+
+/* @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IOLINK_V0_H */
diff --git a/test/Module.xs b/test/Module.xs
--- /dev/null
+++ b/test/Module.xs
@@ -0,0 +1,63 @@
+/******************************************************************************\r
+ * FILE PURPOSE: IOLINK LLD unit test files.\r
+ ******************************************************************************\r
+ * FILE NAME: module.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the module specification for IOLINK LLD test files.\r
+ *\r
+ * Copyright (C) 2019, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Load the library utility. */\r
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : modBuild\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to add all the source files in the test \r
+ * directory into the package.\r
+ **************************************************************************/\r
+function modBuild() \r
+{\r
+ /* Add all the .c files to the release package. */\r
+ var testFiles = libUtility.listAllFiles (".c", "test", true);\r
+ for (var k = 0 ; k < testFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
+\r
+ /* Add all the .h files to the release package. */\r
+ var testFiles = libUtility.listAllFiles (".h", "test", true);\r
+ for (var k = 0 ; k < testFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
+\r
+ /* Add all the makefiles files to the release package. */\r
+ var testFiles = libUtility.listAllFiles ("makefile", "test", true);\r
+ for (var k = 0 ; k < testFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
+\r
+ /* Add all the .cmd files to the release package. */\r
+ var testFiles = libUtility.listAllFiles (".cmd", "test", true);\r
+ for (var k = 0 ; k < testFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
+\r
+ /* Add all the .cfg files to the release package. */\r
+ var testFiles = libUtility.listAllFiles (".cfg", "test", true);\r
+ for (var k = 0 ; k < testFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
+\r
+ /* Add the .txt to the package */\r
+ var testFiles = libUtility.listAllFiles (".txt", "test", true);\r
+ for (var k = 0 ; k < testFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = testFiles[k];\r
+ \r
+ /* Add all the .mk files to the release package. */\r
+ var mkFiles = libUtility.listAllFiles (".mk", "test", true);\r
+ for (var k = 0 ; k < mkFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k];\r
+\r
+ /* Add all the .xs files to the release package. */\r
+ var mkFiles = libUtility.listAllFiles (".xs", "test", true);\r
+ for (var k = 0 ; k < mkFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k];\r
+}\r
diff --git a/test/iq2_stack_test/.ccsproject b/test/iq2_stack_test/.ccsproject
--- /dev/null
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<?ccsproject version="1.0"?>
+<projectOptions>
+ <ccsVersion value="7.3.0"/>
+ <deviceVariant value="Cortex A.AM4379"/>
+ <deviceFamily value="TMS470"/>
+ <deviceEndianness value="little"/>
+ <codegenToolVersion value="GNU_4.9.3:Linaro"/>
+ <isElfFormat value="true"/>
+ <rts value="libc.a"/>
+ <createSlaveProjects value=""/>
+ <defaultConfiguration value="AM437x_release"/>
+ <filesToOpen value=""/>
+ <isTargetManual value="false"/>
+ <connection value="common/targetdb/connections/TIXDS100v2_Connection.xml"/>
+</projectOptions>
diff --git a/test/iq2_stack_test/.cproject b/test/iq2_stack_test/.cproject
--- /dev/null
@@ -0,0 +1,335 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="com.ti.ccstudio.buildDefinitions.TMS470.Default.841046752">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.TMS470.Default.841046752" moduleId="org.eclipse.cdt.core.settings" name="AM437x_debug">
+ <macros>
+ <stringMacro name="IA_SDK_HOME" type="VALUE_TEXT" value="C:\ti\PRU-ICSS-Profinet_Slave_01.00.01.00"/>
+ <stringMacro name="PDK_INSTALL_PATH" type="VALUE_TEXT" value="C:\ti\pdk_am437x_1_0_6\packages"/>
+ </macros>
+ <externalSettings/>
+ <extensions>
+ <extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.rtsc.xdctools.parsers.ErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" errorParsers="org.eclipse.rtsc.xdctools.parsers.ErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="com.ti.ccstudio.buildDefinitions.TMS470.Default.841046752" name="AM437x_debug" parent="com.ti.ccstudio.buildDefinitions.TMS470.Default" postbuildStep="${PDK_INSTALL_PATH}/pdkAppImageCreate.bat ${PDK_INSTALL_PATH} ${CG_TOOL_ROOT} ${PROJECT_LOC}/${ConfigName} ${ProjName} AM437x arm">
+ <folderInfo id="com.ti.ccstudio.buildDefinitions.TMS470.Default.841046752." name="/" resourcePath="">
+ <toolChain id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.DebugToolchain.1289061598" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.linkerDebug.2021108620">
+ <option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1507333211" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" useByScannerDiscovery="false" valueType="stringList">
+ <listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=Cortex A.AM4379"/>
+ <listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+ <listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
+ <listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
+ <listOptionValue builtIn="false" value="XDC_VERSION=3.32.1.22_core"/>
+ <listOptionValue builtIn="false" value="INACTIVE_REPOS="/>
+ <listOptionValue builtIn="false" value="EXPANDED_REPOS="/>
+ <listOptionValue builtIn="false" value="CCS_MBS_VERSION=6.1.3"/>
+ <listOptionValue builtIn="false" value="PRODUCTS=com.ti.sdo.edma3:2.12.3;com.ti.rtsc.NDK:2.25.1.11;com.ti.rtsc.SYSBIOS:6.46.4.53;com.ti.uia:2.0.6.52;com.ti.pdk.am437x:1.0.6;"/>
+ <listOptionValue builtIn="false" value="PRODUCT_MACRO_IMPORTS={"com.ti.rtsc.SYSBIOS":["${BIOS_INCLUDE_PATH}","${BIOS_LIBRARY_PATH}","${BIOS_LIBRARIES}","${BIOS_SYMBOLS}"],"com.ti.pdk.am437x":["${TI_PDK_INCLUDE_PATH}","${TI_PDK_LIBRARY_PATH}","${TI_PDK_LIBRARIES}","${TI_PDK_SYMBOLS}"],"com.ti.rtsc.NDK":["${NDK_INCLUDE_PATH}","${NDK_LIBRARY_PATH}","${NDK_LIBRARIES}","${NDK_SYMBOLS}"],"com.ti.sdo.edma3":["${EDMA3_LLD_INCLUDE_PATH}","${EDMA3_LLD_LIBRARY_PATH}","${EDMA3_LLD_LIBRARIES}","${EDMA3_LLD_SYMBOLS}"],"com.ti.uia":["${COM_TI_UIA_INCLUDE_PATH}","${COM_TI_UIA_LIBRARY_PATH}","${COM_TI_UIA_LIBRARIES}","${COM_TI_UIA_SYMBOLS}"]}"/>
+ <listOptionValue builtIn="false" value="RTSC_MBS_VERSION=7.0.0"/>
+ <listOptionValue builtIn="false" value="OUTPUT_TYPE=rtscApplication:executable"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.192776143" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" useByScannerDiscovery="false" value="GNU_4.9.3:Linaro" valueType="string"/>
+ <targetPlatform id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.targetPlatformDebug.1528955991" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.targetPlatformDebug"/>
+ <builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.builderDebug.1777969997" keepEnvironmentInBuildfile="false" name="GNU Make" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.builderDebug"/>
+ <tool id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.compilerDebug.847045106" name="GNU Compiler" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.compilerDebug">
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DEFINE.438769607" name="Define symbols (-D)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DEFINE" useByScannerDiscovery="false" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="${COM_TI_UIA_SYMBOLS}"/>
+ <listOptionValue builtIn="false" value="${EDMA3_LLD_SYMBOLS}"/>
+ <listOptionValue builtIn="false" value="${NDK_SYMBOLS}"/>
+ <listOptionValue builtIn="false" value="${TI_PDK_SYMBOLS}"/>
+ <listOptionValue builtIn="false" value="${BIOS_SYMBOLS}"/>
+ <listOptionValue builtIn="false" value="am4379"/>
+ <listOptionValue builtIn="false" value="SOC_AM437x"/>
+ <listOptionValue builtIn="false" value="core0"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MCPU.666539156" name="Target CPU (-mcpu)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MCPU" useByScannerDiscovery="false" value="cortex-a9" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MTUNE.1633517674" name="Tune code for the given processor (-mtune)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MTUNE" useByScannerDiscovery="false" value="cortex-a9" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MARCH.41464525" name="Specify the name of the target architecture (-march)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MARCH" useByScannerDiscovery="false" value="armv7-a" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.CODE_STATE.1590584837" name="Code state" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.CODE_STATE" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.CODE_STATE.ARM" valueType="enumerated"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MFLOAT_ABI.252746421" name="Specify if floating point hardware should be used (-mfloat-abi)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MFLOAT_ABI" useByScannerDiscovery="false" value="hard" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.INCLUDE_PATH.602442339" name="Include paths (-I)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.INCLUDE_PATH" useByScannerDiscovery="false" valueType="includePath">
+ <listOptionValue builtIn="false" value="${COM_TI_UIA_INCLUDE_PATH}"/>
+ <listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/io_link/iq_stack_master_v1_1_2_2}"/>
+ <listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/io_link}"/>
+ <listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/io_link/iq_stack_master_v1_1_2_2/pl}"/>
+ <listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/io_link/iq_stack_master_v1_1_2_2/dl}"/>
+ <listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/io_link/iq_stack_master_v1_1_2_2/al}"/>
+ <listOptionValue builtIn="false" value="${EDMA3_LLD_INCLUDE_PATH}"/>
+ <listOptionValue builtIn="false" value="${NDK_INCLUDE_PATH}"/>
+ <listOptionValue builtIn="false" value="${TI_PDK_INCLUDE_PATH}"/>
+ <listOptionValue builtIn="false" value="${BIOS_INCLUDE_PATH}"/>
+ <listOptionValue builtIn="false" value="${PROJECT_ROOT}"/>
+ <listOptionValue builtIn="false" value="${PDK_INSTALL_PATH}"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}"/>
+ <listOptionValue builtIn="false" value="${NDK_INSTALL_DIR}"/>
+ <listOptionValue builtIn="false" value="${PDK_INSTALL_PATH}/ti/starterware/include"/>
+ <listOptionValue builtIn="false" value="${PDK_INSTALL_PATH}/ti/starterware/include/am43xx"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/examples/profinet_slave"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/protocols/profinet_slave/include/IRT"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/third_party/protocols/profinet_slave/include/IRT"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/third_party/protocols/profinet_slave/include"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/protocols/profinet_slave/firmware/v1.0"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/third_party/protocols/snmp/include"/>
+ <listOptionValue builtIn="false" value="${CG_TOOL_INCLUDE_PATH}"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.OPT_LEVEL.2108187702" name="Optimization Level" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.OPT_LEVEL" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.OPT_LEVEL.0" valueType="enumerated"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.FUNCTION_SECTIONS.787344344" name="Place each function into its own section (-ffunction-sections)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.FUNCTION_SECTIONS" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DATA_SECTIONS.1500733797" name="Place data items into their own section (-fdata-sections)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DATA_SECTIONS" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DEBUG.107530636" name="Generate debug information (-g)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DEBUG" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DWARF_VERSION.796842188" name="Generate debug information in DWARF version (-gdwarf-)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DWARF_VERSION" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DWARF_VERSION.2" valueType="enumerated"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.STRICT_DWARF.1915799112" name="Do not emit DWARF additions beyond selected version (-gstrict-dwarf)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.STRICT_DWARF" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.ASM_SPECIFIC_FLAGS.433944921" name="Assembly source specific flags" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.ASM_SPECIFIC_FLAGS" useByScannerDiscovery="false" valueType="stringList">
+ <listOptionValue builtIn="false" value="-x assembler"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.OTHER_FLAGS.904538731" name="Other flags" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.OTHER_FLAGS" useByScannerDiscovery="false" valueType="stringList">
+ <listOptionValue builtIn="false" value="-pedantic"/>
+ <listOptionValue builtIn="false" value="-std=c99"/>
+ </option>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__C_SRCS.1191046032" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__C_SRCS"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__CPP_SRCS.525766962" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__CPP_SRCS"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__ASM_SRCS.984761986" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__ASM_SRCS"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__ASM2_SRCS.187370773" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__ASM2_SRCS"/>
+ </tool>
+ <tool id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.linkerDebug.2021108620" name="GNU Linker" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.linkerDebug">
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.DEFSYM.780013619" name="Define a symbol (--defsym)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.DEFSYM" useByScannerDiscovery="false" valueType="stringList">
+ <listOptionValue builtIn="false" value="STACKSIZE=0x18000"/>
+ <listOptionValue builtIn="false" value="HEAPSIZE=0x400"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.OUTPUT_FILE.1652343884" name="Output file (-o)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.OUTPUT_FILE" useByScannerDiscovery="false" value="${ProjName}.out" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.MAP_FILE.338721169" name="Write a map file (-Map)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.MAP_FILE" useByScannerDiscovery="false" value="${ProjName}.map" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.NOSTARTFILES.1299062318" name="Do not use the standard system startup files when linking (-nostartfiles)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.NOSTARTFILES" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.NODEFAULTLIBS.449129388" name="Do not use the standard system libraries when linking (-nodefaultlibs)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.NODEFAULTLIBS" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.STATIC.2118356925" name="Do not link with the shared libraries (-static)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.STATIC" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.GC_SECTIONS.1506115649" name="Remove unused sections (--gc-sections)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.GC_SECTIONS" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.LIBRARY.567648978" name="Libraries (-l, --library)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.LIBRARY" useByScannerDiscovery="false" valueType="libs">
+ <listOptionValue builtIn="false" value="${COM_TI_UIA_LIBRARIES}"/>
+ <listOptionValue builtIn="false" value="${EDMA3_LLD_LIBRARIES}"/>
+ <listOptionValue builtIn="false" value="${NDK_LIBRARIES}"/>
+ <listOptionValue builtIn="false" value="${TI_PDK_LIBRARIES}"/>
+ <listOptionValue builtIn="false" value="${BIOS_LIBRARIES}"/>
+ <listOptionValue builtIn="false" value="rdimon"/>
+ <listOptionValue builtIn="false" value="gcc"/>
+ <listOptionValue builtIn="false" value="profinet_slave_stack_IRT_AM437x_arm"/>
+ <listOptionValue builtIn="false" value="snmp_core_stack_AM437x_arm"/>
+ <listOptionValue builtIn="false" value="c"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.SEARCH_PATH.760258227" name="Library search path (-L, --library-path)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.SEARCH_PATH" useByScannerDiscovery="false" valueType="libPaths">
+ <listOptionValue builtIn="false" value="${COM_TI_UIA_LIBRARY_PATH}"/>
+ <listOptionValue builtIn="false" value="${EDMA3_LLD_LIBRARY_PATH}"/>
+ <listOptionValue builtIn="false" value="${NDK_LIBRARY_PATH}"/>
+ <listOptionValue builtIn="false" value="${TI_PDK_LIBRARY_PATH}"/>
+ <listOptionValue builtIn="false" value="${BIOS_LIBRARY_PATH}"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/third_party/protocols/profinet_slave/stack_lib/am437x/a9/IRT"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/third_party/protocols/snmp/stack_lib/am437x/a9"/>
+ <listOptionValue builtIn="false" value="${BIOS_CG_ROOT}/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/lib/fpu"/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/profinet_slave_IRT_AM437x_arm/io_link/iq_stack_master_v1_1_2_2/al}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/profinet_slave_IRT_AM437x_arm/io_link/iq_stack_master_v1_1_2_2/dl}""/>
+ <listOptionValue builtIn="false" value=""${workspace_loc:/profinet_slave_IRT_AM437x_arm/io_link/iq_stack_master_v1_1_2_2/pl}""/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.OTHER_FLAGS.2115682743" name="Other flags" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.OTHER_FLAGS" useByScannerDiscovery="false" valueType="stringList">
+ <listOptionValue builtIn="false" value="-Wl,--start-group"/>
+ </option>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__CMD_SRCS.383450570" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__CMD_SRCS"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__CMD2_SRCS.472584641" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__CMD2_SRCS"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__GEN_CMDS.2000185622" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__GEN_CMDS"/>
+ </tool>
+ <tool id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.hex.1392414505" name="GNU Objcopy Utility" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.hex"/>
+ <tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.543505853" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH.2132680163" name="Package repositories (--xdcpath)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH" useByScannerDiscovery="false" valueType="stringList">
+ <listOptionValue builtIn="false" value="${BIOS_CG_ROOT}/packages"/>
+ <listOptionValue builtIn="false" value="${TI_PDK_INSTALL_DIR}/packages"/>
+ <listOptionValue builtIn="false" value="${NDK_INSTALL_DIR}/packages"/>
+ <listOptionValue builtIn="false" value="${EDMA3_LLD_INSTALL_DIR}/packages"/>
+ <listOptionValue builtIn="false" value="${COM_TI_UIA_INSTALL_DIR}/packages"/>
+ <listOptionValue builtIn="false" value="${TARGET_CONTENT_BASE}"/>
+ </option>
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET.1357304661" name="Target (-t)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET" useByScannerDiscovery="false" value="gnu.targets.arm.A9F" valueType="string"/>
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM.896541588" name="Platform (-p)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM" useByScannerDiscovery="false" value="ti.platforms.evmAM437X" valueType="string"/>
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM_RAW.1219061703" name="Platform (-p)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM_RAW" useByScannerDiscovery="false" value="ti.platforms.evmAM437X" valueType="string"/>
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE.363932003" name="Build-profile (-r)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE" useByScannerDiscovery="false" value="release" valueType="string"/>
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR.1506756574" name="Compiler tools directory (-c)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR" useByScannerDiscovery="false" value="${CG_TOOL_ROOT}" valueType="string"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ <fileInfo id="com.ti.ccstudio.buildDefinitions.TMS470.Default.841046752.752725571" name="ioLink_powerSwitchTask.h" rcbsApplicability="disable" resourcePath="io_link/ioLink_powerSwitchTask.h" toolsToInvoke=""/>
+ <fileInfo id="com.ti.ccstudio.buildDefinitions.TMS470.Default.841046752.508457791" name="ioLink_LEDTask.h" rcbsApplicability="disable" resourcePath="io_link/ioLink_LEDTask.h" toolsToInvoke=""/>
+ <sourceEntries>
+ <entry excluding="io_link/Files for alternative PRU Software" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+ </sourceEntries>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ <cconfiguration id="com.ti.ccstudio.buildDefinitions.TMS470.Default.620537363">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.TMS470.Default.620537363" moduleId="org.eclipse.cdt.core.settings" name="AM437x_release">
+ <macros>
+ <stringMacro name="IA_SDK_HOME" type="VALUE_TEXT" value="C:\ti\PRU-ICSS-Profinet_Slave_01.00.01.00"/>
+ <stringMacro name="PDK_INSTALL_PATH" type="VALUE_TEXT" value="C:\ti\pdk_am437x_1_0_6\packages"/>
+ </macros>
+ <externalSettings/>
+ <extensions>
+ <extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.rtsc.xdctools.parsers.ErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" errorParsers="org.eclipse.rtsc.xdctools.parsers.ErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser" id="com.ti.ccstudio.buildDefinitions.TMS470.Default.620537363" name="AM437x_release" parent="com.ti.ccstudio.buildDefinitions.TMS470.Default" postbuildStep="${PDK_INSTALL_PATH}/pdkAppImageCreate.bat ${PDK_INSTALL_PATH} ${CG_TOOL_ROOT} ${PROJECT_LOC}/${ConfigName} ${ProjName} AM437x arm">
+ <folderInfo id="com.ti.ccstudio.buildDefinitions.TMS470.Default.620537363." name="/" resourcePath="">
+ <toolChain id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.DebugToolchain.2063233006" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.linkerDebug.1633344561">
+ <option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.1898062202" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
+ <listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=Cortex A.AM4379"/>
+ <listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
+ <listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
+ <listOptionValue builtIn="false" value="CCS_MBS_VERSION=6.1.3"/>
+ <listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
+ <listOptionValue builtIn="false" value="RTSC_MBS_VERSION=7.0.0"/>
+ <listOptionValue builtIn="false" value="XDC_VERSION=3.32.1.22_core"/>
+ <listOptionValue builtIn="false" value="OUTPUT_TYPE=rtscApplication:executable"/>
+ <listOptionValue builtIn="false" value="PRODUCTS=com.ti.rtsc.SYSBIOS:6.46.4.53;com.ti.pdk.am437x:1.0.6;com.ti.rtsc.NDK:2.25.1.11;com.ti.sdo.edma3:2.12.3;"/>
+ <listOptionValue builtIn="false" value="PRODUCT_MACRO_IMPORTS={"com.ti.rtsc.SYSBIOS":["${BIOS_INCLUDE_PATH}","${BIOS_LIBRARY_PATH}","${BIOS_LIBRARIES}","${BIOS_SYMBOLS}"],"com.ti.pdk.am437x":["${TI_PDK_INCLUDE_PATH}","${TI_PDK_LIBRARY_PATH}","${TI_PDK_LIBRARIES}","${TI_PDK_SYMBOLS}"],"com.ti.rtsc.NDK":["${NDK_INCLUDE_PATH}","${NDK_LIBRARY_PATH}","${NDK_LIBRARIES}","${NDK_SYMBOLS}"],"com.ti.sdo.edma3":["${EDMA3_LLD_INCLUDE_PATH}","${EDMA3_LLD_LIBRARY_PATH}","${EDMA3_LLD_LIBRARIES}","${EDMA3_LLD_SYMBOLS}"]}"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION.169115203" name="Compiler version" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_CODEGEN_VERSION" value="GNU_4.9.3:Linaro" valueType="string"/>
+ <targetPlatform id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.targetPlatformDebug.1888047519" name="Platform" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.targetPlatformDebug"/>
+ <builder buildPath="${BuildDirectory}" id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.builderDebug.580083181" keepEnvironmentInBuildfile="false" name="GNU Make" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.builderDebug"/>
+ <tool id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.compilerDebug.326105930" name="GNU Compiler" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.compilerDebug">
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DEFINE.1286627762" name="Define symbols (-D)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DEFINE" valueType="definedSymbols">
+ <listOptionValue builtIn="false" value="${EDMA3_LLD_SYMBOLS}"/>
+ <listOptionValue builtIn="false" value="${NDK_SYMBOLS}"/>
+ <listOptionValue builtIn="false" value="${TI_PDK_SYMBOLS}"/>
+ <listOptionValue builtIn="false" value="${BIOS_SYMBOLS}"/>
+ <listOptionValue builtIn="false" value="am4379"/>
+ <listOptionValue builtIn="false" value="SOC_AM437x"/>
+ <listOptionValue builtIn="false" value="core0"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MCPU.1251040985" name="Target CPU (-mcpu)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MCPU" useByScannerDiscovery="false" value="cortex-a9" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MTUNE.1059816363" name="Tune code for the given processor (-mtune)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MTUNE" useByScannerDiscovery="false" value="cortex-a9" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MARCH.514929480" name="Specify the name of the target architecture (-march)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MARCH" useByScannerDiscovery="false" value="armv7-a" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.CODE_STATE.1096499001" name="Code state" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.CODE_STATE" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.CODE_STATE.ARM" valueType="enumerated"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.INCLUDE_PATH.2044294947" name="Include paths (-I)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.INCLUDE_PATH" valueType="includePath">
+ <listOptionValue builtIn="false" value="${EDMA3_LLD_INCLUDE_PATH}"/>
+ <listOptionValue builtIn="false" value="${NDK_INCLUDE_PATH}"/>
+ <listOptionValue builtIn="false" value="${TI_PDK_INCLUDE_PATH}"/>
+ <listOptionValue builtIn="false" value="${BIOS_INCLUDE_PATH}"/>
+ <listOptionValue builtIn="false" value="${PROJECT_ROOT}"/>
+ <listOptionValue builtIn="false" value="${PDK_INSTALL_PATH}"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}"/>
+ <listOptionValue builtIn="false" value="${NDK_INSTALL_DIR}"/>
+ <listOptionValue builtIn="false" value="${PDK_INSTALL_PATH}/ti/starterware/include"/>
+ <listOptionValue builtIn="false" value="${PDK_INSTALL_PATH}/ti/starterware/include/am43xx"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/examples/profinet_slave"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/protocols/profinet_slave/include/IRT"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/third_party/protocols/profinet_slave/include/IRT"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/third_party/protocols/profinet_slave/include"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/protocols/profinet_slave/firmware/v1.0"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/third_party/protocols/snmp/include"/>
+ <listOptionValue builtIn="false" value="${CG_TOOL_INCLUDE_PATH}"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.ASM_SPECIFIC_FLAGS.1136923363" name="Assembly source specific flags" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.ASM_SPECIFIC_FLAGS" useByScannerDiscovery="false" valueType="stringList">
+ <listOptionValue builtIn="false" value="-x assembler"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.OTHER_FLAGS.761553050" name="Other flags" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.OTHER_FLAGS" useByScannerDiscovery="false" valueType="stringList">
+ <listOptionValue builtIn="false" value="-pedantic"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MFLOAT_ABI.439972559" name="Specify if floating point hardware should be used (-mfloat-abi)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.MFLOAT_ABI" useByScannerDiscovery="false" value="hard" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.OPT_LEVEL.488864692" name="Optimization Level" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.OPT_LEVEL" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.OPT_LEVEL.2" valueType="enumerated"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.FUNCTION_SECTIONS.1314283972" name="Place each function into its own section (-ffunction-sections)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.FUNCTION_SECTIONS" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DATA_SECTIONS.548929398" name="Place data items into their own section (-fdata-sections)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compilerID.DATA_SECTIONS" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__C_SRCS.215869365" name="C Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__C_SRCS"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__CPP_SRCS.278558910" name="C++ Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__CPP_SRCS"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__ASM_SRCS.2060319585" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__ASM_SRCS"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__ASM2_SRCS.714118368" name="Assembly Sources" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.compiler.inputType__ASM2_SRCS"/>
+ </tool>
+ <tool id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.linkerDebug.1633344561" name="GNU Linker" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exe.linkerDebug">
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.DEFSYM.1538588504" name="Define a symbol (--defsym)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.DEFSYM" useByScannerDiscovery="false" valueType="stringList">
+ <listOptionValue builtIn="false" value="STACKSIZE=0x18000"/>
+ <listOptionValue builtIn="false" value="HEAPSIZE=0x400"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.OUTPUT_FILE.82084885" name="Output file (-o)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.OUTPUT_FILE" useByScannerDiscovery="false" value="${ProjName}.out" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.MAP_FILE.1148659666" name="Write a map file (-Map)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.MAP_FILE" useByScannerDiscovery="false" value="${ProjName}.map" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.LIBRARY.603544636" name="Libraries (-l, --library)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.LIBRARY" useByScannerDiscovery="false" valueType="libs">
+ <listOptionValue builtIn="false" value="${EDMA3_LLD_LIBRARIES}"/>
+ <listOptionValue builtIn="false" value="${NDK_LIBRARIES}"/>
+ <listOptionValue builtIn="false" value="${TI_PDK_LIBRARIES}"/>
+ <listOptionValue builtIn="false" value="${BIOS_LIBRARIES}"/>
+ <listOptionValue builtIn="false" value="rdimon"/>
+ <listOptionValue builtIn="false" value="gcc"/>
+ <listOptionValue builtIn="false" value="profinet_slave_stack_IRT_AM437x_arm"/>
+ <listOptionValue builtIn="false" value="snmp_core_stack_AM437x_arm"/>
+ <listOptionValue builtIn="false" value="c"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.SEARCH_PATH.22794948" name="Library search path (-L, --library-path)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.SEARCH_PATH" valueType="libPaths">
+ <listOptionValue builtIn="false" value="${EDMA3_LLD_LIBRARY_PATH}"/>
+ <listOptionValue builtIn="false" value="${NDK_LIBRARY_PATH}"/>
+ <listOptionValue builtIn="false" value="${TI_PDK_LIBRARY_PATH}"/>
+ <listOptionValue builtIn="false" value="${BIOS_LIBRARY_PATH}"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/third_party/protocols/profinet_slave/stack_lib/am437x/a9/IRT"/>
+ <listOptionValue builtIn="false" value="${IA_SDK_HOME}/third_party/protocols/snmp/stack_lib/am437x/a9"/>
+ <listOptionValue builtIn="false" value="${BIOS_CG_ROOT}/packages/gnu/targets/arm/libs/install-native/arm-none-eabi/lib/fpu"/>
+ </option>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.NOSTARTFILES.1849850355" name="Do not use the standard system startup files when linking (-nostartfiles)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.NOSTARTFILES" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.NODEFAULTLIBS.289260633" name="Do not use the standard system libraries when linking (-nodefaultlibs)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.NODEFAULTLIBS" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.STATIC.61537465" name="Do not link with the shared libraries (-static)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.STATIC" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.GC_SECTIONS.718905986" name="Remove unused sections (--gc-sections)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.GC_SECTIONS" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+ <option id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.OTHER_FLAGS.1653402324" name="Other flags" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.linkerID.OTHER_FLAGS" useByScannerDiscovery="false" valueType="stringList">
+ <listOptionValue builtIn="false" value="-Wl,--start-group"/>
+ </option>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__CMD_SRCS.1405747790" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__CMD_SRCS"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__CMD2_SRCS.1051086346" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__CMD2_SRCS"/>
+ <inputType id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__GEN_CMDS.311746714" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.exeLinker.inputType__GEN_CMDS"/>
+ </tool>
+ <tool id="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.hex.882626006" name="GNU Objcopy Utility" superClass="com.ti.ccstudio.buildDefinitions.TMS470_GNU_4.0.hex"/>
+ <tool id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.998984482" name="XDCtools" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool">
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR.753227534" name="Compiler tools directory (-c)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.CODEGEN_TOOL_DIR" value="${CG_TOOL_ROOT}" valueType="string"/>
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET.863535938" name="Target (-t)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.TARGET" value="gnu.targets.arm.A9F" valueType="string"/>
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM.2006289205" name="Platform (-p)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM" value="ti.platforms.evmAM437X" valueType="string"/>
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM_RAW.784047650" name="Platform (-p)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.PLATFORM_RAW" value="ti.platforms.evmAM437X" valueType="string"/>
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE.1482135461" name="Build-profile (-r)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.BUILD_PROFILE" value="release" valueType="string"/>
+ <option id="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH.1790252595" name="Package repositories (--xdcpath)" superClass="com.ti.rtsc.buildDefinitions.XDC_3.16.tool.XDC_PATH" valueType="stringList">
+ <listOptionValue builtIn="false" value="${BIOS_CG_ROOT}/packages"/>
+ <listOptionValue builtIn="false" value="${TI_PDK_INSTALL_DIR}/packages"/>
+ <listOptionValue builtIn="false" value="${NDK_INSTALL_DIR}/packages"/>
+ <listOptionValue builtIn="false" value="${EDMA3_LLD_INSTALL_DIR}/packages"/>
+ <listOptionValue builtIn="false" value="${TARGET_CONTENT_BASE}"/>
+ </option>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="profinet_slave_IRT_AM437x_arm.com.ti.ccstudio.buildDefinitions.TMS470.ProjectType.351476288" name="TMS470" projectType="com.ti.ccstudio.buildDefinitions.TMS470.ProjectType"/>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+ <project-mappings>
+ <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/>
+ <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/>
+ <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>
+ <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
+ <content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>
+ </project-mappings>
+ </storageModule>
+ <storageModule moduleId="refreshScope" versionNumber="2">
+ <configuration configurationName="AM437x_debug">
+ <resource resourceType="PROJECT" workspacePath="/profinet_slave_IRT_AM437x_arm"/>
+ </configuration>
+ <configuration configurationName="AM437x_release">
+ <resource resourceType="PROJECT" workspacePath="/profinet_slave_IRT_AM437x_arm"/>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration"/>
+</cproject>
diff --git a/test/iq2_stack_test/.project b/test/iq2_stack_test/.project
--- /dev/null
@@ -0,0 +1,270 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>profinet_slave_IRT_AM437x_arm</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature</nature>
+ <nature>com.ti.ccstudio.core.ccsNature</nature>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+ <linkedResources>
+ <link>
+ <name>am437x_app_arm.cfg</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/profinet_slave/am437x_app_arm.cfg</locationURI>
+ </link>
+ <link>
+ <name>board_am437x</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>board_common</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>icss_emacFwConfig.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/protocols/profinet_slave/firmware/icss_emacFwConfig.c</locationURI>
+ </link>
+ <link>
+ <name>osal</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>pn_soc.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/profinet_slave/AM437x/pn_soc.c</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_driver</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_snmp</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>snmp_core_driver</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>soc_am437x</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>source_pn</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>source_snmp</name>
+ <type>2</type>
+ <locationURI>virtual:/virtual</locationURI>
+ </link>
+ <link>
+ <name>board_am437x/board_gpioLed.c</name>
+ <type>1</type>
+ <location>C:/ti/PRU-ICSS-Profinet_Slave_01.00.01.00/examples/board/idkAM437x/board_gpioLed.c</location>
+ </link>
+ <link>
+ <name>board_am437x/board_i2cLed.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/board/idkAM437x/board_i2cLed.c</locationURI>
+ </link>
+ <link>
+ <name>board_am437x/board_phy.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/board/idkAM437x/board_phy.c</locationURI>
+ </link>
+ <link>
+ <name>board_am437x/board_spi.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/board/idkAM437x/board_spi.c</locationURI>
+ </link>
+ <link>
+ <name>board_common/board_misc.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/board/common/board_misc.c</locationURI>
+ </link>
+ <link>
+ <name>board_common/board_tlk105.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/board/common/board_tlk105.c</locationURI>
+ </link>
+ <link>
+ <name>board_common/board_tlkphy.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/board/common/board_tlkphy.c</locationURI>
+ </link>
+ <link>
+ <name>board_common/delay_us.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/board/common/delay_us.c</locationURI>
+ </link>
+ <link>
+ <name>board_common/icss_emac_osal.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/board/common/icss_emac_osal.c</locationURI>
+ </link>
+ <link>
+ <name>board_common/mdio_drv.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/board/common/mdio_drv.c</locationURI>
+ </link>
+ <link>
+ <name>board_common/osdrv_ndkdeviceconfig.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/board/common/osdrv_ndkdeviceconfig.c</locationURI>
+ </link>
+ <link>
+ <name>osal/ClockP_tirtos.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/osal/ClockP_tirtos.c</locationURI>
+ </link>
+ <link>
+ <name>osal/MailboxP_tirtos.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/osal/MailboxP_tirtos.c</locationURI>
+ </link>
+ <link>
+ <name>osal/SwiP_tirtos.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/osal/SwiP_tirtos.c</locationURI>
+ </link>
+ <link>
+ <name>osal/TaskP_tirtos.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/osal/TaskP_tirtos.c</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_driver/iPNDrv.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/protocols/profinet_slave/drivers/iPNDrv.c</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_driver/iPNLegacy.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/protocols/profinet_slave/drivers/iPNLegacy.c</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_driver/iPnOs.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/protocols/profinet_slave/drivers/iPnOs.c</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_driver/iPtcpDrv.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/protocols/profinet_slave/drivers/iPtcpDrv.c</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_driver/iRtcDrv.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/protocols/profinet_slave/drivers/iRtcDrv.c</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_driver/iRtcDrv2.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/protocols/profinet_slave/drivers/iRtcDrv2.c</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_snmp/mib_impl.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/profinet_slave/snmp/mib_impl.c</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_snmp/mibvars.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/profinet_slave/snmp/mibvars.c</locationURI>
+ </link>
+ <link>
+ <name>profinet_device_snmp/snmp_lldp_interface.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/examples/profinet_slave/snmp/snmp_lldp_interface.c</locationURI>
+ </link>
+ <link>
+ <name>snmp_core_driver/snmp_ndk_interface.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/protocols/snmp/drivers/snmp_ndk_interface.c</locationURI>
+ </link>
+ <link>
+ <name>soc_am437x/GPIO_soc.c</name>
+ <type>1</type>
+ <locationURI>PDK_INSTALL_PATH/ti/drv/gpio/soc/am437x/GPIO_soc.c</locationURI>
+ </link>
+ <link>
+ <name>soc_am437x/I2C_soc.c</name>
+ <type>1</type>
+ <locationURI>PDK_INSTALL_PATH/ti/drv/i2c/soc/am437x/I2C_soc.c</locationURI>
+ </link>
+ <link>
+ <name>soc_am437x/UART_soc.c</name>
+ <type>1</type>
+ <locationURI>PDK_INSTALL_PATH/ti/drv/uart/soc/am437x/UART_soc.c</locationURI>
+ </link>
+ <link>
+ <name>soc_am437x/pruicss_soc.c</name>
+ <type>1</type>
+ <locationURI>PDK_INSTALL_PATH/ti/drv/pruss/soc/am437x/pruicss_soc.c</locationURI>
+ </link>
+ <link>
+ <name>source_pn/duauser.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/third_party/protocols/profinet_slave/source/duauser.c</locationURI>
+ </link>
+ <link>
+ <name>source_pn/os_sckt.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/third_party/protocols/profinet_slave/source/os_sckt.c</locationURI>
+ </link>
+ <link>
+ <name>source_snmp/inport.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/third_party/protocols/snmp/source/inport.c</locationURI>
+ </link>
+ <link>
+ <name>source_snmp/osporttk.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/third_party/protocols/snmp/source/osporttk.c</locationURI>
+ </link>
+ <link>
+ <name>source_snmp/sockport.c</name>
+ <type>1</type>
+ <locationURI>IA_SDK_HOME/third_party/protocols/snmp/source/sockport.c</locationURI>
+ </link>
+ </linkedResources>
+ <variableList>
+ <variable>
+ <name>IA_SDK_HOME</name>
+ <value>file:/C:/ti/PRU-ICSS-Profinet_Slave_01.00.01.00</value>
+ </variable>
+ <variable>
+ <name>PDK_INSTALL_PATH</name>
+ <value>file:/C:/ti/pdk_am437x_1_0_6/packages</value>
+ </variable>
+ </variableList>
+</projectDescription>
diff --git a/test/iq2_stack_test/.xdchelp b/test/iq2_stack_test/.xdchelp
diff --git a/test/iq2_stack_test/README.txt b/test/iq2_stack_test/README.txt
--- /dev/null
@@ -0,0 +1 @@
+The IQ2 master stack is not free. We have to get permission from IQ2 if we want to use it for commercial purposes.
\ No newline at end of file
diff --git a/test/iq2_stack_test/am437x/armv7/bios/iolink_arm_idkam437x.cfg b/test/iq2_stack_test/am437x/armv7/bios/iolink_arm_idkam437x.cfg
--- /dev/null
@@ -0,0 +1,336 @@
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var Main = xdc.useModule('xdc.runtime.Main');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Swi = xdc.useModule('ti.sysbios.knl.Swi');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var ti_sysbios_hal_Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var Mailbox = xdc.useModule('ti.sysbios.knl.Mailbox');
+var Timer = xdc.useModule('ti.sysbios.hal.Timer');
+var SysStd = xdc.useModule('xdc.runtime.SysStd');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+System.SupportProxy = SysStd;
+
+var SemiHostsupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');
+
+/* Load the OSAL package */
+/*
+var osType = "tirtos"
+var Osal = xdc.useModule('ti.osal.Settings');
+Osal.osType = osType;
+
+var Uart = xdc.loadPackage('ti.drv.uart');
+var I2c = xdc.loadPackage('ti.drv.i2c');
+var Pruss = xdc.loadPackage('ti.drv.pruss');
+var Gpio = xdc.loadPackage('ti.drv.gpio');
+
+var deviceType = "am437x";
+var Csl = xdc.loadPackage('ti.csl');
+Csl.Settings.deviceType = deviceType;
+
+var socType = "am437x";
+
+var Board = xdc.loadPackage('ti.board');
+Board.Settings.boardName = "idkAM437x";
+
+var socType = "am437x";
+var Spi = xdc.loadPackage('ti.drv.spi');
+Spi.Settings.socType = socType;
+*/
+
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * The BIOS module will create the default heap for the system.
+ * Specify the size of this default heap.
+ */
+BIOS.heapSize = 1048576; /* 524288; */
+BIOS.libType = BIOS.LibType_Debug;
+BIOS.assertsEnabled = true;
+BIOS.logsEnabled = true;
+BIOS.cpuFreq.lo = 600000000;
+BIOS.rtsGateType = BIOS.GateHwi;
+
+SysMin.bufSize = 0x100;
+System.SupportProxy = SysMin;
+
+Defaults.common$.diags_INTERNAL = Diags.ALWAYS_ON;
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_ON;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+Clock.tickPeriod = 500;
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 32768;
+/*
+ * special memory management tells Sys/Bios link to ignore data sections
+ * we will handle instead in .cmd file
+ */
+
+Task.defaultStackSize = 2048;
+Task.idleTaskStackSize = 2048;
+
+/* BIOS instances for our example */
+var semaphore0Params = new Semaphore.Params();
+semaphore0Params.instance.name = "switchReady";
+semaphore0Params.mode = Semaphore.Mode_BINARY;
+Program.global.switchReady = Semaphore.create(null, semaphore0Params);
+Program.sectMap[".c_int00"] = new Program.SectionSpec();
+Program.sectMap[".c_int00"].loadAddress = 0x80000000;
+
+
+
+/***********************************************
+ * MMU Configuration *
+ ***********************************************/
+var Mmu = xdc.useModule('ti.sysbios.family.arm.a8.Mmu');
+Mmu.enableMMU = true;
+
+
+
+/* Force peripheral section to be NON cacheable strongly-ordered memory */
+/*var peripheralAttrs = {
+ type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
+ tex: 0,
+ bufferable : false, // bufferable
+ cacheable : false, // cacheable
+ shareable : false, // shareable
+ noexecute : true, // not executable
+ domain : 0,
+ imp : 1,
+ accPerm : 3,
+};
+
+/* Define the base address of the 1 Meg page the peripheral resides in. */
+/*var peripheralBaseAddr = 0x44e00400;
+
+/* Configure the corresponding MMU page descriptor accordingly */
+/*Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
+ peripheralBaseAddr,
+ peripheralAttrs);
+
+
+/* Define the base address of the 1 Meg page the peripheral resides in. */
+/*var peripheralBaseAddr = 0x481a6000;
+0x40000000
+/* Configure the corresponding MMU page descriptor accordingly */
+/*Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
+ peripheralBaseAddr,
+ peripheralAttrs);
+
+
+
+/* Define the base address of the 1 Meg page the peripheral resides in. */
+/*var peripheralBaseAddr = 0x4a300000;
+
+/* Configure the corresponding MMU page descriptor accordingly */
+/*Mmu.setFirstLevelDescMeta(peripheralBaseAddr,
+ peripheralBaseAddr,
+ peripheralAttrs);
+
+
+/* Force peripheral section to be NON cacheable strongly-ordered memory */
+var peripheralAttrs = {
+ type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
+ tex: 0,
+ bufferable : false, // bufferable
+ cacheable : false, // cacheable
+ shareable : false, // shareable
+ noexecute : true, // not executable
+};
+
+/* Define the base address of the 1 Meg page the peripheral resides in. */
+var peripheralBaseAddr = 0x44DF2800;
+
+/* Configure the corresponding MMU page descriptor accordingly */
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+
+/* Force peripheral section to be NON cacheable strongly-ordered memory */
+var peripheralAttrs = {
+ type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
+ tex: 1,
+ bufferable : false, // bufferable
+ cacheable : true, // cacheable
+ shareable : false, // shareable
+ noexecute : false, // not executable
+};
+
+/* MMU configuration for QSPI CS0 Maddr1space - Cacheable */
+var peripheralBaseAddr = 0x30000000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for QSPI CS0 Maddr1space - Cacheable */
+var peripheralBaseAddr = 0x30100000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for QSPI CS0 Maddr1space - Cacheable */
+var peripheralBaseAddr = 0x30200000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for QSPI CS0 Maddr1space - Cacheable */
+var peripheralBaseAddr = 0x30300000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+
+/* Force peripheral section to be NON cacheable strongly-ordered memory */
+var peripheralAttrs = {
+ type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
+ tex: 1,
+ bufferable : true, // bufferable
+ cacheable : false, // cacheable
+ shareable : false, // shareable
+ noexecute : false, // not executable
+};
+
+/* MMU configuration for PRCM - Non Cacheable | Bufferable : Device */
+var peripheralBaseAddr = 0x44D00000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for Clock Module, PRM, GPIO0, UART0, I2C0, Non Cacheable | Bufferable : Device */
+var peripheralBaseAddr = 0x44E00000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for QSPI MMR Maddr0space -Non Cacheable | Bufferable : Device */
+var peripheralBaseAddr = 0x47900000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for UART1,UART2,I2C1,McSPI0,McASP0 CFG,McASP1 CFG,DMTIMER,GPIO1 - Non Cacheable | Bufferable Device */
+var peripheralBaseAddr = 0x48000000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+
+var peripheralAttrs = {
+ type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
+ tex: 0,
+ bufferable : false, // bufferable
+ cacheable : false, // cacheable
+ shareable : false, // shareable
+ noexecute : false, // not executable
+};
+
+/* MMU configuration for I2C2,McSPI1,UART3,UART4,UART5, GPIO2,GPIO3,MMC1 - Non Cacheable | Non Bufferable : Strongly Ordered */
+var peripheralBaseAddr = 0x48100000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+
+var peripheralAttrs = {
+ type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
+ tex: 1,
+ bufferable : true, // bufferable
+ cacheable : false, // cacheable
+ shareable : false, // shareable
+ noexecute : false, // not executable
+};
+
+/* MMU configuration for GPIO2,GPIO3,MMC1 - Non Cacheable | Non Bufferable : Strongly Ordered */
+var peripheralBaseAddr = 0x481C0000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for */
+var peripheralBaseAddr = 0x48200000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for PWM - Non Cacheable | Bufferable : Device */
+var peripheralBaseAddr = 0x48300000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for EDMA3CC - Non Cacheable | Bufferable : Device */
+var peripheralBaseAddr = 0x49000000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for L4 FAST CFG- Non Cacheable | Bufferable : Device */
+var peripheralBaseAddr = 0x4A000000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+/* MMU configuration for CPSW -Non Cacheable | Bufferable : Device */
+var peripheralBaseAddr = 0x4A100000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+
+var peripheralAttrs = {
+ type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
+ tex: 1,
+ bufferable : true, // bufferable
+ cacheable : false, // cacheable
+ shareable : true, // shareable
+ noexecute : false, // not executable
+};
+
+/* MMU configuration for PRU-ICSS0/1 -Non Cacheable | Bufferable : Shared Device */
+var peripheralBaseAddr = 0x54400000;
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
+
+
+var peripheralAttrs = {
+ type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
+ tex: 1,
+ bufferable : true, // bufferable
+ cacheable : false, // cacheable
+ shareable : true, // shareable
+ noexecute : false, // not executable
+};
+
+/* MMU configuration for //PRUSS1 -Bufferable| Non Cacheable | Shareable */
+var peripheralBaseAddr = 0x40300000; // Should it be bufferable??
+Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);
diff --git a/test/iq2_stack_test/makefile b/test/iq2_stack_test/makefile
--- /dev/null
@@ -0,0 +1,68 @@
+# Makefile for IOLINK unit test app
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+
+
+ifeq ($(IS_BAREMETAL),yes)
+BUILD_OS_TYPE = baremetal
+CFLAGS_OS_DEFINES =
+LNKFLAGS_LOCAL_mpu1_0 += --entry Entry
+COMP_LIST_COMMON = osal_nonos
+ifeq ($(ARCH),c66x)
+ COMP_LIST_COMMON += csl_intc
+else
+ COMP_LIST_COMMON += csl_init
+endif
+EXTERNAL_INTERFACES =
+XDC_CFG_FILE_a9host =
+else
+BUILD_OS_TYPE = tirtos
+CFLAGS_OS_DEFINES = -DUSE_BIOS
+EXTERNAL_INTERFACES = bios xdc
+COMP_LIST_COMMON = osal_tirtos
+XDC_CFG_FILE_a9host = ./$(SOC)/armv7/bios/iolink_arm_idkam437x.cfg
+endif
+
+SRCDIR = . src $(IOLINK_STACK_INSTALL_PATH) $(IOLINK_STACK_INSTALL_PATH)/al $(IOLINK_STACK_INSTALL_PATH)/dl $(IOLINK_STACK_INSTALL_PATH)/pl
+INCDIR = . src $(IOLINK_STACK_INSTALL_PATH) $(IOLINK_STACK_INSTALL_PATH)/al $(IOLINK_STACK_INSTALL_PATH)/dl $(IOLINK_STACK_INSTALL_PATH)/pl
+INCDIR += $(PDK_INSTALL_PATH)/ti/starterware/include/am43xx/ $(PDK_INSTALL_PATH)/ti/starterware/include/hw/
+
+# Common source files across all platforms and cores
+SRCS_COMMON += main_iolink_test.c ioLink_LEDTask.c ioLink_powerSwitchTask.c ioLink_TLC59281.c iq_stack_api.c tsc_adc_ss.c board_gpioLed.c
+SRCS_COMMON += mst_appl.c mst_al.c mst_cm.c mst_ds.c mst_iol.c mst_sm.c mst_dl_eh.c mst_dl_meh.c mst_dl_mh.c mst_dl_oh.c mst_dl_sh.c mst_pl.c
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk $(EXTERNAL_INTERFACES)
+
+
+ifeq ($(BUILD_OS_TYPE), tirtos)
+IOLINK_OS_TYPE=
+else
+IOLINK_OS_TYPE=_Baremetal
+endif
+
+#Name of the directory created under packages/ti/binary/
+APP_NAME = IOLINK$(IOLINK_OS_TYPE)_IQ2Stack_TestApp
+# Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
+LOCAL_APP_NAME = IOLINK$(IOLINK_OS_TYPE)_IQ2Stack_$(BOARD)_$(CORE)TestApp
+
+COMP_LIST_COMMON += iolink pruss uart gpio spi
+
+# List all the components required by the application
+COMP_LIST_COMMON += csl board
+
+PACKAGE_SRCS_COMMON = .
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(CFLAGS_IOLINK_DMA) $(CFLAGS_OS_DEFINES)
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/test/iq2_stack_test/src/IOLINK_log.h b/test/iq2_stack_test/src/IOLINK_log.h
--- /dev/null
@@ -0,0 +1,76 @@
+/**
+ * \file IOLINK_log.h
+ *
+ * \brief This file contains the prototypes for the log print functions. By
+ default the prints will be directed to serial console using UART.
+ *
+ */
+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _IOLINK_LOG_H
+#define _IOLINK_LOG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <xdc/runtime/System.h>
+
+/* UART Header files */
+#include <ti/drv/uart/UART.h>
+#include <ti/drv/uart/UART_stdio.h>
+
+/**********************************************************************
+ ************************** Global Variables **************************
+ **********************************************************************/
+extern void UART_printf(const char *pcString, ...);
+
+/**********************************************************************
+ ************************** Macros ************************************
+ **********************************************************************/
+/* Enable the below macro to have prints on the IO Console */
+#define IO_CONSOLE
+
+#ifndef IO_CONSOLE
+#define IOLINK_log UART_printf
+#else
+#define IOLINK_log System_printf
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _IOLINK_LOG_H */
diff --git a/test/iq2_stack_test/src/board_gpioLed.c b/test/iq2_stack_test/src/board_gpioLed.c
--- /dev/null
@@ -0,0 +1,155 @@
+/**
+ * \file board_gpioLed.c
+ *
+ * \brief:
+ * GPIO LED configurations
+ *
+ *
+ */
+
+/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * ALL RIGHTS RESERVED
+ */
+
+#include <stdio.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/csl/soc.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+#include <ti/starterware/include/am43xx/chipdb_defs.h>
+#include <ti/drv/iolink/test/iq2_stack_test/src/board_gpioLed.h>
+
+
+extern int32_t PINMUXModuleConfig(chipdbModuleID_t moduleId, uint32_t instNum,
+ void *pParam1);
+
+/***********************************************************************/
+/* Macros */
+/***********************************************************************/
+
+/* GPIO Driver board specific pin configuration structure */
+GPIO_PinConfig gpioPinConfigs[] =
+{
+ /* Output pin : AM437x_IDK_RED0_LED */
+ GPIO_DEVICE_CONFIG(2u + 1u, 24u) |
+ GPIO_CFG_OUTPUT ,
+
+ /* Output pin :AM437x_IDK_GRN0_LED */
+ GPIO_DEVICE_CONFIG(2u + 1u, 25u) |
+ GPIO_CFG_OUTPUT,
+
+ /* Output pin : AM437x_IDK_YEL0_LED */
+ GPIO_DEVICE_CONFIG(2u + 1u, 22u) |
+ GPIO_CFG_OUTPUT,
+
+ /* Output pin : AM437x_IDK_RED1_LED */
+ GPIO_DEVICE_CONFIG(2u + 1u, 23u) |
+ GPIO_CFG_OUTPUT ,
+
+ /* Output pin : AM437x_IDK_GRN1_LED */
+ GPIO_DEVICE_CONFIG(4u + 1u, 13u) |
+ GPIO_CFG_OUTPUT,
+
+ /* Output pin : AM437x_IDK_YEL1_LED */
+ GPIO_DEVICE_CONFIG(4u + 1u, 16u) |
+ GPIO_CFG_OUTPUT,
+
+ /* Output pin : AM437x_IDK_YEL1_LED */
+ GPIO_DEVICE_CONFIG(3u + 1u, 1u) |
+ GPIO_CFG_OUTPUT,
+
+ /* Output pin : IO Link Enable Port 0 */
+ GPIO_DEVICE_CONFIG(1u + 1u, 9u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : IO Link Enable Port 1 */
+ GPIO_DEVICE_CONFIG(0u + 1u, 3u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : IO Link Enable Port 2 */
+ GPIO_DEVICE_CONFIG(1u + 1u, 14u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : IO Link Enable Port 3 */
+ GPIO_DEVICE_CONFIG(1u + 1u, 15u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : IO Link Enable Port 4 */
+ GPIO_DEVICE_CONFIG(1u + 1u, 12u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : IO Link Enable Port 5 */
+ GPIO_DEVICE_CONFIG(1u + 1u, 13u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : IO Link Enable Port 6 */
+ GPIO_DEVICE_CONFIG(5u + 1u, 1u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : IO Link Enable Port 7 */
+ GPIO_DEVICE_CONFIG(2u + 1u, 12u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : TPS4H160 L_SEL 15*/
+ GPIO_DEVICE_CONFIG(5u + 1u, 20u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : TPS4H160 L_SEH 16*/
+ GPIO_DEVICE_CONFIG(4u + 1u, 21u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : TPS4H160 H_SEL 17*/
+ GPIO_DEVICE_CONFIG(0u + 1u, 15u) | GPIO_CFG_OUTPUT,
+
+ /* Output pin : TPS4H160 H_SEH 18*/
+ GPIO_DEVICE_CONFIG(4u + 1u, 14u) | GPIO_CFG_OUTPUT,
+
+ /* Input pin : TPS4H160 L_Fault 19*/
+ GPIO_DEVICE_CONFIG(4u + 1u, 15u) | GPIO_CFG_INPUT,
+
+ /* Input pin : TPS4H160 H_Fault 20*/
+ GPIO_DEVICE_CONFIG(0u + 1u, 14u) | GPIO_CFG_INPUT,
+};
+
+/* GPIO Driver call back functions */
+GPIO_CallbackFxn gpioCallbackFunctions[] =
+{
+ NULL
+};
+
+/* GPIO Driver configuration structure */
+GPIO_v1_Config GPIO_v1_config =
+{
+ gpioPinConfigs,
+ gpioCallbackFunctions,
+ sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
+ sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
+ 0x2U,
+};
+
+void gpioLedPinmuxConfig()
+{
+ PINMUXModuleConfig(CHIPDB_MOD_ID_GPIO, 2U, NULL);
+}
+
+void Board_setTriColorLED(uint32_t gpioLeds, uint8_t value)
+{
+ if(gpioLeds & BOARD_TRICOLOR0_RED)
+ {
+ GPIO_write(0, value);
+ }
+
+ if(gpioLeds & BOARD_TRICOLOR0_GREEN)
+ {
+ GPIO_write(1, value);
+ }
+
+ if(gpioLeds & BOARD_TRICOLOR0_YELLOW)
+ {
+ GPIO_write(2, value);
+ }
+
+ if(gpioLeds & BOARD_TRICOLOR1_RED)
+ {
+ GPIO_write(3, value);
+ }
+
+ if(gpioLeds & BOARD_TRICOLOR1_GREEN)
+ {
+ GPIO_write(4, value);
+ }
+
+ if(gpioLeds & BOARD_TRICOLOR1_YELLOW)
+ {
+ GPIO_write(5, value);
+ }
+}
diff --git a/test/iq2_stack_test/src/board_gpioLed.h b/test/iq2_stack_test/src/board_gpioLed.h
--- /dev/null
@@ -0,0 +1,112 @@
+/**
+ * \file board_gpioLed.c
+ *
+ * \brief:
+ * GPIO LED configurations
+ *
+ *
+ */
+
+/*
+ * Copyright (c) 2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ **/
+#ifndef _BOARD_GPIOLED_H_
+#define _BOARD_GPIOLED_H_
+
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+/***********************************************************************/
+/* Macros */
+/***********************************************************************/
+/** @def BOARD_TRICOLOR0_RED
+ * Macro for configuring Tri color0 Red
+ */
+#define BOARD_TRICOLOR0_RED (1u << (0u))
+/** @def BOARD_TRICOLOR0_GREEN
+ * Macro for configuring Tri color0 green
+ */
+#define BOARD_TRICOLOR0_GREEN (1u << (1u))
+/** @def BOARD_TRICOLOR0_YELLOW
+ * Macro for configuring Tri color0 yellow
+ */
+#define BOARD_TRICOLOR0_YELLOW (1u << (2u))
+/** @def BOARD_TRICOLOR1_RED
+ * Macro for configuring Tri color1 red
+ */
+#define BOARD_TRICOLOR1_RED (1u << (3u))
+/** @def BOARD_TRICOLOR1_GREEN
+ * Macro for configuring Tri color1 green
+ */
+#define BOARD_TRICOLOR1_GREEN (1u << (4u))
+/** @def BOARD_TRICOLOR1_YELLOW
+ * Macro for configuring Tri color1 yellow
+ */
+#define BOARD_TRICOLOR1_YELLOW (1u << (5u))
+
+#ifdef TIESC_SPI_SLAVE_MODE
+#ifdef iceAMIC11x
+#define SPI_SLAVE_PDI_INT_PIN 7
+#define SPI_SLAVE_FIRMWARE_LOADED_PIN 8
+#else
+#define SPI_SLAVE_PDI_INT_PIN 19
+#endif
+#endif
+
+#ifdef TIESC_SPI_MASTER_MODE
+#define SPI_MASTER_PDI_INT_PIN 19
+#define SPI_MASTER_SYNC0_INT_PIN 20
+#define SPI_MASTER_SYNC1_INT_PIN 21
+#endif
+
+#ifdef SOC_K2G
+#define BOARD_LCD_BST_CONV_CTL_GPIO 12
+#define BOARD_LCD_RESET 13
+#endif
+
+#define GPIO_PIN_VAL_LOW (0U)
+#define GPIO_PIN_VAL_HIGH (1U)
+
+/**
+ * @brief GPIO Pinmux configuration
+ */
+void gpioLedPinmuxConfig();
+
+/**
+ * @brief API used for toggling Tri color LED
+ *
+ * @param gpioLeds LEDs to toggle
+ * @param value set or reset
+ */
+void Board_setTriColorLED(uint32_t gpioLeds, uint8_t value);
+
+#endif /* _BOARD_GPIOLED_H_*/
diff --git a/test/iq2_stack_test/src/ioLink_LEDTask.c b/test/iq2_stack_test/src/ioLink_LEDTask.c
--- /dev/null
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * file: ioLink_LEDTask.c
+ *
+ * brief: PRU IO-Link master LED driver
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <xdc/std.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/Error.h>
+#include <ti/sysbios/knl/Mailbox.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/BIOS.h>
+#include <xdc/cfg/global.h>
+
+#include <ti/drv/iolink/test/iq2_stack_test/src/ioLink_LEDTask.h>
+#include <ti/drv/iolink/test/iq2_stack_test/src/ioLink_TLC59281.h>
+
+/* ========================================================================== */
+/* Local Variables */
+/* ========================================================================== */
+
+#define PORTS 8
+#define LEDSPERPORT 2
+
+static enum ledenum leds[PORTS][LEDSPERPORT];
+static int led_timer[PORTS][LEDSPERPORT];
+
+struct led_mapping_struct{
+ int port;
+ int led;
+};
+
+struct LEDMSGstruct{
+ int port;
+ int led;
+ enum ledenum state;
+};
+
+/*
+ * defines how LEDs are mapped
+ * index is the LED number on GPIO or LED driver
+ * each entry defines the IO-Link port and LED number on this port
+ */
+ static const struct led_mapping_struct led_mapping[] =
+{
+ {3, 1}, /* 1st LED -> port 4 LED 1 */
+ {3, 0}, /* 2ns LED -> port 4 LED 0 */
+ {2, 0},
+ {2, 1},
+ {0, 0},
+ {0, 1},
+ {6, 1},
+ {6, 0},
+ {4, 0},
+ {4, 1},
+ {5, 1},
+ {5, 0},
+ {7, 1},
+ {7, 0},
+ {1, 1},
+ {1, 0},
+};
+
+#define SLOWBLINKTIME 500 /* 500 ms */
+#define FASTBLINKTIME 200 /* 200 ms */
+#define TICKRATE 100 /* 100 ms */
+
+struct led_cfg_struct{
+ void(*initLEDs)();
+ void(*deinitLEDs)();
+ void(*updateLEDs)(uint32_t);
+};
+
+/* define which functions have to be used to control the LEDs */
+static struct led_cfg_struct IOLink_leds =
+{
+ TLC59281_initLEDs,
+ TLC59281_deInitLEDs,
+ TLC59281_updateLEDs,
+};
+
+static Mailbox_Handle mBoxLEDs;
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+void IO_Link_LEDs(int port, int led, enum ledenum state){
+ struct LEDMSGstruct msg;
+ if(mBoxLEDs == 0) return;
+ msg.port = port;
+ msg.led = led;
+ msg.state = state;
+ Mailbox_post(mBoxLEDs, &msg, BIOS_WAIT_FOREVER);
+}
+
+void IOLink_LEDTask(UArg arg0){
+ uint32_t led_state=0;
+ int i;
+ struct LEDMSGstruct msg;
+ IOLink_leds.initLEDs();
+
+ Mailbox_Params mboxParams;
+ Error_Block eb;
+ Error_init(&eb);
+ Mailbox_Params_init(&mboxParams);
+ mBoxLEDs = Mailbox_create(sizeof(msg), 5, &mboxParams, &eb);
+ if (mBoxLEDs == NULL) {
+ System_printf("taskFxn(): %s\n", Error_getMsg(&eb) );
+ System_abort("Mailbox create failed");
+ }
+
+ while(1){
+
+ while(Mailbox_pend(mBoxLEDs, &msg, 1) == TRUE){
+ if(msg.port < PORTS && msg.led < LEDSPERPORT)
+ leds[msg.port][msg.led] = msg.state;
+ }
+
+ for(i=0; i<sizeof(led_mapping)/sizeof(led_mapping[0]); i++){
+ led_timer[led_mapping[i].port][led_mapping[i].led]++;
+
+ switch(leds[led_mapping[i].port][led_mapping[i].led]){
+ case led_off:
+ led_state &= ~(1<<i);
+ break;
+ case led_on:
+ led_state |= 1<<i;
+ break;
+ case led_blink_slow:
+ if(led_timer[led_mapping[i].port][led_mapping[i].led] > SLOWBLINKTIME/TICKRATE){
+ led_state ^= 1<<i;
+ led_timer[led_mapping[i].port][led_mapping[i].led] = 0;
+ }
+ break;
+ case led_blink_fast:
+ if(led_timer[led_mapping[i].port][led_mapping[i].led] > FASTBLINKTIME/TICKRATE){
+ led_state ^= 1<<i;
+ led_timer[led_mapping[i].port][led_mapping[i].led] = 0;
+ }
+ break;
+ }
+ }
+
+ IOLink_leds.updateLEDs(led_state);
+ Task_sleep(200); /* tick time is 500us ?! */
+ }
+}
diff --git a/test/iq2_stack_test/src/ioLink_LEDTask.h b/test/iq2_stack_test/src/ioLink_LEDTask.h
--- /dev/null
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * file: ioLink_LEDTask.h
+ *
+ * brief: PRU IO-Link master LED driver
+ */
+
+#ifndef IO_LINK_IOLINK_LEDTASK_H_
+#define IO_LINK_IOLINK_LEDTASK_H_
+
+/* ========================================================================== */
+/* Local Variables */
+/* ========================================================================== */
+
+enum ledenum {led_off, led_on, led_blink_slow, led_blink_fast};
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+void IO_Link_LEDs(int port, int led, enum ledenum state);
+extern void IOLink_LEDTask(UArg arg0);
+
+#endif /* IO_LINK_IOLINK_LEDTASK_H_ */
diff --git a/test/iq2_stack_test/src/ioLink_TLC59281.c b/test/iq2_stack_test/src/ioLink_TLC59281.c
--- /dev/null
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * file: ioLink_TLC59281.c
+ *
+ * brief: PRU IO-Link master TLC59281 driver
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdint.h>
+
+#include <ti/drv/spi/SPI.h>
+
+#include <ti/drv/spi/soc/SPI_soc.h>
+#include <ti/drv/spi/test/src/SPI_log.h>
+//#include <ti/drv/spi/test/src/SPI_board.h>
+#include <ti/board/board.h>
+#include <ti/starterware/include/hw/am437x.h>
+#include <ti/starterware/include/hw/hw_control_am43xx.h>
+
+/* ========================================================================== */
+/* Local Variables */
+/* ========================================================================== */
+
+static SPI_Handle hwHandle; /* SPI handle */
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+void TLC59281_initLEDs(void){
+ SPI_Params spiParams;
+ SPI_v1_HWAttrs *hwAttrs;
+ SPI_v1_ChnCfg *chnCfg;
+
+ SPI_Params_init(&spiParams);
+ spiParams.frameFormat = SPI_POL0_PHA0;
+ spiParams.dataSize = 16;
+ spiParams.bitRate = 1000000;
+ spiParams.transferTimeout = 10;
+ SPI_init();
+
+ hwHandle = (SPI_Handle)SPI_open(0, &spiParams);
+ hwAttrs = (SPI_v1_HWAttrs*)hwHandle->hwAttrs;
+ chnCfg = &(hwAttrs->chnCfg[0]);
+ chnCfg->dataLineCommMode = MCSPI_DATA_LINE_COMM_MODE_1; /* configure SPI to use D1 to send, instead of D0 */
+
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_SPI0_D1), 0x13070000); /* configure SPI0_D1 pin to SPI mode */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_SPI0_CS0), 0x13070000); /* configure SPI0_CS0 pin to SPI mode */
+}
+
+void TLC59281_deInitLEDs(void){
+ SPI_close(hwHandle);
+}
+
+void TLC59281_updateLEDs(uint32_t leds){
+ SPI_Transaction transaction; /* SPI transaction structure */
+ uint32_t txBuf, rxBuf, terminateXfer = 1;
+
+ txBuf = (leds&0xffff);
+
+ transaction.txBuf = (uint8_t *) &txBuf;
+ transaction.rxBuf = (uint8_t *) &rxBuf;
+ transaction.count = 1;
+ transaction.arg = (void *)&terminateXfer;
+
+ SPI_transfer(hwHandle, &transaction);
+}
+
+
diff --git a/test/iq2_stack_test/src/ioLink_TLC59281.h b/test/iq2_stack_test/src/ioLink_TLC59281.h
--- /dev/null
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * file: ioLink_TLC59281.h
+ *
+ * brief: PRU IO-Link master TLC59281 driver
+ */
+
+#ifndef IO_LINK_IOLINK_TLC59281_H_
+#define IO_LINK_IOLINK_TLC59281_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include "ioLink_LEDTask.h"
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+extern void TLC59281_initLEDs(void);
+extern void TLC59281_deInitLEDs(void);
+extern void TLC59281_updateLEDs(uint32_t leds);
+
+
+#endif /* IO_LINK_IOLINK_TLC59281_H_ */
diff --git a/test/iq2_stack_test/src/ioLink_powerSwitchTask.c b/test/iq2_stack_test/src/ioLink_powerSwitchTask.c
--- /dev/null
@@ -0,0 +1,361 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * file: ioLink_powerSwitchTask.c
+ *
+ * brief: PRU IO-Link master power switch driver
+ */
+
+//NOTE: This file is not final and should be used with caution.
+// There is a quick fix applied to this driver which deactivates its functionality and switches all outputs on.
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <xdc/std.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/Error.h>
+#include <ti/sysbios/knl/Mailbox.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/BIOS.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <xdc/cfg/global.h>
+
+#include <ti/board/board.h>
+#include <ti/starterware/include/hw/am437x.h>
+#include <ti/starterware/include/hw/hw_control_am43xx.h>
+#include <ti/starterware/include/hw/hw_tsc_adc_ss.h>
+#include <ti/starterware/include/tsc_adc_ss.h>
+
+#include <ti/csl/src/ip/gpio/V1/hw_gpio.h>
+#include <ti/csl/csl_adc.h>
+#include <ti/csl/cslr_synctimer.h>
+#include <ti/csl/csl_types.h>
+//#include <ti/csl/soc.h>
+#include <ti/csl/hw_types.h>
+
+#include <ti/drv/iolink/test/iq2_stack_test/src/ioLink_powerSwitchTask.h>
+
+/* ========================================================================== */
+/* Local Variables */
+/* ========================================================================== */
+
+static Mailbox_Handle mBoxPower;
+
+struct powerMSGstruct{
+ int port;
+ enum portStateenum state;
+};
+
+static int enable_mappig[] = {
+ /* see board_gpioLed.c for ports */
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14
+};
+
+/*
+ * 15 - L_SEL
+ * 16 - L_SEH
+ * 17 - H_SEL
+ * 18 - H_SEH
+ * 19 - L_Fault
+ * 20 - H_Fault
+ */
+
+static int port_state[8] =
+{
+ 0,0,0,0,0,0,0,0
+};
+
+enum adc_enum{ADC1, ADC5};
+
+struct current_sense_mapping{
+ enum adc_enum adc;
+ int pin1;
+ int pin2;
+ int fault_in;
+};
+
+static struct current_sense_mapping current_sense[] = {
+ {ADC5, 16, -1, 19},
+ {ADC5, 16, 15, 19},
+ {ADC5, 15, -1, 19},
+ {ADC5, -1, -1, 19},
+ {ADC1, 18, -1, 20},
+ {ADC1, 18, 17, 20},
+ {ADC1, 17, -1, 20},
+ {ADC1, -1, -1, 20},
+};
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+/**
+ * Power up or down a port
+ */
+void IO_Link_Power(int port, enum portStateenum state){
+ struct powerMSGstruct msg;
+ if(mBoxPower == 0) return;
+ msg.port = port;
+ msg.state = state;
+ Mailbox_post(mBoxPower, &msg, BIOS_WAIT_FOREVER);
+}
+
+/**
+ * Return power state of a port
+ */
+int IO_Link_getPower(int port){
+ return port_state[port];
+}
+
+/* Macro representing the module clock of TSCADC. */
+#define TSCADC_MODULE_CLOCK (24000000U)
+
+/* Macro representing the AFE clock of TSCADC. */
+#define TSCADC_AFE_CLOCK (3000000U)
+
+/* Macro representing the base address of TSCADC module. */
+#define TSCADC_BASE_ADDR (0x44E0D000U)
+
+/**
+ * internal use
+ * init and read two channels of the ADC
+ */
+static void adc_get(int *ch0, int *ch1, int channel0, int channel1){
+ tscAdcStepCfg_t adcStepCfg;
+ uint32_t fifoNum[2U];
+ uint32_t index;
+ int fifoCount;
+
+ /* Configure the ADC AFE clock. */
+ TSCADCClkDivConfig(TSCADC_BASE_ADDR, TSCADC_MODULE_CLOCK, TSCADC_AFE_CLOCK);
+
+ /* Enable the step ID tag. */
+ TSCADCStepIdTagEnable(TSCADC_BASE_ADDR, TRUE);
+
+ /* Disable the write protection for Step config registers. */
+ TSCADCStepConfigProtectionEnable(TSCADC_BASE_ADDR, FALSE);
+
+ adcStepCfg.adcNegativeInpRef = TSCADC_NEGATIVE_REF_VSSA;
+ adcStepCfg.adcPositiveInpRef = TSCADC_POSITIVE_REF_VDDA;
+ adcStepCfg.adcNegativeInpChan = TSCADC_INPUT_VREFN;
+ adcStepCfg.adcPositiveInpChan = channel0;
+ adcStepCfg.enableXppsw = FALSE;
+ adcStepCfg.enableXnpsw = FALSE;
+ adcStepCfg.enableYppsw = FALSE;
+ adcStepCfg.enableXnnsw = FALSE;
+ adcStepCfg.enableYpnsw = FALSE;
+ adcStepCfg.enableYnnsw = FALSE;
+ adcStepCfg.enableWpnsw = FALSE;
+
+ fifoNum[0U] = TSCADC_FIFO_SEL_0;
+ fifoNum[1U] = TSCADC_FIFO_SEL_1;
+
+ for (index = 0U; index < 2U; index++)
+ {
+ if (1U == index)
+ {
+ adcStepCfg.adcPositiveInpChan = channel1;
+ }
+
+ /* Configure the ADC steps. */
+ TSCADCStepConfig(TSCADC_BASE_ADDR, (index + 1U),
+ FALSE, &adcStepCfg);
+
+ /* Configure the ADC FIFO. */
+ TSCADCFIFOIRQThresholdLevelConfig(TSCADC_BASE_ADDR, (index + 1U),
+ fifoNum[index], 2U, TRUE);
+
+ /* Configure the Step mode. */
+ TSCADCStepMode(TSCADC_BASE_ADDR, (index + 1U),
+ TSCADC_STEP_MODE_SW_ENABLED_ONE_SHOT);
+
+ /* Enable the ADC steps. */
+ TSCADCConfigureStepEnable(TSCADC_BASE_ADDR, (index + 1U), TRUE);
+ }
+
+ TSCADCIntrClear(TSCADC_BASE_ADDR,
+ (TSCADC_INTR_MASK_HW_PEN_EVENT_ASYNC |
+ TSCADC_INTR_MASK_END_OF_SEQUENCE |
+ TSCADC_INTR_MASK_FIFO0_THRESHOLD |
+ TSCADC_INTR_MASK_FIFO0_OVERRUN |
+ TSCADC_INTR_MASK_FIFO0_UNDERFLOW |
+ TSCADC_INTR_MASK_FIFO1_THRESHOLD |
+ TSCADC_INTR_MASK_FIFO1_OVERRUN |
+ TSCADC_INTR_MASK_FIFO1_UNDERFLOW |
+ TSCADC_INTR_MASK_OUT_OF_RANGE |
+ TSCADC_INTR_MASK_PEN_UP_EVENT |
+ TSCADC_INTR_MASK_HW_PEN_EVENT_SYNC));
+
+ TSCADCEventInterruptEnable(TSCADC_BASE_ADDR, TSCADC_INTR_MASK_END_OF_SEQUENCE);
+
+ TSCADCEnable(TSCADC_BASE_ADDR, TRUE);
+
+ //wait for finished
+ while(!(TSCADCIntStatus(TSCADC_BASE_ADDR) & TSCADC_INTR_MASK_END_OF_SEQUENCE));
+ TSCADCIntrClear(TSCADC_BASE_ADDR, TSCADC_INTR_MASK_END_OF_SEQUENCE);
+
+ fifoCount = TSCADCGetFifoWordCount(TSCADC_BASE_ADDR, TSCADC_FIFO_SEL_0);
+ if(fifoCount){
+ *ch0 = TSCADCFIFOADCDataRead(TSCADC_BASE_ADDR, TSCADC_FIFO_SEL_0);
+ }
+
+ fifoCount = TSCADCGetFifoWordCount(TSCADC_BASE_ADDR, TSCADC_FIFO_SEL_1);
+ if(fifoCount){
+ *ch1 = TSCADCFIFOADCDataRead(TSCADC_BASE_ADDR, TSCADC_FIFO_SEL_1);
+ }
+
+ //UART_printf("fifo 0: 0x%x fifo 1: 0x%x\n", *ch0, *ch1);
+
+ TSCADCEnable(TSCADC_BASE_ADDR, FALSE);
+}
+
+/**
+ * internal use
+ * select one current sense port of the high side switch
+ */
+static void select_input(int port){
+ int i;
+
+ for(i=0; i<4; i++)
+ GPIO_write(15+i, 0); // clear all sel outputs
+
+ // select input
+ if(current_sense[port].pin1 != -1)
+ GPIO_write(current_sense[port].pin1, 1);
+ if(current_sense[port].pin2 != -1)
+ GPIO_write(current_sense[port].pin2, 1);
+
+ Task_sleep(10); // some time to settle
+}
+
+/**
+ * return current in mA at specified port
+ */
+float IO_Link_get_current(int port){
+ int ch0, ch1;
+ select_input(port);
+ adc_get(&ch0, &ch1, TSCADC_INPUT_CHANNEL1, TSCADC_INPUT_CHANNEL5);
+
+ switch(current_sense[port].adc){
+ case ADC5: //L_CS
+ return ch1*1150.0/4096.0;
+ case ADC1: //H_CS
+ return ch0*1150.0/4096.0;
+ }
+ return -1; //1.15A FS
+}
+
+/**
+ * return input current measured by INA253 in mA
+ */
+float IO_Link_get_input_current(void){
+ int ch0, ch1;
+ adc_get(&ch0, &ch1, TSCADC_INPUT_CHANNEL3, TSCADC_INPUT_CHANNEL3);
+ return ((ch0+ch1)/2)*9000.0/4096.0; //9A FS
+}
+
+/**
+ * return state of the fault output of high side switch
+ */
+int IO_Link_get_fault(int port){
+ select_input(port);
+ return GPIO_read(current_sense[port].fault_in);
+}
+
+void IOLink_powerSwitchTask(UArg arg0){
+ struct powerMSGstruct msg;
+ int i;
+ int current;
+ int fault;
+ int current_sense_channel=0;
+ GPIO_init();
+
+ Mailbox_Params mboxParams;
+ Error_Block eb;
+ Error_init(&eb);
+ Mailbox_Params_init(&mboxParams);
+ mBoxPower = Mailbox_create(sizeof(msg), 5, &mboxParams, &eb);
+ if (mBoxPower == NULL) {
+ System_printf("taskFxn(): %s\n", Error_getMsg(&eb) );
+ System_abort("Mailbox create failed");
+ }
+
+ /* enable signals */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_UART0_RTSN), 0x13000007); /* configure UART0_RTSN pin to as GPIO1_9 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_SPI0_D0), 0x13000007); /* configure SPI0_D0 pin to as GPIO0_3 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_GPMC_AD14), 0x13000007); /* configure GPMC_AD14 pin to as GPIO1_14 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_GPMC_AD15), 0x13000007); /* configure GPMC_AD15 pin to as GPIO1_15 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_GPMC_AD12), 0x13000007); /* configure GPMC_AD12 pin to as GPIO1_12 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_GPMC_AD13), 0x13000007); /* configure GPMC_AD13 pin to as GPIO1_13 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_UART3_RTSN), 0x13000007); /* configure UART3_RTSN pin to as GPIO5_1 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_LCD_DATA6), 0x13000007); /* configure DSS_DATA6 pin to as GPIO2_12 */
+
+ /* current sense select signals */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_CCDC0_DATA1), 0x13000007); /* configure CAM0_DATA1 pin to as GPIO5_20 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_CCDC1_DATA7), 0x13000007); /* configure CAM1_DAT7 pin to as GPIO4_21 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_UART1_TXD), 0x13000007); /* configure UART1_TXD pin to as GPIO0_15 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_CCDC1_DATA0), 0x13000007); /* configure CAM1_DAT0 pin to as GPIO4_14 */
+
+ /* fault signals */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_CCDC1_DATA1), 0x13070007); /* configure CAM1_DAT1 pin to as GPIO4_14 */
+ HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_CONF_UART1_RXD), 0x13070007); /* configure UART1_RXD pin to as GPIO0_14 */
+
+
+ for(i=0; i<sizeof(enable_mappig)/sizeof(enable_mappig[0]); i++)
+ GPIO_setConfig(enable_mappig[i], GPIO_CFG_OUTPUT|GPIO_CFG_OUT_LOW);
+
+ while(1){
+ if (Mailbox_pend(mBoxPower, &msg, 200) == TRUE) {
+ GPIO_write(enable_mappig[msg.port], msg.state);
+ port_state[msg.port] = msg.state;
+ }
+ current = IO_Link_get_current(current_sense_channel);
+ fault = IO_Link_get_fault(current_sense_channel);
+ /* detect fault condition and reset port */
+ if(fault == 0 && current > 1148){
+ GPIO_write(enable_mappig[current_sense_channel], 0);
+ port_state[current_sense_channel] = 0;
+ }
+ //current sense debug output (console)
+ //printf("Port %d, Current %d, Total %d\n", current_sense_channel, current, (int)IO_Link_get_input_current());
+ current_sense_channel++;
+ if(current_sense_channel>7) current_sense_channel = 0;
+ }
+}
+
diff --git a/test/iq2_stack_test/src/ioLink_powerSwitchTask.h b/test/iq2_stack_test/src/ioLink_powerSwitchTask.h
--- /dev/null
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * file: ioLink_powerSwitchTask.h
+ *
+ * brief: PRU IO-Link master power switch driver
+ */
+
+//NOTE: This file is not final and should be used with caution.
+// There is a quick fix applied to this driver which deactivates its functionality and switches all outputs on.
+
+#ifndef IO_LINK_IOLINK_POWERSWITCHTASK_H_
+#define IO_LINK_IOLINK_POWERSWITCHTASK_H_
+
+/* ========================================================================== */
+/* Local Variables */
+/* ========================================================================== */
+
+enum portStateenum{port_off=0, port_on=1};
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+extern float IO_Link_get_current(int port);
+extern int IO_Link_get_fault(int port);
+extern float IO_Link_get_input_current(void);
+extern void IO_Link_Power(int port, enum portStateenum state);
+extern int IO_Link_getPower(int port);
+extern void IOLink_powerSwitchTask(UArg arg0);
+
+#endif /* IO_LINK_IOLINK_POWERSWITCHTASK_H_ */
diff --git a/test/iq2_stack_test/src/iq_stack_api.c b/test/iq2_stack_test/src/iq_stack_api.c
--- /dev/null
@@ -0,0 +1,233 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file iq_stack_api.c
+ *
+ * @brief IO-Link IQ2 Master stack interface
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+#include <ti/drv/iolink/test/iq2_stack_test/src/iq_stack_api.h>
+#include <mst_pl.h>
+
+
+IOLINK_v0_Callbacks iolinkCallbacks =
+{
+ IO_Link_cycleTimerCallback,
+ IO_Link_swTimerCallback,
+ IO_Link_adjTimerCallback,
+ IO_Link_xferRspCallback,
+ IO_Link_xferErrRspCallback
+};
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+extern IOLINK_Handle iolinkHandles[];
+
+int8_t IO_Link_sendCommand(uint8_t instance, uint8_t port, uint8_t command, uint8_t arg)
+{
+ int8_t retVal = 0;
+ uint32_t data[3];
+
+ if ((iolinkHandles[instance] == NULL) || (port >= (uint8_t)IOLINK_MAX_NUM_CHN))
+ {
+ retVal = -1;
+ }
+
+ if ((command != IO_LINK_COMMAND_STARTPULSE) && ((command != IO_LINK_COMMAND_SETCOM)))
+ {
+ retVal = -1;
+ }
+
+ if (retVal == 0)
+ {
+ data[0] = (uint32_t)port;
+ data[1] = (uint32_t)command;
+ data[2] = (uint32_t)arg;
+ IOLINK_control(iolinkHandles[instance], IOLINK_CTRL_SEND_CMD, (void *)data);
+ }
+
+ return (retVal);
+}
+
+int8_t IO_Link_setBuffer(uint8_t instance, uint8_t port, uint8_t txBufLen, uint8_t rxBufLen, uint8_t *txBuf, uint8_t *rxBuf)
+{
+ int8_t retVal = 0;
+ uint32_t data[5];
+
+ if ((iolinkHandles[instance] == NULL) || (port >= (uint8_t)IOLINK_MAX_NUM_CHN))
+ {
+ retVal = -1;
+ }
+
+ if (retVal == 0)
+ {
+ data[0] = (uint32_t)port;
+ data[1] = (uint32_t)txBufLen;
+ data[2] = (uint32_t)rxBufLen;
+ data[3] = (uint32_t)txBuf;
+ data[4] = (uint32_t)rxBuf;
+ IOLINK_control(iolinkHandles[instance], IOLINK_CTRL_SET_XFER_BUFFER, (void *)data);
+ }
+
+ return (retVal);
+}
+
+void IO_Link_sendBuffer(uint8_t instance, uint8_t port)
+{
+ uint32_t channel;
+
+ if ((iolinkHandles[instance] != NULL) && (port < (uint8_t)IOLINK_MAX_NUM_CHN))
+ {
+ channel = (uint32_t)port;
+ IOLINK_control(iolinkHandles[instance], IOLINK_CTRL_START_XFER, (void *)&channel);
+ }
+}
+
+void IO_Link_start10msTimer(uint8_t instance, uint8_t port)
+{
+ uint32_t data[4] = {0, };
+
+ if ((iolinkHandles[instance] != NULL) && (port < (uint8_t)IOLINK_MAX_NUM_CHN))
+ {
+ data[0] = (uint32_t)port;
+ data[1] = IOLINK_TIMER_TYPE_10MS;
+ IOLINK_control(iolinkHandles[instance], IOLINK_CTRL_START_TIMER, (void *)data);
+ }
+}
+
+void IO_Link_stop10msTimer(uint8_t instance, uint8_t port)
+{
+ uint32_t data[2] = {0, };
+
+ if ((iolinkHandles[instance] != NULL) && (port < (uint8_t)IOLINK_MAX_NUM_CHN))
+ {
+ data[0] = (uint32_t)port;
+ data[1] = IOLINK_TIMER_TYPE_10MS;
+ IOLINK_control(iolinkHandles[instance], IOLINK_CTRL_STOP_TIMER, (void *)data);
+ }
+}
+
+void IO_Link_setCycleTimer(uint8_t instance, uint8_t port, uint32_t delay)
+{
+ uint32_t data[2] = {0, };
+
+ if ((iolinkHandles[instance] != NULL) && (port < (uint8_t)IOLINK_MAX_NUM_CHN))
+ {
+ data[0] = (uint32_t)port;
+ data[1] = delay;
+ IOLINK_control(iolinkHandles[instance], IOLINK_CTRL_SET_CYCLE_TIMER, (void *)data);
+ }
+}
+
+void IO_Link_startCycleTimer(uint8_t instance, uint8_t port)
+{
+ uint32_t data[4] = {0, };
+
+ if ((iolinkHandles[instance] != NULL) && (port < (uint8_t)IOLINK_MAX_NUM_CHN))
+ {
+ data[0] = (uint32_t)port;
+ data[1] = IOLINK_TIMER_TYPE_CYCLE;
+ IOLINK_control(iolinkHandles[instance], IOLINK_CTRL_START_TIMER, (void *)data);
+ }
+}
+
+void IO_Link_stopCycleTimer(uint8_t instance, uint8_t port)
+{
+ uint32_t data[2] = {0, };
+
+ if ((iolinkHandles[instance] != NULL) && (port < (uint8_t)IOLINK_MAX_NUM_CHN))
+ {
+ data[0] = (uint32_t)port;
+ data[1] = IOLINK_TIMER_TYPE_CYCLE;
+ IOLINK_control(iolinkHandles[instance], IOLINK_CTRL_STOP_TIMER, (void *)data);
+ }
+}
+
+void IO_Link_startAdjustableTimer(uint8_t instance, uint8_t port, uint8_t type, double t)
+{
+ uint32_t data[4] = {0, };
+
+ if ((iolinkHandles[instance] != NULL) && (port < (uint8_t)IOLINK_MAX_NUM_CHN))
+ {
+ data[0] = (uint32_t)port;
+ data[1] = IOLINK_TIMER_TYPE_ADJ;
+ data[2] = (uint32_t)type;
+ data[3] = (uint32_t)(t * 24.0); /* t in usec, t * 24 timeout match count with 24 MHz clock */
+ IOLINK_control(iolinkHandles[instance], IOLINK_CTRL_START_TIMER, (void *)data);
+ }
+}
+
+void IO_Link_stopAdjustableTimer()
+{
+ uint32_t timerType = IOLINK_TIMER_TYPE_ADJ;
+
+ IOLINK_control(iolinkHandles[0], IOLINK_CTRL_STOP_TIMER, (void *)&timerType);
+}
+
+void IO_Link_cycleTimerCallback(IOLINK_Handle handle, uint32_t channel)
+{
+ MPL_TimerCallback((uint8_t)channel, MPL_CYCLE_TIMER_DELAY);
+}
+
+void IO_Link_swTimerCallback(IOLINK_Handle handle, uint32_t channel)
+{
+ MPL_SWTimerCallback((uint8_t)channel);
+}
+
+void IO_Link_adjTimerCallback(IOLINK_Handle handle, uint32_t channel, uint32_t delayType)
+{
+ if (delayType == IOLINK_TIMER_ADJ_TREN)
+ {
+ MPL_TimerCallback((uint8_t)channel, MPL_TREN_MASTER_MESSAGE_DELAY);
+ }
+ else
+ {
+ MPL_TimerCallback((uint8_t)channel, MPL_TDMT_MASTER_MESSAGE_DELAY);
+ }
+}
+
+void IO_Link_xferRspCallback(IOLINK_Handle handle, uint32_t channel)
+{
+ MPL_SendRecv_rsp((uint8_t)channel);
+}
+
+void IO_Link_xferErrRspCallback(IOLINK_Handle handle, uint32_t channel)
+{
+ MPL_SendRecvError_rsp((uint8_t)channel);
+}
diff --git a/test/iq2_stack_test/src/iq_stack_api.h b/test/iq2_stack_test/src/iq_stack_api.h
--- /dev/null
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** ============================================================================
+ * @file iq_stack_api.h
+ *
+ * @brief IO-Link IQ2 Master stack interface
+ *
+ * ============================================================================
+ */
+
+#ifndef IQ_STACK_API_H
+#define IQ_STACK_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ti/drv/iolink/src/v0/IOLINK_v0.h>
+
+/**
+ * \brief IO-Link handle definitions
+ */
+#define IO_LINK_HANDLE_ICSS0_PRU0 ((uint8_t)IOLINK_HANDLE_ICSS0_PRU0)
+#define IO_LINK_HANDLE_ICSS0_PRU1 ((uint8_t)IOLINK_HANDLE_ICSS0_PRU1)
+#define IO_LINK_HANDLE_ICSS1_PRU0 ((uint8_t)IOLINK_HANDLE_ICSS1_PRU0)
+#define IO_LINK_HANDLE_ICSS1_PRU1 ((uint8_t)IOLINK_HANDLE_ICSS1_PRU1)
+
+/**
+ * \brief IO-Link commands
+ */
+#define IO_LINK_COMMAND_STARTPULSE ((uint8_t)IOLINK_COMMAND_STARTPULSE)
+#define IO_LINK_COMMAND_SETCOM ((uint8_t)IOLINK_COMMAND_SETCOM)
+
+/**
+ * \brief IO-Link adjuster timer types
+ */
+#define IO_LINK_TIMER_TYPE_TREN ((uint8_t)IOLINK_TIMER_ADJ_TREN)
+#define IO_LINK_TIMER_TYPE_TDMT ((uint8_t)IOLINK_TIMER_ADJ_TDMT)
+
+/*
+ * @brief Function to send user specified command to the PRU
+ *
+ * @param instance IOLINK ICSS PRU instance #
+ *
+ * @param port IOLINK channel #
+ *
+ * @param command command code
+ *
+ * @param arg argument of the command
+ *
+ * @return 0: success, -1: fail.
+ *
+ * @note: commands:
+ *
+ * command = IO_LINK_COMMAND_STARTPULSE
+ * - This command will generate a startpulse
+ * - arg: can be set to anything
+ *
+ * command = IO_LINK_COMMAND_SETCOM
+ * - This command will set the COM rate to arg
+ * - arg: sets the COM rate (1 = COM1; 2 = COM2; 3 = COM3)
+ */
+extern int8_t IO_Link_sendCommand(uint8_t instance, uint8_t port, uint8_t command, uint8_t arg);
+
+/*
+ * @brief Function to set the channel tx and rx buffer
+ *
+ * @param instance IOLINK ICSS PRU instance #
+ *
+ * @param port IOLINK channel #
+ *
+ * @param txBufLen length (<= 128) of the the data in bytes stored in the tx buffer
+ *
+ * @param rxBufLen length (<= 128) of the the data in bytes stored in the rx buffer
+ *
+ * @param txBuf tx buffer pointer
+ *
+ * @param rxBuf rx buffer pointer
+ *
+ * @return 0: success, -1: fail.
+ *
+ */
+extern int8_t IO_Link_setBuffer(uint8_t instance, uint8_t port, uint8_t txBufLen, uint8_t rxBufLen, uint8_t *txBuf, uint8_t *rxBuf);
+
+/*
+ * @brief Function to send the data to PRU
+ *
+ * @param instance IOLINK ICSS PRU instance #
+ *
+ * @param port IOLINK channel #
+ *
+ * @return none
+ *
+ * @note: This API call start a new communication cycle
+ *
+ */
+extern void IO_Link_sendBuffer(uint8_t instance, uint8_t port);
+
+/*
+ * @brief Function to start the 10 ms timer
+ *
+ * @param instance IOLINK ICSS PRU instance #
+ *
+ * @param port IOLINK channel #
+ *
+ * @return none
+ *
+ */
+extern void IO_Link_start10msTimer(uint8_t instance, uint8_t port);
+
+/*
+ * @brief Function to stop the 10 ms timer
+ *
+ * @param instance IOLINK ICSS PRU instance #
+ *
+ * @param port IOLINK channel #
+ *
+ * @return none
+ *
+ */
+extern void IO_Link_stop10msTimer(uint8_t instance, uint8_t port);
+
+/*
+ * @brief Function to control the cycle time of a channel
+ *
+ * @param instance IOLINK ICSS PRU instance #
+ *
+ * @param port IOLINK channel #
+ *
+ * @param delay delay time of the cycle timer
+ *
+ * @return none
+ *
+ */
+extern void IO_Link_setCycleTimer(uint8_t instance, uint8_t port, uint32_t delay);
+
+/*
+ * @brief Function to start the cycle timer
+ *
+ * @param instance IOLINK ICSS PRU instance #
+ *
+ * @param port IOLINK channel #
+ *
+ * @return none
+ *
+ */
+extern void IO_Link_startCycleTimer(uint8_t instance, uint8_t port);
+
+/*
+ * @brief Function to stop the cycle timer
+ *
+ * @param instance IOLINK ICSS PRU instance #
+ *
+ * @param port IOLINK channel #
+ *
+ * @return none
+ *
+ */
+extern void IO_Link_stopCycleTimer(uint8_t instance, uint8_t port);
+
+/*
+ * @brief Function to start the adjustable timer
+ *
+ * @param instance IOLINK ICSS PRU instance #
+ *
+ * @param port IOLINK channel #
+ *
+ * @param type adjustable timer type IOLINK_TIMER_TYPE_TREN or IOLINK_TIMER_TYPE_TDMT
+ *
+ * @param t adjustable time t in usec
+ *
+ * @return none
+ *
+ * @note: the adjustable timer is used to measure the start up sequence timings.
+ * It will generate an Interrupt as soon as the time t (given in us) is elapsed.
+ *
+ */
+extern void IO_Link_startAdjustableTimer(uint8_t instance, uint8_t port, uint8_t type, double t);
+
+/*
+ * @brief Function to stop the adjustable timer
+ *
+ * @return none
+ */
+extern void IO_Link_stopAdjustableTimer(void);
+
+/*
+ * @brief 10usec timer callback function to the stack
+ *
+ * @param handle IOLINK handle #
+ *
+ * @param channel IOLINK channel #
+ *
+ * @return none
+ *
+ */
+extern void IO_Link_cycleTimerCallback(IOLINK_Handle handle, uint32_t channel);
+
+/*
+ * @brief 10ms timer callback function to the stack
+ *
+ * @param handle IOLINK handle #
+ *
+ * @param channel IOLINK channel #
+ *
+ * @return none
+ *
+ */
+extern void IO_Link_swTimerCallback(IOLINK_Handle handle, uint32_t channel);
+
+/*
+ * @brief adjustable timer callback function to the stack
+ *
+ * @param handle IOLINK handle #
+ *
+ * @param channel IOLINK channel #
+ *
+ * @param delayType Adjustable timer delay type
+ *
+ * @return none
+ *
+ */
+extern void IO_Link_adjTimerCallback(IOLINK_Handle handle, uint32_t channel, uint32_t delayType);
+
+/*
+ * @brief data transfer response callback function to the stack
+ *
+ * @param handle IOLINK handle #
+ *
+ * @param channel IOLINK channel #
+ *
+ * @return none
+ *
+ */
+extern void IO_Link_xferRspCallback(IOLINK_Handle handle, uint32_t channel);
+
+/*
+ * @brief data transfer error response callback function to the stack
+ *
+ * @param handle IOLINK handle #
+ *
+ * @param channel IOLINK channel #
+ *
+ * @return none
+ *
+ */
+extern void IO_Link_xferErrRspCallback(IOLINK_Handle handle, uint32_t channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IQ_STACK_API_H */
diff --git a/test/iq2_stack_test/src/main_iolink_test.c b/test/iq2_stack_test/src/main_iolink_test.c
--- /dev/null
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http:;www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/* file: main_iolink_test.c
+ *
+ * brief: IO-Link master unit test code
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+#include <stdint.h>
+
+#include <xdc/std.h>
+#include <xdc/cfg/global.h>
+#include <xdc/runtime/System.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/knl/Semaphore.h>
+#include <xdc/runtime/Error.h>
+#include <ti/sysbios/knl/Clock.h>
+
+#include <ti/starterware/include/hw/am437x.h>
+#include <ti/starterware/include/am43xx/chipdb_defs.h>
+#include <ti/starterware/include/soc_control.h>
+#include <ti/starterware/include/prcm.h>
+#include <ti/csl/src/ip/icss/V1/cslr_icss_cfg.h>
+
+#include <ti/drv/pruss/pruicss.h>
+#include <ti/drv/iolink/src/v0/IOLINK_v0.h>
+#include <ti/drv/iolink/test/iq2_stack_test/src/ioLink_LEDTask.h>
+#include <ti/drv/iolink/test/iq2_stack_test/src/ioLink_powerSwitchTask.h>
+
+#include <ti/board/board.h>
+
+IOLINK_Handle iolinkHandles[2] = {NULL, };
+
+extern IOLINK_v0_Callbacks iolinkCallbacks;
+extern void mst_main (void);
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+void IO_Link_Master_Stack_Task(UArg arg0)
+{
+ IOLINK_Params params;
+ uint32_t instance = 0;
+
+ /* Initialize the PRU IO-Link driver */
+ IOLINK_init();
+
+ /* Open IO-Link instance */
+ IOLINK_Params_init(¶ms);
+ iolinkHandles[instance] = IOLINK_open(instance, ¶ms);
+
+ /* run the IO-Link master stack */
+ if (iolinkHandles[instance] != NULL)
+ {
+ IOLINK_control(iolinkHandles[instance], IOLINK_CTRL_SET_CALLBACKS, (void *)(&iolinkCallbacks));
+ mst_main();
+ }
+
+}
+
+int32_t IOLINK_boardInit(void)
+{
+ Board_STATUS boardStatus;
+ uint32_t timerInstance = 4;
+ int32_t retVal = 0;
+
+ boardStatus = Board_init(BOARD_INIT_MODULE_CLOCK |
+ BOARD_INIT_ICSS_PINMUX |
+ BOARD_INIT_UART_STDIO);
+
+ if (boardStatus == BOARD_SOK)
+ {
+ PRCMModuleEnable(CHIPDB_MOD_ID_PWMSS, 0, 0);
+
+ /* Clock source selection */
+ SOCCtrlTimerClkSrcSelect(timerInstance,
+ SOC_CTRL_DMTIMER_CLK_SRC_M_OSC_24M);
+ PRCMModuleEnable(CHIPDB_MOD_ID_DMTIMER, timerInstance , FALSE);
+ PRCMModuleEnable(CHIPDB_MOD_ID_DMTIMER, timerInstance + 2, FALSE);
+
+ /*Pinmux for LatchO in AM437x IDK*/
+ *((uint32_t *)0x44E10978) = 0x00050006;
+
+ //Board_phyReset(2);
+
+ /* Set ICSS1 in no standby mode */
+ HW_WR_FIELD32(0x54426000U + CSL_ICSSCFG_SYSCFG,
+ CSL_ICSSCFG_SYSCFG_STANDBY_MODE , 1);
+ }
+ else
+ {
+ retVal = -1;
+ }
+
+ return (retVal);
+}
+
+int main()
+{
+ Task_Params taskParams;
+
+ if (IOLINK_boardInit() == 0)
+ {
+ /* create a new task for the LED driver */
+ Task_Params_init(&taskParams);
+ taskParams.priority = 10;
+ taskParams.stackSize = 2048*4;
+ taskParams.instance->name = "ioLink LED Task";
+ Task_create((Task_FuncPtr)IOLink_LEDTask, &taskParams, NULL);
+
+ /* create a new task for the high side switch driver */
+ Task_Params_init(&taskParams);
+ taskParams.priority = 10;
+ taskParams.stackSize = 2048*4;
+ taskParams.instance->name = "ioLink Power Switch Task";
+ Task_create((Task_FuncPtr)IOLink_powerSwitchTask, &taskParams, NULL);
+
+ /* create the IO-Link Master Stack Task */
+ Task_Params_init(&taskParams);
+ taskParams.priority = 11;
+ taskParams.stackSize = 2048;
+ taskParams.instance->name = "ioLink Master Task";
+ Task_create((Task_FuncPtr)IO_Link_Master_Stack_Task, &taskParams, NULL);
+
+ BIOS_start();
+ }
+
+ return 0;
+}
diff --git a/test/iq2_stack_test/src/tsc_adc_ss.c b/test/iq2_stack_test/src/tsc_adc_ss.c
--- /dev/null
@@ -0,0 +1,694 @@
+/**
+ * \file tsc_adc_ss.c
+ *
+ * \brief This file contains the function definitions for the device
+ * abstraction layer for TSC_ADC_SS IP.
+ */
+
+/**
+ * \copyright Copyright (C) 2013 Texas Instruments Incorporated -
+ * http://www.ti.com/
+ */
+
+/**
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+#include <ti/starterware/include/types.h>
+//#include "hw_types.h"
+#include <ti/csl/hw_types.h>
+#include <ti/starterware/include/tsc_adc_ss.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+
+/* ========================================================================== */
+/* Structures and Enums */
+/* ========================================================================== */
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+uint32_t TSCADCGetRevision(uint32_t baseAddr)
+{
+ return(HW_RD_REG32(baseAddr + ADC0_REVISION));
+}
+
+void TSCADCClkDivConfig(uint32_t baseAddr, uint32_t moduleClk,
+ uint32_t afeInputClk)
+{
+ uint32_t clkDiv = 0U;
+
+ clkDiv = moduleClk/afeInputClk;
+
+ /* Configure the clock divider value. */
+ HW_WR_FIELD32((baseAddr + ADC0_ADC_CLKDIV),
+ ADC0_ADC_CLKDIV,
+ (clkDiv - 1));
+}
+
+void TSCADCSetHwEventMap(uint32_t baseAddr, uint32_t hwEvent)
+{
+ /* Set the hardware event. */
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_HW_EVT_MAPPING, hwEvent);
+}
+
+void TSCADCSetMode(uint32_t baseAddr, uint32_t mode)
+{
+ if (TSCADC_MODE_GP_ADC == mode)
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_TOUCH_SCREEN_EN,
+ ADC0_CTRL_TOUCH_SCREEN_EN_DISABLE);
+ }
+ else if ((TSCADC_MODE_FOUR_WIRE == mode) || (TSCADC_MODE_FIVE_WIRE == mode))
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_TOUCH_SCREEN_EN,
+ ADC0_CTRL_TOUCH_SCREEN_EN_ENABLE);
+ }
+ else
+ {
+ /* Perform nothing. */
+ }
+
+ /* Configure the TSCADC mode. */
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL), ADC0_CTRL_AFE_PEN,
+ mode);
+}
+
+void TSCADCStepIdTagEnable(uint32_t baseAddr, uint32_t enableStepIdTag)
+{
+ /* Configure the Step ID tag. */
+ if (TRUE == enableStepIdTag)
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_STEP_ID_TAG,
+ ADC0_CTRL_STEP_ID_TAG_CHANNELID);
+ }
+ else
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_STEP_ID_TAG,
+ ADC0_CTRL_STEP_ID_TAG_WRZERO);
+ }
+}
+
+void TSCADCStepConfigWrProtectEnable(uint32_t baseAddr,
+ uint32_t enableWrProtect)
+{
+ if (TRUE == enableWrProtect)
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_STEPCONFIG_WRITEPROTECT_N,
+ ADC0_CTRL_STEPCONFIG_WRITEPROTECT_N_PROTECTED);
+ }
+ else
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_STEPCONFIG_WRITEPROTECT_N,
+ ADC0_CTRL_STEPCONFIG_WRITEPROTECT_N_NOTPROTECTED);
+ }
+}
+
+void TSCADCTsIdleStepConfig(uint32_t baseAddr,
+ uint32_t enableDiffCtrl,
+ tscAdcStepCfg_t *pStepCfg)
+{
+ uint32_t regVal = 0U;
+
+ /* Configure the differential control. */
+ if (TRUE == enableDiffCtrl)
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_IDLECONFIG),
+ ADC0_IDLECONFIG_DIFF_CNTRL,
+ ADC0_IDLECONFIG_DIFF_CNTRL_DIFFERENTIAL);
+ }
+ else
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_IDLECONFIG),
+ ADC0_IDLECONFIG_DIFF_CNTRL,
+ ADC0_IDLECONFIG_DIFF_CNTRL_SINGLE);
+ }
+
+ regVal = HW_RD_REG32(baseAddr + ADC0_IDLECONFIG);
+
+ /* Configure the negative reference voltage. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_SEL_RFM_SWC,
+ pStepCfg->adcNegativeInpRef);
+
+ /* Configure the positive reference voltage. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_SEL_RFP_SWC,
+ pStepCfg->adcPositiveInpRef);
+
+ /* Configure the negative input channel. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_SEL_INM_SWM,
+ pStepCfg->adcNegativeInpChan);
+
+ /* Configure the positive input channel. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_SEL_INP_SWC,
+ pStepCfg->adcPositiveInpChan);
+
+ /* Control the XPPSW pin. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_XPPSW_SWC,
+ pStepCfg->enableXppsw);
+
+ /* Control the XNPSW pin. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_XNPSW_SWC,
+ pStepCfg->enableXnpsw);
+
+ /* Control the YPPSW pin. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_YPPSW_SWC,
+ pStepCfg->enableYppsw);
+
+ /* Control the XNNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_XNNSW_SWC,
+ pStepCfg->enableXnnsw);
+
+ /* Control the YPNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_YPNSW_SWC,
+ pStepCfg->enableYpnsw);
+
+ /* Control the YNNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_YNNSW_SWC,
+ pStepCfg->enableYnnsw);
+
+ /* Control the WPNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_IDLECONFIG_WPNSW_SWC,
+ pStepCfg->enableWpnsw);
+
+ /* Write variable value to register. */
+ HW_WR_REG32((baseAddr + ADC0_IDLECONFIG), regVal);
+}
+
+void TSCADCTsChargeStepConfig(uint32_t baseAddr,
+ uint32_t enableDiffCtrl,
+ tscAdcStepCfg_t *pStepCfg)
+{
+ uint32_t regVal = 0U;
+
+ /* Configure the differential control. */
+ if (TRUE == enableDiffCtrl)
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_TS_CHARGE_STEPCONFIG),
+ ADC0_TS_CHARGE_STEPCONFIG_DIFF_CNTRL,
+ ADC0_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_DIFFERENTIAL);
+ }
+ else
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_TS_CHARGE_STEPCONFIG),
+ ADC0_TS_CHARGE_STEPCONFIG_DIFF_CNTRL,
+ ADC0_TS_CHARGE_STEPCONFIG_DIFF_CNTRL_SINGLE);
+ }
+
+ regVal = HW_RD_REG32(baseAddr + ADC0_TS_CHARGE_STEPCONFIG);
+
+ /* Configure the negative reference voltage. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC,
+ pStepCfg->adcNegativeInpRef);
+
+ /* Configure the positive reference voltage. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC,
+ pStepCfg->adcPositiveInpRef);
+
+ /* Configure the negative input channel. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_SEL_INM_SWM,
+ pStepCfg->adcNegativeInpChan);
+
+ /* Configure the positive input channel. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_SEL_INP_SWC,
+ pStepCfg->adcPositiveInpChan);
+
+ /* Control the XPPSW pin. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_XPPSW_SWC,
+ pStepCfg->enableXppsw);
+
+ /* Control the XNPSW pin. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_XNPSW_SWC,
+ pStepCfg->enableXnpsw);
+
+ /* Control the YPPSW pin. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_YPPSW_SWC,
+ pStepCfg->enableYppsw);
+
+ /* Control the XNNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_XNNSW_SWC,
+ pStepCfg->enableXnnsw);
+
+ /* Control the YPNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_YPNSW_SWC,
+ pStepCfg->enableYpnsw);
+
+ /* Control the YNNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_YNNSW_SWC,
+ pStepCfg->enableYnnsw);
+
+ /* Control the WPNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_TS_CHARGE_STEPCONFIG_WPNSW_SWC,
+ pStepCfg->enableWpnsw);
+
+ /* Write variable value to register. */
+ HW_WR_REG32((baseAddr + ADC0_TS_CHARGE_STEPCONFIG), regVal);
+}
+
+void TSCADCTsChargeStepDelay(uint32_t baseAddr, uint32_t openDelay)
+{
+ /* Configure the open delay. */
+ HW_WR_FIELD32((baseAddr + ADC0_TS_CHARGE_DELAY),
+ ADC0_TS_CHARGE_DELAY_OPENDELAY,
+ openDelay);
+}
+
+void TSCADCStepConfig(uint32_t baseAddr,
+ uint32_t stepNum,
+ uint32_t enableDiffCtrl,
+ tscAdcStepCfg_t *pStepCfg)
+{
+ uint32_t regVal = 0U;
+
+ /* Configure the differential control. */
+ if (TRUE == enableDiffCtrl)
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_STEPCONFIG(stepNum - 1)),
+ ADC0_STEPCONFIG_DIFF_CNTRL,
+ ADC0_STEPCONFIG_DIFF_CNTRL_DIFFERENTIAL);
+ }
+ else
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_STEPCONFIG(stepNum - 1U)),
+ ADC0_STEPCONFIG_DIFF_CNTRL,
+ ADC0_STEPCONFIG_DIFF_CNTRL_SINGLE);
+ }
+
+ regVal = HW_RD_REG32(baseAddr + ADC0_STEPCONFIG(stepNum - 1U));
+
+ /* Configure the negative reference voltage. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_SEL_RFM_SWC,
+ pStepCfg->adcNegativeInpRef);
+
+ /* Configure the positive reference voltage. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_SEL_RFP_SWC,
+ pStepCfg->adcPositiveInpRef);
+
+ /* Configure the negative input channel. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_SEL_INM_SWC,
+ pStepCfg->adcNegativeInpChan);
+
+ /* Configure the positive input channel. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_SEL_INP_SWC,
+ pStepCfg->adcPositiveInpChan);
+
+ /* Control the XPPSW pin. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_XPPSW_SWC,
+ pStepCfg->enableXppsw);
+
+ /* Control the XNPSW pin. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_XNPSW_SWC,
+ pStepCfg->enableXnpsw);
+
+ /* Control the YPPSW pin. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_YPPSW_SWC,
+ pStepCfg->enableYppsw);
+
+ /* Control the XNNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_XNNSW_SWC,
+ pStepCfg->enableXnnsw);
+
+ /* Control the YPNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_YPNSW_SWC,
+ pStepCfg->enableYpnsw);
+
+ /* Control the YNNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_YNNSW_SWC,
+ pStepCfg->enableYnnsw);
+
+ /* Control the WPNSW pin. */
+ HW_SET_FIELD(regVal, ADC0_STEPCONFIG_WPNSW_SWC,
+ pStepCfg->enableWpnsw);
+
+ /* Write variable value to register. */
+ HW_WR_REG32((baseAddr + ADC0_STEPCONFIG(stepNum - 1U)), regVal);
+}
+
+void TSCADCStepFifoConfig(uint32_t baseAddr,
+ uint32_t stepNum,
+ uint32_t fifoSel,
+ uint32_t sampleLvl,
+ uint32_t enableIrq)
+{
+ /* Configure the Fifo. */
+ HW_WR_FIELD32((baseAddr + ADC0_STEPCONFIG(stepNum - 1)),
+ ADC0_STEPCONFIG_FIFO_SELECT,
+ fifoSel);
+
+ if (TRUE == enableIrq)
+ {
+ /* Enable IRQ request. */
+ HW_WR_FIELD32((baseAddr + ADC0_FIFOTHR(fifoSel - 1)),
+ ADC0_FIFOTHR_FIFO_THR_LEVEL,
+ (sampleLvl - 1));
+ }
+ else
+ {
+ /* Enable DMA request. */
+ HW_WR_FIELD32((baseAddr + ADC0_DMAREQ(fifoSel - 1)),
+ ADC0_DMAREQ_DMA_REQUEST_LEVEL,
+ (sampleLvl - 1));
+ }
+}
+
+void TSCADCStepMode(uint32_t baseAddr, uint32_t stepNum, uint32_t stepMode)
+{
+ /* Configure the step mode. */
+ HW_WR_FIELD32((baseAddr + ADC0_STEPCONFIG(stepNum - 1)),
+ ADC0_STEPCONFIG_MODE,
+ stepMode);
+}
+
+void TSCADCStepSamplesAvg(uint32_t baseAddr,
+ uint32_t stepNum,
+ uint32_t avgConfig)
+{
+ /* Configure the number of samples to be averaged. */
+ HW_WR_FIELD32((baseAddr + ADC0_STEPCONFIG(stepNum - 1)),
+ ADC0_STEPCONFIG_AVERAGING,
+ avgConfig);
+}
+
+void TSCADCStepDelayConfig(uint32_t baseAddr,
+ uint32_t stepNum,
+ uint32_t sampleDelay,
+ uint32_t openDelay)
+{
+ /* Configure the sample delay. */
+ HW_WR_FIELD32((baseAddr + ADC0_STEPDELAY(stepNum - 1)),
+ ADC0_STEPDELAY_SAMPLEDELAY,
+ sampleDelay);
+
+ /* Configure the open delay. */
+ HW_WR_FIELD32((baseAddr + ADC0_STEPDELAY(stepNum - 1)),
+ ADC0_STEPDELAY_OPENDELAY,
+ openDelay);
+}
+
+void TSCADCStepEnable(uint32_t baseAddr, uint32_t stepNum, uint32_t enableStep)
+{
+ uint32_t regVal = HW_RD_REG32(baseAddr + ADC0_STEPEN);
+
+ if (TRUE == enableStep)
+ {
+ regVal |= (1 << stepNum);
+ }
+ else
+ {
+ regVal &= ~(1 << stepNum);
+ }
+
+ HW_WR_REG32((baseAddr + ADC0_STEPEN), regVal);
+}
+
+void TSCADCDmaFifoEnable(uint32_t baseAddr,
+ uint32_t fifoSel,
+ uint32_t enableDma)
+{
+ uint32_t regVal = 0U;
+
+ if (TRUE == enableDma)
+ {
+ regVal = HW_RD_REG32(baseAddr + ADC0_DMAEN_SET);
+ regVal |= 0x1 << fifoSel;
+ HW_WR_REG32((baseAddr + ADC0_DMAEN_SET), regVal);
+ }
+ else
+ {
+ regVal = HW_RD_REG32(baseAddr + ADC0_DMAEN_CLR);
+ regVal |= 0x1 << fifoSel;
+ HW_WR_REG32((baseAddr + ADC0_DMAEN_CLR), regVal);
+ }
+}
+
+void TSCADCAfePowerDown(uint32_t baseAddr)
+{
+ /* Power down the ADC AFE. */
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL), ADC0_CTRL_POWER_DOWN,
+ ADC0_CTRL_POWER_DOWN_AFEPOWERDOWN);
+}
+
+void TSCADCAfePowerUp(uint32_t baseAddr)
+{
+ /* Power up the ADC. */
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL), ADC0_CTRL_POWER_DOWN,
+ ADC0_CTRL_POWER_DOWN_AFEPOWERUP);
+}
+
+void TSCADCStepRangeCheckEnable(uint32_t baseAddr,
+ uint32_t stepNum,
+ uint32_t enableRangeChk)
+{
+ if (TRUE == enableRangeChk)
+ {
+ /* Enable out of range check feature. */
+ HW_WR_FIELD32((baseAddr + ADC0_STEPCONFIG(stepNum - 1)),
+ ADC0_STEPCONFIG_RANGE_CHECK,
+ ADC0_STEPCONFIG_RANGE_CHECK_ENABLE);
+ }
+ else
+ {
+ /* Disable out of range check feature. */
+ HW_WR_FIELD32((baseAddr + ADC0_STEPCONFIG(stepNum - 1)),
+ ADC0_STEPCONFIG_RANGE_CHECK,
+ ADC0_STEPCONFIG_RANGE_CHECK_DISABLE);
+ }
+}
+
+uint32_t TSCADCGetFifoStepId(uint32_t baseAddr, uint32_t fifoSel)
+{
+ uint32_t fifoReg = 0;
+
+ if (TSCADC_FIFO_SEL_0 == fifoSel)
+ {
+ fifoReg = ADC0_FIFO0DATA;
+ }
+ else
+ {
+ fifoReg = ADC0_FIFO1DATA;
+ }
+
+ return(HW_RD_FIELD32((baseAddr + fifoReg), ADC0_FIFO0DATA_ADCCHNLID));
+}
+
+uint32_t TSCADCGetFifoData(uint32_t baseAddr, uint32_t fifoSel)
+{
+ uint32_t fifoReg = 0;
+
+ if (TSCADC_FIFO_SEL_0 == fifoSel)
+ {
+ fifoReg = ADC0_FIFO0DATA;
+ }
+ else
+ {
+ fifoReg = ADC0_FIFO1DATA;
+ }
+
+ return(HW_RD_FIELD32((baseAddr + fifoReg), ADC0_FIFO0DATA_ADCDATA));
+}
+
+uint32_t TSCADCGetFifoWordCount(uint32_t baseAddr, uint32_t fifoSel)
+{
+ /* Return the number of words present in FIFO. */
+ return(HW_RD_FIELD32((baseAddr + ADC0_FIFOCOUNT(fifoSel)),
+ ADC0_FIFOCOUNT_WORDS_IN_FIFO));
+}
+
+void TSCADCIntrClear(uint32_t baseAddr, uint32_t intrFlags)
+{
+ /* Clear the interrupt status. */
+ HW_WR_REG32((baseAddr + ADC0_IRQSTS), intrFlags);
+}
+
+uint32_t TSCADCIntrStatus(uint32_t baseAddr)
+{
+ /* Return the interrupt status. */
+ return(HW_RD_REG32(baseAddr + ADC0_IRQSTS));
+}
+
+void TSCADCIntrEnable(uint32_t baseAddr, uint32_t intrFlags)
+{
+ uint32_t regVal = HW_RD_REG32(baseAddr + ADC0_IRQEN_SET);
+
+ /* Enable the interrupts. */
+ regVal |= intrFlags;
+ HW_WR_REG32((baseAddr + ADC0_IRQEN_SET), regVal);
+}
+
+void TSCADCIntrDisable(uint32_t baseAddr, uint32_t intrFlags)
+{
+ uint32_t regVal = HW_RD_REG32(baseAddr + ADC0_IRQEN_CLR);
+
+ /* Disable the interrupts. */
+ regVal |= intrFlags;
+ HW_WR_REG32((baseAddr + ADC0_IRQEN_CLR), regVal);
+}
+
+void TSCADCIntrTrigger(uint32_t baseAddr, uint32_t intrFlags)
+{
+ uint32_t regVal = HW_RD_REG32(baseAddr + ADC0_IRQSTS_RAW);
+
+ /* Set the raw interrupts. */
+ regVal |= intrFlags;
+ HW_WR_REG32((baseAddr + ADC0_IRQSTS_RAW), regVal);
+}
+
+uint32_t TSCADCIntrRawStatus(uint32_t baseAddr)
+{
+ return(HW_RD_REG32(baseAddr + ADC0_IRQSTS_RAW));
+}
+
+uint32_t TSCADCStatus(uint32_t baseAddr)
+{
+ /* Return the ADC status. */
+ return(HW_RD_REG32(baseAddr + ADC0_ADCSTAT));
+}
+
+void TSCADCEnable(uint32_t baseAddr, uint32_t enableAdc)
+{
+ /* Enable/Disable the TSCADC. */
+ if (TRUE == enableAdc)
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_EN,
+ ADC0_CTRL_EN_ENABLE);
+ }
+ else
+ {
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_EN,
+ ADC0_CTRL_EN_DISABLE);
+ }
+}
+
+void TSCADCSetIdleMode(uint32_t baseAddr, uint32_t idleMode)
+{
+ /* Configure the Idle mode. */
+ HW_WR_FIELD32((baseAddr + ADC0_SYSCONFIG),
+ ADC0_SYSCONFIG_IDLEMODE,
+ idleMode);
+}
+
+void TSCADCTsWakeupPenEventEnable(uint32_t baseAddr, uint32_t enableWakeup)
+{
+ if (TRUE == enableWakeup)
+ {
+ /* Enable wakeup. */
+ HW_WR_FIELD32((baseAddr + ADC0_IRQWAKEUP),
+ ADC0_IRQWAKEUP_WAKEEN0,
+ ADC0_IRQWAKEUP_WAKEEN0_ENABLED);
+ }
+ else
+ {
+ /* Disable wakeup. */
+ HW_WR_FIELD32((baseAddr + ADC0_IRQWAKEUP),
+ ADC0_IRQWAKEUP_WAKEEN0,
+ ADC0_IRQWAKEUP_WAKEEN0_DISABLED);
+ }
+}
+
+void TSCADCHwPreemptEnable(uint32_t baseAddr, uint32_t enableHwPreempt)
+{
+ if (TRUE == enableHwPreempt)
+ {
+ /* Enable preemption. */
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_HW_PREEMPT,
+ ADC0_CTRL_HW_PREEMPT);
+ }
+ else
+ {
+ /* Disable preemption. */
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_HW_PREEMPT,
+ ADC0_CTRL_HW_PREEMPT_NOPREEMPT);
+ }
+}
+
+void TSCADCSetBias(uint32_t baseAddr, uint32_t adcBiasSel)
+{
+ /* Configure the TSCADC Bias. */
+ HW_WR_FIELD32((baseAddr + ADC0_CTRL),
+ ADC0_CTRL_ADC_BIAS_SELECT,
+ adcBiasSel);
+}
+
+void TSCADCSetRange(uint32_t baseAddr,
+ uint32_t lowRange,
+ uint32_t highRange)
+{
+ /* Configure the low range value. */
+ HW_WR_FIELD32((baseAddr + ADC0_ADCRANGE),
+ ADC0_ADCRANGE_LOW_RANGE_DATA,
+ lowRange);
+
+ /* Configure the high range value. */
+ HW_WR_FIELD32((baseAddr + ADC0_ADCRANGE),
+ ADC0_ADCRANGE_HIGH_RANGE_DATA,
+ highRange);
+}
+
+void TSCADCMiscConfig(uint32_t baseAddr,
+ uint32_t spareInputVal,
+ uint32_t spareOutputVal)
+{
+ /* Configure the spare input value. */
+ HW_WR_FIELD32((baseAddr + ADC0_ADC_MISC),
+ ADC0_ADC_MISC_AFE_SPARE_INPUT,
+ spareInputVal);
+
+ /* Configure the spare output value. */
+ HW_WR_FIELD32((baseAddr + ADC0_ADC_MISC),
+ ADC0_ADC_MISC_AFE_SPARE_OUTPUT,
+ spareOutputVal);
+}
+
+/* ========================================================================== */
+/* Deprecated Function Definitions */
+/* ========================================================================== */
+
+uint32_t TSCADCIsDMAFIFOEnabled(uint32_t baseAddr, uint32_t fifoSel)
+{
+ return((HW_RD_REG32(baseAddr + ADC0_DMAEN_SET) >>
+ fifoSel) & 0x1U);
+}