1 /* ============================================================================
2 * Copyright (c) Texas Instruments Incorporated 2012-2013
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
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13 * documentation and/or other materials provided with the
14 * distribution.
15 *
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17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33 /** ============================================================================
34 * @file iqn2fl_hwControlAux.h
35 *
36 * @brief API Auxilary header file for IQN2 to set HW control
37 *
38 */
40 #ifndef _IQN2FLHWCONTROLAUX_H_
41 #define _IQN2FLHWCONTROLAUX_H_
43 #include <ti/drv/iqn2/iqn2fl.h>
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
50 /**
51 * Hardware Control Functions of IQN2
52 */
54 /** ============================================================================
55 * @n@b Iqn2Fl_ailEfeGlobalEnableSet
56 *
57 * @b Description
58 * @n This function sets AIL EFE Global Enable
59 *
60 * @b Arguments
61 * @verbatim
63 hIqn2 Handle to the iqn2 instance (should use hIqn2->arg_ail to select AIL instance)
65 @endverbatim
66 *
67 * <b> Return Value </b> None
68 *
69 * <b> Pre Condition </b>
70 * @n Iqn2Fl_init(), Iqn2Fl_open()
71 *
72 * <b> Post Condition </b>
73 * @n None
74 *
75 * @b Writes
76 * @n AIL_IQ_EFE_GLOBAL_EN_SET_STB
77 *
78 * @b Example
79 * @verbatim
80 uint32_t arg = 0x1234; write of any value sets global enable
81 hIqn2->arg_ail = IQN2FL_AIL_0; // configure AIL 0
82 Iqn2Fl_ailEfeGlobalEnableSet (hIqn2, arg);
83 @endverbatim
84 * ===========================================================================
85 */
86 static inline
87 void Iqn2Fl_ailEfeGlobalEnableSet (
88 Iqn2Fl_Handle hIqn2,
89 uint32_t arg
90 )
91 {
92 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_SI_IQ_EFE_CONFIG_GROUP.AIL_IQ_EFE_GLOBAL_EN_SET_STB, IQN_AIL_AIL_IQ_EFE_GLOBAL_EN_SET_STB_DONT_CARE, arg);
93 }
95 /** ============================================================================
96 * @n@b Iqn2Fl_ailEfeGlobalEnableClear
97 *
98 * @b Description
99 * @n This function clears AIL EFE Global Enable
100 *
101 * @b Arguments
102 * @verbatim
104 hIqn2 Handle to the iqn2 instance (should use hIqn2->arg_ail to select AIL instance)
106 @endverbatim
107 *
108 * <b> Return Value </b> None
109 *
110 * <b> Pre Condition </b>
111 * @n Iqn2Fl_init(), Iqn2Fl_open()
112 *
113 * <b> Post Condition </b>
114 * @n None
115 *
116 * @b Writes
117 * @n AIL_IQ_EFE_GLOBAL_EN_CLR_STB
118 *
119 * @b Example
120 * @verbatim
121 uint32_t arg = 0x1234; write of any value clears global enable
122 hIqn2->arg_ail = IQN2FL_AIL_0; // configure AIL 0
123 Iqn2Fl_ailEfeGlobalEnableClear (hIqn2, arg);
124 @endverbatim
125 * ===========================================================================
126 */
127 static inline
128 void Iqn2Fl_ailEfeGlobalEnableClear (
129 Iqn2Fl_Handle hIqn2,
130 uint32_t arg
131 )
132 {
133 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_SI_IQ_EFE_CONFIG_GROUP.AIL_IQ_EFE_GLOBAL_EN_CLR_STB, IQN_AIL_AIL_IQ_EFE_GLOBAL_EN_CLR_STB_DONT_CARE, arg);
134 }
136 /** ============================================================================
137 * @n@b Iqn2Fl_setupAilEgrSchCpriRadstdCfgRegs
138 *
139 * @b Description
140 * @n This function configures AIL PE CPRI RADSTD CFG
141 *
142 * @b Arguments
143 * @verbatim
145 hIqn2 Handle to the iqn2 instance (should use hIqn2->arg_ail to select AIL instance)
146 pAilSiIqCpriRadstdCfg Pointer containing "Setup" properties for IQN2.
148 @endverbatim
149 *
150 * <b> Return Value </b> None
151 *
152 * <b> Pre Condition </b>
153 * @n Iqn2Fl_init(), Iqn2Fl_open()
154 *
155 * <b> Post Condition </b>
156 * @n None
157 *
158 * @b Writes
159 * @n AIL_IQ_PE_CPRI_RADSTD_CFG, AIL_IQ_PE_CPRI_RADSTD1_CFG, AIL_IQ_PE_CPRI_RADSTD2_CFG
160 *
161 * @b Example
162 * @verbatim
163 hIqn2->arg_ail = IQN2FL_AIL_0; // configure AIL 0
164 Iqn2Fl_setupAilEgrSchCpriRadstdCfgRegs (hIqn2, &ail_iq_pe_cpri_radstd_cfg);
165 @endverbatim
166 * ===========================================================================
167 */
168 static inline
169 void Iqn2Fl_setupAilEgrSchCpriRadstdCfgRegs (
170 Iqn2Fl_Handle hIqn2,
171 Iqn2Fl_AilSiIqCpriRadstdCfg *pAilSiIqCpriRadstdCfg
172 )
173 {
174 uint32_t tempReg, i;
176 /* Setup PE CPRI RADIO STANDARD CONFIGURATION REGISTER PART 0-2 */
177 for (i = 0; i < 8; i++)
178 {
179 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_SI_IQ_E_SCH_CPRI.AIL_IQ_PE_CPRI_RADSTD_CFG[i],
180 IQN_AIL_AIL_IQ_PE_CPRI_RADSTD_CFG_EN,
181 pAilSiIqCpriRadstdCfg->radstd_cfg_en[i]);
183 tempReg = CSL_FMK(IQN_AIL_AIL_IQ_PE_CPRI_RADSTD1_CFG_BFRM_OFFSET,
184 pAilSiIqCpriRadstdCfg->radstd1_cfg_bfrm_offset[i]) |
185 CSL_FMK(IQN_AIL_AIL_IQ_PE_CPRI_RADSTD1_CFG_HFRM_OFFSET,
186 pAilSiIqCpriRadstdCfg->radstd1_cfg_hfrm_offset[i]);
187 hIqn2->regs->Ail[hIqn2->arg_ail].AIL_SI_IQ_E_SCH_CPRI.AIL_IQ_PE_CPRI_RADSTD1_CFG[i] = tempReg;
189 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_SI_IQ_E_SCH_CPRI.AIL_IQ_PE_CPRI_RADSTD2_CFG[i],
190 IQN_AIL_AIL_IQ_PE_CPRI_RADSTD2_CFG_BFRM_NUM,
191 pAilSiIqCpriRadstdCfg->radstd2_cfg_bfrm_num[i]);
192 }
193 }
195 /** ============================================================================
196 * @n@b Iqn2Fl_ailEctlGlobalEnableSet
197 *
198 * @b Description
199 * @n This function sets AIL ECTL Global Enable
200 *
201 * @b Arguments
202 * @verbatim
204 hIqn2 Handle to the iqn2 instance (should use hIqn2->arg_ail to select AIL instance)
206 @endverbatim
207 *
208 * <b> Return Value </b> None
209 *
210 * <b> Pre Condition </b>
211 * @n Iqn2Fl_init(), Iqn2Fl_open()
212 *
213 * <b> Post Condition </b>
214 * @n None
215 *
216 * @b Writes
217 * @n AIL_ECTL_GLOBAL_EN_SET_STB
218 *
219 * @b Example
220 * @verbatim
221 uint32_t arg = 0x1234; write of any value sets global enable
222 hIqn2->arg_ail = IQN2FL_AIL_0; // configure AIL 0
223 Iqn2Fl_ailEctlGlobalEnableSet (hIqn2, arg);
224 @endverbatim
225 * ===========================================================================
226 */
227 static inline
228 void Iqn2Fl_ailEctlGlobalEnableSet (
229 Iqn2Fl_Handle hIqn2,
230 uint32_t arg
231 )
232 {
233 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_ECTL_PKT_IF.AIL_ECTL_GLOBAL_EN_SET_STB, IQN_AIL_AIL_ECTL_GLOBAL_EN_SET_STB_DONT_CARE, arg);
234 }
236 /** ============================================================================
237 * @n@b Iqn2Fl_ailEctlGlobalEnableClear
238 *
239 * @b Description
240 * @n This function clears AIL ECTL Global Enable
241 *
242 * @b Arguments
243 * @verbatim
245 hIqn2 Handle to the iqn2 instance (should use hIqn2->arg_ail to select AIL instance)
247 @endverbatim
248 *
249 * <b> Return Value </b> None
250 *
251 * <b> Pre Condition </b>
252 * @n Iqn2Fl_init(), Iqn2Fl_open()
253 *
254 * <b> Post Condition </b>
255 * @n None
256 *
257 * @b Writes
258 * @n AIL_ECTL_GLOBAL_EN_CLR_STB
259 *
260 * @b Example
261 * @verbatim
262 uint32_t arg = 0x1234; write of any value clears global enable
263 hIqn2->arg_ail = IQN2FL_AIL_0; // configure AIL 0
264 Iqn2Fl_ailEctlGlobalEnableClear (hIqn2, arg);
265 @endverbatim
266 * ===========================================================================
267 */
268 static inline
269 void Iqn2Fl_ailEctlGlobalEnableClear (
270 Iqn2Fl_Handle hIqn2,
271 uint32_t arg
272 )
273 {
274 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_ECTL_PKT_IF.AIL_ECTL_GLOBAL_EN_CLR_STB, IQN_AIL_AIL_ECTL_GLOBAL_EN_CLR_STB_DONT_CARE, arg);
275 }
277 /** ============================================================================
278 * @n@b Iqn2Fl_ailIctlGlobalEnableSet
279 *
280 * @b Description
281 * @n This function sets AIL ICTL Global Enable
282 *
283 * @b Arguments
284 * @verbatim
286 hIqn2 Handle to the iqn2 instance (should use hIqn2->arg_ail to select AIL instance)
288 @endverbatim
289 *
290 * <b> Return Value </b> None
291 *
292 * <b> Pre Condition </b>
293 * @n Iqn2Fl_init(), Iqn2Fl_open()
294 *
295 * <b> Post Condition </b>
296 * @n None
297 *
298 * @b Writes
299 * @n AIL_ICTL_GLOBAL_EN_SET_STB
300 *
301 * @b Example
302 * @verbatim
303 uint32_t arg = 0x1234; write of any value sets global enable
304 hIqn2->arg_ail = IQN2FL_AIL_0; // configure AIL 0
305 Iqn2Fl_ailIctlGlobalEnableSet (hIqn2, arg);
306 @endverbatim
307 * ===========================================================================
308 */
309 static inline
310 void Iqn2Fl_ailIctlGlobalEnableSet (
311 Iqn2Fl_Handle hIqn2,
312 uint32_t arg
313 )
314 {
315 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_ICTL_PKT_IF.AIL_ICTL_GLOBAL_EN_SET_STB, IQN_AIL_AIL_ICTL_GLOBAL_EN_SET_STB_DONT_CARE, arg);
316 }
318 /** ============================================================================
319 * @n@b Iqn2Fl_ailIctlGlobalEnableClear
320 *
321 * @b Description
322 * @n This function clears AIL ICTL Global Enable
323 *
324 * @b Arguments
325 * @verbatim
327 hIqn2 Handle to the iqn2 instance (should use hIqn2->arg_ail to select AIL instance)
329 @endverbatim
330 *
331 * <b> Return Value </b> None
332 *
333 * <b> Pre Condition </b>
334 * @n Iqn2Fl_init(), Iqn2Fl_open()
335 *
336 * <b> Post Condition </b>
337 * @n None
338 *
339 * @b Writes
340 * @n AIL_ICTL_GLOBAL_EN_CLR_STB
341 *
342 * @b Example
343 * @verbatim
344 uint32_t arg = 0x1234; write of any value clears global enable
345 hIqn2->arg_ail = IQN2FL_AIL_0; // configure AIL 0
346 Iqn2Fl_ailIctlGlobalEnableClear (hIqn2, arg);
347 @endverbatim
348 * ===========================================================================
349 */
350 static inline
351 void Iqn2Fl_ailIctlGlobalEnableClear (
352 Iqn2Fl_Handle hIqn2,
353 uint32_t arg
354 )
355 {
356 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_ICTL_PKT_IF.AIL_ICTL_GLOBAL_EN_CLR_STB, IQN_AIL_AIL_ICTL_GLOBAL_EN_CLR_STB_DONT_CARE, arg);
357 }
359 /** ============================================================================
360 * @n@b Iqn2Fl_ailIfeGlobalEnableSet
361 *
362 * @b Description
363 * @n This function sets AIL IFE Global Enable
364 *
365 * @b Arguments
366 * @verbatim
368 hIqn2 Handle to the iqn2 instance (should use hIqn2->arg_ail to select AIL instance)
370 @endverbatim
371 *
372 * <b> Return Value </b> None
373 *
374 * <b> Pre Condition </b>
375 * @n Iqn2Fl_init(), Iqn2Fl_open()
376 *
377 * <b> Post Condition </b>
378 * @n None
379 *
380 * @b Writes
381 * @n AIL_IQ_IFE_GLOBAL_EN_SET_STB
382 *
383 * @b Example
384 * @verbatim
385 uint32_t arg = 0x1234; write of any value sets global enable
386 hIqn2->arg_ail = IQN2FL_AIL_0; // configure AIL 0
387 Iqn2Fl_ailIfeGlobalEnableSet (hIqn2, arg);
388 @endverbatim
389 * ===========================================================================
390 */
391 static inline
392 void Iqn2Fl_ailIfeGlobalEnableSet (
393 Iqn2Fl_Handle hIqn2,
394 uint32_t arg
395 )
396 {
397 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_IQ_IFE_CONFIG_GROUP.AIL_IQ_IFE_GLOBAL_EN_SET_STB, IQN_AIL_AIL_IQ_IFE_GLOBAL_EN_SET_STB_DONT_CARE, arg);
398 }
400 /** ============================================================================
401 * @n@b Iqn2Fl_ailIfeGlobalEnableClear
402 *
403 * @b Description
404 * @n This function clears AIL IFE Global Enable
405 *
406 * @b Arguments
407 * @verbatim
409 hIqn2 Handle to the iqn2 instance (should use hIqn2->arg_ail to select AIL instance)
411 @endverbatim
412 *
413 * <b> Return Value </b> None
414 *
415 * <b> Pre Condition </b>
416 * @n Iqn2Fl_init(), Iqn2Fl_open()
417 *
418 * <b> Post Condition </b>
419 * @n None
420 *
421 * @b Writes
422 * @n AIL_IQ_IFE_GLOBAL_EN_CLR_STB
423 *
424 * @b Example
425 * @verbatim
426 uint32_t arg = 0x1234; write of any value clears global enable
427 hIqn2->arg_ail = IQN2FL_AIL_0; // configure AIL 0
428 Iqn2Fl_ailIfeGlobalEnableClear (hIqn2, arg);
429 @endverbatim
430 * ===========================================================================
431 */
432 static inline
433 void Iqn2Fl_ailIfeGlobalEnableClear (
434 Iqn2Fl_Handle hIqn2,
435 uint32_t arg
436 )
437 {
438 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_IQ_IFE_CONFIG_GROUP.AIL_IQ_IFE_GLOBAL_EN_CLR_STB, IQN_AIL_AIL_IQ_IFE_GLOBAL_EN_CLR_STB_DONT_CARE, arg);
439 }
441 /** ============================================================================
442 * @n@b Iqn2Fl_setupAilPdCpriAxcRadstdCfgRegs
443 *
444 * @b Description
445 * @n This function configures AIL PD CPRI AXC RADSTD CFG
446 *
447 * @b Arguments
448 * @verbatim
450 hIqn2 Handle to the iqn2 instance (should use hIqn2->arg_ail to select AIL instance)
451 pAilPdCpriAxcRadstdCfg Pointer containing "Setup" properties for IQN2.
453 @endverbatim
454 *
455 * <b> Return Value </b> None
456 *
457 * <b> Pre Condition </b>
458 * @n Iqn2Fl_init(), Iqn2Fl_open()
459 *
460 * <b> Post Condition </b>
461 * @n None
462 *
463 * @b Writes
464 * @n AIL_PD_CPRI_RADSTD_CFG, AIL_PD_CPRI_RADSTD1_CFG, AIL_PD_CPRI_RADSTD2_CFG
465 *
466 * @b Example
467 * @verbatim
468 hIqn2->arg_ail = IQN2FL_AIL_0; // configure AIL 0
469 Iqn2Fl_setupAilPdCpriAxcRadstdCfgRegs (hIqn2, &ail_iq_pd_cpri_axc_radstd_cfg);
470 @endverbatim
471 * ===========================================================================
472 */
473 static inline
474 void Iqn2Fl_setupAilPdCpriAxcRadstdCfgRegs (
475 Iqn2Fl_Handle hIqn2,
476 Iqn2Fl_AilSiIqCpriRadstdCfg *pAilPdCpriAxcRadstdCfg
477 )
478 {
479 uint32_t tempReg, i;
481 /* Setup PD CPRI RADIO STANDARD CONFIGURATION REGISTER PART 0-2 */
482 for (i = 0; i < 8; i++)
483 {
484 /* AIL PD CPRI RADSTD CFG */
485 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_PD_CPRI_AXC_CFG.AIL_PD_CPRI_RADSTD_CFG[i],
486 IQN_AIL_AIL_PD_CPRI_RADSTD_CFG_EN,
487 pAilPdCpriAxcRadstdCfg->radstd_cfg_en[i]);
489 /* AIL PD CPRI RADSTD1 CFG */
490 tempReg = CSL_FMK(IQN_AIL_AIL_PD_CPRI_RADSTD1_CFG_BFRM_OFFSET,
491 pAilPdCpriAxcRadstdCfg->radstd1_cfg_bfrm_offset[i]) |
492 CSL_FMK(IQN_AIL_AIL_PD_CPRI_RADSTD1_CFG_HFRM_OFFSET,
493 pAilPdCpriAxcRadstdCfg->radstd1_cfg_hfrm_offset[i]);
494 hIqn2->regs->Ail[hIqn2->arg_ail].AIL_PD_CPRI_AXC_CFG.AIL_PD_CPRI_RADSTD1_CFG[i] = tempReg;
496 /* AIL PD CPRI RADSTD2 CFG */
497 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_PD_CPRI_AXC_CFG.AIL_PD_CPRI_RADSTD2_CFG[i],
498 IQN_AIL_AIL_PD_CPRI_RADSTD2_CFG_BFRM_NUM,
499 pAilPdCpriAxcRadstdCfg->radstd2_cfg_bfrm_num[i]);
500 }
501 }
503 /** ============================================================================
504 * @n@b Iqn2Fl_setupAilUatGenCtlUatCfgRegs
505 *
506 * @b Description
507 * @n IQN2 AIL UAT GEN CTL UAT configuration registers setup
508 *
509 * @b Arguments
510 * @verbatim
512 hIqn2 Handle to the iqn2 instance
513 pUatCfg Pointer to @a Iqn2Fl_UatCfg
515 @endverbatim
516 *
517 * <b> Return Value </b> Iqn2Fl_Status
518 *
519 * <b> Pre Condition </b>
520 * @n Iqn2Fl_init(), Iqn2Fl_open()
521 *
522 * <b> Post Condition </b>
523 * @n None
524 *
525 * @b Writes
526 * @n AIL_UAT_CFG
527 *
528 * @b Example
529 * @verbatim
530 Iqn2Fl_setupAilUatGenCtlUatCfgRegs (hIqn2, &ail_uat_cfg);
531 @endverbatim
532 * ===========================================================================
533 */
534 static inline
535 Iqn2Fl_Status Iqn2Fl_setupAilUatGenCtlUatCfgRegs(
536 Iqn2Fl_Handle hIqn2,
537 Iqn2Fl_UatCfg *pUatCfg
538 )
539 {
540 uint32_t tempReg;
542 tempReg = CSL_FMK(IQN_AIL_AIL_UAT_CFG_UAT_RUN,
543 pUatCfg->uat_run) |
544 CSL_FMK(IQN_AIL_AIL_UAT_CFG_DIAG_SYNC,
545 pUatCfg->diag_sync);
546 hIqn2->regs->Ail[hIqn2->arg_ail].AIL_UAT_GEN_CTL.AIL_UAT_CFG = tempReg;
548 return IQN2FL_SOK;
549 }
551 /** ============================================================================
552 * @n@b Iqn2Fl_setupAilPhyCiLutACfgRegs
553 *
554 * @b Description
555 * @n IQN2 AIL PHY CI LUT A configuration registers setup
556 *
557 * @b Arguments
558 * @verbatim
560 hIqn2 Handle to the iqn2 instance
561 pAilPhyLutSetup Pointer to @a Iqn2Fl_AilPhyLutSetup
563 @endverbatim
564 *
565 * <b> Return Value </b> Iqn2Fl_Status
566 *
567 * <b> Pre Condition </b>
568 * @n Iqn2Fl_init(), Iqn2Fl_open()
569 *
570 * <b> Post Condition </b>
571 * @n None
572 *
573 * @b Writes
574 * @n AIL_PHY_CI_LUT_A
575 *
576 * @b Example
577 * @verbatim
578 Iqn2Fl_setupAilPhyCiLutACfgRegs (hIqn2, &ail_phy_ci_lut_a_cfg);
579 @endverbatim
580 * ===========================================================================
581 */
582 static inline
583 Iqn2Fl_Status Iqn2Fl_setupAilPhyCiLutACfgRegs(
584 Iqn2Fl_Handle hIqn2,
585 Iqn2Fl_AilPhyLutSetup *pAilPhyLutSetup
586 )
587 {
588 uint32_t tempReg;
590 tempReg = CSL_FMK(IQN_AIL_AIL_PHY_CI_LUTA_CFG_SMPL_COUNT,
591 pAilPhyLutSetup->smpl_count) |
592 CSL_FMK(IQN_AIL_AIL_PHY_CI_LUTA_CFG_SMPL_OFFSET,
593 pAilPhyLutSetup->smpl_offset) |
594 CSL_FMK(IQN_AIL_AIL_PHY_CI_LUTA_CFG_SMPL_TYPE,
595 pAilPhyLutSetup->smpl_type) |
596 CSL_FMK(IQN_AIL_AIL_PHY_CI_LUTA_CFG_SMPL_LAST,
597 pAilPhyLutSetup->smpl_last);
598 hIqn2->regs->Ail[hIqn2->arg_ail].AIL_PHY_CI_LUT_A[pAilPhyLutSetup->index].AIL_PHY_CI_LUTA_CFG = tempReg;
600 return IQN2FL_SOK;
601 }
603 /** ============================================================================
604 * @n@b Iqn2Fl_setupAilPhyCiLutBCfgRegs
605 *
606 * @b Description
607 * @n IQN2 AIL PHY CI LUT B configuration registers setup
608 *
609 * @b Arguments
610 * @verbatim
612 hIqn2 Handle to the iqn2 instance
613 pAilPhyLutSetup Pointer to @a Iqn2Fl_AilPhyLutSetup
615 @endverbatim
616 *
617 * <b> Return Value </b> Iqn2Fl_Status
618 *
619 * <b> Pre Condition </b>
620 * @n Iqn2Fl_init(), Iqn2Fl_open()
621 *
622 * <b> Post Condition </b>
623 * @n None
624 *
625 * @b Writes
626 * @n AIL_PHY_CI_LUT_B
627 *
628 * @b Example
629 * @verbatim
630 Iqn2Fl_setupAilPhyCiLutBCfgRegs (hIqn2, &ail_phy_ci_lut_b_cfg);
631 @endverbatim
632 * ===========================================================================
633 */
634 static inline
635 Iqn2Fl_Status Iqn2Fl_setupAilPhyCiLutBCfgRegs(
636 Iqn2Fl_Handle hIqn2,
637 Iqn2Fl_AilPhyLutSetup *pAilPhyLutSetup
638 )
639 {
640 uint32_t tempReg;
642 tempReg = CSL_FMK(IQN_AIL_AIL_PHY_CI_LUTB_CFG_SMPL_COUNT,
643 pAilPhyLutSetup->smpl_count) |
644 CSL_FMK(IQN_AIL_AIL_PHY_CI_LUTB_CFG_SMPL_OFFSET,
645 pAilPhyLutSetup->smpl_offset) |
646 CSL_FMK(IQN_AIL_AIL_PHY_CI_LUTB_CFG_SMPL_TYPE,
647 pAilPhyLutSetup->smpl_type) |
648 CSL_FMK(IQN_AIL_AIL_PHY_CI_LUTB_CFG_SMPL_LAST,
649 pAilPhyLutSetup->smpl_last);
650 hIqn2->regs->Ail[hIqn2->arg_ail].AIL_PHY_CI_LUT_B[pAilPhyLutSetup->index].AIL_PHY_CI_LUTB_CFG = tempReg;
652 return IQN2FL_SOK;
653 }
655 /** ============================================================================
656 * @n@b Iqn2Fl_setupAilPhyCoLutACfgRegs
657 *
658 * @b Description
659 * @n IQN2 AIL PHY CO LUT A configuration registers setup
660 *
661 * @b Arguments
662 * @verbatim
664 hIqn2 Handle to the iqn2 instance
665 pAilPhyLutSetup Pointer to @a Iqn2Fl_AilPhyLutSetup
667 @endverbatim
668 *
669 * <b> Return Value </b> Iqn2Fl_Status
670 *
671 * <b> Pre Condition </b>
672 * @n Iqn2Fl_init(), Iqn2Fl_open()
673 *
674 * <b> Post Condition </b>
675 * @n None
676 *
677 * @b Writes
678 * @n AIL_PHY_CO_LUT_A
679 *
680 * @b Example
681 * @verbatim
682 Iqn2Fl_setupAilPhyCoLutACfgRegs (hIqn2, &ail_phy_co_lut_a_cfg);
683 @endverbatim
684 * ===========================================================================
685 */
686 static inline
687 Iqn2Fl_Status Iqn2Fl_setupAilPhyCoLutACfgRegs(
688 Iqn2Fl_Handle hIqn2,
689 Iqn2Fl_AilPhyLutSetup *pAilPhyLutSetup
690 )
691 {
692 uint32_t tempReg;
694 tempReg = CSL_FMK(IQN_AIL_AIL_PHY_CO_LUTA_CFG_SMPL_COUNT,
695 pAilPhyLutSetup->smpl_count) |
696 CSL_FMK(IQN_AIL_AIL_PHY_CO_LUTA_CFG_SMPL_OFFSET,
697 pAilPhyLutSetup->smpl_offset) |
698 CSL_FMK(IQN_AIL_AIL_PHY_CO_LUTA_CFG_SMPL_TYPE,
699 pAilPhyLutSetup->smpl_type) |
700 CSL_FMK(IQN_AIL_AIL_PHY_CO_LUTA_CFG_SMPL_LAST,
701 pAilPhyLutSetup->smpl_last);
702 hIqn2->regs->Ail[hIqn2->arg_ail].AIL_PHY_CO_LUT_A[pAilPhyLutSetup->index].AIL_PHY_CO_LUTA_CFG = tempReg;
704 return IQN2FL_SOK;
705 }
707 /** ============================================================================
708 * @n@b Iqn2Fl_setupAilPhyCoLutBCfgRegs
709 *
710 * @b Description
711 * @n IQN2 AIL PHY CO LUT B configuration registers setup
712 *
713 * @b Arguments
714 * @verbatim
716 hIqn2 Handle to the iqn2 instance
717 pAilPhyLutSetup Pointer to @a Iqn2Fl_AilPhyLutSetup
719 @endverbatim
720 *
721 * <b> Return Value </b> Iqn2Fl_Status
722 *
723 * <b> Pre Condition </b>
724 * @n Iqn2Fl_init(), Iqn2Fl_open()
725 *
726 * <b> Post Condition </b>
727 * @n None
728 *
729 * @b Writes
730 * @n AIL_PHY_CO_LUT_B
731 *
732 * @b Example
733 * @verbatim
734 Iqn2Fl_setupAilPhyCoLutBCfgRegs (hIqn2, &ail_phy_co_lut_b_cfg);
735 @endverbatim
736 * ===========================================================================
737 */
738 static inline
739 Iqn2Fl_Status Iqn2Fl_setupAilPhyCoLutBCfgRegs(
740 Iqn2Fl_Handle hIqn2,
741 Iqn2Fl_AilPhyLutSetup *pAilPhyLutSetup
742 )
743 {
744 uint32_t tempReg;
746 tempReg = CSL_FMK(IQN_AIL_AIL_PHY_CO_LUTB_CFG_SMPL_COUNT,
747 pAilPhyLutSetup->smpl_count) |
748 CSL_FMK(IQN_AIL_AIL_PHY_CO_LUTB_CFG_SMPL_OFFSET,
749 pAilPhyLutSetup->smpl_offset) |
750 CSL_FMK(IQN_AIL_AIL_PHY_CO_LUTB_CFG_SMPL_TYPE,
751 pAilPhyLutSetup->smpl_type) |
752 CSL_FMK(IQN_AIL_AIL_PHY_CO_LUTB_CFG_SMPL_LAST,
753 pAilPhyLutSetup->smpl_last);
754 hIqn2->regs->Ail[hIqn2->arg_ail].AIL_PHY_CO_LUT_B[pAilPhyLutSetup->index].AIL_PHY_CO_LUTB_CFG = tempReg;
756 return IQN2FL_SOK;
757 }
759 /** ============================================================================
760 * @n@b Iqn2Fl_updateEgressAilRadioStandardTc
761 *
762 * @b Description
763 * @n This functions updates the Radio Framing Sample Terminal Count Configuration Register for
764 * for a symbol index of a radio standard id. Used for LTE to implement runtime updates required
765 * by MBSFN implementation.
766 *
767 * @b Arguments
768 * @verbatim
770 hIqn2 Handle to the iqn2 instance
771 radioStdId Radio Standard ID
772 symbolSize New symbol size (sample count)
773 symbolIndex Symbol index
775 @endverbatim
776 *
777 * <b> Return Value </b> Iqn2Fl_Status
778 *
779 * <b> Pre Condition </b>
780 * @n Iqn2Fl_init(), Iqn2Fl_open(), Iqn2Fl_hwSetup
781 *
782 * <b> Post Condition </b>
783 * @n None
784 *
785 * @b Writes
786 * @n AIL_IQ_EFE_FRM_SAMP_TC_CFG
787 *
788 * @b Example
789 * @verbatim
790 Iqn2Fl_updateEgressAilRadioStandardTc (hIqn2, radioStdId, symbolSize, symbolIndex);
791 @endverbatim
792 * ===========================================================================
793 */
794 static inline
795 Iqn2Fl_Status Iqn2Fl_updateEgressAilRadioStandardTc(
796 Iqn2Fl_Handle hIqn2,
797 uint32_t radioStdId,
798 uint32_t symbolSize,
799 uint32_t symbolIndex
800 )
801 {
802 uint32_t startIdx;
804 startIdx = CSL_FEXT(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_SI_IQ_EFE_RADIO_STANDARD_GROUP.AIL_IQ_EFE_FRM_TC_CFG[radioStdId],IQN_AIL_AIL_IQ_EFE_FRM_TC_CFG_INDEX_SC);
805 CSL_FINS(hIqn2->regs->Ail[hIqn2->arg_ail].AIL_IQ_EFE_FRM_SAMP_TC_MMR_RAM[startIdx+symbolIndex].AIL_IQ_EFE_FRM_SAMP_TC_CFG, IQN_AIL_AIL_IQ_EFE_FRM_SAMP_TC_CFG_SAMP_TC,symbolSize);
807 return IQN2FL_SOK;
808 }
810 /** ============================================================================
811 * @n@b Iqn2Fl_setupTopVcSysStsSwResetStbRegs
812 *
813 * @b Description
814 * @n IQN2 Top VC Sys Status SW Reset Stb registers setup
815 *
816 * @b Arguments
817 * @verbatim
819 hIqn2 Handle to the iqn2 instance
820 pTopVCSwResetStbSetup Pointer containing "Setup" properties for IQN2.
822 @endverbatim
823 *
824 * <b> Return Value </b> Iqn2Fl_Status
825 *
826 * <b> Pre Condition </b>
827 * @n Iqn2Fl_init(), Iqn2Fl_open()
828 *
829 * <b> Post Condition </b>
830 * @n None
831 *
832 * @b Writes
833 * @n VC_SW_RESET_STB
834 *
835 * @b Example
836 * @verbatim
837 Iqn2Fl_setupTopVcSysStsSwResetStbRegs (hIqn2, &vc_sys_sts_sw_reset_stb);
838 @endverbatim
839 * ===========================================================================
840 */
841 static inline
842 Iqn2Fl_Status Iqn2Fl_setupTopVcSysStsSwResetStbRegs(
843 Iqn2Fl_Handle hIqn2,
844 Iqn2Fl_TopVCSwResetStbSetup *pTopVCSwResetStbSetup
845 )
846 {
847 uint32_t tempReg;
849 /* Setup VC SW RESET STB register fields */
850 tempReg = CSL_FMK(IQN2_TOP_VC_SW_RESET_STB_SW_RESET,
851 pTopVCSwResetStbSetup->sw_reset) |
852 CSL_FMK(IQN2_TOP_VC_SW_RESET_STB_SW_RESET_AID,
853 pTopVCSwResetStbSetup->sw_reset_aid) |
854 CSL_FMK(IQN2_TOP_VC_SW_RESET_STB_SW_RESET_DIO,
855 pTopVCSwResetStbSetup->sw_reset_dio) |
856 CSL_FMK(IQN2_TOP_VC_SW_RESET_STB_SW_RESET_PKTDMA,
857 pTopVCSwResetStbSetup->sw_reset_pktdma) |
858 CSL_FMK(IQN2_TOP_VC_SW_RESET_STB_SW_RESET_AIL0,
859 pTopVCSwResetStbSetup->sw_reset_ail0) |
860 CSL_FMK(IQN2_TOP_VC_SW_RESET_STB_SW_RESET_AIL1,
861 pTopVCSwResetStbSetup->sw_reset_ail1) |
862 CSL_FMK(IQN2_TOP_VC_SW_RESET_STB_SW_RESET_AIL2,
863 pTopVCSwResetStbSetup->sw_reset_ail2) |
864 CSL_FMK(IQN2_TOP_VC_SW_RESET_STB_SW_RESET_AIL3,
865 pTopVCSwResetStbSetup->sw_reset_ail3);
866 hIqn2->regs->Top.VC_SYS_STS_CFG.VC_SW_RESET_STB = tempReg;
868 return IQN2FL_SOK;
869 }
871 /** ============================================================================
872 * @n@b Iqn2Fl_setupAt2Events24ArrayRegs
873 *
874 * @b Description
875 * @n IQN2 AT2 Events 24Array registers setup
876 *
877 * @b Arguments
878 * @verbatim
880 hIqn2 Handle to the iqn2 instance
881 pIqn2Fl_At2Events24Array Pointer containing "Setup" properties for IQN2.
883 @endverbatim
884 *
885 * <b> Return Value </b> Iqn2Fl_Status
886 *
887 * <b> Pre Condition </b>
888 * @n Iqn2Fl_init(), Iqn2Fl_open()
889 *
890 * <b> Post Condition </b>
891 * @n None
892 *
893 * @b Writes
894 * @n AT2_EVENTS_24ARRAY
895 *
896 * @b Example
897 * @verbatim
898 Iqn2Fl_setupAt2Events24ArrayRegs (hIqn2, &at2_events_24array);
899 @endverbatim
900 * ===========================================================================
901 */
902 static inline
903 Iqn2Fl_Status Iqn2Fl_setupAt2Events24ArrayRegs(
904 Iqn2Fl_Handle hIqn2,
905 Iqn2Fl_At2Events24Array *pIqn2Fl_At2Events24Array
906 )
907 {
908 uint32_t i, tempReg;
910 /* Setup AT2 EVENTS 24ARRAY - EVENT OFFSET CFG */
911 for (i = 0; i < 24; i++)
912 {
913 tempReg = CSL_FMK(IQN_AT2_AT2_EVENT_OFFSET_CFG_VAL,
914 pIqn2Fl_At2Events24Array->at2_events_24array_offset_cfg_val[i]) |
915 CSL_FMK(IQN_AT2_AT2_EVENT_OFFSET_CFG_EVT_STRB_SEL,
916 pIqn2Fl_At2Events24Array->at2_events_24array_offset_cfg_evt_strb_sel[i]);
917 hIqn2->regs->At2.AT2_EVENTS_24ARRAY[i].AT2_EVENT_OFFSET_CFG = tempReg;
918 }
920 /* Setup AT2 EVENTS 24ARRAY - EVENT MOD TC CFG */
921 for (i = 0; i < 24; i++)
922 {
923 CSL_FINS(hIqn2->regs->At2.AT2_EVENTS_24ARRAY[i].AT2_EVENT_MOD_TC_CFG,
924 IQN_AT2_AT2_EVENT_MOD_TC_CFG_VAL,
925 pIqn2Fl_At2Events24Array->at2_events_24array_mod_tc_cfg_val[i]);
926 }
928 /* Setup AT2 EVENTS 24ARRAY - EVENT MASK LSBS CFG */
929 for (i = 0; i < 24; i++)
930 {
931 CSL_FINS(hIqn2->regs->At2.AT2_EVENTS_24ARRAY[i].AT2_EVENT_MASK_LSBS_CFG,
932 IQN_AT2_AT2_EVENT_MASK_LSBS_CFG_VAL,
933 pIqn2Fl_At2Events24Array->at2_events_24array_mask_lsbs_cfg_val[i]);
934 }
936 /* Setup AT2 EVENTS 24ARRAY - EVENT MASK MSBS CFG */
937 for (i = 0; i < 24; i++)
938 {
939 CSL_FINS(hIqn2->regs->At2.AT2_EVENTS_24ARRAY[i].AT2_EVENT_MASK_MSBS_CFG,
940 IQN_AT2_AT2_EVENT_MASK_MSBS_CFG_VAL,
941 pIqn2Fl_At2Events24Array->at2_events_24array_mask_msbs_cfg_val[i]);
942 }
944 return IQN2FL_SOK;
945 }
947 /** ============================================================================
948 * @n@b Iqn2Fl_setupAid2UatEgrRadtOffsetCfgRegs
949 *
950 * @b Description
951 * @n IQN2 AID2 UAT Egress Radio Timers offset configuration
952 *
953 * @b Arguments
954 * @verbatim
956 hIqn2 Handle to the iqn2 instance
957 pOffsetCfg Pointer to Iqn2Fl_RadtOffsetCfg
959 @endverbatim
960 *
961 * <b> Return Value </b> Iqn2Fl_Status
962 *
963 * <b> Pre Condition </b>
964 * @n Iqn2Fl_init(), Iqn2Fl_open()
965 *
966 * <b> Post Condition </b>
967 * @n None
968 *
969 * @b Writes
970 * @n AID2_UAT_EGR_RADT_OFFSET_CFG
971 *
972 * @b Example
973 * @verbatim
974 Iqn2Fl_setupAid2UatEgrRadtOffsetCfgRegs (hIqn2, &offset_cfg);
975 @endverbatim
976 * ===========================================================================
977 */
978 static inline
979 Iqn2Fl_Status Iqn2Fl_setupAid2UatEgrRadtOffsetCfgRegs(
980 Iqn2Fl_Handle hIqn2,
981 Iqn2Fl_RadtOffsetCfg *pOffsetCfg
982 )
983 {
984 uint32_t i = pOffsetCfg->radio_std;
986 /* Setup AID2 UAT EGR RADT - OFFSET CFG */
987 CSL_FINS(hIqn2->regs->Aid2.AID2_UAT_EGR_RADT[i].AID2_UAT_EGR_RADT_OFFSET_CFG,
988 IQN_AID2_AID2_UAT_EGR_RADT_OFFSET_CFG_VAL,
989 pOffsetCfg->offset);
991 return IQN2FL_SOK;
992 }
994 /** ============================================================================
995 * @n@b Iqn2Fl_setupAid2UatIngRadtOffsetCfgRegs
996 *
997 * @b Description
998 * @n IQN2 AID2 UAT Ingress Radio Timers offset configuration
999 *
1000 * @b Arguments
1001 * @verbatim
1003 hIqn2 Handle to the iqn2 instance
1004 pOffsetCfg Pointer to Iqn2Fl_RadtOffsetCfg
1006 @endverbatim
1007 *
1008 * <b> Return Value </b> Iqn2Fl_Status
1009 *
1010 * <b> Pre Condition </b>
1011 * @n Iqn2Fl_init(), Iqn2Fl_open()
1012 *
1013 * <b> Post Condition </b>
1014 * @n None
1015 *
1016 * @b Writes
1017 * @n AID2_UAT_ING_RADT_OFFSET_CFG
1018 *
1019 * @b Example
1020 * @verbatim
1021 Iqn2Fl_setupAid2UatIngRadtOffsetCfgRegs (hIqn2, &offset_cfg);
1022 @endverbatim
1023 * ===========================================================================
1024 */
1025 static inline
1026 Iqn2Fl_Status Iqn2Fl_setupAid2UatIngRadtOffsetCfgRegs(
1027 Iqn2Fl_Handle hIqn2,
1028 Iqn2Fl_RadtOffsetCfg *pOffsetCfg
1029 )
1030 {
1031 uint32_t i = pOffsetCfg->radio_std;
1033 /* Setup AID2 UAT ING RADT - OFFSET CFG */
1034 CSL_FINS(hIqn2->regs->Aid2.AID2_UAT_ING_RADT[i].AID2_UAT_ING_RADT_OFFSET_CFG,
1035 IQN_AID2_AID2_UAT_ING_RADT_OFFSET_CFG_VAL,
1036 pOffsetCfg->offset);
1038 return IQN2FL_SOK;
1039 }
1041 /** ============================================================================
1042 * @n@b Iqn2Fl_setupAid2UatGenCtlUatCfgRegs
1043 *
1044 * @b Description
1045 * @n IQN2 AID2 UAT GEN CTL UAT configuration registers setup
1046 *
1047 * @b Arguments
1048 * @verbatim
1050 hIqn2 Handle to the iqn2 instance
1051 pUatCfg Pointer to @a Iqn2Fl_UatCfg
1053 @endverbatim
1054 *
1055 * <b> Return Value </b> Iqn2Fl_Status
1056 *
1057 * <b> Pre Condition </b>
1058 * @n Iqn2Fl_init(), Iqn2Fl_open()
1059 *
1060 * <b> Post Condition </b>
1061 * @n None
1062 *
1063 * @b Writes
1064 * @n AID2_UAT_CFG
1065 *
1066 * @b Example
1067 * @verbatim
1068 Iqn2Fl_setupAid2UatGenCtlUatCfgRegs (hIqn2, &aid2_uat_cfg);
1069 @endverbatim
1070 * ===========================================================================
1071 */
1072 static inline
1073 Iqn2Fl_Status Iqn2Fl_setupAid2UatGenCtlUatCfgRegs(
1074 Iqn2Fl_Handle hIqn2,
1075 Iqn2Fl_UatCfg *pUatCfg
1076 )
1077 {
1078 uint32_t tempReg;
1080 tempReg = CSL_FMK(IQN_AID2_AID2_UAT_CFG_UAT_RUN,
1081 pUatCfg->uat_run) |
1082 CSL_FMK(IQN_AID2_AID2_UAT_CFG_DIAG_SYNC,
1083 pUatCfg->diag_sync);
1084 hIqn2->regs->Aid2.AID2_UAT_GEN_CTL.AID2_UAT_CFG = tempReg;
1086 return IQN2FL_SOK;
1087 }
1089 /** ============================================================================
1090 * @n@b Iqn2Fl_setupAid2UatRadtEvtRegs
1091 *
1092 * @b Description
1093 * @n IQN2 AID2 UAT RADT EVT registers setup per RADT (event num)
1094 *
1095 * @b Arguments
1096 * @verbatim
1098 hIqn2 Handle to the iqn2 instance
1099 pUatRadtEvtCfg Pointer containing "Setup" properties for IQN2.
1101 @endverbatim
1102 *
1103 * <b> Return Value </b> Iqn2Fl_Status
1104 *
1105 * <b> Pre Condition </b>
1106 * @n Iqn2Fl_init(), Iqn2Fl_open()
1107 *
1108 * <b> Post Condition </b>
1109 * @n None
1110 *
1111 * @b Writes
1112 * @n
1113 *
1114 * @b Example
1115 * @verbatim
1116 Iqn2Fl_setupAid2UatRadtEvtRegs (hIqn2, &uat_radt_evt_cfg);
1117 @endverbatim
1118 * ===========================================================================
1119 */
1120 static inline
1121 Iqn2Fl_Status Iqn2Fl_setupAid2UatRadtEvtRegs(
1122 Iqn2Fl_Handle hIqn2,
1123 Iqn2Fl_UatRadtEvtSetup *pUatRadtEvtCfg
1124 )
1125 {
1126 uint32_t i = pUatRadtEvtCfg->event_num;
1128 /* EVT RADT CMP CFG */
1129 CSL_FINS(hIqn2->regs->Aid2.AID2_UAT_RADT_EVT[i].AID2_UAT_EVT_RADT_CMP_CFG,
1130 IQN_AID2_AID2_UAT_EVT_RADT_CMP_CFG_VAL,
1131 pUatRadtEvtCfg->cmp_cfg_val);
1133 /* EVT CLK CNT TC CFG */
1134 CSL_FINS(hIqn2->regs->Aid2.AID2_UAT_RADT_EVT[i].AID2_UAT_EVT_CLK_CNT_TC_CFG,
1135 IQN_AID2_AID2_UAT_EVT_CLK_CNT_TC_CFG_VAL,
1136 pUatRadtEvtCfg->clk_cnt_tc);
1138 return IQN2FL_SOK;
1139 }
1141 /** ============================================================================
1142 * @n@b Iqn2Fl_updateEgressAid2RadioStandardTc
1143 *
1144 * @b Description
1145 * @n This functions updates the Radio Framing Sample Terminal Count Configuration Register for
1146 * for a symbol index of a radio standard id. Used for LTE to implement runtime updates required
1147 * by MBSFN implementation.
1148 *
1149 * @b Arguments
1150 * @verbatim
1152 hIqn2 Handle to the iqn2 instance
1153 radioStdId Radio Standard ID
1154 symbolSize New symbol size (sample count)
1155 symbolIndex Symbol index
1157 @endverbatim
1158 *
1159 * <b> Return Value </b> Iqn2Fl_Status
1160 *
1161 * <b> Pre Condition </b>
1162 * @n Iqn2Fl_init(), Iqn2Fl_open(), Iqn2Fl_hwSetup
1163 *
1164 * <b> Post Condition </b>
1165 * @n None
1166 *
1167 * @b Writes
1168 * @n AID2_IQ_EFE_FRM_SAMP_TC_CFG
1169 *
1170 * @b Example
1171 * @verbatim
1172 Iqn2Fl_updateEgressAid2RadioStandardTc (hIqn2, radioStdId, symbolSize, symbolIndex);
1173 @endverbatim
1174 * ===========================================================================
1175 */
1176 static inline
1177 Iqn2Fl_Status Iqn2Fl_updateEgressAid2RadioStandardTc(
1178 Iqn2Fl_Handle hIqn2,
1179 uint32_t radioStdId,
1180 uint32_t symbolSize,
1181 uint32_t symbolIndex
1182 )
1183 {
1184 uint32_t startIdx;
1186 startIdx = CSL_FEXT(hIqn2->regs->Aid2.AID2_SI_IQ_EFE_RADIO_STANDARD_GROUP.AID2_IQ_EFE_FRM_TC_CFG[radioStdId],IQN_AID2_AID2_IQ_EFE_FRM_TC_CFG_INDEX_SC);
1187 CSL_FINS(hIqn2->regs->Aid2.AID2_IQ_EFE_FRM_SAMP_TC_MMR_RAM[startIdx+symbolIndex].AID2_IQ_EFE_FRM_SAMP_TC_CFG, IQN_AID2_AID2_IQ_EFE_FRM_SAMP_TC_CFG_SAMP_TC, symbolSize);
1189 return IQN2FL_SOK;
1190 }
1192 /** ============================================================================
1193 * @n@b Iqn2Fl_setupDio2UatEgrRadtOffsetCfgRegs
1194 *
1195 * @b Description
1196 * @n IQN2 DIO2 UAT Egress Radio Timers offset configuration
1197 *
1198 * @b Arguments
1199 * @verbatim
1201 hIqn2 Handle to the iqn2 instance
1202 pOffsetCfg Pointer to Iqn2Fl_RadtOffsetCfg
1204 @endverbatim
1205 *
1206 * <b> Return Value </b> Iqn2Fl_Status
1207 *
1208 * <b> Pre Condition </b>
1209 * @n Iqn2Fl_init(), Iqn2Fl_open()
1210 *
1211 * <b> Post Condition </b>
1212 * @n None
1213 *
1214 * @b Writes
1215 * @n DIO2_UAT_EGR_RADT_OFFSET_CFG
1216 *
1217 * @b Example
1218 * @verbatim
1219 Iqn2Fl_setupDio2UatEgrRadtOffsetCfgRegs (hIqn2, &offset_cfg);
1220 @endverbatim
1221 * ===========================================================================
1222 */
1223 static inline
1224 Iqn2Fl_Status Iqn2Fl_setupDio2UatEgrRadtOffsetCfgRegs(
1225 Iqn2Fl_Handle hIqn2,
1226 Iqn2Fl_RadtOffsetCfg *pOffsetCfg
1227 )
1228 {
1229 uint32_t i = pOffsetCfg->radio_std;
1231 /* Setup DIO2 UAT EGR RADT - OFFSET CFG */
1232 CSL_FINS(hIqn2->regs->Dio2.DIO2_UAT_EGR_RADT[i].DIO2_UAT_EGR_RADT_OFFSET_CFG,
1233 IQN_DIO2_DIO2_UAT_EGR_RADT_OFFSET_CFG_VAL,
1234 pOffsetCfg->offset);
1236 return IQN2FL_SOK;
1237 }
1239 /** ============================================================================
1240 * @n@b Iqn2Fl_setupDio2UatIngRadtOffsetCfgRegs
1241 *
1242 * @b Description
1243 * @n IQN2 DIO2 UAT Ingress Radio Timers offset configuration
1244 *
1245 * @b Arguments
1246 * @verbatim
1248 hIqn2 Handle to the iqn2 instance
1249 pOffsetCfg Pointer to Iqn2Fl_RadtOffsetCfg
1251 @endverbatim
1252 *
1253 * <b> Return Value </b> Iqn2Fl_Status
1254 *
1255 * <b> Pre Condition </b>
1256 * @n Iqn2Fl_init(), Iqn2Fl_open()
1257 *
1258 * <b> Post Condition </b>
1259 * @n None
1260 *
1261 * @b Writes
1262 * @n DIO2_UAT_ING_RADT_OFFSET_CFG
1263 *
1264 * @b Example
1265 * @verbatim
1266 Iqn2Fl_setupDio2UatIngRadtOffsetCfgRegs (hIqn2, &offset_cfg);
1267 @endverbatim
1268 * ===========================================================================
1269 */
1270 static inline
1271 Iqn2Fl_Status Iqn2Fl_setupDio2UatIngRadtOffsetCfgRegs(
1272 Iqn2Fl_Handle hIqn2,
1273 Iqn2Fl_RadtOffsetCfg *pOffsetCfg
1274 )
1275 {
1276 uint32_t i = pOffsetCfg->radio_std;
1278 /* Setup DIO2 UAT ING RADT - OFFSET CFG */
1279 CSL_FINS(hIqn2->regs->Dio2.DIO2_UAT_ING_RADT[i].DIO2_UAT_ING_RADT_OFFSET_CFG,
1280 IQN_DIO2_DIO2_UAT_ING_RADT_OFFSET_CFG_VAL,
1281 pOffsetCfg->offset);
1283 return IQN2FL_SOK;
1284 }
1286 /** ============================================================================
1287 * @n@b Iqn2Fl_setupDio2UatRadtEvtRegs
1288 *
1289 * @b Description
1290 * @n IQN2 DIO2 UAT RADT EVT registers setup per RADT (event num)
1291 *
1292 * @b Arguments
1293 * @verbatim
1295 hIqn2 Handle to the iqn2 instance
1296 pUatRadtEvtCfg Pointer containing "Setup" properties for IQN2.
1298 @endverbatim
1299 *
1300 * <b> Return Value </b> Iqn2Fl_Status
1301 *
1302 * <b> Pre Condition </b>
1303 * @n Iqn2Fl_init(), Iqn2Fl_open()
1304 *
1305 * <b> Post Condition </b>
1306 * @n None
1307 *
1308 * @b Writes
1309 * @n
1310 *
1311 * @b Example
1312 * @verbatim
1313 Iqn2Fl_setupDio2UatRadtEvtRegs (hIqn2, &uat_radt_evt_cfg);
1314 @endverbatim
1315 * ===========================================================================
1316 */
1317 static inline
1318 Iqn2Fl_Status Iqn2Fl_setupDio2UatRadtEvtRegs(
1319 Iqn2Fl_Handle hIqn2,
1320 Iqn2Fl_UatRadtEvtSetup *pUatRadtEvtCfg
1321 )
1322 {
1323 uint32_t i = pUatRadtEvtCfg->event_num;
1325 /* EVT RADT CMP CFG */
1326 CSL_FINS(hIqn2->regs->Dio2.DIO2_UAT_RADT_EVT[i].DIO2_UAT_EVT_RADT_CMP_CFG,
1327 IQN_DIO2_DIO2_UAT_EVT_RADT_CMP_CFG_VAL,
1328 pUatRadtEvtCfg->cmp_cfg_val);
1330 /* EVT CLK CNT TC CFG */
1331 CSL_FINS(hIqn2->regs->Dio2.DIO2_UAT_RADT_EVT[i].DIO2_UAT_EVT_CLK_CNT_TC_CFG,
1332 IQN_DIO2_DIO2_UAT_EVT_CLK_CNT_TC_CFG_VAL,
1333 pUatRadtEvtCfg->clk_cnt_tc);
1335 return IQN2FL_SOK;
1336 }
1338 /** ============================================================================
1339 * @n@b Iqn2Fl_setupDio2UatDioEgrRadtOffsetCfgRegs
1340 *
1341 * @b Description
1342 * @n IQN2 DIO2 UAT DIO2 Egress Radio Timers offset configuration
1343 *
1344 * @b Arguments
1345 * @verbatim
1347 hIqn2 Handle to the iqn2 instance
1348 pOffsetCfg Pointer to Iqn2Fl_RadtOffsetCfg
1350 @endverbatim
1351 *
1352 * <b> Return Value </b> Iqn2Fl_Status
1353 *
1354 * <b> Pre Condition </b>
1355 * @n Iqn2Fl_init(), Iqn2Fl_open()
1356 *
1357 * <b> Post Condition </b>
1358 * @n None
1359 *
1360 * @b Writes
1361 * @n DIO2_UAT_DIO_EGR_RADT_OFFSET_CFG
1362 *
1363 * @b Example
1364 * @verbatim
1365 Iqn2Fl_setupDio2UatDioEgrRadtOffsetCfgRegs (hIqn2, &offset_cfg);
1366 @endverbatim
1367 * ===========================================================================
1368 */
1369 static inline
1370 Iqn2Fl_Status Iqn2Fl_setupDio2UatDioEgrRadtOffsetCfgRegs(
1371 Iqn2Fl_Handle hIqn2,
1372 Iqn2Fl_RadtOffsetCfg *pOffsetCfg
1373 )
1374 {
1375 uint32_t i = pOffsetCfg->radio_std;
1377 /* Setup DIO2 UAT DIO EGR RADT - OFFSET CFG */
1378 CSL_FINS(hIqn2->regs->Dio2.DIO2_UAT_DIO_EGR_RADT[i].DIO2_UAT_DIO_EGR_RADT_OFFSET_CFG,
1379 IQN_DIO2_DIO2_UAT_DIO_EGR_RADT_OFFSET_CFG_VAL,
1380 pOffsetCfg->offset);
1382 return IQN2FL_SOK;
1383 }
1385 /** ============================================================================
1386 * @n@b Iqn2Fl_setupDio2UatDioIngRadtOffsetCfgRegs
1387 *
1388 * @b Description
1389 * @n IQN2 DIO2 UAT DIO2 Ingress Radio Timers offset configuration
1390 *
1391 * @b Arguments
1392 * @verbatim
1394 hIqn2 Handle to the iqn2 instance
1395 pOffsetCfg Pointer to Iqn2Fl_RadtOffsetCfg
1397 @endverbatim
1398 *
1399 * <b> Return Value </b> Iqn2Fl_Status
1400 *
1401 * <b> Pre Condition </b>
1402 * @n Iqn2Fl_init(), Iqn2Fl_open()
1403 *
1404 * <b> Post Condition </b>
1405 * @n None
1406 *
1407 * @b Writes
1408 * @n DIO2_UAT_DIO_ING_RADT_OFFSET_CFG
1409 *
1410 * @b Example
1411 * @verbatim
1412 Iqn2Fl_setupDio2UatDioIngRadtOffsetCfgRegs (hIqn2, &offset_cfg);
1413 @endverbatim
1414 * ===========================================================================
1415 */
1416 static inline
1417 Iqn2Fl_Status Iqn2Fl_setupDio2UatDioIngRadtOffsetCfgRegs(
1418 Iqn2Fl_Handle hIqn2,
1419 Iqn2Fl_RadtOffsetCfg *pOffsetCfg
1420 )
1421 {
1422 uint32_t i = pOffsetCfg->radio_std;
1424 /* Setup DIO2 UAT DIO ING RADT - OFFSET CFG */
1425 CSL_FINS(hIqn2->regs->Dio2.DIO2_UAT_DIO_ING_RADT[i].DIO2_UAT_DIO_ING_RADT_OFFSET_CFG,
1426 IQN_DIO2_DIO2_UAT_DIO_ING_RADT_OFFSET_CFG_VAL,
1427 pOffsetCfg->offset);
1429 return IQN2FL_SOK;
1430 }
1432 /** ============================================================================
1433 * @n@b Iqn2Fl_setupDio2UatGenCtlUatCfgRegs
1434 *
1435 * @b Description
1436 * @n IQN2 DIO2 UAT GEN CTL UAT configuration registers setup
1437 *
1438 * @b Arguments
1439 * @verbatim
1441 hIqn2 Handle to the iqn2 instance
1442 pUatCfg Pointer to @a Iqn2Fl_UatCfg
1444 @endverbatim
1445 *
1446 * <b> Return Value </b> Iqn2Fl_Status
1447 *
1448 * <b> Pre Condition </b>
1449 * @n Iqn2Fl_init(), Iqn2Fl_open()
1450 *
1451 * <b> Post Condition </b>
1452 * @n None
1453 *
1454 * @b Writes
1455 * @n DIO2_UAT_CFG
1456 *
1457 * @b Example
1458 * @verbatim
1459 Iqn2Fl_setupDio2UatGenCtlUatCfgRegs (hIqn2, &dio2_uat_cfg);
1460 @endverbatim
1461 * ===========================================================================
1462 */
1463 static inline
1464 Iqn2Fl_Status Iqn2Fl_setupDio2UatGenCtlUatCfgRegs(
1465 Iqn2Fl_Handle hIqn2,
1466 Iqn2Fl_UatCfg *pUatCfg
1467 )
1468 {
1469 uint32_t tempReg;
1471 tempReg = CSL_FMK(IQN_DIO2_DIO2_UAT_CFG_UAT_RUN,
1472 pUatCfg->uat_run) |
1473 CSL_FMK(IQN_DIO2_DIO2_UAT_CFG_DIAG_SYNC,
1474 pUatCfg->diag_sync);
1475 hIqn2->regs->Dio2.DIO2_UAT_GEN_CTL.DIO2_UAT_CFG = tempReg;
1477 return IQN2FL_SOK;
1478 }
1480 /** ============================================================================
1481 * @n@b Iqn2Fl_setupDio2CoreIngDmaCfg0Regs
1482 *
1483 * @b Description
1484 * @n DIO2 CORE INGRESS - I DMA CFG0 setup
1485 *
1486 * @b Arguments
1487 * @verbatim
1489 hIqn2 Handle to the iqn2 instance
1490 pDio2CoreDmaCfg0 Pointer containing "Setup" properties for IQN2.
1492 @endverbatim
1493 *
1494 * <b> Return Value </b> Iqn2Fl_Status
1495 *
1496 * <b> Pre Condition </b>
1497 * @n Iqn2Fl_init(), Iqn2Fl_open()
1498 *
1499 * <b> Post Condition </b>
1500 * @n None
1501 *
1502 * @b Writes
1503 * @n DIO2_CORE_INGRESS
1504 *
1505 * @b Example
1506 * @verbatim
1507 Iqn2Fl_setupDio2CoreIngDmaCfg0Regs (hIqn2, &dio2_core_ing_dma_cfg0[0]);
1508 @endverbatim
1509 * ===========================================================================
1510 */
1511 static inline
1512 Iqn2Fl_Status Iqn2Fl_setupDio2CoreIngDmaCfg0Regs(
1513 Iqn2Fl_Handle hIqn2,
1514 Iqn2Fl_Dio2CoreDmaCfg0 *pDio2CoreDmaCfg0
1515 )
1516 {
1517 uint32_t tempReg, i;
1519 /* Setup DIO2 CORE INGRESS - I DMA CFG0 */
1520 for (i = 0; i < 3; i++)
1521 {
1522 tempReg = CSL_FMK(IQN_DIO2_DIO2_I_DMA_CFG0_DMA_BRST_LN,
1523 pDio2CoreDmaCfg0[i].dma_brst_ln) |
1524 CSL_FMK(IQN_DIO2_DIO2_I_DMA_CFG0_DMA_NUM_QWD,
1525 pDio2CoreDmaCfg0[i].dma_num_qwd) |
1526 CSL_FMK(IQN_DIO2_DIO2_I_DMA_CFG0_RSA_CNVRT_EN,
1527 pDio2CoreDmaCfg0[i].rsa_cnvrt_en) |
1528 CSL_FMK(IQN_DIO2_DIO2_I_DMA_CFG0_DMA_ENG_EN,
1529 pDio2CoreDmaCfg0[i].dma_eng_en) |
1530 CSL_FMK(IQN_DIO2_DIO2_I_DMA_CFG0_DMA_NUM_BLKS,
1531 pDio2CoreDmaCfg0[i].dma_num_blks);
1532 hIqn2->regs->Dio2.DIO2_CORE_INGRESS[i].DIO2_I_DMA_CFG0 = tempReg;
1533 }
1535 return IQN2FL_SOK;
1536 }
1538 /** ============================================================================
1539 * @n@b Iqn2Fl_setupDio2CoreIngressRegs
1540 *
1541 * @b Description
1542 * @n IQN2 DIO2 CORE INGRESS registers setup
1543 *
1544 * @b Arguments
1545 * @verbatim
1547 hIqn2 Handle to the iqn2 instance
1548 pDio2CoreIngress Pointer containing "Setup" properties for IQN2.
1550 @endverbatim
1551 *
1552 * <b> Return Value </b> Iqn2Fl_Status
1553 *
1554 * <b> Pre Condition </b>
1555 * @n Iqn2Fl_init(), Iqn2Fl_open()
1556 *
1557 * <b> Post Condition </b>
1558 * @n None
1559 *
1560 * @b Writes
1561 * @n DIO2_CORE_INGRESS
1562 *
1563 * @b Example
1564 * @verbatim
1565 Iqn2Fl_setupDio2CoreIngressRegs (hIqn2, &dio2_core_ing);
1566 @endverbatim
1567 * ===========================================================================
1568 */
1569 static inline
1570 Iqn2Fl_Status Iqn2Fl_setupDio2CoreIngressRegs(
1571 Iqn2Fl_Handle hIqn2,
1572 Iqn2Fl_Dio2CoreIngressSetup *pDio2CoreIngress
1573 )
1574 {
1575 uint32_t i, tempReg;
1577 /* Setup DIO2 CORE INGRESS - I TABLE SEL CFG */
1578 for (i = 0; i < 3; i++)
1579 {
1580 tempReg = CSL_FMK(IQN_DIO2_DIO2_I_TABLE_SEL_CFG_BCN_TABLE_SEL,
1581 pDio2CoreIngress->bcn_table_sel[i]) |
1582 CSL_FMK(IQN_DIO2_DIO2_I_TABLE_SEL_CFG_DMA_NUM_AXC,
1583 pDio2CoreIngress->dma_num_axc[i]);
1584 hIqn2->regs->Dio2.DIO2_CORE_INGRESS[i].DIO2_I_TABLE_SEL_CFG = tempReg;
1585 }
1587 /* Setup DIO2 CORE INGRESS - I DMA CFG0 */
1588 Iqn2Fl_setupDio2CoreIngDmaCfg0Regs (hIqn2, &(pDio2CoreIngress->dma_cfg0[0]));
1590 /* Setup DIO2 CORE INGRESS - I DMA CFG1 */
1591 for (i = 0; i < 3; i++)
1592 {
1593 CSL_FINS(hIqn2->regs->Dio2.DIO2_CORE_INGRESS[i].DIO2_I_DMA_CFG1,
1594 IQN_DIO2_DIO2_I_DMA_CFG1_DMA_BLK_ADDR_STRIDE,
1595 pDio2CoreIngress->dma_cfg1_dma_blk_addr_stride[i]);
1596 }
1598 return IQN2FL_SOK;
1599 }
1601 /** ============================================================================
1602 * @n@b Iqn2Fl_setupDio2CoreEgrDmaCfg0Regs
1603 *
1604 * @b Description
1605 * @n DIO2 CORE EGRESS - E DMA CFG0 setup
1606 *
1607 * @b Arguments
1608 * @verbatim
1610 hIqn2 Handle to the iqn2 instance
1611 pDio2CoreDmaCfg0 Pointer containing "Setup" properties for IQN2.
1613 @endverbatim
1614 *
1615 * <b> Return Value </b> Iqn2Fl_Status
1616 *
1617 * <b> Pre Condition </b>
1618 * @n Iqn2Fl_init(), Iqn2Fl_open()
1619 *
1620 * <b> Post Condition </b>
1621 * @n None
1622 *
1623 * @b Writes
1624 * @n DIO2_CORE_EGRESS
1625 *
1626 * @b Example
1627 * @verbatim
1628 Iqn2Fl_setupDio2CoreEgrDmaCfg0Regs (hIqn2, &dio2_core_egr_dma_cfg0[0]);
1629 @endverbatim
1630 * ===========================================================================
1631 */
1632 static inline
1633 Iqn2Fl_Status Iqn2Fl_setupDio2CoreEgrDmaCfg0Regs(
1634 Iqn2Fl_Handle hIqn2,
1635 Iqn2Fl_Dio2CoreDmaCfg0 *pDio2CoreDmaCfg0
1636 )
1637 {
1638 uint32_t tempReg, i;
1640 /* Setup DIO2 CORE EGRESS - E DMA CFG0 */
1641 for (i = 0; i < 3; i++)
1642 {
1643 tempReg = CSL_FMK(IQN_DIO2_DIO2_E_DMA_CFG0_DMA_BRST_LN,
1644 pDio2CoreDmaCfg0[i].dma_brst_ln) |
1645 CSL_FMK(IQN_DIO2_DIO2_E_DMA_CFG0_DMA_NUM_QWD,
1646 pDio2CoreDmaCfg0[i].dma_num_qwd) |
1647 CSL_FMK(IQN_DIO2_DIO2_E_DMA_CFG0_RSA_CNVRT_EN,
1648 pDio2CoreDmaCfg0[i].rsa_cnvrt_en) |
1649 CSL_FMK(IQN_DIO2_DIO2_E_DMA_CFG0_DMA_ENG_EN,
1650 pDio2CoreDmaCfg0[i].dma_eng_en) |
1651 CSL_FMK(IQN_DIO2_DIO2_E_DMA_CFG0_DMA_NUM_BLKS,
1652 pDio2CoreDmaCfg0[i].dma_num_blks);
1653 hIqn2->regs->Dio2.DIO2_CORE_EGRESS[i].DIO2_E_DMA_CFG0 = tempReg;
1654 }
1656 return IQN2FL_SOK;
1657 }
1659 /** ============================================================================
1660 * @n@b Iqn2Fl_setupDio2CoreEgressRegs
1661 *
1662 * @b Description
1663 * @n IQN2 DIO2 CORE EGRESS registers setup
1664 *
1665 * @b Arguments
1666 * @verbatim
1668 hIqn2 Handle to the iqn2 instance
1669 pDio2CoreEgress Pointer containing "Setup" properties for IQN2.
1671 @endverbatim
1672 *
1673 * <b> Return Value </b> Iqn2Fl_Status
1674 *
1675 * <b> Pre Condition </b>
1676 * @n Iqn2Fl_init(), Iqn2Fl_open()
1677 *
1678 * <b> Post Condition </b>
1679 * @n None
1680 *
1681 * @b Writes
1682 * @n DIO2_CORE_EGRESS
1683 *
1684 * @b Example
1685 * @verbatim
1686 Iqn2Fl_setupDio2CoreEgressRegs (hIqn2, &dio2_core_egr);
1687 @endverbatim
1688 * ===========================================================================
1689 */
1690 static inline
1691 Iqn2Fl_Status Iqn2Fl_setupDio2CoreEgressRegs(
1692 Iqn2Fl_Handle hIqn2,
1693 Iqn2Fl_Dio2CoreEgressSetup *pDio2CoreEgress
1694 )
1695 {
1696 uint32_t i, tempReg;
1698 /* Setup DIO2 CORE EGRESS - E TABLE SEL CFG */
1699 for (i = 0; i < 3; i++)
1700 {
1701 tempReg = CSL_FMK(IQN_DIO2_DIO2_E_TABLE_SEL_CFG_BCN_TABLE_SEL,
1702 pDio2CoreEgress->bcn_table_sel[i]) |
1703 CSL_FMK(IQN_DIO2_DIO2_E_TABLE_SEL_CFG_DMA_NUM_AXC,
1704 pDio2CoreEgress->dma_num_axc[i]);
1705 hIqn2->regs->Dio2.DIO2_CORE_EGRESS[i].DIO2_E_TABLE_SEL_CFG = tempReg;
1706 }
1708 /* Setup DIO2 CORE EGRESS - E DMA CFG0 */
1709 Iqn2Fl_setupDio2CoreEgrDmaCfg0Regs (hIqn2, &(pDio2CoreEgress->dma_cfg0[0]));
1711 /* Setup DIO2 CORE EGRESS - E DMA CFG1 */
1712 for (i = 0; i < 3; i++)
1713 {
1714 CSL_FINS(hIqn2->regs->Dio2.DIO2_CORE_EGRESS[i].DIO2_E_DMA_CFG1,
1715 IQN_DIO2_DIO2_E_DMA_CFG1_DMA_BLK_ADDR_STRIDE,
1716 pDio2CoreEgress->dma_cfg1_dma_blk_addr_stride[i]);
1717 }
1719 return IQN2FL_SOK;
1720 }
1722 /** ============================================================================
1723 * @n@b Iqn2Fl_setupDio2IngDbcntxRamMmrRegs
1724 *
1725 * @b Description
1726 * @n DIO2 I DBCNT0/1/2 RAM MMR setup
1727 *
1728 * @b Arguments
1729 * @verbatim
1731 hIqn2 Handle to the iqn2 instance
1732 eng_idx DIO engine number. Valid values 0 to 2.
1733 pDio2DbcntxRamMmr Pointer containing "Setup" properties for IQN2.
1735 @endverbatim
1736 *
1737 * <b> Return Value </b> Iqn2Fl_Status
1738 *
1739 * <b> Pre Condition </b>
1740 * @n Iqn2Fl_init(), Iqn2Fl_open()
1741 *
1742 * <b> Post Condition </b>
1743 * @n None
1744 *
1745 * @b Writes
1746 * @n DIO2_I_DBCNT0_RAM_MMR, DIO2_I_DBCNT1_RAM_MMR, DIO2_I_DBCNT2_RAM_MMR
1747 *
1748 * @b Example
1749 * @verbatim
1750 Iqn2Fl_setupDio2IngDbcntxRamMmrRegs (hIqn2, &dio2_i_dbcntx_ram_mmr[0]);
1751 @endverbatim
1752 * ===========================================================================
1753 */
1754 static inline
1755 Iqn2Fl_Status Iqn2Fl_setupDio2IngDbcntxRamMmrRegs(
1756 Iqn2Fl_Handle hIqn2,
1757 uint32_t eng_idx,
1758 Iqn2Fl_Dio2DbcntxRamMmr *pDio2DbcntxRamMmr
1759 )
1760 {
1761 uint32_t tempReg, i;
1763 if (eng_idx == 0)
1764 {
1765 /* Setup DIO2 I DBCNT0 RAM MMR */
1766 for (i = 0; i < 32; i++)
1767 {
1768 /* Setup DIO2 I TABLE0 BASE ADDR CFG */
1769 CSL_FINS(hIqn2->regs->Dio2.DIO2_I_DBCNT0_RAM_MMR[i].DIO2_I_TABLE0_BASE_ADDR_CFG,
1770 IQN_DIO2_DIO2_I_TABLE0_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
1771 pDio2DbcntxRamMmr->dma_vbus_base_addr_axc[i]);
1773 /* Setup DIO2 I TABLE0 CTRL CFG */
1774 tempReg = CSL_FMK(IQN_DIO2_DIO2_I_TABLE0_CTRL_CFG_CH_ID,
1775 pDio2DbcntxRamMmr->ch_id[i]) |
1776 CSL_FMK(IQN_DIO2_DIO2_I_TABLE0_CTRL_CFG_CH_EN,
1777 pDio2DbcntxRamMmr->ch_en[i]);
1778 hIqn2->regs->Dio2.DIO2_I_DBCNT0_RAM_MMR[i].DIO2_I_TABLE0_CTRL_CFG = tempReg;
1779 }
1780 }
1781 else if (eng_idx == 1)
1782 {
1783 /* Setup DIO2 I DBCNT1 RAM MMR */
1784 for (i = 0; i < 32; i++)
1785 {
1786 /* Setup DIO2 I TABLE1 BASE ADDR CFG */
1787 CSL_FINS(hIqn2->regs->Dio2.DIO2_I_DBCNT1_RAM_MMR[i].DIO2_I_TABLE1_BASE_ADDR_CFG,
1788 IQN_DIO2_DIO2_I_TABLE1_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
1789 pDio2DbcntxRamMmr->dma_vbus_base_addr_axc[i]);
1791 /* Setup DIO2 I TABLE1 CTRL CFG */
1792 tempReg = CSL_FMK(IQN_DIO2_DIO2_I_TABLE1_CTRL_CFG_CH_ID,
1793 pDio2DbcntxRamMmr->ch_id[i]) |
1794 CSL_FMK(IQN_DIO2_DIO2_I_TABLE1_CTRL_CFG_CH_EN,
1795 pDio2DbcntxRamMmr->ch_en[i]);
1796 hIqn2->regs->Dio2.DIO2_I_DBCNT1_RAM_MMR[i].DIO2_I_TABLE1_CTRL_CFG = tempReg;
1797 }
1798 }
1799 else if (eng_idx == 2)
1800 {
1801 /* Setup DIO2 I DBCNT2 RAM MMR */
1802 for (i = 0; i < 32; i++)
1803 {
1804 /* Setup DIO2 I TABLE2 BASE ADDR CFG */
1805 CSL_FINS(hIqn2->regs->Dio2.DIO2_I_DBCNT2_RAM_MMR[i].DIO2_I_TABLE2_BASE_ADDR_CFG,
1806 IQN_DIO2_DIO2_I_TABLE2_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
1807 pDio2DbcntxRamMmr->dma_vbus_base_addr_axc[i]);
1809 /* Setup DIO2 I TABLE2 CTRL CFG */
1810 tempReg = CSL_FMK(IQN_DIO2_DIO2_I_TABLE2_CTRL_CFG_CH_ID,
1811 pDio2DbcntxRamMmr->ch_id[i]) |
1812 CSL_FMK(IQN_DIO2_DIO2_I_TABLE2_CTRL_CFG_CH_EN,
1813 pDio2DbcntxRamMmr->ch_en[i]);
1814 hIqn2->regs->Dio2.DIO2_I_DBCNT2_RAM_MMR[i].DIO2_I_TABLE2_CTRL_CFG = tempReg;
1815 }
1816 }
1817 else
1818 {
1819 return IQN2FL_INVPARAMS;
1820 }
1822 return IQN2FL_SOK;
1823 }
1825 /** ============================================================================
1826 * @n@b Iqn2Fl_setupDio2EgrDbcntxRamMmrRegs
1827 *
1828 * @b Description
1829 * @n DIO2 E DBCNT0/1/2 RAM MMR setup
1830 *
1831 * @b Arguments
1832 * @verbatim
1834 hIqn2 Handle to the iqn2 instance
1835 eng_idx DIO engine number. Valid values 0 to 2.
1836 pDio2DbcntxRamMmr Pointer containing "Setup" properties for IQN2.
1838 @endverbatim
1839 *
1840 * <b> Return Value </b> Iqn2Fl_Status
1841 *
1842 * <b> Pre Condition </b>
1843 * @n Iqn2Fl_init(), Iqn2Fl_open()
1844 *
1845 * <b> Post Condition </b>
1846 * @n None
1847 *
1848 * @b Writes
1849 * @n DIO2_E_DBCNT0_RAM_MMR, DIO2_E_DBCNT1_RAM_MMR, DIO2_E_DBCNT2_RAM_MMR
1850 *
1851 * @b Example
1852 * @verbatim
1853 Iqn2Fl_setupDio2EgrDbcntxRamMmrRegs (hIqn2, &dio2_e_dbcntx_ram_mmr[0]);
1854 @endverbatim
1855 * ===========================================================================
1856 */
1857 static inline
1858 Iqn2Fl_Status Iqn2Fl_setupDio2EgrDbcntxRamMmrRegs(
1859 Iqn2Fl_Handle hIqn2,
1860 uint32_t eng_idx,
1861 Iqn2Fl_Dio2DbcntxRamMmr *pDio2DbcntxRamMmr
1862 )
1863 {
1864 uint32_t tempReg, i;
1866 if (eng_idx == 0)
1867 {
1868 /* Setup DIO2 E DBCNT0 RAM MMR */
1869 for (i = 0; i < 32; i++)
1870 {
1871 /* Setup DIO2 E TABLE0 BASE ADDR CFG */
1872 CSL_FINS(hIqn2->regs->Dio2.DIO2_E_DBCNT0_RAM_MMR[i].DIO2_E_TABLE0_BASE_ADDR_CFG,
1873 IQN_DIO2_DIO2_E_TABLE0_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
1874 pDio2DbcntxRamMmr->dma_vbus_base_addr_axc[i]);
1876 /* Setup DIO2 E TABLE0 CTRL CFG */
1877 tempReg = CSL_FMK(IQN_DIO2_DIO2_E_TABLE0_CTRL_CFG_CH_ID,
1878 pDio2DbcntxRamMmr->ch_id[i]) |
1879 CSL_FMK(IQN_DIO2_DIO2_E_TABLE0_CTRL_CFG_CH_EN,
1880 pDio2DbcntxRamMmr->ch_en[i]);
1881 hIqn2->regs->Dio2.DIO2_E_DBCNT0_RAM_MMR[i].DIO2_E_TABLE0_CTRL_CFG = tempReg;
1882 }
1883 }
1884 else if (eng_idx == 1)
1885 {
1886 /* Setup DIO2 E DBCNT1 RAM MMR */
1887 for (i = 0; i < 32; i++)
1888 {
1889 /* Setup DIO2 E TABLE1 BASE ADDR CFG */
1890 CSL_FINS(hIqn2->regs->Dio2.DIO2_E_DBCNT1_RAM_MMR[i].DIO2_E_TABLE1_BASE_ADDR_CFG,
1891 IQN_DIO2_DIO2_E_TABLE1_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
1892 pDio2DbcntxRamMmr->dma_vbus_base_addr_axc[i]);
1894 /* Setup DIO2 E TABLE1 CTRL CFG */
1895 tempReg = CSL_FMK(IQN_DIO2_DIO2_E_TABLE1_CTRL_CFG_CH_ID,
1896 pDio2DbcntxRamMmr->ch_id[i]) |
1897 CSL_FMK(IQN_DIO2_DIO2_E_TABLE1_CTRL_CFG_CH_EN,
1898 pDio2DbcntxRamMmr->ch_en[i]);
1899 hIqn2->regs->Dio2.DIO2_E_DBCNT1_RAM_MMR[i].DIO2_E_TABLE1_CTRL_CFG = tempReg;
1900 }
1901 }
1902 else if (eng_idx == 2)
1903 {
1904 /* Setup DIO2 E DBCNT2 RAM MMR */
1905 for (i = 0; i < 32; i++)
1906 {
1907 /* Setup DIO2 E TABLE2 BASE ADDR CFG */
1908 CSL_FINS(hIqn2->regs->Dio2.DIO2_E_DBCNT2_RAM_MMR[i].DIO2_E_TABLE2_BASE_ADDR_CFG,
1909 IQN_DIO2_DIO2_E_TABLE2_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
1910 pDio2DbcntxRamMmr->dma_vbus_base_addr_axc[i]);
1912 /* Setup DIO2 E TABLE2 CTRL CFG */
1913 tempReg = CSL_FMK(IQN_DIO2_DIO2_E_TABLE2_CTRL_CFG_CH_ID,
1914 pDio2DbcntxRamMmr->ch_id[i]) |
1915 CSL_FMK(IQN_DIO2_DIO2_E_TABLE2_CTRL_CFG_CH_EN,
1916 pDio2DbcntxRamMmr->ch_en[i]);
1917 hIqn2->regs->Dio2.DIO2_E_DBCNT2_RAM_MMR[i].DIO2_E_TABLE2_CTRL_CFG = tempReg;
1918 }
1919 }
1920 else
1921 {
1922 return IQN2FL_INVPARAMS;
1923 }
1925 return IQN2FL_SOK;
1926 }
1929 /** ============================================================================
1930 * @n@b Iqn2Fl_setupDio2ReconfigureEngine
1931 *
1932 * @b Description
1933 * @n In cases where:
1934 * - DIO parameters need to be adjusted by, for instance Physical Layer software
1935 * - IQN2 is configured via LLD from ARM Linux or any other software entity external to, for instance Physical layer software
1936 * IQN2 functional layer has dedicated hardware control commands and auxiliary APIs that can be used prior to enabling the AT2 events.
1937 * Iqn2Fl_setupDio2ReconfigureEngine() is an API that allows to reconfigure the following Egress/Ingress DIO parameters:
1938 * - num_block
1939 * - block_addr_stride
1940 * - axc_buffer_start_addr
1941 *
1942 * @b Arguments
1943 * @verbatim
1945 hIqn2 Handle to the iqn2 instance
1946 Iqn2Fl_Dio2ReconfigureEngineSetup Pointer containing "Iqn2Fl_Dio2ReconfigureEngineSetup" properties for DIO2.
1948 @endverbatim
1949 *
1950 * <b> Return Value </b> Iqn2Fl_Status
1951 *
1952 * <b> Pre Condition </b>
1953 * @n Iqn2Fl_init(), Iqn2Fl_open()
1954 *
1955 * <b> Post Condition </b>
1956 * @n None
1957 *
1958 * @b Writes
1959 * @n DIO2_RECONFIGURE_ENGINE
1960 *
1961 * @b Example
1962 * @verbatim
1963 Iqn2Fl_setupDio2ReconfigureEngine (hIqn2, &dio2_reconfigure_engine);
1964 @endverbatim
1965 * ===========================================================================
1966 */
1967 static inline
1968 Iqn2Fl_Status Iqn2Fl_setupDio2ReconfigureEngine(
1969 Iqn2Fl_Handle hIqn2,
1970 Iqn2Fl_Dio2ReconfigureEngineSetup *pDio2ReconfigureEngine
1971 )
1972 {
1973 uint32_t idx, i;
1975 idx = pDio2ReconfigureEngine->engine_idx;
1977 CSL_FINS(hIqn2->regs->Dio2.DIO2_CORE_EGRESS[idx].DIO2_E_DMA_CFG0,
1978 IQN_DIO2_DIO2_E_DMA_CFG0_DMA_NUM_BLKS,
1979 pDio2ReconfigureEngine->egress_num_block);
1981 CSL_FINS(hIqn2->regs->Dio2.DIO2_CORE_INGRESS[idx].DIO2_I_DMA_CFG0,
1982 IQN_DIO2_DIO2_I_DMA_CFG0_DMA_NUM_BLKS,
1983 pDio2ReconfigureEngine->ingress_num_block);
1985 CSL_FINS(hIqn2->regs->Dio2.DIO2_CORE_EGRESS[idx].DIO2_E_DMA_CFG1,
1986 IQN_DIO2_DIO2_E_DMA_CFG1_DMA_BLK_ADDR_STRIDE,
1987 pDio2ReconfigureEngine->egress_block_addr_stride);
1989 CSL_FINS(hIqn2->regs->Dio2.DIO2_CORE_INGRESS[idx].DIO2_I_DMA_CFG1,
1990 IQN_DIO2_DIO2_I_DMA_CFG1_DMA_BLK_ADDR_STRIDE,
1991 pDio2ReconfigureEngine->ingress_block_addr_stride);
1993 if(idx == 0)
1994 {
1995 for (i=0; i< 16; i++)
1996 {
1997 CSL_FINS(hIqn2->regs->Dio2.DIO2_E_DBCNT0_RAM_MMR[i].DIO2_E_TABLE0_BASE_ADDR_CFG,
1998 IQN_DIO2_DIO2_E_TABLE0_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
1999 pDio2ReconfigureEngine->egress_axc_buffer_start_addr[i]);
2001 CSL_FINS(hIqn2->regs->Dio2.DIO2_I_DBCNT0_RAM_MMR[i].DIO2_I_TABLE0_BASE_ADDR_CFG,
2002 IQN_DIO2_DIO2_I_TABLE0_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2003 pDio2ReconfigureEngine->ingress_axc_buffer_start_addr[i]);
2004 }
2005 } else if (idx == 1) {
2006 for (i=0; i< 16; i++)
2007 {
2008 CSL_FINS(hIqn2->regs->Dio2.DIO2_E_DBCNT1_RAM_MMR[i].DIO2_E_TABLE1_BASE_ADDR_CFG,
2009 IQN_DIO2_DIO2_E_TABLE1_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2010 pDio2ReconfigureEngine->egress_axc_buffer_start_addr[i]);
2012 CSL_FINS(hIqn2->regs->Dio2.DIO2_I_DBCNT1_RAM_MMR[i].DIO2_I_TABLE1_BASE_ADDR_CFG,
2013 IQN_DIO2_DIO2_I_TABLE1_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2014 pDio2ReconfigureEngine->ingress_axc_buffer_start_addr[i]);
2015 }
2016 } else if (idx == 2){
2017 for (i=0; i< 16; i++)
2018 {
2019 CSL_FINS(hIqn2->regs->Dio2.DIO2_E_DBCNT2_RAM_MMR[i].DIO2_E_TABLE2_BASE_ADDR_CFG,
2020 IQN_DIO2_DIO2_E_TABLE2_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2021 pDio2ReconfigureEngine->egress_axc_buffer_start_addr[i]);
2023 CSL_FINS(hIqn2->regs->Dio2.DIO2_I_DBCNT2_RAM_MMR[i].DIO2_I_TABLE2_BASE_ADDR_CFG,
2024 IQN_DIO2_DIO2_I_TABLE2_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2025 pDio2ReconfigureEngine->ingress_axc_buffer_start_addr[i]);
2026 }
2027 }
2029 return IQN2FL_SOK;
2030 } // Iqn2Fl_setupDio2ReconfigureEngine
2032 /** ============================================================================
2033 * @n@b Iqn2Fl_setupDio2ReconfigureEgressEngine
2034 *
2035 * @b Description
2036 * @n In cases where:
2037 * - DIO parameters need to be adjusted by, for instance Physical Layer software
2038 * - IQN2 is configured via LLD from ARM Linux or any other software entity external to, for instance Physical layer software
2039 * IQN2 functional layer has dedicated hardware control commands and auxiliary APIs that can be used prior to enabling the AT2 events.
2040 * Iqn2Fl_setupDio2ReconfigureEgressEngine() is an API that allows to reconfigure the following Egress DIO parameters.
2041 *
2042 * @b Arguments
2043 * @verbatim
2045 hIqn2 Handle to the iqn2 instance
2046 pDio2ReconfigureEgrEngine Pointer containing "Iqn2Fl_Dio2ReconfigureEgrEngineSetup" properties for IQN2.
2048 @endverbatim
2049 *
2050 * <b> Return Value </b> Iqn2Fl_Status
2051 *
2052 * <b> Pre Condition </b>
2053 * @n Iqn2Fl_init(), Iqn2Fl_open()
2054 *
2055 * <b> Post Condition </b>
2056 * @n None
2057 *
2058 * @b Writes
2059 * @n DIO2_CORE_EGRESS
2060 *
2061 * @b Example
2062 * @verbatim
2063 Iqn2Fl_setupDio2ReconfigureEgressEngine (hIqn2, &pDio2ReconfigureEgrEngine);
2064 @endverbatim
2065 * ===========================================================================
2066 */
2067 static inline
2068 Iqn2Fl_Status Iqn2Fl_setupDio2ReconfigureEgressEngine(
2069 Iqn2Fl_Handle hIqn2,
2070 Iqn2Fl_Dio2ReconfigureEgrEngineSetup *pDio2ReconfigureEgrEngine
2071 )
2072 {
2073 uint32_t tempReg;
2074 uint32_t idx, i;
2076 idx = pDio2ReconfigureEgrEngine->engine_idx;
2078 /* Setup DIO2 CORE EGRESS - E TABLE SEL CFG */
2079 tempReg = CSL_FMK(IQN_DIO2_DIO2_E_TABLE_SEL_CFG_BCN_TABLE_SEL,
2080 pDio2ReconfigureEgrEngine->bcn_table_sel) |
2081 CSL_FMK(IQN_DIO2_DIO2_E_TABLE_SEL_CFG_DMA_NUM_AXC,
2082 pDio2ReconfigureEgrEngine->dma_num_axc);
2083 hIqn2->regs->Dio2.DIO2_CORE_EGRESS[idx].DIO2_E_TABLE_SEL_CFG = tempReg;
2085 /* Setup DIO2 CORE EGRESS - E DMA CFG0 */
2086 tempReg = CSL_FMK(IQN_DIO2_DIO2_E_DMA_CFG0_DMA_BRST_LN,
2087 pDio2ReconfigureEgrEngine->dma_cfg0.dma_brst_ln) |
2088 CSL_FMK(IQN_DIO2_DIO2_E_DMA_CFG0_DMA_NUM_QWD,
2089 pDio2ReconfigureEgrEngine->dma_cfg0.dma_num_qwd) |
2090 CSL_FMK(IQN_DIO2_DIO2_E_DMA_CFG0_RSA_CNVRT_EN,
2091 pDio2ReconfigureEgrEngine->dma_cfg0.rsa_cnvrt_en) |
2092 CSL_FMK(IQN_DIO2_DIO2_E_DMA_CFG0_DMA_ENG_EN,
2093 pDio2ReconfigureEgrEngine->dma_cfg0.dma_eng_en) |
2094 CSL_FMK(IQN_DIO2_DIO2_E_DMA_CFG0_DMA_NUM_BLKS,
2095 pDio2ReconfigureEgrEngine->dma_cfg0.dma_num_blks);
2096 hIqn2->regs->Dio2.DIO2_CORE_EGRESS[idx].DIO2_E_DMA_CFG0 = tempReg;
2098 /* Setup DIO2 CORE EGRESS - E DMA CFG1 */
2099 CSL_FINS(hIqn2->regs->Dio2.DIO2_CORE_EGRESS[idx].DIO2_E_DMA_CFG1,
2100 IQN_DIO2_DIO2_E_DMA_CFG1_DMA_BLK_ADDR_STRIDE,
2101 pDio2ReconfigureEgrEngine->dma_cfg1_dma_blk_addr_stride);
2103 if(idx == 0)
2104 {
2105 for (i=(0 + (16*pDio2ReconfigureEgrEngine->bcn_table_sel)); i< (16 + (16*pDio2ReconfigureEgrEngine->bcn_table_sel)); i++)
2106 {
2107 CSL_FINS(hIqn2->regs->Dio2.DIO2_E_DBCNT0_RAM_MMR[i].DIO2_E_TABLE0_BASE_ADDR_CFG,
2108 IQN_DIO2_DIO2_E_TABLE0_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2109 pDio2ReconfigureEgrEngine->axc_buffer_start_addr[i]);
2111 tempReg = CSL_FMK(IQN_DIO2_DIO2_E_TABLE0_CTRL_CFG_CH_ID,
2112 pDio2ReconfigureEgrEngine->ch_id[i]) |
2113 CSL_FMK(IQN_DIO2_DIO2_E_TABLE0_CTRL_CFG_CH_EN,
2114 pDio2ReconfigureEgrEngine->ch_en[i]);
2115 hIqn2->regs->Dio2.DIO2_E_DBCNT0_RAM_MMR[i].DIO2_E_TABLE0_CTRL_CFG = tempReg;
2116 }
2117 } else if (idx == 1) {
2118 for (i=(0 + (16*pDio2ReconfigureEgrEngine->bcn_table_sel)); i< (16 + (16*pDio2ReconfigureEgrEngine->bcn_table_sel)); i++)
2119 {
2120 CSL_FINS(hIqn2->regs->Dio2.DIO2_E_DBCNT1_RAM_MMR[i].DIO2_E_TABLE1_BASE_ADDR_CFG,
2121 IQN_DIO2_DIO2_E_TABLE1_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2122 pDio2ReconfigureEgrEngine->axc_buffer_start_addr[i]);
2124 tempReg = CSL_FMK(IQN_DIO2_DIO2_E_TABLE1_CTRL_CFG_CH_ID,
2125 pDio2ReconfigureEgrEngine->ch_id[i]) |
2126 CSL_FMK(IQN_DIO2_DIO2_E_TABLE1_CTRL_CFG_CH_EN,
2127 pDio2ReconfigureEgrEngine->ch_en[i]);
2128 hIqn2->regs->Dio2.DIO2_E_DBCNT1_RAM_MMR[i].DIO2_E_TABLE1_CTRL_CFG = tempReg;
2129 }
2130 } else if (idx == 2){
2131 for (i=(0 + (16*pDio2ReconfigureEgrEngine->bcn_table_sel)); i< (16 + (16*pDio2ReconfigureEgrEngine->bcn_table_sel)); i++)
2132 {
2133 CSL_FINS(hIqn2->regs->Dio2.DIO2_E_DBCNT2_RAM_MMR[i].DIO2_E_TABLE2_BASE_ADDR_CFG,
2134 IQN_DIO2_DIO2_E_TABLE2_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2135 pDio2ReconfigureEgrEngine->axc_buffer_start_addr[i]);
2137 tempReg = CSL_FMK(IQN_DIO2_DIO2_E_TABLE2_CTRL_CFG_CH_ID,
2138 pDio2ReconfigureEgrEngine->ch_id[i]) |
2139 CSL_FMK(IQN_DIO2_DIO2_E_TABLE2_CTRL_CFG_CH_EN,
2140 pDio2ReconfigureEgrEngine->ch_en[i]);
2141 hIqn2->regs->Dio2.DIO2_E_DBCNT2_RAM_MMR[i].DIO2_E_TABLE2_CTRL_CFG = tempReg;
2142 }
2143 }
2145 return IQN2FL_SOK;
2146 }
2148 /** ============================================================================
2149 * @n@b Iqn2Fl_setupDio2ReconfigureIngressEngine
2150 *
2151 * @b Description
2152 * @n In cases where:
2153 * - DIO parameters need to be adjusted by, for instance Physical Layer software
2154 * - IQN2 is configured via LLD from ARM Linux or any other software entity external to, for instance Physical layer software
2155 * IQN2 functional layer has dedicated hardware control commands and auxiliary APIs that can be used prior to enabling the AT2 events.
2156 * Iqn2Fl_setupDio2ReconfigureIngressEngine() is an API that allows to reconfigure the following Ingress DIO parameters.
2157 *
2158 * @b Arguments
2159 * @verbatim
2161 hIqn2 Handle to the iqn2 instance
2162 pDio2ReconfigureEgrEngine Pointer containing "Iqn2Fl_Dio2ReconfigureEgrEngineSetup" properties for IQN2.
2164 @endverbatim
2165 *
2166 * <b> Return Value </b> Iqn2Fl_Status
2167 *
2168 * <b> Pre Condition </b>
2169 * @n Iqn2Fl_init(), Iqn2Fl_open()
2170 *
2171 * <b> Post Condition </b>
2172 * @n None
2173 *
2174 * @b Writes
2175 * @n DIO2_CORE_INGRESS
2176 *
2177 * @b Example
2178 * @verbatim
2179 Iqn2Fl_setupDio2ReconfigureIngressEngine (hIqn2, &pDio2ReconfigureEgrEngine);
2180 @endverbatim
2181 * ===========================================================================
2182 */
2183 static inline
2184 Iqn2Fl_Status Iqn2Fl_setupDio2ReconfigureIngressEngine(
2185 Iqn2Fl_Handle hIqn2,
2186 Iqn2Fl_Dio2ReconfigureIngrEngineSetup *pDio2ReconfigureIngrEngine
2187 )
2188 {
2189 uint32_t tempReg;
2190 uint32_t idx, i;
2192 idx = pDio2ReconfigureIngrEngine->engine_idx;
2194 /* Setup DIO2 CORE INGRESS - E TABLE SEL CFG */
2195 tempReg = CSL_FMK(IQN_DIO2_DIO2_I_TABLE_SEL_CFG_BCN_TABLE_SEL,
2196 pDio2ReconfigureIngrEngine->bcn_table_sel) |
2197 CSL_FMK(IQN_DIO2_DIO2_I_TABLE_SEL_CFG_DMA_NUM_AXC,
2198 pDio2ReconfigureIngrEngine->dma_num_axc);
2199 hIqn2->regs->Dio2.DIO2_CORE_INGRESS[idx].DIO2_I_TABLE_SEL_CFG = tempReg;
2201 /* Setup DIO2 CORE INGRESS - E DMA CFG0 */
2202 tempReg = CSL_FMK(IQN_DIO2_DIO2_I_DMA_CFG0_DMA_BRST_LN,
2203 pDio2ReconfigureIngrEngine->dma_cfg0.dma_brst_ln) |
2204 CSL_FMK(IQN_DIO2_DIO2_I_DMA_CFG0_DMA_NUM_QWD,
2205 pDio2ReconfigureIngrEngine->dma_cfg0.dma_num_qwd) |
2206 CSL_FMK(IQN_DIO2_DIO2_I_DMA_CFG0_RSA_CNVRT_EN,
2207 pDio2ReconfigureIngrEngine->dma_cfg0.rsa_cnvrt_en) |
2208 CSL_FMK(IQN_DIO2_DIO2_I_DMA_CFG0_DMA_ENG_EN,
2209 pDio2ReconfigureIngrEngine->dma_cfg0.dma_eng_en) |
2210 CSL_FMK(IQN_DIO2_DIO2_I_DMA_CFG0_DMA_NUM_BLKS,
2211 pDio2ReconfigureIngrEngine->dma_cfg0.dma_num_blks);
2212 hIqn2->regs->Dio2.DIO2_CORE_INGRESS[idx].DIO2_I_DMA_CFG0 = tempReg;
2214 /* Setup DIO2 CORE INGRESS - E DMA CFG1 */
2215 CSL_FINS(hIqn2->regs->Dio2.DIO2_CORE_INGRESS[idx].DIO2_I_DMA_CFG1,
2216 IQN_DIO2_DIO2_I_DMA_CFG1_DMA_BLK_ADDR_STRIDE,
2217 pDio2ReconfigureIngrEngine->dma_cfg1_dma_blk_addr_stride);
2219 if(idx == 0)
2220 {
2221 for (i=(0 + (16*pDio2ReconfigureIngrEngine->bcn_table_sel)); i< (16 + (16*pDio2ReconfigureIngrEngine->bcn_table_sel)); i++)
2222 {
2223 CSL_FINS(hIqn2->regs->Dio2.DIO2_I_DBCNT0_RAM_MMR[i].DIO2_I_TABLE0_BASE_ADDR_CFG,
2224 IQN_DIO2_DIO2_I_TABLE0_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2225 pDio2ReconfigureIngrEngine->axc_buffer_start_addr[i]);
2227 tempReg = CSL_FMK(IQN_DIO2_DIO2_I_TABLE0_CTRL_CFG_CH_ID,
2228 pDio2ReconfigureIngrEngine->ch_id[i]) |
2229 CSL_FMK(IQN_DIO2_DIO2_I_TABLE0_CTRL_CFG_CH_EN,
2230 pDio2ReconfigureIngrEngine->ch_en[i]);
2231 hIqn2->regs->Dio2.DIO2_I_DBCNT0_RAM_MMR[i].DIO2_I_TABLE0_CTRL_CFG = tempReg;
2232 }
2233 } else if (idx == 1) {
2234 for (i=(0 + (16*pDio2ReconfigureIngrEngine->bcn_table_sel)); i< (16 + (16*pDio2ReconfigureIngrEngine->bcn_table_sel)); i++)
2235 {
2236 CSL_FINS(hIqn2->regs->Dio2.DIO2_I_DBCNT1_RAM_MMR[i].DIO2_I_TABLE1_BASE_ADDR_CFG,
2237 IQN_DIO2_DIO2_I_TABLE1_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2238 pDio2ReconfigureIngrEngine->axc_buffer_start_addr[i]);
2240 tempReg = CSL_FMK(IQN_DIO2_DIO2_I_TABLE1_CTRL_CFG_CH_ID,
2241 pDio2ReconfigureIngrEngine->ch_id[i]) |
2242 CSL_FMK(IQN_DIO2_DIO2_I_TABLE1_CTRL_CFG_CH_EN,
2243 pDio2ReconfigureIngrEngine->ch_en[i]);
2244 hIqn2->regs->Dio2.DIO2_I_DBCNT1_RAM_MMR[i].DIO2_I_TABLE1_CTRL_CFG = tempReg;
2245 }
2246 } else if (idx == 2){
2247 for (i=(0 + (16*pDio2ReconfigureIngrEngine->bcn_table_sel)); i< (16 + (16*pDio2ReconfigureIngrEngine->bcn_table_sel)); i++)
2248 {
2249 CSL_FINS(hIqn2->regs->Dio2.DIO2_I_DBCNT2_RAM_MMR[i].DIO2_I_TABLE2_BASE_ADDR_CFG,
2250 IQN_DIO2_DIO2_I_TABLE2_BASE_ADDR_CFG_DMA_VBUS_BASE_ADDR_AXC,
2251 pDio2ReconfigureIngrEngine->axc_buffer_start_addr[i]);
2253 tempReg = CSL_FMK(IQN_DIO2_DIO2_I_TABLE2_CTRL_CFG_CH_ID,
2254 pDio2ReconfigureIngrEngine->ch_id[i]) |
2255 CSL_FMK(IQN_DIO2_DIO2_I_TABLE2_CTRL_CFG_CH_EN,
2256 pDio2ReconfigureIngrEngine->ch_en[i]);
2257 hIqn2->regs->Dio2.DIO2_I_DBCNT2_RAM_MMR[i].DIO2_I_TABLE2_CTRL_CFG = tempReg;
2258 }
2259 }
2261 return IQN2FL_SOK;
2262 }
2264 #ifdef __cplusplus
2265 }
2266 #endif
2268 #endif /* _IQN2FLHWCONTROLAUX_H_ */