36e4e45b894b412debfc09a34ea6e96fedd0a16c
[keystone-rtos/mcbsp-lld.git] / example / c6657 / MCBSPDigLpbk / sample_c6657_cfg.c
1 /*
2  * sample_galileo_cfg.c
3  *
4  * Platform specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES                     2u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS                                        1u
49 //const unsigned int numDsps = NUM_DSPS;
51 #define CGEM_REG_START                  (0x01800000)
54 extern cregister volatile unsigned int DNUM;
56 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
59 /* Determine the processor id by reading DNUM register. */
60 unsigned short determineProcId()
61         {
62         volatile unsigned int *addr;
63         unsigned int core_no;
65     /* Identify the core number */
66     addr = (unsigned int *)(CGEM_REG_START+0x40000);
67     core_no = ((*addr) & 0x000F0000)>>16;
69         return core_no;
70         }
72 signed char*  getGlobalAddr(signed char* addr)
73 {
74     if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
75     {
76         return (addr); /* The address is already a global address */
77     }
79     return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
80 }
81 /** Whether global configuration required for EDMA3 or not.
82  * This configuration should be done only once for the EDMA3 hardware by
83  * any one of the masters (i.e. DSPs).
84  * It can be changed depending on the use-case.
85  */
86 unsigned int gblCfgReqdArray [NUM_DSPS] = {
87                                                                         0,      /* DSP#0 is Master, will do the global init */
89                                                                         };
91 unsigned short isGblConfigRequired(unsigned int dspNum)
92         {
93         return gblCfgReqdArray[dspNum];
94         }
96 /* Semaphore handles */
97 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL};
100 /* Variable which will be used internally for referring number of Event Queues. */
101 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 2u};
103 /* Variable which will be used internally for referring number of TCs. */
104 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 2u};
106 /**
107  * Variable which will be used internally for referring transfer completion
108  * interrupt. Completion interrupts for all the shadow regions and all the
109  * EDMA3 controllers are captured since it is a multi-DSP platform.
110  */
111 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
112                                                                                                         {
113                                                                                                         0x88, 0x89, 0x8a, 0x8b,
114                                                                                                         0x8c, 0x8d, 0x8e, 0x8f,
115                                                                                                         },
116                                                                                                         {
117                                                                                                         0x90, 0x91, 0x92, 0x93,
118                                                                                                         0x94, 0x95, 0x96, 0x97,
119                                                                                                         },
120                                                                                                 };
122 /**
123  * Variable which will be used internally for referring channel controller's
124  * error interrupt.
125  */
126 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {0x99, 0x9c};
128 /**
129  * Variable which will be used internally for referring transfer controllers'
130  * error interrupts.
131  */
132 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {
133                                                                                                         {
134                                                                                                         0xA0,0xA1, 0u, 0u,
135                                                                                                         0u, 0u, 0u, 0u,
136                                                                                                         },
137                                                                                                         {
138                                                                                                         0xA4, 0xA5, 0u, 0u,
139                                                                                                         0u, 0u, 0u, 0u,
140                                                                                                         },
141                                                                                                 };
143 /* Driver Object Initialization Configuration */
144 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
145         {
146                 {
147                 /* EDMA3 INSTANCE# 0 */
148                 /** Total number of DMA Channels supported by the EDMA3 Controller */
149                 64u,
150                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
151                 8u,
152                 /** Total number of TCCs supported by the EDMA3 Controller */
153                 64u,
154                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
155                 512u,
156                 /** Total number of Event Queues in the EDMA3 Controller */
157                 2u,
158                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
159                 2u,
160                 /** Number of Regions on this EDMA3 controller */
161                 8u,
163                 /**
164                  * \brief Channel mapping existence
165                  * A value of 0 (No channel mapping) implies that there is fixed association
166                  * for a channel number to a parameter entry number or, in other words,
167                  * PaRAM entry n corresponds to channel n.
168                  */
169                 1u,
171                 /** Existence of memory protection feature */
172                 1u,
174                 /** Global Register Region of CC Registers */
175                 (void *)0x02700000u,
176                 /** Transfer Controller (TC) Registers */
177                 {
178                 (void *)0x02760000u,
179                 (void *)0x02768000u,
180                 (void *)NULL,
181                 (void *)NULL,
182                 (void *)NULL,
183                 (void *)NULL,
184                 (void *)NULL,
185                 (void *)NULL,
186                 },
187                 /** Interrupt no. for Transfer Completion */
188                 0x88,
189                 /** Interrupt no. for CC Error */
190                 0x99,
191                 /** Interrupt no. for TCs Error */
192                 {
193                 0xA0,
194                 0xA1,
195                 0u,
196                 0u,
197                 0u,
198                 0u,
199                 0u,
200                 0u,
201                 },
203                 /**
204                  * \brief EDMA3 TC priority setting
205                  *
206                  * User can program the priority of the Event Queues
207                  * at a system-wide level.  This means that the user can set the
208                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
209                  * relative to IO initiated by the other bus masters on the
210                  * device (ARM, DSP, USB, etc)
211                  */
212                 {
213                 0u,
214                 1u,
215                 0u,
216                 0u,
217                 0u,
218                 0u,
219                 0u,
220                 0u,
221                 },
222                 /**
223                  * \brief To Configure the Threshold level of number of events
224                  * that can be queued up in the Event queues. EDMA3CC error register
225                  * (CCERR) will indicate whether or not at any instant of time the
226                  * number of events queued up in any of the event queues exceeds
227                  * or equals the threshold/watermark value that is set
228                  * in the queue watermark threshold register (QWMTHRA).
229                  */
230                 {
231                 16u,
232                 16u,
233                 0u,
234                 0u,
235                 0u,
236                 0u,
237                 0u,
238                 0u,
239                 },
241                 /**
242                  * \brief To Configure the Default Burst Size (DBS) of TCs.
243                  * An optimally-sized command is defined by the transfer controller
244                  * default burst size (DBS). Different TCs can have different
245                  * DBS values. It is defined in Bytes.
246                  */
247                 {
248                 128u,
249                 128u,
250                 0u,
251                 0u,
252                 0u,
253                 0u,
254                 0u,
255                 0u,
256                 },
258                 /**
259                  * \brief Mapping from each DMA channel to a Parameter RAM set,
260                  * if it exists, otherwise of no use.
261                  */
262                 {
263                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
264                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
265                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
266                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
267                 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
268                 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
269                 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
270                 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u,
271                 },
273                  /**
274                   * \brief Mapping from each DMA channel to a TCC. This specific
275                   * TCC code will be returned when the transfer is completed
276                   * on the mapped channel.
277                   */
278                 {
279                 0u, 1u, 2u, EDMA3_RM_CH_NO_TCC_MAP, 4u, 5u, 6u, EDMA3_RM_CH_NO_TCC_MAP,
280                 8u, 9u, 10u, EDMA3_RM_CH_NO_TCC_MAP, 12u, 13u, 14u, EDMA3_RM_CH_NO_TCC_MAP,
281                 16u, 17u, 18u, EDMA3_RM_CH_NO_TCC_MAP, 20u, 21u, 22u, EDMA3_RM_CH_NO_TCC_MAP,
282                 24u, 25u, 26u, 27u, 28u, 29u, 30u, EDMA3_RM_CH_NO_TCC_MAP,
283                 32u, 33u, 34u, 35u, 36u, 37u, 38u, EDMA3_RM_CH_NO_TCC_MAP,
284                 40u, 41u, 42u, EDMA3_RM_CH_NO_TCC_MAP, 44u, 45u, 46u, EDMA3_RM_CH_NO_TCC_MAP,
285                 48u, 49u, 50u, 51u, 52u, 53u, 54u, EDMA3_RM_CH_NO_TCC_MAP,
286                 56u, 57u, 58u, 59u, 60u, 61u, 62u, EDMA3_RM_CH_NO_TCC_MAP
287                 },
289                 /**
290                  * \brief Mapping of DMA channels to Hardware Events from
291                  * various peripherals, which use EDMA for data transfer.
292                  * All channels need not be mapped, some can be free also.
293                  */
294                 {
295                 0x0F000000u,
296                 0x0000000Fu
297                 }
298                 },
300                 {
301                 /* EDMA3 INSTANCE# 1 */
302                 /** Total number of DMA Channels supported by the EDMA3 Controller */
303                 64u,
304                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
305                 8u,
306                 /** Total number of TCCs supported by the EDMA3 Controller */
307                 64u,
308                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
309                 512u,
310                 /** Total number of Event Queues in the EDMA3 Controller */
311                 2u,
312                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
313                 2u,
314                 /** Number of Regions on this EDMA3 controller */
315                 8u,
317                 /**
318                  * \brief Channel mapping existence
319                  * A value of 0 (No channel mapping) implies that there is fixed association
320                  * for a channel number to a parameter entry number or, in other words,
321                  * PaRAM entry n corresponds to channel n.
322                  */
323                 1u,
325                 /** Existence of memory protection feature */
326                 1u,
328                 /** Global Register Region of CC Registers */
329                 (void *)0x02728000U,
330                 /** Transfer Controller (TC) Registers */
331                 {
332                 (void *)0x027b0000U,
333                 (void *)0x027b8000U,
334                 (void *)NULL,
335                 (void *)NULL,
336                 (void *)NULL,
337                 (void *)NULL,
338                 (void *)NULL,
339                 (void *)NULL,
340                 },
341                 /** Interrupt no. for Transfer Completion */
342                 0x90,
343                 /** Interrupt no. for CC Error */
344                 0x9c,
345                 /** Interrupt no. for TCs Error */
346                 {
347                 0xA2,
348                 0xA3,
349                 0u,
350                 0u,
351                 0u,
352                 0u,
353                 0u,
354                 0u,
355                 },
357                 /**
358                  * \brief EDMA3 TC priority setting
359                  *
360                  * User can program the priority of the Event Queues
361                  * at a system-wide level.  This means that the user can set the
362                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
363                  * relative to IO initiated by the other bus masters on the
364                  * device (ARM, DSP, USB, etc)
365                  */
366                 {
367                 0u,
368                 1u,
369                 0u,
370                 0u,
371                 0u,
372                 0u,
373                 0u,
374                 0u
375                 },
376                 /**
377                  * \brief To Configure the Threshold level of number of events
378                  * that can be queued up in the Event queues. EDMA3CC error register
379                  * (CCERR) will indicate whether or not at any instant of time the
380                  * number of events queued up in any of the event queues exceeds
381                  * or equals the threshold/watermark value that is set
382                  * in the queue watermark threshold register (QWMTHRA).
383                  */
384                 {
385                 16u,
386                 16u,
387                 0u,
388                 0u,
389                 0u,
390                 0u,
391                 0u,
392                 0u
393                 },
395                 /**
396                  * \brief To Configure the Default Burst Size (DBS) of TCs.
397                  * An optimally-sized command is defined by the transfer controller
398                  * default burst size (DBS). Different TCs can have different
399                  * DBS values. It is defined in Bytes.
400                  */
401                 {
402                 64u,
403                 64u,
404                 0u,
405                 0u,
406                 0u,
407                 0u,
408                 0u,
409                 0u
410                 },
412                 /**
413                  * \brief Mapping from each DMA channel to a Parameter RAM set,
414                  * if it exists, otherwise of no use.
415                  */
416                 {
417                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
418                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
419                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
420                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
421                 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
422                 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
423                 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
424                 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
425                 },
427                  /**
428                   * \brief Mapping from each DMA channel to a TCC. This specific
429                   * TCC code will be returned when the transfer is completed
430                   * on the mapped channel.
431                   */
432                 {
433                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
434                 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
435                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
436                 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
437                 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
438                 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
439                 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
440                 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
441                 },
443                 /**
444                  * \brief Mapping of DMA channels to Hardware Events from
445                  * various peripherals, which use EDMA for data transfer.
446                  * All channels need not be mapped, some can be free also.
447                  */
448                 {
449                 0x00000000u,
450                 0xFFF00000u
451                 }
452                 },
454         };
456 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
457         {
458                 /* EDMA3 INSTANCE# 0 */
459                 {
460                         /* Resources owned/reserved by region 0 */
461                         {
462                                 /* ownPaRAMSets */
463                                 /* 31     0     63    32     95    64     127   96 */
464                                 {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000FFFu,
465                                 /* 159  128     191  160     223  192     255  224 */
466                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
467                                 /* 287  256     319  288     351  320     383  352 */
468                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
469                                 /* 415  384     447  416     479  448     511  480 */
470                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
472                                 /* ownDmaChannels */
473                                 /* 31     0     63    32 */
474                                 {0x0f00000Fu, 0x0000000Fu},
476                                 /* ownQdmaChannels */
477                                 /* 31     0 */
478                                 {0x00000003u},
480                                 /* ownTccs */
481                                 /* 31     0     63    32 */
482                                 {0x0f00000Fu, 0x000000FFu},
484                                 /* resvdPaRAMSets */
485                                 /* 31     0     63    32     95    64     127   96 */
486                                 {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
487                                 /* 159  128     191  160     223  192     255  224 */
488                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
489                                 /* 287  256     319  288     351  320     383  352 */
490                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
491                                 /* 415  384     447  416     479  448     511  480 */
492                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
494                                 /* resvdDmaChannels */
495                                 /* 31           0 */
496                                 {0x00000003u, 0x00000000u},
498                                 /* resvdQdmaChannels */
499                                 /* 31     0 */
500                                 {0x00000000u},
502                                 /* resvdTccs */
503                                 /* 31           0 */
504                                 {0x00000003u, 0x00000000u},
505                         },
507                 /* Resources owned/reserved by region 1 */
508                         {
509                                 /* ownPaRAMSets */
510                                 /* 31     0     63    32     95    64     127   96 */
511                                 {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
512                                 /* 159  128     191  160     223  192     255  224 */
513                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
514                                 /* 287  256     319  288     351  320     383  352 */
515                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
516                                 /* 415  384     447  416     479  448     511  480 */
517                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
519                                 /* ownDmaChannels */
520                                 /* 31     0     63    32 */
521                                 {0x000000F0u, 0x00000000u},
523                                 /* ownQdmaChannels */
524                                 /* 31     0 */
525                                 {0x0000000Cu},
527                                 /* ownTccs */
528                                 /* 31     0     63    32 */
529                                 {0x000000F0u, 0x00000000u},
531                                 /* resvdPaRAMSets */
532                                 /* 31     0     63    32     95    64     127   96 */
533                                 {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
534                                 /* 159  128     191  160     223  192     255  224 */
535                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
536                                 /* 287  256     319  288     351  320     383  352 */
537                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
538                                 /* 415  384     447  416     479  448     511  480 */
539                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
541                                 /* resvdDmaChannels */
542                                 /* 31     0     63    32 */
543                                 {0x00000030u, 0x00000000u},
545                                 /* resvdQdmaChannels */
546                                 /* 31     0 */
547                                 {0x00000000u},
549                                 /* resvdTccs */
550                                 /* 31     0     63    32 */
551                                 {0x00000030u, 0x00000000u},
552                         },
554                 /* Resources owned/reserved by region 2 */
555                         {
556                                 /* ownPaRAMSets */
557                                 /* 31     0     63    32     95    64     127   96 */
558                                 {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x00000000u,
559                                 /* 159  128     191  160     223  192     255  224 */
560                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
561                                 /* 287  256     319  288     351  320     383  352 */
562                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
563                                 /* 415  384     447  416     479  448     511  480 */
564                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
566                                 /* ownDmaChannels */
567                                 /* 31     0     63    32 */
568                                 {0x00000F00u, 0x00000000u},
570                                 /* ownQdmaChannels */
571                                 /* 31     0 */
572                                 {0x00000030u},
574                                 /* ownTccs */
575                                 /* 31     0     63    32 */
576                                 {0x00000F00u, 0x00000000u},
578                                 /* resvdPaRAMSets */
579                                 /* 31     0     63    32     95    64     127   96 */
580                                 {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
581                                 /* 159  128     191  160     223  192     255  224 */
582                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
583                                 /* 287  256     319  288     351  320     383  352 */
584                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
585                                 /* 415  384     447  416     479  448     511  480 */
586                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
588                                 /* resvdDmaChannels */
589                                 /* 31     0     63    32 */
590                                 {0x00000300u, 0x00000000u},
592                                 /* resvdQdmaChannels */
593                                 /* 31     0 */
594                                 {0x00000000u},
596                                 /* resvdTccs */
597                                 /* 31     0     63    32 */
598                                 {0x00000300u, 0x00000000u},
599                         },
601                 /* Resources owned/reserved by region 3 */
602                         {
603                                 /* ownPaRAMSets */
604                                 /* 31     0     63    32     95    64     127   96 */
605                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFF000u,
606                                 /* 159  128     191  160     223  192     255  224 */
607                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
608                                 /* 287  256     319  288     351  320     383  352 */
609                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
610                                 /* 415  384     447  416     479  448     511  480 */
611                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
613                                 /* ownDmaChannels */
614                                 /* 31     0     63    32 */
615                                 {0x0000F000u, 0x00000000u},
617                                 /* ownQdmaChannels */
618                                 /* 31     0 */
619                                 {0x000000C0u},
621                                 /* ownTccs */
622                                 /* 31     0     63    32 */
623                                 {0x0000F000u, 0x00000000u},
625                                 /* resvdPaRAMSets */
626                                 /* 31     0     63    32     95    64     127   96 */
627                                 {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
628                                 /* 159  128     191  160     223  192     255  224 */
629                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
630                                 /* 287  256     319  288     351  320     383  352 */
631                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
632                                 /* 415  384     447  416     479  448     511  480 */
633                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
635                                 /* resvdDmaChannels */
636                                 /* 31     0     63    32 */
637                                 {0x00003000u, 0x00000000u},
639                                 /* resvdQdmaChannels */
640                                 /* 31     0 */
641                                 {0x00000000u},
643                                 /* resvdTccs */
644                                 /* 31     0     63    32 */
645                                 {0x00003000u, 0x00000000u},
646                         },
648                 /* Resources owned/reserved by region 4 */
649                         {
650                                 /* ownPaRAMSets */
651                                 /* 31     0     63    32     95    64     127   96 */
652                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
653                                 /* 159  128     191  160     223  192     255  224 */
654                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
655                                 /* 287  256     319  288     351  320     383  352 */
656                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
657                                 /* 415  384     447  416     479  448     511  480 */
658                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
660                                 /* ownDmaChannels */
661                                 /* 31     0     63    32 */
662                                 {0x00000000u, 0x00000000u},
664                                 /* ownQdmaChannels */
665                                 /* 31     0 */
666                                 {0x00000000u},
668                                 /* ownTccs */
669                                 /* 31     0     63    32 */
670                                 {0x00000000u, 0x00000000u},
672                                 /* resvdPaRAMSets */
673                                 /* 31     0     63    32     95    64     127   96 */
674                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
675                                 /* 159  128     191  160     223  192     255  224 */
676                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
677                                 /* 287  256     319  288     351  320     383  352 */
678                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
679                                 /* 415  384     447  416     479  448     511  480 */
680                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
682                                 /* resvdDmaChannels */
683                                 /* 31     0     63    32 */
684                                 {0x00000000u, 0x00000000u},
686                                 /* resvdQdmaChannels */
687                                 /* 31     0 */
688                                 {0x00000000u},
690                                 /* resvdTccs */
691                                 /* 31     0     63    32 */
692                                 {0x00000000u, 0x00000000u},
693                         },
695                 /* Resources owned/reserved by region 5 */
696                         {
697                                 /* ownPaRAMSets */
698                                 /* 31     0     63    32     95    64     127   96 */
699                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
700                                 /* 159  128     191  160     223  192     255  224 */
701                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
702                                 /* 287  256     319  288     351  320     383  352 */
703                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
704                                 /* 415  384     447  416     479  448     511  480 */
705                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
707                                 /* ownDmaChannels */
708                                 /* 31     0     63    32 */
709                                 {0x00000000u, 0x00000000u},
711                                 /* ownQdmaChannels */
712                                 /* 31     0 */
713                                 {0x00000000u},
715                                 /* ownTccs */
716                                 /* 31     0     63    32 */
717                                 {0x00000000u, 0x00000000u},
719                                 /* resvdPaRAMSets */
720                                 /* 31     0     63    32     95    64     127   96 */
721                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
722                                 /* 159  128     191  160     223  192     255  224 */
723                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
724                                 /* 287  256     319  288     351  320     383  352 */
725                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
726                                 /* 415  384     447  416     479  448     511  480 */
727                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
729                                 /* resvdDmaChannels */
730                                 /* 31     0     63    32 */
731                                 {0x00000000u, 0x00000000u},
733                                 /* resvdQdmaChannels */
734                                 /* 31     0 */
735                                 {0x00000000u},
737                                 /* resvdTccs */
738                                 /* 31     0     63    32 */
739                                 {0x00000000u, 0x00000000u},
740                         },
742                 /* Resources owned/reserved by region 6 */
743                         {
744                                 /* ownPaRAMSets */
745                                 /* 31     0     63    32     95    64     127   96 */
746                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
747                                 /* 159  128     191  160     223  192     255  224 */
748                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
749                                 /* 287  256     319  288     351  320     383  352 */
750                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
751                                 /* 415  384     447  416     479  448     511  480 */
752                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
754                                 /* ownDmaChannels */
755                                 /* 31     0     63    32 */
756                                 {0x00000000u, 0x00000000u},
758                                 /* ownQdmaChannels */
759                                 /* 31     0 */
760                                 {0x00000000u},
762                                 /* ownTccs */
763                                 /* 31     0     63    32 */
764                                 {0x00000000u, 0x00000000u},
766                                 /* resvdPaRAMSets */
767                                 /* 31     0     63    32     95    64     127   96 */
768                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
769                                 /* 159  128     191  160     223  192     255  224 */
770                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
771                                 /* 287  256     319  288     351  320     383  352 */
772                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
773                                 /* 415  384     447  416     479  448     511  480 */
774                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
776                                 /* resvdDmaChannels */
777                                 /* 31     0     63    32 */
778                                 {0x00000000u, 0x00000000u},
780                                 /* resvdQdmaChannels */
781                                 /* 31     0 */
782                                 {0x00000000u},
784                                 /* resvdTccs */
785                                 /* 31     0     63    32 */
786                                 {0x00000000u, 0x00000000u},
787                         },
789                 /* Resources owned/reserved by region 7 */
790                         {
791                                 /* ownPaRAMSets */
792                                 /* 31     0     63    32     95    64     127   96 */
793                                 {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
794                                 /* 159  128     191  160     223  192     255  224 */
795                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
796                                 /* 287  256     319  288     351  320     383  352 */
797                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
798                                 /* 415  384     447  416     479  448     511  480 */
799                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
801                                 /* ownDmaChannels */
802                                 /* 31     0     63    32 */
803                                 {0x00000000u, 0x00000000u},
805                                 /* ownQdmaChannels */
806                                 /* 31     0 */
807                                 {0x00000000u},
809                                 /* ownTccs */
810                                 /* 31     0     63    32 */
811                                 {0x00000000u, 0x00000000u},
813                                 /* resvdPaRAMSets */
814                                 /* 31     0     63    32     95    64     127   96 */
815                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
816                                 /* 159  128     191  160     223  192     255  224 */
817                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
818                                 /* 287  256     319  288     351  320     383  352 */
819                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
820                                 /* 415  384     447  416     479  448     511  480 */
821                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
823                                 /* resvdDmaChannels */
824                                 /* 31     0     63    32 */
825                                 {0x00000000u, 0x00000000u},
827                                 /* resvdQdmaChannels */
828                                 /* 31     0 */
829                                 {0x00000000u},
831                                 /* resvdTccs */
832                                 /* 31     0     63    32 */
833                                 {0x00000000u, 0x00000000u},
834                         },
835             },
837                 /* EDMA3 INSTANCE# 1 */
838             {
839                 /* Resources owned/reserved by region 0 */
840                         {
841                                 /* ownPaRAMSets */
842                                 /* 31     0     63    32     95    64     127   96 */
843                                 {0x0000FFFFu, 0x00F00000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
844                                 /* 159  128     191  160     223  192     255  224 */
845                                  0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
846                                 /* 287  256     319  288     351  320     383  352 */
847                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
848                                 /* 415  384     447  416     479  448     511  480 */
849                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
851                                 /* ownDmaChannels */
852                                 /* 31     0     63    32 */
853                                 {0x0000FFFFu, 0x00F00000u},
855                                 /* ownQdmaChannels */
856                                 /* 31     0 */
857                                 {0x00000003u},
859                                 /* ownTccs */
860                                 /* 31     0     63    32 */
861                                 {0x0000FFFFu, 0x00F00000u},
863                                 /* resvdPaRAMSets */
864                                 /* 31     0     63    32     95    64     127   96 */
865                                 {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
866                                 /* 159  128     191  160     223  192     255  224 */
867                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
868                                 /* 287  256     319  288     351  320     383  352 */
869                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
870                                 /* 415  384     447  416     479  448     511  480 */
871                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
873                                 /* resvdDmaChannels */
874                                 /* 31     0     63    32 */
875                                 {0x00003FFFu, 0x00000000u},
877                                 /* resvdQdmaChannels */
878                                 /* 31     0 */
879                                 {0x00000000u},
881                                 /* resvdTccs */
882                                 /* 31     0     63    32 */
883                                 {0x00003FFFu, 0x00000000u},
884                         },
886                 /* Resources owned/reserved by region 1 */
887                         {
888                                 /* ownPaRAMSets */
889                                 /* 31     0     63    32     95    64     127   96 */
890                                 {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
891                                 /* 159  128     191  160     223  192     255  224 */
892                                  0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
893                                 /* 287  256     319  288     351  320     383  352 */
894                                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
895                                 /* 415  384     447  416     479  448     511  480 */
896                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
898                                 /* ownDmaChannels */
899                                 /* 31     0     63    32 */
900                                 {0xFFFF0000u, 0x00000000u},
902                                 /* ownQdmaChannels */
903                                 /* 31     0 */
904                                 {0x0000000Cu},
906                                 /* ownTccs */
907                                 /* 31     0     63    32 */
908                                 {0xFFFF0000u, 0x00000000u},
910                                 /* resvdPaRAMSets */
911                                 /* 31     0     63    32     95    64     127   96 */
912                                 {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
913                                 /* 159  128     191  160     223  192     255  224 */
914                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
915                                 /* 287  256     319  288     351  320     383  352 */
916                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
917                                 /* 415  384     447  416     479  448     511  480 */
918                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
920                                 /* resvdDmaChannels */
921                                 /* 31     0     63    32 */
922                                 {0x3FFF0000u, 0x00000000u},
924                                 /* resvdQdmaChannels */
925                                 /* 31     0 */
926                                 {0x00000000u},
928                                 /* resvdTccs */
929                                 /* 31     0     63    32 */
930                                 {0x3FFF0000u, 0x00000000u},
931                         },
933                 /* Resources owned/reserved by region 2 */
934                         {
935                                 /* ownPaRAMSets */
936                                 /* 31     0     63    32     95    64     127   96 */
937                                 {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
938                                 /* 159  128     191  160     223  192     255  224 */
939                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
940                                 /* 287  256     319  288     351  320     383  352 */
941                                  0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
942                                 /* 415  384     447  416     479  448     511  480 */
943                                  0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
945                                 /* ownDmaChannels */
946                                 /* 31     0     63    32 */
947                                 {0x00000000u, 0x0000FFFFu},
949                                 /* ownQdmaChannels */
950                                 /* 31     0 */
951                                 {0x00000030u},
953                                 /* ownTccs */
954                                 /* 31     0     63    32 */
955                                 {0x00000000u, 0x0000FFFFu},
957                                 /* resvdPaRAMSets */
958                                 /* 31     0     63    32     95    64     127   96 */
959                                 {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
960                                 /* 159  128     191  160     223  192     255  224 */
961                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
962                                 /* 287  256     319  288     351  320     383  352 */
963                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
964                                 /* 415  384     447  416     479  448     511  480 */
965                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
967                                 /* resvdDmaChannels */
968                                 /* 31     0     63    32 */
969                                 {0x00000000u, 0x00003FFFu},
971                                 /* resvdQdmaChannels */
972                                 /* 31     0 */
973                                 {0x00000000u},
975                                 /* resvdTccs */
976                                 /* 31     0     63    32 */
977                                 {0x00000000u, 0x00003FFFu},
978                         },
980                 /* Resources owned/reserved by region 3 */
981                         {
982                                 /* ownPaRAMSets */
983                                 /* 31     0     63    32     95    64     127   96 */
984                                 {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
985                                 /* 159  128     191  160     223  192     255  224 */
986                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
987                                 /* 287  256     319  288     351  320     383  352 */
988                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
989                                 /* 415  384     447  416     479  448     511  480 */
990                                  0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
992                                 /* ownDmaChannels */
993                                 /* 31     0     63    32 */
994                                 {0x00000000u, 0xFFFF0000u},
996                                 /* ownQdmaChannels */
997                                 /* 31     0 */
998                                 {0x000000C0u},
1000                                 /* ownTccs */
1001                                 /* 31     0     63    32 */
1002                                 {0x00000000u, 0xFFFF0000u},
1004                                 /* resvdPaRAMSets */
1005                                 /* 31     0     63    32     95    64     127   96 */
1006                                 {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
1007                                 /* 159  128     191  160     223  192     255  224 */
1008                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1009                                 /* 287  256     319  288     351  320     383  352 */
1010                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1011                                 /* 415  384     447  416     479  448     511  480 */
1012                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
1014                                 /* resvdDmaChannels */
1015                                 /* 31     0     63    32 */
1016                                 {0x00000000u, 0x3FFF0000u},
1018                                 /* resvdQdmaChannels */
1019                                 /* 31     0 */
1020                                 {0x00000000u},
1022                                 /* resvdTccs */
1023                                 /* 31     0     63    32 */
1024                                 {0x00000000u, 0x3FFF0000u},
1025                         },
1027                 /* Resources owned/reserved by region 4 */
1028                         {
1029                                 /* ownPaRAMSets */
1030                                 /* 31     0     63    32     95    64     127   96 */
1031                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1032                                 /* 159  128     191  160     223  192     255  224 */
1033                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1034                                 /* 287  256     319  288     351  320     383  352 */
1035                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1036                                 /* 415  384     447  416     479  448     511  480 */
1037                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1039                                 /* ownDmaChannels */
1040                                 /* 31     0     63    32 */
1041                                 {0x00000000u, 0x00000000u},
1043                                 /* ownQdmaChannels */
1044                                 /* 31     0 */
1045                                 {0x00000000u},
1047                                 /* ownTccs */
1048                                 /* 31     0     63    32 */
1049                                 {0x00000000u, 0x00000000u},
1051                                 /* resvdPaRAMSets */
1052                                 /* 31     0     63    32     95    64     127   96 */
1053                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1054                                 /* 159  128     191  160     223  192     255  224 */
1055                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1056                                 /* 287  256     319  288     351  320     383  352 */
1057                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1058                                 /* 415  384     447  416     479  448     511  480 */
1059                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1061                                 /* resvdDmaChannels */
1062                                 /* 31     0     63    32 */
1063                                 {0x00000000u, 0x00000000u},
1065                                 /* resvdQdmaChannels */
1066                                 /* 31     0 */
1067                                 {0x00000000u},
1069                                 /* resvdTccs */
1070                                 /* 31     0     63    32 */
1071                                 {0x00000000u, 0x00000000u},
1072                         },
1074                 /* Resources owned/reserved by region 5 */
1075                         {
1076                                 /* ownPaRAMSets */
1077                                 /* 31     0     63    32     95    64     127   96 */
1078                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1079                                 /* 159  128     191  160     223  192     255  224 */
1080                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1081                                 /* 287  256     319  288     351  320     383  352 */
1082                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1083                                 /* 415  384     447  416     479  448     511  480 */
1084                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1086                                 /* ownDmaChannels */
1087                                 /* 31     0     63    32 */
1088                                 {0x00000000u, 0x00000000u},
1090                                 /* ownQdmaChannels */
1091                                 /* 31     0 */
1092                                 {0x00000000u},
1094                                 /* ownTccs */
1095                                 /* 31     0     63    32 */
1096                                 {0x00000000u, 0x00000000u},
1098                                 /* resvdPaRAMSets */
1099                                 /* 31     0     63    32     95    64     127   96 */
1100                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1101                                 /* 159  128     191  160     223  192     255  224 */
1102                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1103                                 /* 287  256     319  288     351  320     383  352 */
1104                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1105                                 /* 415  384     447  416     479  448     511  480 */
1106                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1108                                 /* resvdDmaChannels */
1109                                 /* 31     0     63    32 */
1110                                 {0x00000000u, 0x00000000u},
1112                                 /* resvdQdmaChannels */
1113                                 /* 31     0 */
1114                                 {0x00000000u},
1116                                 /* resvdTccs */
1117                                 /* 31     0     63    32 */
1118                                 {0x00000000u, 0x00000000u},
1119                         },
1121                 /* Resources owned/reserved by region 6 */
1122                         {
1123                                 /* ownPaRAMSets */
1124                                 /* 31     0     63    32     95    64     127   96 */
1125                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1126                                 /* 159  128     191  160     223  192     255  224 */
1127                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1128                                 /* 287  256     319  288     351  320     383  352 */
1129                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1130                                 /* 415  384     447  416     479  448     511  480 */
1131                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1133                                 /* ownDmaChannels */
1134                                 /* 31     0     63    32 */
1135                                 {0x00000000u, 0x00000000u},
1137                                 /* ownQdmaChannels */
1138                                 /* 31     0 */
1139                                 {0x00000000u},
1141                                 /* ownTccs */
1142                                 /* 31     0     63    32 */
1143                                 {0x00000000u, 0x00000000u},
1145                                 /* resvdPaRAMSets */
1146                                 /* 31     0     63    32     95    64     127   96 */
1147                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1148                                 /* 159  128     191  160     223  192     255  224 */
1149                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1150                                 /* 287  256     319  288     351  320     383  352 */
1151                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1152                                 /* 415  384     447  416     479  448     511  480 */
1153                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1155                                 /* resvdDmaChannels */
1156                                 /* 31     0     63    32 */
1157                                 {0x00000000u, 0x00000000u},
1159                                 /* resvdQdmaChannels */
1160                                 /* 31     0 */
1161                                 {0x00000000u},
1163                                 /* resvdTccs */
1164                                 /* 31     0     63    32 */
1165                                 {0x00000000u, 0x00000000u},
1166                         },
1168                 /* Resources owned/reserved by region 7 */
1169                         {
1170                                 /* ownPaRAMSets */
1171                                 /* 31     0     63    32     95    64     127   96 */
1172                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1173                                 /* 159  128     191  160     223  192     255  224 */
1174                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1175                                 /* 287  256     319  288     351  320     383  352 */
1176                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1177                                 /* 415  384     447  416     479  448     511  480 */
1178                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1180                                 /* ownDmaChannels */
1181                                 /* 31     0     63    32 */
1182                                 {0x00000000u, 0x00000000u},
1184                                 /* ownQdmaChannels */
1185                                 /* 31     0 */
1186                                 {0x00000000u},
1188                                 /* ownTccs */
1189                                 /* 31     0     63    32 */
1190                                 {0x00000000u, 0x00000000u},
1192                                 /* resvdPaRAMSets */
1193                                 /* 31     0     63    32     95    64     127   96 */
1194                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1195                                 /* 159  128     191  160     223  192     255  224 */
1196                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1197                                 /* 287  256     319  288     351  320     383  352 */
1198                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
1199                                 /* 415  384     447  416     479  448     511  480 */
1200                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
1202                                 /* resvdDmaChannels */
1203                                 /* 31     0     63    32 */
1204                                 {0x00000000u, 0x00000000u},
1206                                 /* resvdQdmaChannels */
1207                                 /* 31     0 */
1208                                 {0x00000000u},
1210                                 /* resvdTccs */
1211                                 /* 31     0     63    32 */
1212                                 {0x00000000u, 0x00000000u},
1213                         },
1214             },
1215         };
1217 /* End of File */