Fixing the loopback test issue on C6657
[keystone-rtos/mcbsp-lld.git] / example / c6657 / MCBSPDigLpbk / sample_c6657_cfg.c
1 /*
2  * sample_c6657_cfg.c
3  *
4  * Platform specific EDMA3 hardware related information like number of transfer
5  * controllers, various interrupt ids etc. It is used while interrupts
6  * enabling / disabling. It needs to be ported for different SoCs.
7  *
8  * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
9  *
10  *
11  *  Redistribution and use in source and binary forms, with or without
12  *  modification, are permitted provided that the following conditions
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the
20  *    documentation and/or other materials provided with the
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39 */
41 #include <ti/sdo/edma3/rm/edma3_rm.h>
43 /* Number of EDMA3 controllers present in the system */
44 #define NUM_EDMA3_INSTANCES                     1u
45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
47 /* Number of DSPs present in the system */
48 #define NUM_DSPS                                        2u
49 //const unsigned int numDsps = NUM_DSPS;
51 #define CGEM_REG_START                  (0x01800000)
54 extern cregister volatile unsigned int DNUM;
56 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
59 /* Determine the processor id by reading DNUM register. */
60 unsigned short determineProcId()
61         {
62         volatile unsigned int *addr;
63         unsigned int core_no;
65     /* Identify the core number */
66     addr = (unsigned int *)(CGEM_REG_START+0x40000);
67     core_no = ((*addr) & 0x000F0000)>>16;
69         return core_no;
70         }
72 signed char*  getGlobalAddr(signed char* addr)
73 {
74     if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
75     {
76         return (addr); /* The address is already a global address */
77     }
79     return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
80 }
81 /** Whether global configuration required for EDMA3 or not.
82  * This configuration should be done only once for the EDMA3 hardware by
83  * any one of the masters (i.e. DSPs).
84  * It can be changed depending on the use-case.
85  */
86 unsigned int gblCfgReqdArray [NUM_DSPS] = {
87                                                                         0,      /* DSP#0 is Master, will do the global init */
88                                                                         1,      /* DSP#1 is Slave, will not do the global init  */
89                                                                         };
91 unsigned short isGblConfigRequired(unsigned int dspNum)
92         {
93         return gblCfgReqdArray[dspNum];
94         }
96 /* Semaphore handles */
97 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
100 /* Variable which will be used internally for referring number of Event Queues. */
101 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {4u};
103 /* Variable which will be used internally for referring number of TCs. */
104 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {4u};
106 /**
107  * Variable which will be used internally for referring transfer completion
108  * interrupt. Completion interrupts for all the shadow regions and all the
109  * EDMA3 controllers are captured since it is a multi-DSP platform.
110  */
111 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
112                                                                                                         {
113                                                                                                         24u, 25u, 26u, 27u,
114                                                                                                         28u, 29u, 30u, 31u,
115                                                                                                         },
116                                                                                                 };
118 /**
119  * Variable which will be used internally for referring channel controller's
120  * error interrupt.
121  */
122 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {16u};
124 /**
125  * Variable which will be used internally for referring transfer controllers'
126  * error interrupts.
127  */
128 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {
129                                                                                                         {
130                                                                                                         18u, 19u, 20u, 21u,
131                                                                                                         0u, 0u, 0u, 0u,
132                                                                                                         },
133                                                                                                 };
135 /* Driver Object Initialization Configuration */
136 EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
137         {
138                 {
139                 /* EDMA3 INSTANCE# 0 */
140                 /** Total number of DMA Channels supported by the EDMA3 Controller */
141                 64u,
142                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
143                 8u,
144                 /** Total number of TCCs supported by the EDMA3 Controller */
145                 64u,
146                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
147                 512u,
148                 /** Total number of Event Queues in the EDMA3 Controller */
149                 4u,
150                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
151                 4u,
152                 /** Number of Regions on this EDMA3 controller */
153                 8u,
155                 /**
156                  * \brief Channel mapping existence
157                  * A value of 0 (No channel mapping) implies that there is fixed association
158                  * for a channel number to a parameter entry number or, in other words,
159                  * PaRAM entry n corresponds to channel n.
160                  */
161                 1u,
163                 /** Existence of memory protection feature */
164                 1u,
166                 /** Global Register Region of CC Registers */
167                 (void *)0x02740000u,
168                 /** Transfer Controller (TC) Registers */
169                 {
170                 (void *)0x02790000u,
171                 (void *)0x02798000u,
172                 (void *)0x027A0000u,
173                 (void *)0x027A8000u,
174                 (void *)NULL,
175                 (void *)NULL,
176                 (void *)NULL,
177                 (void *)NULL
178                 },
179                 /** Interrupt no. for Transfer Completion */
180                 24u,
181                 /** Interrupt no. for CC Error */
182                 16u,
183                 /** Interrupt no. for TCs Error */
184                 {
185                 18u,
186                 19u,
187                 20u,
188                 21u,
189                 0u,
190                 0u,
191                 0u,
192                 0u,
193                 },
195                 /**
196                  * \brief EDMA3 TC priority setting
197                  *
198                  * User can program the priority of the Event Queues
199                  * at a system-wide level.  This means that the user can set the
200                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
201                  * relative to IO initiated by the other bus masters on the
202                  * device (ARM, DSP, USB, etc)
203                  */
204                 {
205                 0u,
206                 1u,
207                 2u,
208                 3u,
209                 0u,
210                 0u,
211                 0u,
212                 0u
213                 },
214                 /**
215                  * \brief To Configure the Threshold level of number of events
216                  * that can be queued up in the Event queues. EDMA3CC error register
217                  * (CCERR) will indicate whether or not at any instant of time the
218                  * number of events queued up in any of the event queues exceeds
219                  * or equals the threshold/watermark value that is set
220                  * in the queue watermark threshold register (QWMTHRA).
221                  */
222                 {
223                 16u,
224                 16u,
225                 16u,
226                 16u,
227                 0u,
228                 0u,
229                 0u,
230                 0u
231                 },
233                 /**
234                  * \brief To Configure the Default Burst Size (DBS) of TCs.
235                  * An optimally-sized command is defined by the transfer controller
236                  * default burst size (DBS). Different TCs can have different
237                  * DBS values. It is defined in Bytes.
238                  */
239                 {
240                 64u,
241                 64u,
242                 64u,
243                 64u,
244                 0u,
245                 0u,
246                 0u,
247                 0u
248                 },
250                 /**
251                  * \brief Mapping from each DMA channel to a Parameter RAM set,
252                  * if it exists, otherwise of no use.
253                  */
254                 {
255                     EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
256         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
257         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
258         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
259         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
260         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
261         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
262         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
263         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
264         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
265         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
266         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
267         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
268         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
269         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
270         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
271         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
272         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
273         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
274         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
275         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
276         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
277         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
278         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
279         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
280         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
281         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
282         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
283         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
284         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
285         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
286         EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
287                 },
289                  /**
290                   * \brief Mapping from each DMA channel to a TCC. This specific
291                   * TCC code will be returned when the transfer is completed
292                   * on the mapped channel.
293                   */
294                 {
295                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
296                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
297                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
298                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
299                 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
300                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 
301     EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
302                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 
303     EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
304                 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
305                 },
307                 /**
308                  * \brief Mapping of DMA channels to Hardware Events from
309                  * various peripherals, which use EDMA for data transfer.
310                  * All channels need not be mapped, some can be free also.
311                  */
312                 {
313                 0xFFFFFFFFu,
314                 0xFF0000FFu
315                 }
316                 },
317         };
319 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
320         {
321                 /* EDMA3 INSTANCE# 0 */
322                 {
323                 /* Resources owned/reserved by region 0 */
324                         {
325                                 /* ownPaRAMSets */
326                                 /* 31     0     63    32     95    64     127   96 */
327                                 {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
328                                 /* 159  128     191  160     223  192     255  224 */
329                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
330                                 /* 287  256     319  288     351  320     383  352 */
331                                  0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
332                                 /* 415  384     447  416     479  448     511  480 */
333                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
335                                 /* ownDmaChannels */
336                                 /* 31     0     63    32 */
337                                 {0x00000000u, 0x0000FF00u},
339                                 /* ownQdmaChannels */
340                                 /* 31     0 */
341                                 {0x0000000Fu},
343                                 /* ownTccs */
344                                 /* 31     0     63    32 */
345                                 {0x00000000u, 0x0000FFF0u},
347                                 /* resvdPaRAMSets */
348                                 /* 31     0     63    32     95    64     127   96 */
349                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
350                                 /* 159  128     191  160     223  192     255  224 */
351                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
352                                 /* 287  256     319  288     351  320     383  352 */
353                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
354                                 /* 415  384     447  416     479  448     511  480 */
355                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
357                                 /* resvdDmaChannels */
358                                 /* 31     0     63    32 */
359                                 {0xFFFFFFFFu, 0xFF0000FFu},
361                                 /* resvdQdmaChannels */
362                                 /* 31     0 */
363                                 {0x00000000u},
365                                 /* resvdTccs */
366                                 /* 31     0     63    32 */
367                                 {0xFFFFFFFFu, 0xFF0000FFu},
368                         },
370                 /* Resources owned/reserved by region 1 */
371                         {
372                                 /* ownPaRAMSets */
373                                 /* 31     0     63    32     95    64     127   96 */
374                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
375                                 /* 159  128     191  160     223  192     255  224 */
376                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
377                                 /* 287  256     319  288     351  320     383  352 */
378                                  0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
379                                 /* 415  384     447  416     479  448     511  480 */
380                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
382                                 /* ownDmaChannels */
383                                 /* 31     0     63    32 */
384                                 {0x00000000u, 0x00FF0000u},
386                                 /* ownQdmaChannels */
387                                 /* 31     0 */
388                                 {0x000000F0u},
390                                 /* ownTccs */
391                                 /* 31     0     63    32 */
392                                 {0x00000000u, 0x00FF0000u},
394                                 /* resvdPaRAMSets */
395                                 /* 31     0     63    32     95    64     127   96 */
396                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
397                                 /* 159  128     191  160     223  192     255  224 */
398                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
399                                 /* 287  256     319  288     351  320     383  352 */
400                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
401                                 /* 415  384     447  416     479  448     511  480 */
402                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
404                                 /* resvdDmaChannels */
405                                 /* 31     0     63    32 */
406                                 {0xFFFFFFFFu, 0xFF0000FFu},
408                                 /* resvdQdmaChannels */
409                                 /* 31     0 */
410                                 {0x00000000u},
412                                 /* resvdTccs */
413                                 /* 31     0     63    32 */
414                                 {0xFFFFFFFFu, 0xFF0000FFu},
415                         },
417                 /* Resources owned/reserved by region 2 */
418                         {
419                                 /* ownPaRAMSets */
420                                 /* 31     0     63    32     95    64     127   96 */
421                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
422                                 /* 159  128     191  160     223  192     255  224 */
423                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
424                                 /* 287  256     319  288     351  320     383  352 */
425                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
426                                 /* 415  384     447  416     479  448     511  480 */
427                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
429                                 /* ownDmaChannels */
430                                 /* 31     0     63    32 */
431                                 {0x00000000u, 0x00000000u},
433                                 /* ownQdmaChannels */
434                                 /* 31     0 */
435                                 {0x00000000u},
437                                 /* ownTccs */
438                                 /* 31     0     63    32 */
439                                 {0x00000000u, 0x00000000u},
441                                 /* resvdPaRAMSets */
442                                 /* 31     0     63    32     95    64     127   96 */
443                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
444                                 /* 159  128     191  160     223  192     255  224 */
445                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
446                                 /* 287  256     319  288     351  320     383  352 */
447                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
448                                 /* 415  384     447  416     479  448     511  480 */
449                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
451                                 /* resvdDmaChannels */
452                                 /* 31     0     63    32 */
453                                 {0x00000000u, 0x00000000u},
455                                 /* resvdQdmaChannels */
456                                 /* 31     0 */
457                                 {0x00000000u},
459                                 /* resvdTccs */
460                                 /* 31     0     63    32 */
461                                 {0x00000000u, 0x00000000u},
462                         },
464                 /* Resources owned/reserved by region 3 */
465                         {
466                                 /* ownPaRAMSets */
467                                 /* 31     0     63    32     95    64     127   96 */
468                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
469                                 /* 159  128     191  160     223  192     255  224 */
470                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
471                                 /* 287  256     319  288     351  320     383  352 */
472                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
473                                 /* 415  384     447  416     479  448     511  480 */
474                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
476                                 /* ownDmaChannels */
477                                 /* 31     0     63    32 */
478                                 {0x00000000u, 0x00000000u},
480                                 /* ownQdmaChannels */
481                                 /* 31     0 */
482                                 {0x00000000u},
484                                 /* ownTccs */
485                                 /* 31     0     63    32 */
486                                 {0x00000000u, 0x00000000u},
488                                 /* resvdPaRAMSets */
489                                 /* 31     0     63    32     95    64     127   96 */
490                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
491                                 /* 159  128     191  160     223  192     255  224 */
492                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
493                                 /* 287  256     319  288     351  320     383  352 */
494                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
495                                 /* 415  384     447  416     479  448     511  480 */
496                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
498                                 /* resvdDmaChannels */
499                                 /* 31     0     63    32 */
500                                 {0x00000000u, 0x00000000u},
502                                 /* resvdQdmaChannels */
503                                 /* 31     0 */
504                                 {0x00000000u},
506                                 /* resvdTccs */
507                                 /* 31     0     63    32 */
508                                 {0x00000000u, 0x00000000u},
509                         },
511                 /* Resources owned/reserved by region 4 */
512                         {
513                                 /* ownPaRAMSets */
514                                 /* 31     0     63    32     95    64     127   96 */
515                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
516                                 /* 159  128     191  160     223  192     255  224 */
517                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
518                                 /* 287  256     319  288     351  320     383  352 */
519                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
520                                 /* 415  384     447  416     479  448     511  480 */
521                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
523                                 /* ownDmaChannels */
524                                 /* 31     0     63    32 */
525                                 {0x00000000u, 0x00000000u},
527                                 /* ownQdmaChannels */
528                                 /* 31     0 */
529                                 {0x00000000u},
531                                 /* ownTccs */
532                                 /* 31     0     63    32 */
533                                 {0x00000000u, 0x00000000u},
535                                 /* resvdPaRAMSets */
536                                 /* 31     0     63    32     95    64     127   96 */
537                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
538                                 /* 159  128     191  160     223  192     255  224 */
539                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
540                                 /* 287  256     319  288     351  320     383  352 */
541                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
542                                 /* 415  384     447  416     479  448     511  480 */
543                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
545                                 /* resvdDmaChannels */
546                                 /* 31     0     63    32 */
547                                 {0x00000000u, 0x00000000u},
549                                 /* resvdQdmaChannels */
550                                 /* 31     0 */
551                                 {0x00000000u},
553                                 /* resvdTccs */
554                                 /* 31     0     63    32 */
555                                 {0x00000000u, 0x00000000u},
556                         },
558                 /* Resources owned/reserved by region 5 */
559                         {
560                                 /* ownPaRAMSets */
561                                 /* 31     0     63    32     95    64     127   96 */
562                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
563                                 /* 159  128     191  160     223  192     255  224 */
564                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
565                                 /* 287  256     319  288     351  320     383  352 */
566                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
567                                 /* 415  384     447  416     479  448     511  480 */
568                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
570                                 /* ownDmaChannels */
571                                 /* 31     0     63    32 */
572                                 {0x00000000u, 0x00000000u},
574                                 /* ownQdmaChannels */
575                                 /* 31     0 */
576                                 {0x00000000u},
578                                 /* ownTccs */
579                                 /* 31     0     63    32 */
580                                 {0x00000000u, 0x00000000u},
582                                 /* resvdPaRAMSets */
583                                 /* 31     0     63    32     95    64     127   96 */
584                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
585                                 /* 159  128     191  160     223  192     255  224 */
586                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
587                                 /* 287  256     319  288     351  320     383  352 */
588                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
589                                 /* 415  384     447  416     479  448     511  480 */
590                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
592                                 /* resvdDmaChannels */
593                                 /* 31     0     63    32 */
594                                 {0x00000000u, 0x00000000u},
596                                 /* resvdQdmaChannels */
597                                 /* 31     0 */
598                                 {0x00000000u},
600                                 /* resvdTccs */
601                                 /* 31     0     63    32 */
602                                 {0x00000000u, 0x00000000u},
603                         },
605                 /* Resources owned/reserved by region 6 */
606                         {
607                                 /* ownPaRAMSets */
608                                 /* 31     0     63    32     95    64     127   96 */
609                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
610                                 /* 159  128     191  160     223  192     255  224 */
611                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
612                                 /* 287  256     319  288     351  320     383  352 */
613                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
614                                 /* 415  384     447  416     479  448     511  480 */
615                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
617                                 /* ownDmaChannels */
618                                 /* 31     0     63    32 */
619                                 {0x00000000u, 0x00000000u},
621                                 /* ownQdmaChannels */
622                                 /* 31     0 */
623                                 {0x00000000u},
625                                 /* ownTccs */
626                                 /* 31     0     63    32 */
627                                 {0x00000000u, 0x00000000u},
629                                 /* resvdPaRAMSets */
630                                 /* 31     0     63    32     95    64     127   96 */
631                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
632                                 /* 159  128     191  160     223  192     255  224 */
633                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
634                                 /* 287  256     319  288     351  320     383  352 */
635                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
636                                 /* 415  384     447  416     479  448     511  480 */
637                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
639                                 /* resvdDmaChannels */
640                                 /* 31     0     63    32 */
641                                 {0x00000000u, 0x00000000u},
643                                 /* resvdQdmaChannels */
644                                 /* 31     0 */
645                                 {0x00000000u},
647                                 /* resvdTccs */
648                                 /* 31     0     63    32 */
649                                 {0x00000000u, 0x00000000u},
650                         },
652                 /* Resources owned/reserved by region 7 */
653                         {
654                                 /* ownPaRAMSets */
655                                 /* 31     0     63    32     95    64     127   96 */
656                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
657                                 /* 159  128     191  160     223  192     255  224 */
658                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
659                                 /* 287  256     319  288     351  320     383  352 */
660                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
661                                 /* 415  384     447  416     479  448     511  480 */
662                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
664                                 /* ownDmaChannels */
665                                 /* 31     0     63    32 */
666                                 {0x00000000u, 0x00000000u},
668                                 /* ownQdmaChannels */
669                                 /* 31     0 */
670                                 {0x00000000u},
672                                 /* ownTccs */
673                                 /* 31     0     63    32 */
674                                 {0x00000000u, 0x00000000u},
676                                 /* resvdPaRAMSets */
677                                 /* 31     0     63    32     95    64     127   96 */
678                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
679                                 /* 159  128     191  160     223  192     255  224 */
680                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
681                                 /* 287  256     319  288     351  320     383  352 */
682                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
683                                 /* 415  384     447  416     479  448     511  480 */
684                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
686                                 /* resvdDmaChannels */
687                                 /* 31     0     63    32 */
688                                 {0x00000000u, 0x00000000u},
690                                 /* resvdQdmaChannels */
691                                 /* 31     0 */
692                                 {0x00000000u},
694                                 /* resvdTccs */
695                                 /* 31     0     63    32 */
696                                 {0x00000000u, 0x00000000u},
697                         },
698             },
699         };
701 /* End of File */