example/c674x/MCBSPDigLpbk/sample_c6657_cfg.c

   1 /*
   2  * sample_c6657_cfg.c
   3  *
   4  * Platform specific EDMA3 hardware related information like number of transfer
   5  * controllers, various interrupt ids etc. It is used while interrupts
   6  * enabling / disabling. It needs to be ported for different SoCs.
   7  *
   8  * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
   9  *
  10  *
  11  *  Redistribution and use in source and binary forms, with or without
  12  *  modification, are permitted provided that the following conditions
  13  *  are met:
  14  *
  15  *    Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  *
  18  *    Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the
  21  *    distribution.
  22  *
  23  *    Neither the name of Texas Instruments Incorporated nor the names of
  24  *    its contributors may be used to endorse or promote products derived
  25  *    from this software without specific prior written permission.
  26  *
  27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  *
  39 */
  40 #include <ti/csl/cslr_device.h>
  41 #include <ti/sdo/edma3/drv/edma3_drv.h>
  42
  43 /* Number of EDMA3 controllers present in the system */
  44 #define NUM_EDMA3_INSTANCES                     1u
  45 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
  46
  47 /* Number of DSPs present in the system */
  48 #define NUM_DSPS                                        2u
  49 //const unsigned int numDsps = NUM_DSPS;
  50
  51 #define CGEM_REG_START                  (0x01800000)
  52
  53
  54 extern cregister volatile unsigned int DNUM;
  55
  56 #define MAP_LOCAL_TO_GLOBAL_ADDR(addr) ((1<<28)|(DNUM<<24)|(((unsigned int)addr)&0x00ffffff))
  57
  58
  59 /* Determine the processor id by reading DNUM register. */
  60 unsigned short determineProcId()
  61         {
  62         volatile unsigned int *addr;
  63         unsigned int core_no;
  64
  65     /* Identify the core number */
  66     addr = (unsigned int *)(CGEM_REG_START+0x40000);
  67     core_no = ((*addr) & 0x000F0000)>>16;
  68
  69         return core_no;
  70         }
  71
  72 signed char*  getGlobalAddr(signed char* addr)
  73 {
  74     if (((unsigned int)addr & (unsigned int)0xFF000000) != 0)
  75     {
  76         return (addr); /* The address is already a global address */
  77     }
  78
  79     return((signed char*)(MAP_LOCAL_TO_GLOBAL_ADDR(addr)));
  80 }
  81 /** Whether global configuration required for EDMA3 or not.
  82  * This configuration should be done only once for the EDMA3 hardware by
  83  * any one of the masters (i.e. DSPs).
  84  * It can be changed depending on the use-case.
  85  */
  86 unsigned int gblCfgReqdArray [NUM_DSPS] = {
  87                                                                         0,      /* DSP#0 is Master, will do the global init */
  88                                                                         1,      /* DSP#1 is Slave, will not do the global init  */
  89                                                                         };
  90
  91 unsigned short isGblConfigRequired(unsigned int dspNum)
  92         {
  93         return gblCfgReqdArray[dspNum];
  94         }
  95
  96 /* Semaphore handles */
  97 EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
  98
  99
 100 /* Variable which will be used internally for referring number of Event Queues. */
 101 unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {4u};
 102
 103 /* Variable which will be used internally for referring number of TCs. */
 104 unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {4u};
 105
 106 /**
 107  * Variable which will be used internally for referring transfer completion
 108  * interrupt. Completion interrupts for all the shadow regions and all the
 109  * EDMA3 controllers are captured since it is a multi-DSP platform.
 110  */
 111 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
 112                                                                                                         {
 113                                                                                                         24u, 25u, 26u, 27u,
 114                                                                                                         28u, 29u, 30u, 31u,
 115                                                                                                         },
 116                                                                                                 };
 117
 118 /**
 119  * Variable which will be used internally for referring channel controller's
 120  * error interrupt.
 121  */
 122 unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {16u};
 123
 124 /**
 125  * Variable which will be used internally for referring transfer controllers'
 126  * error interrupts.
 127  */
 128 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {
 129                                                                                                         {
 130                                                                                                         18u, 19u, 20u, 21u,
 131                                                                                                         0u, 0u, 0u, 0u,
 132                                                                                                         },
 133                                                                                                 };
 134
 135 /* Driver Object Initialization Configuration */
 136 EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
 137         {
 138                 {
 139                 /* EDMA3 INSTANCE# 0 */
 140                 /** Total number of DMA Channels supported by the EDMA3 Controller */
 141                 64u,
 142                 /** Total number of QDMA Channels supported by the EDMA3 Controller */
 143                 8u,
 144                 /** Total number of TCCs supported by the EDMA3 Controller */
 145                 64u,
 146                 /** Total number of PaRAM Sets supported by the EDMA3 Controller */
 147                 512u,
 148                 /** Total number of Event Queues in the EDMA3 Controller */
 149                 4u,
 150                 /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
 151                 4u,
 152                 /** Number of Regions on this EDMA3 controller */
 153                 8u,
 154
 155                 /**
 156                  * \brief Channel mapping existence
 157                  * A value of 0 (No channel mapping) implies that there is fixed association
 158                  * for a channel number to a parameter entry number or, in other words,
 159                  * PaRAM entry n corresponds to channel n.
 160                  */
 161                 1u,
 162
 163                 /** Existence of memory protection feature */
 164                 1u,
 165
 166                 /** Global Register Region of CC Registers */
 167                 (void *)0x02740000u,
 168                 /** Transfer Controller (TC) Registers */
 169                 {
 170                 (void *)0x02790000u,
 171                 (void *)0x02798000u,
 172                 (void *)0x027A0000u,
 173                 (void *)0x027A8000u,
 174                 (void *)NULL,
 175                 (void *)NULL,
 176                 (void *)NULL,
 177                 (void *)NULL
 178                 },
 179                 /** Interrupt no. for Transfer Completion */
 180                 24u,
 181                 /** Interrupt no. for CC Error */
 182                 16u,
 183                 /** Interrupt no. for TCs Error */
 184                 {
 185                 18u,
 186                 19u,
 187                 20u,
 188                 21u,
 189                 0u,
 190                 0u,
 191                 0u,
 192                 0u,
 193                 },
 194
 195                 /**
 196                  * \brief EDMA3 TC priority setting
 197                  *
 198                  * User can program the priority of the Event Queues
 199                  * at a system-wide level.  This means that the user can set the
 200                  * priority of an IO initiated by either of the TCs (Transfer Controllers)
 201                  * relative to IO initiated by the other bus masters on the
 202                  * device (ARM, DSP, USB, etc)
 203                  */
 204                 {
 205                 0u,
 206                 0u,
 207                 0u,
 208                 0u,
 209                 0u,
 210                 0u,
 211                 0u,
 212                 0u
 213                 },
 214                 /**
 215                  * \brief To Configure the Threshold level of number of events
 216                  * that can be queued up in the Event queues. EDMA3CC error register
 217                  * (CCERR) will indicate whether or not at any instant of time the
 218                  * number of events queued up in any of the event queues exceeds
 219                  * or equals the threshold/watermark value that is set
 220                  * in the queue watermark threshold register (QWMTHRA).
 221                  */
 222                 {
 223                 16u,
 224                 16u,
 225                 16u,
 226                 16u,
 227                 0u,
 228                 0u,
 229                 0u,
 230                 0u
 231                 },
 232
 233                 /**
 234                  * \brief To Configure the Default Burst Size (DBS) of TCs.
 235                  * An optimally-sized command is defined by the transfer controller
 236                  * default burst size (DBS). Different TCs can have different
 237                  * DBS values. It is defined in Bytes.
 238                  */
 239                 {
 240                 64u,
 241                 64u,
 242                 64u,
 243                 64u,
 244                 0u,
 245                 0u,
 246                 0u,
 247                 0u
 248                 },
 249
 250                 /**
 251                  * \brief Mapping from each DMA channel to a Parameter RAM set,
 252                  * if it exists, otherwise of no use.
 253                  */
 254                 {
 255                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
 256                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
 257                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
 258                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
 259                 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
 260                 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
 261                 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
 262                 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
 263                 },
 264
 265                  /**
 266                   * \brief Mapping from each DMA channel to a TCC. This specific
 267                   * TCC code will be returned when the transfer is completed
 268                   * on the mapped channel.
 269                   */
 270                 {
 271                 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
 272                 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
 273                 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
 274                 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
 275                 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
 276                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 277     EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 278                 EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 279     EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
 280                 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
 281                 },
 282
 283                 /**
 284                  * \brief Mapping of DMA channels to Hardware Events from
 285                  * various peripherals, which use EDMA for data transfer.
 286                  * All channels need not be mapped, some can be free also.
 287                  */
 288                 {
 289                 0xFFFFFFFFu,
 290                 0xFFFFFFFFu
 291                 }
 292                 },
 293         };
 294
 295 EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
 296         {
 297                 /* EDMA3 INSTANCE# 0 */
 298                 {
 299                 /* Resources owned/reserved by region 0 */
 300                         {
 301                                 /* ownPaRAMSets */
 302                                 /* 31     0     63    32     95    64     127   96 */
 303                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 304                                 /* 159  128     191  160     223  192     255  224 */
 305                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 306                                 /* 287  256     319  288     351  320     383  352 */
 307                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 308                                 /* 415  384     447  416     479  448     511  480 */
 309                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 310
 311                                 /* ownDmaChannels */
 312                                 /* 31     0     63    32 */
 313                                 {0xFFFFFFFFu, 0xFFFFFFFFu},
 314
 315                                 /* ownQdmaChannels */
 316                                 /* 31     0 */
 317                                 {0x000000FFu},
 318
 319                                 /* ownTccs */
 320                                 /* 31     0     63    32 */
 321         {0xFFFFFFFFu, 0xFFFFFFFFu},
 322
 323                                 /* resvdPaRAMSets */
 324                                 /* 31     0     63    32     95    64     127   96 */
 325                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 326                                 /* 159  128     191  160     223  192     255  224 */
 327                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 328                                 /* 287  256     319  288     351  320     383  352 */
 329                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 330                                 /* 415  384     447  416     479  448     511  480 */
 331                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 332
 333                                 /* resvdDmaChannels */
 334                                 /* 31     0     63    32 */
 335                                 {0x00000000u, 0x00000000u},
 336
 337                                 /* resvdQdmaChannels */
 338                                 /* 31     0 */
 339                                 {0x00000000u},
 340
 341                                 /* resvdTccs */
 342                                 /* 31     0     63    32 */
 343                                 {0x00000000u, 0x00000000u},
 344                         },
 345
 346                 /* Resources owned/reserved by region 1 */
 347                         {
 348                                 /* ownPaRAMSets */
 349                                 /* 31     0     63    32     95    64     127   96 */
 350                                 {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 351                                 /* 159  128     191  160     223  192     255  224 */
 352                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 353                                 /* 287  256     319  288     351  320     383  352 */
 354                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
 355                                 /* 415  384     447  416     479  448     511  480 */
 356                                  0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
 357
 358                                 /* ownDmaChannels */
 359                                 /* 31     0     63    32 */
 360                                 {0xFFFFFFFFu, 0xFFFFFFFFu},
 361
 362                                 /* ownQdmaChannels */
 363                                 /* 31     0 */
 364                                 {0x000000FFu},
 365
 366                                 /* ownTccs */
 367                                 /* 31     0     63    32 */
 368                                 {0xFFFFFFFFu, 0xFFFFFFFFu},
 369
 370                                 /* resvdPaRAMSets */
 371                                 /* 31     0     63    32     95    64     127   96 */
 372                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 373                                 /* 159  128     191  160     223  192     255  224 */
 374                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 375                                 /* 287  256     319  288     351  320     383  352 */
 376                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 377                                 /* 415  384     447  416     479  448     511  480 */
 378                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 379
 380                                 /* resvdDmaChannels */
 381                                 /* 31     0     63    32 */
 382                                 {0x00000000u, 0x00000000u},
 383
 384                                 /* resvdQdmaChannels */
 385                                 /* 31     0 */
 386                                 {0x00000000u},
 387
 388                                 /* resvdTccs */
 389                                 /* 31     0     63    32 */
 390                                 {0x00000000u, 0x00000000u},
 391                         },
 392
 393                 /* Resources owned/reserved by region 2 */
 394                         {
 395                                 /* ownPaRAMSets */
 396                                 /* 31     0     63    32     95    64     127   96 */
 397                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 398                                 /* 159  128     191  160     223  192     255  224 */
 399                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 400                                 /* 287  256     319  288     351  320     383  352 */
 401                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 402                                 /* 415  384     447  416     479  448     511  480 */
 403                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 404
 405                                 /* ownDmaChannels */
 406                                 /* 31     0     63    32 */
 407                                 {0x00000000u, 0x00000000u},
 408
 409                                 /* ownQdmaChannels */
 410                                 /* 31     0 */
 411                                 {0x00000000u},
 412
 413                                 /* ownTccs */
 414                                 /* 31     0     63    32 */
 415                                 {0x00000000u, 0x00000000u},
 416
 417                                 /* resvdPaRAMSets */
 418                                 /* 31     0     63    32     95    64     127   96 */
 419                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 420                                 /* 159  128     191  160     223  192     255  224 */
 421                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 422                                 /* 287  256     319  288     351  320     383  352 */
 423                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 424                                 /* 415  384     447  416     479  448     511  480 */
 425                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 426
 427                                 /* resvdDmaChannels */
 428                                 /* 31     0     63    32 */
 429                                 {0x00000000u, 0x00000000u},
 430
 431                                 /* resvdQdmaChannels */
 432                                 /* 31     0 */
 433                                 {0x00000000u},
 434
 435                                 /* resvdTccs */
 436                                 /* 31     0     63    32 */
 437                                 {0x00000000u, 0x00000000u},
 438                         },
 439
 440                 /* Resources owned/reserved by region 3 */
 441                         {
 442                                 /* ownPaRAMSets */
 443                                 /* 31     0     63    32     95    64     127   96 */
 444                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 445                                 /* 159  128     191  160     223  192     255  224 */
 446                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 447                                 /* 287  256     319  288     351  320     383  352 */
 448                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 449                                 /* 415  384     447  416     479  448     511  480 */
 450                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 451
 452                                 /* ownDmaChannels */
 453                                 /* 31     0     63    32 */
 454                                 {0x00000000u, 0x00000000u},
 455
 456                                 /* ownQdmaChannels */
 457                                 /* 31     0 */
 458                                 {0x00000000u},
 459
 460                                 /* ownTccs */
 461                                 /* 31     0     63    32 */
 462                                 {0x00000000u, 0x00000000u},
 463
 464                                 /* resvdPaRAMSets */
 465                                 /* 31     0     63    32     95    64     127   96 */
 466                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 467                                 /* 159  128     191  160     223  192     255  224 */
 468                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 469                                 /* 287  256     319  288     351  320     383  352 */
 470                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 471                                 /* 415  384     447  416     479  448     511  480 */
 472                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 473
 474                                 /* resvdDmaChannels */
 475                                 /* 31     0     63    32 */
 476                                 {0x00000000u, 0x00000000u},
 477
 478                                 /* resvdQdmaChannels */
 479                                 /* 31     0 */
 480                                 {0x00000000u},
 481
 482                                 /* resvdTccs */
 483                                 /* 31     0     63    32 */
 484                                 {0x00000000u, 0x00000000u},
 485                         },
 486
 487                 /* Resources owned/reserved by region 4 */
 488                         {
 489                                 /* ownPaRAMSets */
 490                                 /* 31     0     63    32     95    64     127   96 */
 491                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 492                                 /* 159  128     191  160     223  192     255  224 */
 493                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 494                                 /* 287  256     319  288     351  320     383  352 */
 495                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 496                                 /* 415  384     447  416     479  448     511  480 */
 497                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 498
 499                                 /* ownDmaChannels */
 500                                 /* 31     0     63    32 */
 501                                 {0x00000000u, 0x00000000u},
 502
 503                                 /* ownQdmaChannels */
 504                                 /* 31     0 */
 505                                 {0x00000000u},
 506
 507                                 /* ownTccs */
 508                                 /* 31     0     63    32 */
 509                                 {0x00000000u, 0x00000000u},
 510
 511                                 /* resvdPaRAMSets */
 512                                 /* 31     0     63    32     95    64     127   96 */
 513                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 514                                 /* 159  128     191  160     223  192     255  224 */
 515                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 516                                 /* 287  256     319  288     351  320     383  352 */
 517                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 518                                 /* 415  384     447  416     479  448     511  480 */
 519                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 520
 521                                 /* resvdDmaChannels */
 522                                 /* 31     0     63    32 */
 523                                 {0x00000000u, 0x00000000u},
 524
 525                                 /* resvdQdmaChannels */
 526                                 /* 31     0 */
 527                                 {0x00000000u},
 528
 529                                 /* resvdTccs */
 530                                 /* 31     0     63    32 */
 531                                 {0x00000000u, 0x00000000u},
 532                         },
 533
 534                 /* Resources owned/reserved by region 5 */
 535                         {
 536                                 /* ownPaRAMSets */
 537                                 /* 31     0     63    32     95    64     127   96 */
 538                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 539                                 /* 159  128     191  160     223  192     255  224 */
 540                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 541                                 /* 287  256     319  288     351  320     383  352 */
 542                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 543                                 /* 415  384     447  416     479  448     511  480 */
 544                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 545
 546                                 /* ownDmaChannels */
 547                                 /* 31     0     63    32 */
 548                                 {0x00000000u, 0x00000000u},
 549
 550                                 /* ownQdmaChannels */
 551                                 /* 31     0 */
 552                                 {0x00000000u},
 553
 554                                 /* ownTccs */
 555                                 /* 31     0     63    32 */
 556                                 {0x00000000u, 0x00000000u},
 557
 558                                 /* resvdPaRAMSets */
 559                                 /* 31     0     63    32     95    64     127   96 */
 560                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 561                                 /* 159  128     191  160     223  192     255  224 */
 562                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 563                                 /* 287  256     319  288     351  320     383  352 */
 564                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 565                                 /* 415  384     447  416     479  448     511  480 */
 566                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 567
 568                                 /* resvdDmaChannels */
 569                                 /* 31     0     63    32 */
 570                                 {0x00000000u, 0x00000000u},
 571
 572                                 /* resvdQdmaChannels */
 573                                 /* 31     0 */
 574                                 {0x00000000u},
 575
 576                                 /* resvdTccs */
 577                                 /* 31     0     63    32 */
 578                                 {0x00000000u, 0x00000000u},
 579                         },
 580
 581                 /* Resources owned/reserved by region 6 */
 582                         {
 583                                 /* ownPaRAMSets */
 584                                 /* 31     0     63    32     95    64     127   96 */
 585                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 586                                 /* 159  128     191  160     223  192     255  224 */
 587                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 588                                 /* 287  256     319  288     351  320     383  352 */
 589                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 590                                 /* 415  384     447  416     479  448     511  480 */
 591                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 592
 593                                 /* ownDmaChannels */
 594                                 /* 31     0     63    32 */
 595                                 {0x00000000u, 0x00000000u},
 596
 597                                 /* ownQdmaChannels */
 598                                 /* 31     0 */
 599                                 {0x00000000u},
 600
 601                                 /* ownTccs */
 602                                 /* 31     0     63    32 */
 603                                 {0x00000000u, 0x00000000u},
 604
 605                                 /* resvdPaRAMSets */
 606                                 /* 31     0     63    32     95    64     127   96 */
 607                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 608                                 /* 159  128     191  160     223  192     255  224 */
 609                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 610                                 /* 287  256     319  288     351  320     383  352 */
 611                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 612                                 /* 415  384     447  416     479  448     511  480 */
 613                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 614
 615                                 /* resvdDmaChannels */
 616                                 /* 31     0     63    32 */
 617                                 {0x00000000u, 0x00000000u},
 618
 619                                 /* resvdQdmaChannels */
 620                                 /* 31     0 */
 621                                 {0x00000000u},
 622
 623                                 /* resvdTccs */
 624                                 /* 31     0     63    32 */
 625                                 {0x00000000u, 0x00000000u},
 626                         },
 627
 628                 /* Resources owned/reserved by region 7 */
 629                         {
 630                                 /* ownPaRAMSets */
 631                                 /* 31     0     63    32     95    64     127   96 */
 632                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 633                                 /* 159  128     191  160     223  192     255  224 */
 634                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 635                                 /* 287  256     319  288     351  320     383  352 */
 636                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 637                                 /* 415  384     447  416     479  448     511  480 */
 638                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 639
 640                                 /* ownDmaChannels */
 641                                 /* 31     0     63    32 */
 642                                 {0x00000000u, 0x00000000u},
 643
 644                                 /* ownQdmaChannels */
 645                                 /* 31     0 */
 646                                 {0x00000000u},
 647
 648                                 /* ownTccs */
 649                                 /* 31     0     63    32 */
 650                                 {0x00000000u, 0x00000000u},
 651
 652                                 /* resvdPaRAMSets */
 653                                 /* 31     0     63    32     95    64     127   96 */
 654                                 {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 655                                 /* 159  128     191  160     223  192     255  224 */
 656                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 657                                 /* 287  256     319  288     351  320     383  352 */
 658                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
 659                                 /* 415  384     447  416     479  448     511  480 */
 660                                  0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 661
 662                                 /* resvdDmaChannels */
 663                                 /* 31     0     63    32 */
 664                                 {0x00000000u, 0x00000000u},
 665
 666                                 /* resvdQdmaChannels */
 667                                 /* 31     0 */
 668                                 {0x00000000u},
 669
 670                                 /* resvdTccs */
 671                                 /* 31     0     63    32 */
 672                                 {0x00000000u, 0x00000000u},
 673                         },
 674             },
 675         };
 676 /**
 677  * Variable which will be used internally for referring mcbsp Xmt
 678  * interrupt.
 679  */
 680 unsigned int ccMcbspXmtInt[CSL_MCBSP_PER_CNT] = {
 681                                                                                         CSL_INTC0_XINT0,
 682                                                                                         CSL_INTC0_XINT1
 683                                                                                                 };
 684 /**
 685  * Variable which will be used internally for referring mcbsp Recv
 686  * interrupt.
 687  */
 688 unsigned int ccMcbspRcvInt[CSL_MCBSP_PER_CNT] = {
 689                                                                                         CSL_INTC0_RINT0,
 690                                                                                         CSL_INTC0_RINT1
 691                                                                                                 };
 692 /* End of File */