1 /*
2 * sample_tci6616_int_reg.c
3 *
4 * Platform specific interrupt registration and un-registration routines.
5 *
6 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
39 #include <ti/sysbios/knl/Semaphore.h>
40 #include <ti/sysbios/family/c64p/Hwi.h>
41 #include <ti/sysbios/family/c64p/EventCombiner.h>
42 #include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
44 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
46 #include <ti/csl/csl_edma3.h>
47 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
48 extern unsigned int ccErrorInt[];
49 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
50 extern unsigned int numEdma3Tc[];
52 void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
53 {
54 &lisrEdma3TC0ErrHandler0,
55 &lisrEdma3TC1ErrHandler0,
56 &lisrEdma3TC2ErrHandler0,
57 &lisrEdma3TC3ErrHandler0,
58 &lisrEdma3TC4ErrHandler0,
59 &lisrEdma3TC5ErrHandler0,
60 &lisrEdma3TC6ErrHandler0,
61 &lisrEdma3TC7ErrHandler0,
62 };
63 #if 0
64 unsigned int hwiInterrupt = 8;
66 /* Host interrupts for transfer completion */
67 //unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
68 unsigned int ccXferHostInt[3][4] = {
69 {32, 24u, 40u, 56u},
70 {9u, 25u, 41u, 57u},
71 {10u, 26u, 42u, 58u},
72 };
73 unsigned int edma3ErrHostInt[3][4] = {
74 {33, 27u, 43u, 59u},
75 {12u, 28u, 44u, 60u},
76 {13u, 29u, 45u, 61u},
77 };
80 extern unsigned int dsp_num;
82 /** To Register the ISRs with the underlying OS, if required */
83 void registerEdma3Interrupts (unsigned int edma3Id)
84 {
85 static UInt32 cookie = 0;
86 Int eventId = 0; /* GEM event id */
87 unsigned int numTc = 0;
89 /* Disabling the global interrupts */
90 cookie = Hwi_disable();
91 #if 0
92 /* Transfer completion ISR */
93 #if 0
94 CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
95 lisrEdma3ComplHandler0,
96 edma3Id,
97 TRUE);
98 CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num],
99 ccXferHostInt[edma3Id][dsp_num]);
100 CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
101 #else
102 // Map system interrupt 15 to host interrupt 8
103 CpIntc_mapSysIntToHostInt(0, 0x88, 32);
105 // Plug the function for event #15
106 CpIntc_dispatchPlug(0x88, lisrEdma3ComplHandler0,edma3Id,TRUE);
108 // Enable host interrupt #8
109 CpIntc_enableHostInt(0,32); // enable host interrupt 8
110 #endif
111 eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
112 eventId = 0x30;
113 EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
114 ccXferHostInt[edma3Id][dsp_num], TRUE);
115 EventCombiner_enableEvent(eventId);
117 /* CC Error ISR */
118 CpIntc_dispatchPlug(ccErrorInt[edma3Id], lisrEdma3CCErrHandler0,
119 edma3Id, TRUE);
120 CpIntc_mapSysIntToHostInt(0, ccErrorInt[edma3Id],
121 edma3ErrHostInt[edma3Id][dsp_num]);
122 /* TC Error ISR */
123 while (numTc < numEdma3Tc[edma3Id])
124 {
125 CpIntc_dispatchPlug(tcErrorInt[edma3Id][numTc],
126 (CpIntc_FuncPtr )(ptrEdma3TcIsrHandler[numTc]),
127 edma3Id, TRUE);
128 CpIntc_mapSysIntToHostInt(0, tcErrorInt[edma3Id][numTc],
129 edma3ErrHostInt[edma3Id][dsp_num]);
130 numTc++;
131 }
132 /* Enable the host interrupt which is common for both CC and TC error */
133 CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
134 eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
135 eventId = 0x31;
136 EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
137 edma3ErrHostInt[edma3Id][dsp_num], TRUE);
138 EventCombiner_enableEvent(eventId);
140 Hwi_enableInterrupt(hwiInterrupt);
141 #else
143 /* enable the 'global' switch */
144 CpIntc_enableAllHostInts(0);
145 {
146 Hwi_Params params;
147 CpIntc_mapSysIntToHostInt(0, 0x88, 32); // I picked host int 32 for CPINTC #0. CPINTC #1 is for cores 4-7
148 CpIntc_dispatchPlug(0x88, lisrEdma3ComplHandler0, 0, TRUE); // the 'arg' parameter could be anything, doesn't have to be 149
149 CpIntc_enableHostInt(0, 32); // CPINT #0 is for cores 0-3, CPINTC #1 is for cores 4-7
150 eventId = CpIntc_getEventId(32); // this should return the GEM event 21 (This was a bug fixed in 6.32.04)
151 eventId = 0x30;
152 Hwi_Params_init(¶ms);
153 params.arg = 32; // required to be the host interrupt #
154 params.eventId = eventId;
155 params.enableInt = TRUE;
156 Hwi_create(8, &CpIntc_dispatch, ¶ms, NULL); // create ISR to handle this event in Hwi vector 8
158 }
159 #endif
160 /* Restore interrupts */
161 Hwi_restore(cookie);
162 }
164 /** To Unregister the ISRs with the underlying OS, if previously registered. */
165 void unregisterEdma3Interrupts (unsigned int edma3Id)
166 {
167 static UInt32 cookie = 0;
168 Int eventId = 0; /* GEM event id */
170 /* Disabling the global interrupts */
171 cookie = Hwi_disable();
173 /* Transfer completion ISR */
174 CpIntc_disableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
175 eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
176 EventCombiner_disableEvent(eventId);
178 /* CC/TC Error ISR */
179 CpIntc_disableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
180 eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
181 EventCombiner_disableEvent(eventId);
183 /* Restore interrupts */
184 Hwi_restore(cookie);
185 }
187 #else
188 /** To Register the ISRs with the underlying OS, if required. */
189 void registerEdma3Interrupts (unsigned int edma3Id)
190 {
191 static UInt32 cookie = 0;
192 unsigned int eventId,numTc = 0;
193 Hwi_Params params;
195 /* Disabling the global interrupts */
196 cookie = Hwi_disable();
198 /* Enable the Xfer Completion Event Interrupt */
199 EventCombiner_dispatchPlug(6,
200 (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
201 edma3Id, 1);
202 EventCombiner_enableEvent(6);
204 Hwi_enableInterrupt(7);
206 # if 0
207 /* Map the EDMA Region 0 transfer complete interrupt to the EDMA ISR Handler. */
208 CpIntc_dispatchPlug(0x88, (CpIntc_FuncPtr)lisrEdma3ComplHandler0, 0, TRUE);
210 /* The configuration is for CPINTC0. We map system interrupt 0x88 to Host Interrupt 32. */
211 CpIntc_mapSysIntToHostInt(0, 0x88, 32);
213 /* Enable the Host Interrupt. */
214 CpIntc_enableHostInt(0, 32);
216 /* Enable the System Interrupt */
217 CpIntc_enableSysInt(0, 0x88);
219 /* Get the event id associated with the host interrupt. */
220 eventId = 0x30;
221 /* enable the 'global' switch */
223 /* Enable the Xfer Completion Event Interrupt */
224 EventCombiner_dispatchPlug(0x30,
225 (EventCombiner_FuncPtr)(&CpIntc_dispatch),
226 32, 1);
227 EventCombiner_enableEvent(0x30);
229 /* Map the EDMA CC error interrupt to the EDMA ISR Handler. */
230 CpIntc_dispatchPlug(0x99, (CpIntc_FuncPtr)lisrEdma3ComplHandler0, 0, TRUE);
232 /* The configuration is for CPINTC0. We map system interrupt 0x99 to Host Interrupt 33. */
233 CpIntc_mapSysIntToHostInt(0, 0x99, 33);
235 /* Enable the Host Interrupt. */
236 CpIntc_enableHostInt(0, 33);
238 /* Enable the System Interrupt */
239 CpIntc_enableSysInt(0, 0x99);
241 /* Get the event id associated with the host interrupt. */
242 eventId = 0x31;
243 /* enable the 'global' switch */
245 /* Enable the Xfer Completion Event Interrupt */
246 EventCombiner_dispatchPlug(0x31,
247 (EventCombiner_FuncPtr)(&CpIntc_dispatch),
248 33, 1);
249 EventCombiner_enableEvent(0x31);
251 /* Map the EDMA TC error interrupt to the EDMA ISR Handler. */
252 CpIntc_dispatchPlug(0x9e, (CpIntc_FuncPtr)lisrEdma3ComplHandler0, 0, TRUE);
254 /* The configuration is for CPINTC0. We map system interrupt 0x9e to Host Interrupt 34. */
255 CpIntc_mapSysIntToHostInt(0, 0x9e, 34);
257 /* Enable the Host Interrupt. */
258 CpIntc_enableHostInt(0, 34);
260 /* Enable the System Interrupt */
261 CpIntc_enableSysInt(0, 0x9e);
263 /* Get the event id associated with the host interrupt. */
264 eventId = 0x32;
265 /* enable the 'global' switch */
267 /* Enable the Xfer Completion Event Interrupt */
268 EventCombiner_dispatchPlug(0x32,
269 (EventCombiner_FuncPtr)(&CpIntc_dispatch),
270 34, 1);
271 EventCombiner_enableEvent(0x32);
275 CpIntc_enableAllHostInts(0);
276 Hwi_enableInterrupt(8);
279 #endif
281 /* Restore interrupts */
282 Hwi_restore(cookie);
283 }
285 /** To Unregister the ISRs with the underlying OS, if previously registered. */
286 void unregisterEdma3Interrupts (unsigned int edma3Id)
287 {
288 static UInt32 cookie = 0;
289 unsigned int numTc = 0;
291 /* Disabling the global interrupts */
292 cookie = Hwi_disable();
294 /* Disable the Xfer Completion Event Interrupt */
295 EventCombiner_disableEvent(ccXferCompInt[edma3Id][0]);
297 /* Disable the CC Error Event Interrupt */
298 EventCombiner_disableEvent(ccErrorInt[edma3Id]);
300 /* Enable the TC Error Event Interrupt, according to the number of TCs. */
301 while (numTc < numEdma3Tc[edma3Id])
302 {
303 EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
304 numTc++;
305 }
307 /* Restore interrupts */
308 Hwi_restore(cookie);
309 }
310 #endif