Fixing the loopback test issue on C6657
[keystone-rtos/mcbsp-lld.git] / example / c6657 / MCBSPDigLpbk / sample_c6657_int_reg.c
index 47b68be7a8b0f9dea225ca4f701237943c16eedb..a727019c7d7d85cc72f13c4d3461e7f7b1b6b81d 100644 (file)
@@ -1,9 +1,9 @@
 /*
- * sample_tci6616_int_reg.c
+ * sample_c6657_int_reg.c
  *
  * Platform specific interrupt registration and un-registration routines.
  *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
  *
  *
  *  Redistribution and use in source and binary forms, with or without
@@ -43,7 +43,6 @@
 
 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
 
-#include <ti/csl/csl_edma3.h>
 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
 extern unsigned int ccErrorInt[];
 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
@@ -60,20 +59,16 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
                                                 &lisrEdma3TC6ErrHandler0,
                                                 &lisrEdma3TC7ErrHandler0,
                                                 };
-#if 0
+
 unsigned int hwiInterrupt = 8;
 
 /* Host interrupts for transfer completion */
 //unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
-unsigned int ccXferHostInt[3][4] = {
-                                                                               {32, 24u, 40u, 56u},
-                                                                               {9u, 25u, 41u, 57u},
-                                                                               {10u, 26u, 42u, 58u},
+unsigned int ccXferHostInt[1][2] = {
+                                                                               {0u, 20u},
                                                                                };
-unsigned int edma3ErrHostInt[3][4] = {
-                                                                               {33, 27u, 43u, 59u},
-                                                                               {12u, 28u, 44u, 60u},
-                                                                               {13u, 29u, 45u, 61u},
+unsigned int edma3ErrHostInt[1][2] = {
+                                                                               {1u, 21u},
                                                                                };
 
 
@@ -88,9 +83,8 @@ void registerEdma3Interrupts (unsigned int edma3Id)
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
-#if 0
+
        /* Transfer completion ISR */
-#if 0
        CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
                                                lisrEdma3ComplHandler0,
                                                edma3Id,
@@ -98,18 +92,7 @@ void registerEdma3Interrupts (unsigned int edma3Id)
        CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num],
                                                                ccXferHostInt[edma3Id][dsp_num]);
        CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
-#else
-       // Map system interrupt 15 to host interrupt 8
-       CpIntc_mapSysIntToHostInt(0, 0x88, 32);
-
-       // Plug the function for event #15
-       CpIntc_dispatchPlug(0x88, lisrEdma3ComplHandler0,edma3Id,TRUE);
-
-       // Enable host interrupt #8
-       CpIntc_enableHostInt(0,32); // enable host interrupt 8
-#endif
     eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
-    eventId = 0x30;
     EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
                                 ccXferHostInt[edma3Id][dsp_num], TRUE);
        EventCombiner_enableEvent(eventId);
@@ -132,31 +115,15 @@ void registerEdma3Interrupts (unsigned int edma3Id)
        /* Enable the host interrupt which is common for both CC and TC error */
        CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
     eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
-    eventId = 0x31;
     EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
                                 edma3ErrHostInt[edma3Id][dsp_num], TRUE);
        EventCombiner_enableEvent(eventId);
 
     Hwi_enableInterrupt(hwiInterrupt);
-#else
 
     /* enable the 'global' switch */
     CpIntc_enableAllHostInts(0);
-    {
-        Hwi_Params params;
-       CpIntc_mapSysIntToHostInt(0, 0x88, 32);                 // I picked host int 32 for CPINTC #0.  CPINTC #1 is for cores 4-7
-           CpIntc_dispatchPlug(0x88, lisrEdma3ComplHandler0, 0, TRUE);   //  the 'arg' parameter could be anything, doesn't have to be 149
-           CpIntc_enableHostInt(0, 32);                                     // CPINT #0 is for cores 0-3, CPINTC #1 is for cores 4-7
-           eventId = CpIntc_getEventId(32);                               // this should return the GEM event 21 (This was a bug fixed in 6.32.04)
-           eventId = 0x30;
-           Hwi_Params_init(&params);
-           params.arg = 32;                                       // required to be the host interrupt #
-           params.eventId = eventId;
-           params.enableInt = TRUE;
-           Hwi_create(8, &CpIntc_dispatch, &params, NULL); // create ISR to handle this event in Hwi vector 8
 
-    }
-#endif
     /* Restore interrupts */
     Hwi_restore(cookie);
     }
@@ -184,127 +151,3 @@ void unregisterEdma3Interrupts (unsigned int edma3Id)
     Hwi_restore(cookie);
     }
 
-#else
-/**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
-    {
-    static UInt32 cookie = 0;
-    unsigned int eventId,numTc = 0;
-    Hwi_Params params;
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    /* Enable the Xfer Completion Event Interrupt */
-    EventCombiner_dispatchPlug(6,
-                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
-                               edma3Id, 1);
-    EventCombiner_enableEvent(6);
-
-    Hwi_enableInterrupt(7);
-
-# if 0
-    /* Map the EDMA Region 0 transfer complete interrupt to the EDMA ISR Handler. */
-    CpIntc_dispatchPlug(0x88, (CpIntc_FuncPtr)lisrEdma3ComplHandler0, 0, TRUE);
-
-    /* The configuration is for CPINTC0. We map system interrupt 0x88 to Host Interrupt 32. */
-    CpIntc_mapSysIntToHostInt(0, 0x88, 32);
-
-    /* Enable the Host Interrupt. */
-    CpIntc_enableHostInt(0, 32);
-
-    /* Enable the System Interrupt */
-    CpIntc_enableSysInt(0, 0x88);
-
-    /* Get the event id associated with the host interrupt. */
-    eventId = 0x30;
-    /* enable the 'global' switch */
-
-   /* Enable the Xfer Completion Event Interrupt */
-        EventCombiner_dispatchPlug(0x30,
-                                                       (EventCombiner_FuncPtr)(&CpIntc_dispatch),
-                               32, 1);
-        EventCombiner_enableEvent(0x30);
-
-        /* Map the EDMA CC error interrupt to the EDMA ISR Handler. */
-            CpIntc_dispatchPlug(0x99, (CpIntc_FuncPtr)lisrEdma3ComplHandler0, 0, TRUE);
-
-            /* The configuration is for CPINTC0. We map system interrupt 0x99 to Host Interrupt 33. */
-            CpIntc_mapSysIntToHostInt(0, 0x99, 33);
-
-            /* Enable the Host Interrupt. */
-            CpIntc_enableHostInt(0, 33);
-
-            /* Enable the System Interrupt */
-            CpIntc_enableSysInt(0, 0x99);
-
-            /* Get the event id associated with the host interrupt. */
-            eventId = 0x31;
-            /* enable the 'global' switch */
-
-           /* Enable the Xfer Completion Event Interrupt */
-                EventCombiner_dispatchPlug(0x31,
-                                                               (EventCombiner_FuncPtr)(&CpIntc_dispatch),
-                                       33, 1);
-                EventCombiner_enableEvent(0x31);
-
-                /* Map the EDMA TC error  interrupt to the EDMA ISR Handler. */
-                           CpIntc_dispatchPlug(0x9e, (CpIntc_FuncPtr)lisrEdma3ComplHandler0, 0, TRUE);
-
-                           /* The configuration is for CPINTC0. We map system interrupt 0x9e to Host Interrupt 34. */
-                           CpIntc_mapSysIntToHostInt(0, 0x9e, 34);
-
-                           /* Enable the Host Interrupt. */
-                           CpIntc_enableHostInt(0, 34);
-
-                           /* Enable the System Interrupt */
-                           CpIntc_enableSysInt(0, 0x9e);
-
-                           /* Get the event id associated with the host interrupt. */
-                           eventId = 0x32;
-                           /* enable the 'global' switch */
-
-                          /* Enable the Xfer Completion Event Interrupt */
-                               EventCombiner_dispatchPlug(0x32,
-                                                                               (EventCombiner_FuncPtr)(&CpIntc_dispatch),
-                                                       34, 1);
-                               EventCombiner_enableEvent(0x32);
-
-
-
-        CpIntc_enableAllHostInts(0);
-        Hwi_enableInterrupt(8);
-
-
-#endif
-
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
-    {
-       static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    /* Disable the Xfer Completion Event Interrupt */
-       EventCombiner_disableEvent(ccXferCompInt[edma3Id][0]);
-
-    /* Disable the CC Error Event Interrupt */
-       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
-
-    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
-    while (numTc < numEdma3Tc[edma3Id])
-       {
-        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
-        numTc++;
-       }
-
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-#endif