X-Git-Url: https://git.ti.com/gitweb?p=keystone-rtos%2Fmcbsp-lld.git;a=blobdiff_plain;f=example%2Fc6657%2FMCBSPDigLpbk%2Fsample_c6657_cfg.c;h=b698e98d206b678fb3b4e7f11bb723f8f7ebd640;hp=36e4e45b894b412debfc09a34ea6e96fedd0a16c;hb=8a3ccc20a3f7dd9bfa4df622695d66150a27e3da;hpb=12ba6ab5d788fc5071a275a0aef8ab4f52979f14 diff --git a/example/c6657/MCBSPDigLpbk/sample_c6657_cfg.c b/example/c6657/MCBSPDigLpbk/sample_c6657_cfg.c index 36e4e45..b698e98 100644 --- a/example/c6657/MCBSPDigLpbk/sample_c6657_cfg.c +++ b/example/c6657/MCBSPDigLpbk/sample_c6657_cfg.c @@ -1,11 +1,11 @@ /* - * sample_galileo_cfg.c + * sample_c6657_cfg.c * * Platform specific EDMA3 hardware related information like number of transfer * controllers, various interrupt ids etc. It is used while interrupts * enabling / disabling. It needs to be ported for different SoCs. * - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ * * * Redistribution and use in source and binary forms, with or without @@ -41,11 +41,11 @@ #include /* Number of EDMA3 controllers present in the system */ -#define NUM_EDMA3_INSTANCES 2u +#define NUM_EDMA3_INSTANCES 1u const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES; /* Number of DSPs present in the system */ -#define NUM_DSPS 1u +#define NUM_DSPS 2u //const unsigned int numDsps = NUM_DSPS; #define CGEM_REG_START (0x01800000) @@ -85,7 +85,7 @@ signed char* getGlobalAddr(signed char* addr) */ unsigned int gblCfgReqdArray [NUM_DSPS] = { 0, /* DSP#0 is Master, will do the global init */ - + 1, /* DSP#1 is Slave, will not do the global init */ }; unsigned short isGblConfigRequired(unsigned int dspNum) @@ -94,14 +94,14 @@ unsigned short isGblConfigRequired(unsigned int dspNum) } /* Semaphore handles */ -EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL}; +EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL}; /* Variable which will be used internally for referring number of Event Queues. */ -unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 2u}; +unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {4u}; /* Variable which will be used internally for referring number of TCs. */ -unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 2u}; +unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {4u}; /** * Variable which will be used internally for referring transfer completion @@ -110,12 +110,8 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 2u}; */ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { { - 0x88, 0x89, 0x8a, 0x8b, - 0x8c, 0x8d, 0x8e, 0x8f, - }, - { - 0x90, 0x91, 0x92, 0x93, - 0x94, 0x95, 0x96, 0x97, + 24u, 25u, 26u, 27u, + 28u, 29u, 30u, 31u, }, }; @@ -123,7 +119,7 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { * Variable which will be used internally for referring channel controller's * error interrupt. */ -unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {0x99, 0x9c}; +unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {16u}; /** * Variable which will be used internally for referring transfer controllers' @@ -131,11 +127,7 @@ unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {0x99, 0x9c}; */ unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = { { - 0xA0,0xA1, 0u, 0u, - 0u, 0u, 0u, 0u, - }, - { - 0xA4, 0xA5, 0u, 0u, + 18u, 19u, 20u, 21u, 0u, 0u, 0u, 0u, }, }; @@ -154,9 +146,9 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = /** Total number of PaRAM Sets supported by the EDMA3 Controller */ 512u, /** Total number of Event Queues in the EDMA3 Controller */ - 2u, + 4u, /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ - 2u, + 4u, /** Number of Regions on this EDMA3 controller */ 8u, @@ -172,182 +164,28 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = 1u, /** Global Register Region of CC Registers */ - (void *)0x02700000u, + (void *)0x02740000u, /** Transfer Controller (TC) Registers */ { - (void *)0x02760000u, - (void *)0x02768000u, - (void *)NULL, - (void *)NULL, - (void *)NULL, + (void *)0x02790000u, + (void *)0x02798000u, + (void *)0x027A0000u, + (void *)0x027A8000u, (void *)NULL, (void *)NULL, (void *)NULL, + (void *)NULL }, /** Interrupt no. for Transfer Completion */ - 0x88, + 24u, /** Interrupt no. for CC Error */ - 0x99, - /** Interrupt no. for TCs Error */ - { - 0xA0, - 0xA1, - 0u, - 0u, - 0u, - 0u, - 0u, - 0u, - }, - - /** - * \brief EDMA3 TC priority setting - * - * User can program the priority of the Event Queues - * at a system-wide level. This means that the user can set the - * priority of an IO initiated by either of the TCs (Transfer Controllers) - * relative to IO initiated by the other bus masters on the - * device (ARM, DSP, USB, etc) - */ - { - 0u, - 1u, - 0u, - 0u, - 0u, - 0u, - 0u, - 0u, - }, - /** - * \brief To Configure the Threshold level of number of events - * that can be queued up in the Event queues. EDMA3CC error register - * (CCERR) will indicate whether or not at any instant of time the - * number of events queued up in any of the event queues exceeds - * or equals the threshold/watermark value that is set - * in the queue watermark threshold register (QWMTHRA). - */ - { - 16u, 16u, - 0u, - 0u, - 0u, - 0u, - 0u, - 0u, - }, - - /** - * \brief To Configure the Default Burst Size (DBS) of TCs. - * An optimally-sized command is defined by the transfer controller - * default burst size (DBS). Different TCs can have different - * DBS values. It is defined in Bytes. - */ - { - 128u, - 128u, - 0u, - 0u, - 0u, - 0u, - 0u, - 0u, - }, - - /** - * \brief Mapping from each DMA channel to a Parameter RAM set, - * if it exists, otherwise of no use. - */ - { - 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, - 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, - 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, - 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, - 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, - 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u, - 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, - 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u, - }, - - /** - * \brief Mapping from each DMA channel to a TCC. This specific - * TCC code will be returned when the transfer is completed - * on the mapped channel. - */ - { - 0u, 1u, 2u, EDMA3_RM_CH_NO_TCC_MAP, 4u, 5u, 6u, EDMA3_RM_CH_NO_TCC_MAP, - 8u, 9u, 10u, EDMA3_RM_CH_NO_TCC_MAP, 12u, 13u, 14u, EDMA3_RM_CH_NO_TCC_MAP, - 16u, 17u, 18u, EDMA3_RM_CH_NO_TCC_MAP, 20u, 21u, 22u, EDMA3_RM_CH_NO_TCC_MAP, - 24u, 25u, 26u, 27u, 28u, 29u, 30u, EDMA3_RM_CH_NO_TCC_MAP, - 32u, 33u, 34u, 35u, 36u, 37u, 38u, EDMA3_RM_CH_NO_TCC_MAP, - 40u, 41u, 42u, EDMA3_RM_CH_NO_TCC_MAP, 44u, 45u, 46u, EDMA3_RM_CH_NO_TCC_MAP, - 48u, 49u, 50u, 51u, 52u, 53u, 54u, EDMA3_RM_CH_NO_TCC_MAP, - 56u, 57u, 58u, 59u, 60u, 61u, 62u, EDMA3_RM_CH_NO_TCC_MAP - }, - - /** - * \brief Mapping of DMA channels to Hardware Events from - * various peripherals, which use EDMA for data transfer. - * All channels need not be mapped, some can be free also. - */ - { - 0x0F000000u, - 0x0000000Fu - } - }, - - { - /* EDMA3 INSTANCE# 1 */ - /** Total number of DMA Channels supported by the EDMA3 Controller */ - 64u, - /** Total number of QDMA Channels supported by the EDMA3 Controller */ - 8u, - /** Total number of TCCs supported by the EDMA3 Controller */ - 64u, - /** Total number of PaRAM Sets supported by the EDMA3 Controller */ - 512u, - /** Total number of Event Queues in the EDMA3 Controller */ - 2u, - /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */ - 2u, - /** Number of Regions on this EDMA3 controller */ - 8u, - - /** - * \brief Channel mapping existence - * A value of 0 (No channel mapping) implies that there is fixed association - * for a channel number to a parameter entry number or, in other words, - * PaRAM entry n corresponds to channel n. - */ - 1u, - - /** Existence of memory protection feature */ - 1u, - - /** Global Register Region of CC Registers */ - (void *)0x02728000U, - /** Transfer Controller (TC) Registers */ - { - (void *)0x027b0000U, - (void *)0x027b8000U, - (void *)NULL, - (void *)NULL, - (void *)NULL, - (void *)NULL, - (void *)NULL, - (void *)NULL, - }, - /** Interrupt no. for Transfer Completion */ - 0x90, - /** Interrupt no. for CC Error */ - 0x9c, /** Interrupt no. for TCs Error */ { - 0xA2, - 0xA3, - 0u, - 0u, + 18u, + 19u, + 20u, + 21u, 0u, 0u, 0u, @@ -366,8 +204,8 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = { 0u, 1u, - 0u, - 0u, + 2u, + 3u, 0u, 0u, 0u, @@ -384,8 +222,8 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = { 16u, 16u, - 0u, - 0u, + 16u, + 16u, 0u, 0u, 0u, @@ -401,8 +239,8 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = { 64u, 64u, - 0u, - 0u, + 64u, + 64u, 0u, 0u, 0u, @@ -414,14 +252,38 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = * if it exists, otherwise of no use. */ { - 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, - 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, - 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, - 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, - 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, - 40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u, - 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, - 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, + EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP }, /** @@ -431,13 +293,15 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = */ { 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u, - 8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u, 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u, - 24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u, 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u, - 40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, - 48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u, - 56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, + 56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u }, /** @@ -446,148 +310,53 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] = * All channels need not be mapped, some can be free also. */ { - 0x00000000u, - 0xFFF00000u + 0xFFFFFFFFu, + 0xFF0000FFu } }, - }; EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = { /* EDMA3 INSTANCE# 0 */ { - /* Resources owned/reserved by region 0 */ + /* Resources owned/reserved by region 0 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000FFFu, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, - - /* ownDmaChannels */ - /* 31 0 63 32 */ - {0x0f00000Fu, 0x0000000Fu}, - - /* ownQdmaChannels */ - /* 31 0 */ - {0x00000003u}, - - /* ownTccs */ - /* 31 0 63 32 */ - {0x0f00000Fu, 0x000000FFu}, - - /* resvdPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u, + {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, - /* resvdDmaChannels */ - /* 31 0 */ - {0x00000003u, 0x00000000u}, - - /* resvdQdmaChannels */ - /* 31 0 */ - {0x00000000u}, - - /* resvdTccs */ - /* 31 0 */ - {0x00000003u, 0x00000000u}, - }, - - /* Resources owned/reserved by region 1 */ - { - /* ownPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, - /* ownDmaChannels */ /* 31 0 63 32 */ - {0x000000F0u, 0x00000000u}, + {0x00000000u, 0x0000FF00u}, /* ownQdmaChannels */ /* 31 0 */ - {0x0000000Cu}, + {0x0000000Fu}, /* ownTccs */ /* 31 0 63 32 */ - {0x000000F0u, 0x00000000u}, + {0x00000000u, 0x0000FFF0u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u, + {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, - - /* resvdDmaChannels */ - /* 31 0 63 32 */ - {0x00000030u, 0x00000000u}, - - /* resvdQdmaChannels */ - /* 31 0 */ - {0x00000000u}, - - /* resvdTccs */ - /* 31 0 63 32 */ - {0x00000030u, 0x00000000u}, - }, - - /* Resources owned/reserved by region 2 */ - { - /* ownPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, - - /* ownDmaChannels */ - /* 31 0 63 32 */ - {0x00000F00u, 0x00000000u}, - - /* ownQdmaChannels */ - /* 31 0 */ - {0x00000030u}, - - /* ownTccs */ - /* 31 0 63 32 */ - {0x00000F00u, 0x00000000u}, - - /* resvdPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* resvdDmaChannels */ /* 31 0 63 32 */ - {0x00000300u, 0x00000000u}, + {0xFFFFFFFFu, 0xFF0000FFu}, /* resvdQdmaChannels */ /* 31 0 */ @@ -595,46 +364,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_ /* resvdTccs */ /* 31 0 63 32 */ - {0x00000300u, 0x00000000u}, + {0xFFFFFFFFu, 0xFF0000FFu}, }, - /* Resources owned/reserved by region 3 */ + /* Resources owned/reserved by region 1 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFF000u, + {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, + 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,}, /* ownDmaChannels */ /* 31 0 63 32 */ - {0x0000F000u, 0x00000000u}, + {0x00000000u, 0x00FF0000u}, /* ownQdmaChannels */ /* 31 0 */ - {0x000000C0u}, + {0x000000F0u}, /* ownTccs */ /* 31 0 63 32 */ - {0x0000F000u, 0x00000000u}, + {0x00000000u, 0x00FF0000u}, /* resvdPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u, + {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 287 256 319 288 351 320 383 352 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, + 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, /* resvdDmaChannels */ /* 31 0 63 32 */ - {0x00003000u, 0x00000000u}, + {0xFFFFFFFFu, 0xFF0000FFu}, /* resvdQdmaChannels */ /* 31 0 */ @@ -642,35 +411,13 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_ /* resvdTccs */ /* 31 0 63 32 */ - {0x00003000u, 0x00000000u}, + {0xFFFFFFFFu, 0xFF0000FFu}, }, - /* Resources owned/reserved by region 4 */ + /* Resources owned/reserved by region 2 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, - - /* ownDmaChannels */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, - - /* ownQdmaChannels */ - /* 31 0 */ - {0x00000000u}, - - /* ownTccs */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, - - /* resvdPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, @@ -679,31 +426,6 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_ /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, - /* resvdDmaChannels */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, - - /* resvdQdmaChannels */ - /* 31 0 */ - {0x00000000u}, - - /* resvdTccs */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, - }, - - /* Resources owned/reserved by region 5 */ - { - /* ownPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, - /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, @@ -739,32 +461,10 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_ {0x00000000u, 0x00000000u}, }, - /* Resources owned/reserved by region 6 */ + /* Resources owned/reserved by region 3 */ { /* ownPaRAMSets */ /* 31 0 63 32 95 64 127 96 */ - {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, - - /* ownDmaChannels */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, - - /* ownQdmaChannels */ - /* 31 0 */ - {0x00000000u}, - - /* ownTccs */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, - - /* resvdPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, /* 159 128 191 160 223 192 255 224 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, @@ -773,31 +473,6 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_ /* 415 384 447 416 479 448 511 480 */ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, - /* resvdDmaChannels */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, - - /* resvdQdmaChannels */ - /* 31 0 */ - {0x00000000u}, - - /* resvdTccs */ - /* 31 0 63 32 */ - {0x00000000u, 0x00000000u}, - }, - - /* Resources owned/reserved by region 7 */ - { - /* ownPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, - /* ownDmaChannels */ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, @@ -832,197 +507,6 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_ /* 31 0 63 32 */ {0x00000000u, 0x00000000u}, }, - }, - - /* EDMA3 INSTANCE# 1 */ - { - /* Resources owned/reserved by region 0 */ - { - /* ownPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x0000FFFFu, 0x00F00000u, 0xFFFFFFFFu, 0xFFFFFFFFu, - /* 159 128 191 160 223 192 255 224 */ - 0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, - - /* ownDmaChannels */ - /* 31 0 63 32 */ - {0x0000FFFFu, 0x00F00000u}, - - /* ownQdmaChannels */ - /* 31 0 */ - {0x00000003u}, - - /* ownTccs */ - /* 31 0 63 32 */ - {0x0000FFFFu, 0x00F00000u}, - - /* resvdPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, - - /* resvdDmaChannels */ - /* 31 0 63 32 */ - {0x00003FFFu, 0x00000000u}, - - /* resvdQdmaChannels */ - /* 31 0 */ - {0x00000000u}, - - /* resvdTccs */ - /* 31 0 63 32 */ - {0x00003FFFu, 0x00000000u}, - }, - - /* Resources owned/reserved by region 1 */ - { - /* ownPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, - /* 287 256 319 288 351 320 383 352 */ - 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, - - /* ownDmaChannels */ - /* 31 0 63 32 */ - {0xFFFF0000u, 0x00000000u}, - - /* ownQdmaChannels */ - /* 31 0 */ - {0x0000000Cu}, - - /* ownTccs */ - /* 31 0 63 32 */ - {0xFFFF0000u, 0x00000000u}, - - /* resvdPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, - - /* resvdDmaChannels */ - /* 31 0 63 32 */ - {0x3FFF0000u, 0x00000000u}, - - /* resvdQdmaChannels */ - /* 31 0 */ - {0x00000000u}, - - /* resvdTccs */ - /* 31 0 63 32 */ - {0x3FFF0000u, 0x00000000u}, - }, - - /* Resources owned/reserved by region 2 */ - { - /* ownPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, - /* 415 384 447 416 479 448 511 480 */ - 0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,}, - - /* ownDmaChannels */ - /* 31 0 63 32 */ - {0x00000000u, 0x0000FFFFu}, - - /* ownQdmaChannels */ - /* 31 0 */ - {0x00000030u}, - - /* ownTccs */ - /* 31 0 63 32 */ - {0x00000000u, 0x0000FFFFu}, - - /* resvdPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, - - /* resvdDmaChannels */ - /* 31 0 63 32 */ - {0x00000000u, 0x00003FFFu}, - - /* resvdQdmaChannels */ - /* 31 0 */ - {0x00000000u}, - - /* resvdTccs */ - /* 31 0 63 32 */ - {0x00000000u, 0x00003FFFu}, - }, - - /* Resources owned/reserved by region 3 */ - { - /* ownPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,}, - - /* ownDmaChannels */ - /* 31 0 63 32 */ - {0x00000000u, 0xFFFF0000u}, - - /* ownQdmaChannels */ - /* 31 0 */ - {0x000000C0u}, - - /* ownTccs */ - /* 31 0 63 32 */ - {0x00000000u, 0xFFFF0000u}, - - /* resvdPaRAMSets */ - /* 31 0 63 32 95 64 127 96 */ - {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u, - /* 159 128 191 160 223 192 255 224 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 287 256 319 288 351 320 383 352 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, - /* 415 384 447 416 479 448 511 480 */ - 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,}, - - /* resvdDmaChannels */ - /* 31 0 63 32 */ - {0x00000000u, 0x3FFF0000u}, - - /* resvdQdmaChannels */ - /* 31 0 */ - {0x00000000u}, - - /* resvdTccs */ - /* 31 0 63 32 */ - {0x00000000u, 0x3FFF0000u}, - }, /* Resources owned/reserved by region 4 */ {