Initial OMAPL/C674 port commit
authorRPrabhu <r-prabhu@ti.com>
Wed, 31 Jan 2018 00:40:37 +0000 (18:40 -0600)
committerRPrabhu <r-prabhu@ti.com>
Wed, 31 Jan 2018 00:40:37 +0000 (18:40 -0600)
14 files changed:
build/buildlib.xs
config.bld
device/omapl138/src/device_mcbsp_loopback.c [new file with mode: 0644]
example/omapl138/MCBSPDigLpbk/MCBSP_DigLpbk_lcdkOMAPL138_c674xExampleProject.txt [new file with mode: 0644]
example/omapl138/MCBSPDigLpbk/bios6_edma3_drv_sample.h [new file with mode: 0644]
example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.c [new file with mode: 0644]
example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg [new file with mode: 0644]
example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd [new file with mode: 0644]
example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c [new file with mode: 0644]
example/omapl138/MCBSPDigLpbk/sample_cs.c [new file with mode: 0644]
example/omapl138/MCBSPDigLpbk/sample_init.c [new file with mode: 0644]
example/omapl138/MCBSPDigLpbk/sample_omapl138_cfg.c [new file with mode: 0644]
example/omapl138/MCBSPDigLpbk/sample_omapl138_int_reg.c [new file with mode: 0644]
package.xs

index a4b70bc37fa31bee45f032c75d7511709e8a12ea..a2c0d1c3b352b3a9c7de7ebe48143d8f44c77e53 100755 (executable)
@@ -257,14 +257,11 @@ function createLibMake(device, makelibname,targetname, objectPath)
       targetDir="m4";
       targetname=M4LE;
       break;
-    case String(ARM11):
-      tooldir="TI_ARM11_GEN_INSTALL_PATH"; 
-      break;
-    case String(C67LE):
+    case String(C674LE):
       tooldir="C6X_GEN_INSTALL_PATH";
       cmdprefix="";
-      targetDir="c66";
-      targetname=C67LE;
+      targetDir="c674";
+      targetname=C674LE;
       break;
 
    }
@@ -483,6 +480,10 @@ function buildLibrary (socName, isSoc, libOptions, libName, target, libFiles)
     else if (target.name == "M4")
     {
         targetDir = "m4";
+    }
+       else if (target.name == "C674")
+    {
+        targetDir = "c674/release";
     }
     else
     {
index 0ba48efeaf19862cfe0d85a01ec1880ec9cfc279..4e07c8072acac31eb5317401771ae6cdd125c3a0 100644 (file)
 
 /* Get the Tools Base directory from the Environment Variable. */
 var toolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var m4ToolsBaseDir  = java.lang.System.getenv("TOOLCHAIN_PATH_M4");
+var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15");
+var a9ToolsBaseDir  = java.lang.System.getenv("TOOLCHAIN_PATH_A9");
+var arm9ToolsBaseDir  = java.lang.System.getenv("TOOLCHAIN_PATH_ARM9");
+var a8ToolsBaseDir  = java.lang.System.getenv("TOOLCHAIN_PATH_A8");
 
 /* Get the extended debug flags */
 var extDbgFlags = java.lang.System.getenv("EXTDBGFLAGS");
+
+/* Get the extended debug flags for A15 */
+var extDbgFlags_a15 = java.lang.System.getenv("EXTDBGFLAGS_A15");
+
+/* Get the extended debug flags for A8 */
+var extDbgFlags_a8 = java.lang.System.getenv("EXTDBGFLAGS_A8");
+
+/* Get the extended debug flags for A9 */
+var extDbgFlags_a9 = java.lang.System.getenv("EXTDBGFLAGS_A9");
+
+/* Get the extended debug flags for ARM9 */
+var extDbgFlags_arm9 = java.lang.System.getenv("EXTDBGFLAGS_ARM9");
+/* Get the extended debug flags for M4 */
+var extDbgFlags_m4 = java.lang.System.getenv("EXTDBGFLAGS_M4");
+
 /* Get the base directory for the MCBSP Driver Package */
 var mcbspDriverPath = new java.io.File(".//").getPath();
 
@@ -37,11 +57,11 @@ if(extDbgFlags)
     C66LE.ccOpts.prefix = C66LE.ccOpts.prefix + " " + extDbgFlags; 
 
 /* C6740 elf compiler configuration for Little Endian Mode. */
-var C67LE           = xdc.useModule('ti.targets.elf.C674');
-C67LE.rootDir       = toolsBaseDir;
-C67LE.ccOpts.prefix = "-mo -o3 -q -k -eo.o";
+var C674LE           = xdc.useModule('ti.targets.elf.C674');
+C674LE.rootDir       = toolsBaseDir;
+C674LE.ccOpts.prefix = "-mo -o3 -q -k -eo.o";
 if(extDbgFlags)     
-    C67LE.ccOpts.prefix = C67LE.ccOpts.prefix + " " + extDbgFlags; 
+    C674LE.ccOpts.prefix = C674LE.ccOpts.prefix + " " + extDbgFlags; 
 
 /* C66 ELF compiler configuration for Big Endian Mode. */
 var C66BE           = xdc.useModule('ti.targets.elf.C66_big_endian');
@@ -50,7 +70,47 @@ C66BE.ccOpts.prefix = "-mo -o3 -q -k -eo.o -DBIGENDIAN";
 if(extDbgFlags)     
     C66BE.ccOpts.prefix = C66BE.ccOpts.prefix + " " + extDbgFlags;
 
-
+/* C674 ELF compiler configuration for Big Endian Mode. */
+var C674BE           = xdc.useModule('ti.targets.elf.C674_big_endian');
+C674BE.rootDir       = toolsBaseDir;
+C674BE.ccOpts.prefix = "-mo -o3 -q -k -eo.o -DBIGENDIAN";
+if(extDbgFlags)     
+    C674BE.ccOpts.prefix = C674BE.ccOpts.prefix + " " + extDbgFlags;
+
+/* ARMv7 A15 compiler configuration */
+var A15LE            = xdc.useModule('gnu.targets.arm.A15F');
+A15LE.rootDir        = a15ToolsBaseDir;
+A15LE.ccOpts.prefix  = "-mno-unaligned-access -c -mtune=cortex-a15 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a15)     
+    A15LE.ccOpts.prefix = A15LE.ccOpts.prefix + " " + extDbgFlags_a15; 
+    
+/* ARMv7 A9 compiler configuration */
+var A9LE            = xdc.useModule('gnu.targets.arm.A9F');
+A9LE.rootDir        = a9ToolsBaseDir;
+A9LE.ccOpts.prefix  = "-mno-unaligned-access -c -mtune=cortex-a9 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a9)     
+    A9LE.ccOpts.prefix = A9LE.ccOpts.prefix + " " + extDbgFlags_a9; 
+
+/* ARMv5 ARM9 compiler configuration */
+var ARM9LE            = xdc.useModule('ti.targets.arm.elf.Arm9');
+ARM9LE.rootDir        = arm9ToolsBaseDir;
+ARM9LE.ccOpts.prefix  = "-mno-unaligned-access -c -mtune=arm926ej-s -msoft-float -mfloat-abi=soft -march=armv5te -marm -DDRA7xx -Dxdc_target_types__=gnu/targets/arm/std.h -Dxdc_target_name__=Arm9 -gstrict-dwarf -Wall -D__ARMv5 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_arm9)     
+    ARM9LE.ccOpts.prefix = ARM9LE.ccOpts.prefix + " " + extDbgFlags_arm9; 
+       
+/* ARMv7 A8 compiler configuration */
+var A8LE            = xdc.useModule('gnu.targets.arm.A8F');
+A8LE.rootDir        = a8ToolsBaseDir;
+A8LE.ccOpts.prefix  = "-mno-unaligned-access -c -mtune=cortex-a8 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";
+if(extDbgFlags_a8)     
+    A8LE.ccOpts.prefix = A8LE.ccOpts.prefix + " " + extDbgFlags_a8; 
+
+/* M4 ELF compiler configuration for Little Endian Mode. */
+var M4LE            = xdc.useModule('ti.targets.arm.elf.M4');
+M4LE.rootDir        = m4ToolsBaseDir;
+M4LE.ccOpts.prefix  = "-o4 -qq -pdsw255 -DMAKEFILE_BUILD";
+if(extDbgFlags_m4)
+    M4LE.ccOpts.prefix = M4LE.ccOpts.prefix + " " + extDbgFlags_m4; 
 
 /* device name (k2?) is inserted between first an second element of this
    list to construct device file name for each device */
@@ -81,16 +141,16 @@ var socs = {
         /* target list */
         targets: [ C66LE, C66BE ]
     },
-    c674x :
+       omapl138 :
     {
-        /* this variable would be reinitialized to true, if XDCARGS contains c674x */
+        /* this variable would be reinitialized to true, if XDCARGS contains omapl138 */
         build: "false",
-        /* SoC lib enabled */
-        socDevLib: "true",
-        /* Library options */
-        copts: " -DSOC_C674X",
-        /* target list */
-        targets: [ C66LE, C66BE ]
+       /* SoC lib enabled */
+       socDevLib: "true",
+       /* Library options */
+       copts: " -DSOC_OMAPL138",
+       /* target list */
+       targets: [ C674LE ]
     },
     c6657 :
     {
diff --git a/device/omapl138/src/device_mcbsp_loopback.c b/device/omapl138/src/device_mcbsp_loopback.c
new file mode 100644 (file)
index 0000000..5d49109
--- /dev/null
@@ -0,0 +1,184 @@
+/*
+ * mcbsp_device.c
+ *
+ * This file contains MCBSP IP related EVM (platform) specific routines
+ * implementation. This file contains the board specific code for enabling 
+ * the use of mcbsp driver, and may contain related device pre-driver 
+ * initialization routines. The file is provided as a sample configuration 
+ * and should be modified by customers for their own platforms and 
+ * configurations.
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/* MCBSP Driver Includes. */
+#include <ti/drv/mcbsp/mcbsp_types.h>
+#include <ti/drv/mcbsp/mcbsp_drv.h>
+#include <ti/drv/mcbsp/mcbsp_osal.h>
+
+/* CSL MCBSP Register Layer */
+#include <ti/csl/cslr_mcbsp.h>
+
+/* CSL Chip Functional Layer */
+// #include <ti/csl/csl_chip.h> // no functional CSL for Freon
+#include <ti/csl/cslr_device.h>
+//#include <ti/csl/soc_OMAPL138.h>
+
+
+/*============================================================================*/
+/*                           IMPORTED VARIABLES                               */
+/*============================================================================*/
+
+extern Mcbsp_HwInfo Mcbsp_deviceInstInfo[CSL_MCBSP_CNT];
+extern Mcbsp_TempBuffer Mcbsp_muteBuf[CSL_MCBSP_CNT];
+
+#ifdef MCBSP_LOOPJOB_ENABLE
+extern Mcbsp_TempBuffer Mcbsp_loopDstBuf[CSL_MCBSP_CNT];
+extern Mcbsp_TempBuffer Mcbsp_loopSrcBuf[CSL_MCBSP_CNT];
+#endif /* MCBSP_LOOPJOB_ENABLE */
+
+/* ========================================================================== */
+/*                           MODULE FUNCTIONS                                 */
+/* ========================================================================== */
+/**
+ * \brief   Initializes McBSP driver's data structures
+ *
+ *          This function initializes the McBSP driver's data structures
+ *          including instance objects and channel objects. This is the 
+ *          MCBSP Driver Initialization API which needs to be invoked by 
+ *          the users to initialize the MCBSP peripheral. This call is 
+ *          *mandatory* and should be called before calling any of the 
+ *          other driver API's.  This can be modified by customers for 
+ *          their application and configuration.
+ *
+ * \return  None
+ */
+void McbspDevice_init(void)
+{
+    int32_t devId = 0;
+    void *key;
+
+    /* Begin Critical Section before accessing shared resources. */
+    key = Mcbsp_osalEnterMultipleCoreCriticalSection ();
+
+    /* Invalidate the Cache Contents */
+    Mcbsp_osalBeginMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo));
+
+    /* initialize the loop job buffers and the mute buffers for all instances  */
+#ifdef MCBSP_LOOPJOB_ENABLE
+    Mcbsp_osalBeginMemAccess ((void *)Mcbsp_loopDstBuf, sizeof(Mcbsp_loopDstBuf));
+    Mcbsp_osalBeginMemAccess ((void *)Mcbsp_loopSrcBuf, sizeof(Mcbsp_loopSrcBuf));
+    memset((void *)Mcbsp_loopDstBuf,0x0,
+        sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_CNT);
+    memset((void *)Mcbsp_loopSrcBuf,0x0,
+        sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_CNT);
+#endif /* MCBSP_LOOPJOB_ENABLE */
+    Mcbsp_osalBeginMemAccess ((void *)Mcbsp_muteBuf, sizeof(Mcbsp_muteBuf));
+    memset((void *)Mcbsp_muteBuf,0x0,
+        sizeof(Mcbsp_TempBuffer) * CSL_MCBSP_CNT);
+
+    /* initialize the information for all the device instances                */
+    for (devId = 0; devId < CSL_MCBSP_CNT; devId++)
+    {
+        if (0 == devId)
+        {
+            /* instance 0 initialisation                                      */
+                /* instance 0 initialisation                                      */
+                           Mcbsp_deviceInstInfo[devId].obj.instNum = (uint32_t)devId;
+                           Mcbsp_deviceInstInfo[devId].obj.regs =
+                               (CSL_McbspRegsOvly)CSL_MCBSP_0_CTRL_REGS;
+                           Mcbsp_deviceInstInfo[devId].obj.fifoRegs =
+                               (CSL_BfifoRegsOvly)CSL_MCBSP_0_FIFO_REGS;
+                           Mcbsp_deviceInstInfo[devId].obj.dataAddress =
+                               (CSL_BdataRegsOvly)CSL_MCBSP_0_DATA_REGS;
+                           Mcbsp_deviceInstInfo[devId].obj.edmaTxEventNum =
+                               (uint32_t)CSL_EDMA3_CHA_MCBSP0_TX;
+                           Mcbsp_deviceInstInfo[devId].obj.edmaRxEventNum =
+                               (uint32_t)CSL_EDMA3_CHA_MCBSP0_RX;
+                           Mcbsp_deviceInstInfo[devId].obj.cpuTxEventNum =
+                               (uint32_t)CSL_INTC_EVENTID_MCBSP0_TXINT ;
+                           Mcbsp_deviceInstInfo[devId].obj.cpuRxEventNum =
+                               (uint32_t)CSL_INTC_EVENTID_MCBSP0_RXINT ;
+                       }
+                       else if (1 == devId)
+                       {
+                           /* instance 1 initialisation                                      */
+                           Mcbsp_deviceInstInfo[devId].obj.instNum = (uint32_t)devId;
+                           Mcbsp_deviceInstInfo[devId].obj.regs =
+                               (CSL_McbspRegsOvly)CSL_MCBSP_1_CTRL_REGS;
+                           Mcbsp_deviceInstInfo[devId].obj.fifoRegs =
+                               (CSL_BfifoRegsOvly)CSL_MCBSP_1_FIFO_REGS;
+                           Mcbsp_deviceInstInfo[devId].obj.dataAddress =
+                               (CSL_BdataRegsOvly)CSL_MCBSP_1_DATA_REGS;
+                           Mcbsp_deviceInstInfo[devId].obj.edmaTxEventNum =
+                               (uint32_t)CSL_EDMA3_CHA_MCBSP1_TX;
+                           Mcbsp_deviceInstInfo[devId].obj.edmaRxEventNum =
+                               (uint32_t)CSL_EDMA3_CHA_MCBSP1_RX;
+                           Mcbsp_deviceInstInfo[devId].obj.cpuTxEventNum =
+                               (uint32_t)CSL_INTC_EVENTID_MCBSP1_TXINT ;
+                           Mcbsp_deviceInstInfo[devId].obj.cpuRxEventNum =
+                               (uint32_t)CSL_INTC_EVENTID_MCBSP1_RXINT ;
+                       }
+                       else
+                       {
+                           /* do nothing                                                     */
+                       }
+
+#ifdef MCBSP_LOOPJOB_ENABLE
+        /* align the buffers to the cache line size                           */
+        Mcbsp_loopSrcBuf[devId].scratchBuffer = (uint32_t *)
+            (((uint32_t)Mcbsp_loopSrcBuf[devId].scratchBuf + 0x7F) & ~0x7F);
+
+        Mcbsp_loopDstBuf[devId].scratchBuffer = (uint32_t *)
+            (((uint32_t)Mcbsp_loopDstBuf[devId].scratchBuf + 0x7F) & ~0x7F);
+
+        Mcbsp_osalEndMemAccess ((void *)Mcbsp_loopSrcBuf, sizeof(Mcbsp_loopSrcBuf));
+        Mcbsp_osalEndMemAccess ((void *)Mcbsp_loopDstBuf, sizeof(Mcbsp_loopDstBuf));
+#endif /* MCBSP_LOOPJOB_ENABLE */
+        Mcbsp_muteBuf[devId].scratchBuffer = (uint32_t *)
+            (((uint32_t)Mcbsp_muteBuf[devId].scratchBuf + 0x7F) & ~0x7F);
+        Mcbsp_osalEndMemAccess ((void *)Mcbsp_muteBuf, sizeof(Mcbsp_muteBuf));
+    }
+
+    /* Writeback Global Objects */
+    Mcbsp_osalEndMemAccess ((void *)Mcbsp_deviceInstInfo, sizeof(Mcbsp_deviceInstInfo));
+
+    /* End Critical Section */
+    Mcbsp_osalExitMultipleCoreCriticalSection (key);
+
+    return;
+}
+
+/* ========================================================================== */
+/*                              END OF FILE                                   */
+/* ========================================================================== */
diff --git a/example/omapl138/MCBSPDigLpbk/MCBSP_DigLpbk_lcdkOMAPL138_c674xExampleProject.txt b/example/omapl138/MCBSPDigLpbk/MCBSP_DigLpbk_lcdkOMAPL138_c674xExampleProject.txt
new file mode 100644 (file)
index 0000000..fc5cee1
--- /dev/null
@@ -0,0 +1,13 @@
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.c" 
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/device/omapl138/src/device_mcbsp_loopback.c"
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd" 
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg" 
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c" 
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_cfg.c" 
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_omapl138_int_reg.c" 
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_cs.c" 
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk/sample_init.c" 
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/src/mcbsp_drv.c"
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/src/mcbsp_edma.c"
+-ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/src/mcbsp_ioctl.c"
+-ccs.setCompilerOptions "-mv6740 --abi=eabi -g --define=SOC_OMAPL138 --define=LCDK_OMAPL138 -DMCBSP_DEBUG_TEMP -mv6740 -g --diag_warning=225 -I${PDK_INSTALL_PATH} -I${BIOS_INSTALL_PATH}/packages -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/omapl138/MCBSPDigLpbk -I${PDK_INSTALL_PATH}/ti/drv/mcbsp/include -I${PDK_INSTALL_PATH}/ti/drv/mcbsp" -rtsc.enableRtsc 
diff --git a/example/omapl138/MCBSPDigLpbk/bios6_edma3_drv_sample.h b/example/omapl138/MCBSPDigLpbk/bios6_edma3_drv_sample.h
new file mode 100644 (file)
index 0000000..5fad8a7
--- /dev/null
@@ -0,0 +1,186 @@
+/*
+ * bios6_edma3_drv_sample.h
+ *
+ * Header file for the sample application for the EDMA3 Driver.
+ *
+ * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef _BIOS6_EDMA3_DRV_SAMPLE_H_
+#define _BIOS6_EDMA3_DRV_SAMPLE_H_
+
+#include <stdio.h>
+#include <ti/sysbios/knl/Semaphore.h>
+
+/* Include EDMA3 Driver */
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Cache line size on the underlying SoC. It needs to be modified
+ * for different cache line sizes, if the Cache is Enabled.
+ */
+#define EDMA3_CACHE_LINE_SIZE_IN_BYTES      (128u)
+
+/* Error returned in case of buffers are not aligned on the cache boundary */
+#define EDMA3_NON_ALIGNED_BUFFERS_ERROR     (-1)
+
+/* Error returned in case of data mismatch */
+#define EDMA3_DATA_MISMATCH_ERROR           (-2)
+
+/**
+ * \brief   EDMA3 Initialization
+ *
+ * This function initializes the EDMA3 Driver for the given EDMA3 controller
+ * and opens a EDMA3 driver instance. It internally calls EDMA3_DRV_create() and
+ * EDMA3_DRV_open(), in that order.
+ *
+ * It also registers interrupt handlers for various EDMA3 interrupts like 
+ * transfer completion or error interrupts.
+ *
+ *  \param  edma3Id    [IN]            EDMA3 Controller Instance Id (Hardware
+ *                                                                     instance id, starting from 0)
+ *  \param  errorCode  [IN/OUT]        Error code while opening DRV instance
+ *  \return EDMA3_DRV_Handle: If successfully opened, the API will return the
+ *                            associated driver's instance handle.
+ */
+EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode);
+
+/**
+ * \brief   EDMA3 De-initialization
+ *
+ * This function de-initializes the EDMA3 Driver for the given EDMA3 controller
+ * and closes the previously opened EDMA3 driver instance. It internally calls 
+ * EDMA3_DRV_close and EDMA3_DRV_delete(), in that order.
+ *
+ * It also un-registers the previously registered interrupt handlers for various 
+ * EDMA3 interrupts.
+ *
+ *  \param  edma3Id    [IN]            EDMA3 Controller Instance Id (Hardware
+ *                                                                     instance id, starting from 0)
+ *  \param  hEdma              [IN]            EDMA3 Driver handle, returned while using
+ *                                                                     edma3init().
+ *  \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma);
+
+
+/**
+ *  \brief   EDMA3 Cache Invalidate
+ *
+ *  This function invalidates the D cache.
+ *
+ *  \param  mem_start_ptr [IN]      Starting address of memory.
+ *                                  Please note that this should be
+ *                                  aligned according to the cache line size.
+ *  \param  num_bytes [IN]          length of buffer
+ *  \return  EDMA3_DRV_SOK if success, else error code in case of error
+ *          or non-alignment of buffers.
+ *
+ * Note: This function is required if the buffer is in DDR.
+ * For other cases, where buffer is NOT in DDR, user
+ * may or may not require the below implementation and
+ * should modify it according to her need.
+ */
+EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr,
+                           unsigned int num_bytes);
+
+
+
+/**
+ * \brief   EDMA3 Cache Flush
+ *
+ *  This function flushes (cleans) the Cache
+ *
+ *  \param  mem_start_ptr [IN]      Starting address of memory.
+ *                                  Please note that this should be
+ *                                  aligned according to the cache line size.
+ *  \param  num_bytes [IN]          length of buffer
+ *  \return  EDMA3_DRV_SOK if success, else error code in case of error
+ *          or non-alignment of buffers.
+ *
+ * Note: This function is required if the buffer is in DDR.
+ * For other cases, where buffer is NOT in DDR, user
+ * may or may not require the below implementation and
+ * should modify it according to her need.
+ */
+EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr,
+                      unsigned int num_bytes);
+
+
+
+/**
+  * Counting Semaphore related functions (OS dependent) should be
+  * called/implemented by the application. A handle to the semaphore
+  * is required while opening the driver/resource manager instance.
+  */
+
+/**
+ * \brief   EDMA3 OS Semaphore Create
+ *
+ *      This function creates a counting semaphore with specified
+ *      attributes and initial value. It should be used to create a semaphore
+ *      with initial value as '1'. The semaphore is then passed by the user
+ *      to the EDMA3 driver/RM for proper sharing of resources.
+ * \param   initVal [IN] is initial value for semaphore
+ * \param   semParams [IN] is the semaphore attributes.
+ * \param   hSem [OUT] is location to receive the handle to just created
+ *      semaphore.
+ * \return  EDMA3_DRV_SOK if successful, else a suitable error code.
+ */
+EDMA3_DRV_Result edma3OsSemCreate(int initVal,
+                                                       const Semaphore_Params *semParams,
+                                                       EDMA3_OS_Sem_Handle *hSem);
+
+
+
+/**
+ * \brief   EDMA3 OS Semaphore Delete
+ *
+ *      This function deletes or removes the specified semaphore
+ *      from the system. Associated dynamically allocated memory
+ *      if any is also freed up.
+ * \param   hSem [IN] handle to the semaphore to be deleted
+ * \return  EDMA3_DRV_SOK if successful else a suitable error code
+ */
+EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem);
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif  /* _BIOS6_EDMA3_DRV_SAMPLE_H_ */
+
diff --git a/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.c b/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.c
new file mode 100644 (file)
index 0000000..8bc44a3
--- /dev/null
@@ -0,0 +1,968 @@
+/*
+ * mcbspMasterDigLpbk.c
+ *
+ * This file contains the test / demo code to demonstrate the McBSP driver
+ * master functionality using Digital Loopback setup. The file configures 
+ * the EVM in master mode.
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/* ========================================================================== */
+/*                            INCLUDE FILES                                   */
+/* ========================================================================== */
+
+#include <ti/sysbios/BIOS.h>
+#include <xdc/std.h>
+#include <ti/sysbios/knl/Task.h>
+#include <string.h>
+#include <ti/sysbios/knl/Queue.h>
+#include <xdc/runtime/System.h>
+
+#include <xdc/cfg/global.h>
+
+/* Include EDMA3 Driver */
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+/* CSL Chip Functional Layer */
+//#include <ti/csl/csl_chip.h>
+
+/* CSL Cache Functional Layer */
+//#include <ti/csl/csl_cacheAux.h>
+
+/* CSL CPINTC Include Files. */
+//#include<ti/csl/csl_cpIntc.h>
+
+/* MCBSP Driver Include File. */
+#include <ti/drv/mcbsp/mcbsp_drv.h>
+#include <ti/drv/mcbsp/mcbsp_osal.h>
+
+/* PlatformLib Include File */
+//#include <ti/platform/platform.h>
+
+
+/* ========================================================================== */
+/*                        EXTERNAL FUNCTIONS                                  */
+/* ========================================================================== */
+
+extern EDMA3_DRV_Handle edma3init(unsigned int edma3Id, EDMA3_DRV_Result *);
+
+extern void McbspDevice_init(void);
+
+extern int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize);
+
+extern void McbspXmtInterrupt_init(void *mcbspTxChan);
+extern void McbspRcvInterrupt_init(void *mcbspRxChan);
+
+/* FPGA Configuration Misc-1 Register offset */
+#define MCBSP_FPGA_MISC_REG_OFFSET (0x0C)
+
+/* ========================================================================== */
+/*                           MACRO DEFINTIONS                                 */
+/* ========================================================================== */
+
+#define NUM_BUFS                     2          /* Max of buffers used in each direction */
+#define FRAMESIZE                   40          /* e.g 5 ms 8 KHz samples         */
+#define NUM_OF_ENABLED_CHANNELS      8          /* Number of slots to be used     */
+#define NUM_OF_MAX_CHANNELS           128                      /* Maximum number of time slots available based on clock settings   */
+#define BUFSIZE                   (NUM_OF_ENABLED_CHANNELS * FRAMESIZE)        /* Total buffer size per frame */
+
+/* Defines the core number responsible for system initialization. */
+#define CORE_SYS_INIT         0
+/* Number of iterations to execute test: Only applicable to INTERNAL CLOCK Loopback test */
+#define NUM_OF_ITERATIONS 10
+
+/* Number of MCBSP Frame structures used for submit channel */
+#define NUM_OF_MCBSP_FRAMES 2
+
+/* Number of buffers initially submitted to Mcbsp lld: Only applicable to
+   External clock test ; Note: This should be set to 2*/
+#define INIT_SUBMIT_Q_CNT 2
+
+/*============================================================================*/
+/*                            GLOBAL VARIABLES                                */
+/*============================================================================*/
+
+/* Shared Memory Variable to ensure synchronizing MCBSP initialization
+ * with all the other cores. */
+/* Created an array to pad the cache line with MCBSP_CACHE_LENGTH size */
+#pragma DATA_ALIGN   (isMCBSPInitialized, MCBSP_MAX_CACHE_ALIGN)
+#pragma DATA_SECTION (isMCBSPInitialized, ".mcbspSharedMem");
+volatile Uint32 isMCBSPInitialized[(MCBSP_CACHE_LENGTH / sizeof(Uint32))] = { 0 };
+
+/* Handle to the EDMA driver instance */
+#pragma DATA_ALIGN   (hEdma, MCBSP_MAX_CACHE_ALIGN)
+EDMA3_DRV_Handle hEdma[(MCBSP_CACHE_LENGTH / sizeof(EDMA3_DRV_Handle))] = { NULL };
+
+/* Handle to MCBSP driver instance */
+typedef void* Mcbsp_DevHandle;
+Mcbsp_DevHandle  hMcbspDev;
+
+/* Handle to MCBSP driver channel instance */
+typedef void* Mcbsp_ChanHandle;
+Mcbsp_ChanHandle  hMcbspTxChan;
+Mcbsp_ChanHandle  hMcbspRxChan;
+
+/* Core Number Identifier */
+UInt32 coreNum = 0xFFFF;
+
+/* Array to hold the pointer to the allocated buffers     */
+void* bufRx[NUM_BUFS];
+void* bufTx[NUM_BUFS];
+
+#ifdef MCBSP_LOOP_PING_PONG
+/* Ping pong buffers used to submit to Mcbsp lld, which will be used in a loop */
+void* bufRxPingPong[INIT_SUBMIT_Q_CNT];
+void* bufTxPingPong[INIT_SUBMIT_Q_CNT];
+#endif
+/* Global Error call back function prototype */
+void mcbsp_GblErrCallback(uint32_t chanHandle,uint32_t spcr_read,uint32_t Arg3);
+
+/* Variables to indicate status of EDMA TX and RX requests */
+volatile uint32_t edmaTxDone = 0;
+volatile uint32_t edmaRxDone = 0;
+/* Global variables to track number of buffers submitted, number of iterations, error counts etc */
+int rxSubmitCount=0, txSubmitCount=0;
+uint32_t num_iterations=0;
+uint32_t num_rx_Call_backs=0, num_tx_Call_backs=0, dummy_call_backs=0;
+uint32_t rxunderflowcnt=0, txunderflowcnt=0;
+uint32_t errBuffCount=0;
+/* Debug variables */
+volatile int debugVar=1;  /* This can be used to maintain a while loop, If set to 0 will exit loop */
+volatile int debugCommand=1;  /* This can be used to set to value below to send command to restart channel  */
+
+#define DEBUG_COMMAND_RESTART_CHANNELS 1
+/**
+ * \brief    Mcbsp Sample rate generator default parameters.
+ *
+ */
+Mcbsp_srgConfig mcbspSrgCfg =
+{
+    FALSE,                     /* No gsync to be used as input is not CLKS    */
+    Mcbsp_ClkSPol_RISING_EDGE, /* Dont care as input clock is not clks        */
+    Mcbsp_SrgClk_CLKCPU,       /* McBSP internal clock to be used             */
+    166666667,                 /* Mcbsp internal clock frequency(PLL-SYSCLK6) */
+    0                          /* frame sync pulse width (val+1) is used      */
+};
+
+/**
+ * \brief    Mcbsp device creation default parameters.
+ *
+ */
+const Mcbsp_Params Mcbsp_PARAMS =
+{
+    Mcbsp_DevMode_McBSP,       /* Use the device as MCBSP                     */
+    Mcbsp_OpMode_DMAINTERRUPT, /* Use DMA mode of operation                   */
+    TRUE,                      /* cache coherency taken care of by driver     */
+    Mcbsp_EmuMode_FREE,        /* Emulation mode free is to be enabled        */
+#ifdef    MCBSP_EXTERNAL_CLOCK
+    Mcbsp_Loopback_DISABLE,    /* Loop back mode disabled                     */
+#else
+    Mcbsp_Loopback_ENABLE,     /* Loop back mode enabled                      */
+#endif
+    &mcbspSrgCfg,              /* sample rate generator configuration         */
+    NULL,                      /* TX pending buffer queue from application    */
+    NULL,                      /* TX floating buffer queue in DMA             */
+    NULL,                      /* RX pending buffer queue from application    */
+    NULL                       /* RX floating buffer queue in DMA             */
+};
+
+#pragma DATA_ALIGN(loopTxJob, MCBSP_MAX_CACHE_ALIGN)
+static Int32 loopTxJob[16] = {
+    /* Filling with Mu law silence pattern : Can be any user defined pattern */
+    0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f,
+    0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f
+};
+#pragma DATA_ALIGN(loopRxJob, MCBSP_MAX_CACHE_ALIGN)
+static Int32 loopRxJob[16] = {
+    0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/**< settings to configure the TX or RX hardware sections                 */
+Mcbsp_DataConfig mcbspChanConfigTx =
+{
+    Mcbsp_Phase_SINGLE,
+    Mcbsp_WordLength_8,
+    Mcbsp_WordLength_8,    /* Dont care for single phase*/
+    NUM_OF_MAX_CHANNELS,
+    NUM_OF_MAX_CHANNELS,      // Only used with dual phase
+    Mcbsp_FrmSync_DETECT,
+#ifdef MCBSP_EXTERNAL_CLOCK
+    Mcbsp_DataDelay_0_BIT,
+#else
+    Mcbsp_DataDelay_1_BIT,
+#endif
+    Mcbsp_Compand_OFF_MSB_FIRST,
+    Mcbsp_BitReversal_DISABLE,
+    Mcbsp_IntMode_ON_SYNCERR,
+    Mcbsp_RxJust_RZF,  /* Dont care for TX         */
+    Mcbsp_DxEna_OFF
+};
+
+/**< settings to configure the TX or RX hardware sections                 */
+Mcbsp_DataConfig mcbspChanConfigRx =
+{
+    Mcbsp_Phase_SINGLE,
+    Mcbsp_WordLength_8,
+    Mcbsp_WordLength_8,    /* Dont care for single phase*/
+    NUM_OF_MAX_CHANNELS,
+    NUM_OF_MAX_CHANNELS,      // Only used with dual phase
+    Mcbsp_FrmSync_DETECT,
+#ifdef MCBSP_EXTERNAL_CLOCK
+    Mcbsp_DataDelay_0_BIT,
+#else
+    Mcbsp_DataDelay_1_BIT,
+#endif
+    Mcbsp_Compand_OFF_MSB_FIRST,
+    Mcbsp_BitReversal_DISABLE,
+    Mcbsp_IntMode_ON_SYNCERR,
+    Mcbsp_RxJust_RZF,  /* Dont care for TX         */
+    Mcbsp_DxEna_OFF
+};
+/**< clock setup for the TX section                     */
+Mcbsp_ClkSetup mcbspClkConfigTx =
+{
+#ifdef MCBSP_EXTERNAL_CLOCK
+    Mcbsp_FsClkMode_EXTERNAL,
+    8000,                   /* 8KHz                   */
+    Mcbsp_TxRxClkMode_EXTERNAL,
+#else
+    Mcbsp_FsClkMode_INTERNAL,
+    8000,                   /* 8KHz                   */
+    Mcbsp_TxRxClkMode_INTERNAL,
+#endif
+    Mcbsp_FsPol_ACTIVE_HIGH,
+    Mcbsp_ClkPol_RISING_EDGE
+};
+
+/**< clock setup for the RX section                     */
+Mcbsp_ClkSetup mcbspClkConfigRx =
+{
+#ifdef MCBSP_EXTERNAL_CLOCK
+    Mcbsp_FsClkMode_EXTERNAL,
+    8000,                   /* 8KHz                   */
+    Mcbsp_TxRxClkMode_EXTERNAL,
+#else
+    Mcbsp_FsClkMode_INTERNAL,
+    8000,                   /* 8KHz                   */
+    Mcbsp_TxRxClkMode_INTERNAL,
+#endif
+    Mcbsp_FsPol_ACTIVE_HIGH,
+    Mcbsp_ClkPol_FALLING_EDGE
+};
+
+/**< Multi channel setup                                                      */
+Mcbsp_McrSetup mcbspMultiChanCtrl =
+{
+    Mcbsp_McmMode_ALL_CHAN_DISABLED_UNMASKED,
+    Mcbsp_PartitionMode_CHAN_0_15,
+    Mcbsp_PartitionMode_CHAN_16_31,
+    Mcbsp_PartitionMode_2
+};
+
+
+Mcbsp_ChanParams mcbspChanparamTx =
+{
+    Mcbsp_WordLength_8,  /* wordlength configured    */
+    &loopTxJob[0],          /* loop job buffer internal */
+    8,                    /* user loopjob length      */
+    mcbsp_GblErrCallback, /* global error callback    */
+    NULL,                 /* edma Handle              */
+    1,                    /* EDMA event queue         */
+    8,                    /* hwi number               */
+    Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED,
+    TRUE,                 /* FIFO mode enabled        */
+    &mcbspChanConfigTx,   /* channel configuration    */
+    &mcbspClkConfigTx,    /* clock configuration      */
+    &mcbspMultiChanCtrl,  /* multi channel control    */
+    0x7531,  /* Enabled timeslots: 0, 4, 5, 8, 10, 12, 13, 14 */
+    0x00,
+    0x00,
+    0x00,
+    NUM_OF_ENABLED_CHANNELS    /* Total number of channels enabled*/
+};
+
+Mcbsp_ChanParams mcbspChanparamRx =
+{
+    Mcbsp_WordLength_8,  /* wordlength configured    */
+    &loopRxJob[0],          /* loop job buffer internal */
+    8,                    /* user loopjob length      */
+    mcbsp_GblErrCallback, /* global error callback    */
+    NULL,                 /* edma Handle              */
+    1,                    /* EDMA event queue         */
+    8,                    /* hwi number               */
+    Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED,
+    TRUE,                 /* FIFO mode enabled        */
+    &mcbspChanConfigRx,   /* channel configuration    */
+    &mcbspClkConfigRx,    /* clock configuration      */
+    &mcbspMultiChanCtrl,  /* multi channel control    */
+    0x7531,  /* Enabled timeslots: 0, 4, 5, 8, 10, 12, 13, 14 */
+    0x00,
+    0x00,
+    0x00,
+    NUM_OF_ENABLED_CHANNELS    /* Total number of channels enabled*/
+};
+
+
+/* ========================================================================== */
+/*                           FUNCTION DEFINITIONS                             */
+/* ========================================================================== */
+
+/*
+ *   This is the application's callback function. The driver will
+ *   call this function whenever an EDMA I/O operation is over.
+ *
+ */
+void mcbspAppCallback(void* arg, Mcbsp_IOBuf *ioBuf)
+{
+    int32_t mode;
+    int32_t *pmode = (int32_t *)arg;
+
+    mode = *pmode;
+    if (mode == MCBSP_MODE_OUTPUT)
+    {
+       if(ioBuf) {
+            num_tx_Call_backs++;
+            edmaTxDone = 1;
+        }else
+            txunderflowcnt++;
+    }
+    else if (mode == MCBSP_MODE_INPUT)
+    {
+        if(ioBuf) {
+            num_rx_Call_backs++;
+            edmaRxDone = 1;
+        }else
+            rxunderflowcnt++;
+    }else
+        dummy_call_backs++;
+    return;
+}
+
+/*
+ *   This is the application's Global error callback function 
+ */
+void mcbsp_GblErrCallback(uint32_t chanHandle,uint32_t spcr_read,uint32_t Arg3)
+{
+    System_printf ("Debug(Core %d): ERROR callback called SPCR: %x", coreNum, spcr_read);
+}
+
+/*
+ * \brief   This function demostrates the use of Mcbsp using digital loopback
+ *          communication setup.
+ *
+ * \param   None
+ *
+ * \return  None
+ */
+void mcbspDigLpbkApp(UArg arg0, UArg arg1)
+{
+    /**< Mcbsp device params                                                  */
+    Mcbsp_Params  mcbspParams;
+
+    /**< Queue to hold the pending packets received from the application      */
+    Queue_Struct  txQueuePendingList, rxQueuePendingList;
+    /**< Queue to manage floating packets in DMA                              */
+    Queue_Struct  txQueueFloatingList, rxQueueFloatingList;
+
+    uint32_t count   = 0, tempCount = 0;
+    int32_t  status  = 0, retval = 0;
+    int32_t  txChanMode = MCBSP_MODE_OUTPUT;
+    int32_t  rxChanMode = MCBSP_MODE_INPUT;
+    uint32_t mcbspTxDone = 0, mcbspRxDone = 0;
+    Mcbsp_IOBuf txFrame[NUM_OF_MCBSP_FRAMES], rxFrame[NUM_OF_MCBSP_FRAMES];
+    int txFrameIndex=0, rxFrameIndex=0;
+    int init_count=0;
+#ifdef MCBSP_LOOP_PING_PONG
+    int pingPongIndex=0;
+#endif
+
+    /* Initialize the OSAL */
+    if (Osal_dataBufferInitMemory(BUFSIZE) < 0)
+    {
+        System_printf ("Debug(Core %d): Error: Unable to initialize the OSAL. \n", coreNum);
+        return;
+    }
+
+    /* update EDMA3 handle to channel parameters */
+    mcbspChanparamTx.edmaHandle = hEdma[0];
+    mcbspChanparamRx.edmaHandle = hEdma[0];
+
+    /* create the pending and floating queue for the TX channel           */
+    Queue_construct(&txQueuePendingList, NULL);
+    Queue_construct(&txQueueFloatingList, NULL);
+
+    /* create the pending and floating queue for the RX channel           */
+    Queue_construct(&rxQueuePendingList, NULL);
+    Queue_construct(&rxQueueFloatingList, NULL);
+
+
+    mcbspParams                 = Mcbsp_PARAMS;
+    mcbspParams.txQPendingList  = &txQueuePendingList;
+    mcbspParams.txQFloatingList = &txQueueFloatingList;
+    mcbspParams.rxQPendingList  = &rxQueuePendingList;
+    mcbspParams.rxQFloatingList = &rxQueueFloatingList;
+
+
+    /* Bind the driver instance with device instance */
+    status = mcbspBindDev(&hMcbspDev, coreNum, &mcbspParams);
+
+    if (status != MCBSP_STATUS_COMPLETED)
+    {
+        System_printf ("Debug(Core %d): MCBSP LLD Bind Device Failed\n", coreNum);
+        return;
+    }
+
+    /* If the user loopjob buffer is in local L2 memory: Convert into Global memory address space */
+    if(mcbspChanparamRx.userLoopJobBuffer)
+        mcbspChanparamRx.userLoopJobBuffer = (void *)Mcbsp_osalLocal2Global(mcbspChanparamRx.userLoopJobBuffer);
+
+    /* Create a RX channel for receiving */
+    status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode);
+    if (MCBSP_STATUS_COMPLETED != status)
+    {
+        System_printf ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum);
+        return;
+    }
+
+    /* If the user loopjob buffer is in local L2 memory: Convert into Global memory address space */
+    if(mcbspChanparamTx.userLoopJobBuffer)
+        mcbspChanparamTx.userLoopJobBuffer = Mcbsp_osalLocal2Global(mcbspChanparamTx.userLoopJobBuffer);
+
+    /* Create a TX channel for the transmission */
+    status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode);
+    if (MCBSP_STATUS_COMPLETED != status)
+    {
+        System_printf ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum);
+        return;
+    }
+
+    /* Register mcbsp interrupts */
+    //McbspRcvInterrupt_init(hMcbspRxChan);
+    //McbspXmtInterrupt_init(hMcbspTxChan);
+
+    /* create the buffers required for the TX and RX operations */
+    for (count = 0; count < (NUM_BUFS); count++)
+    {
+        bufTx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE);
+        bufRx[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE);
+
+        if (bufTx[count] == NULL)
+        {
+            System_printf ("Debug(Core %d): Error: Tx Buffer (%d) Memory Allocation Failed\n", coreNum, count);
+            return;
+        }
+        if (bufRx[count] == NULL)
+        {
+            System_printf ("Debug(Core %d): Error: Rx Buffer (%d) Memory Allocation Failed\n", coreNum, count);
+            return;
+        }
+    }
+#ifdef MCBSP_LOOP_PING_PONG
+    /* create the ping pong buffers required for the TX and RX operations */
+    for (count = 0; count < (NUM_BUFS); count++)
+    {
+        bufRxPingPong[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE);
+        bufTxPingPong[count] = (uint8_t *)Osal_mcbspDataBufferMalloc(BUFSIZE);
+
+        if (bufTxPingPong[count] == NULL)
+        {
+            System_printf ("Debug(Core %d): Error: Tx Ping pong Buffer (%d) Memory Allocation Failed\n", coreNum, count);
+            return;
+        }
+        if (bufRxPingPong[count] == NULL)
+        {
+            System_printf ("Debug(Core %d): Error: Rx Ping pong Buffer (%d) Memory Allocation Failed\n", coreNum, count);
+            return;
+        }
+    }
+#endif
+    /* Fill the buffers with known data and transmit the same and 
+       check if the same pattern is received */
+    for (count = 0; count < (NUM_BUFS); count++)
+    {
+        memset((uint8_t *)bufTx[count], 0, BUFSIZE);
+        for (tempCount = 0; tempCount < BUFSIZE; tempCount++)
+        {
+            ((uint8_t *)bufTx[count])[tempCount] = (tempCount % 0x100);
+        }
+    }
+    System_printf ("Debug(Core %d): If required to restart set debugCommand variable to %d\n", coreNum, DEBUG_COMMAND_RESTART_CHANNELS);
+
+restart_mcbsp_point:
+    txFrameIndex=0;
+    rxFrameIndex=0;
+    init_count=0;
+#ifdef MCBSP_EXTERNAL_CLOCK
+    /* Initial loading of ping ping buffers */
+    for(init_count =0 ; init_count < INIT_SUBMIT_Q_CNT; init_count++)
+    {
+#ifdef MCBSP_LOOP_PING_PONG
+        memset((uint8_t *)bufRxPingPong[init_count], 0, BUFSIZE);
+
+        /* RX frame processing */
+        rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ;
+        rxFrame[rxFrameIndex].addr = (void*)bufRxPingPong[init_count];
+#else
+        memset((uint8_t *)bufRx[init_count], 0, BUFSIZE);
+
+
+        /* RX frame processing */
+        rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ;
+        rxFrame[rxFrameIndex].addr = (void*)bufRx[init_count];
+#endif
+
+        rxFrame[rxFrameIndex].size = BUFSIZE;
+        rxFrame[rxFrameIndex].arg = (uint32_t) hMcbspRxChan;
+        rxFrame[rxFrameIndex].status = MCBSP_STATUS_COMPLETED;
+        rxFrame[rxFrameIndex].misc = 1;   /* reserved - used in callback to indicate asynch packet */
+
+        status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame[rxFrameIndex]);
+        if (status != MCBSP_STATUS_PENDING)
+        {
+            System_printf ("Debug(Core %d): Error: RX buffer #%d submission FAILED\n", coreNum, init_count);
+            retval = 1;
+        }
+        else
+        {
+#ifdef MCBSP_APP_VERBOSE
+            System_printf ("Debug(Core %d): RX buffer #%d is submitted to MCBSP driver\n", coreNum, init_count);
+#endif
+        }
+        rxFrameIndex++;
+        rxFrameIndex = (rxFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : rxFrameIndex;
+
+        rxSubmitCount++;
+
+        /* TX frame processing */
+        txFrame[txFrameIndex].cmd = Mcbsp_IOBuf_Cmd_WRITE;
+#ifdef MCBSP_LOOP_PING_PONG
+        txFrame[txFrameIndex].addr = (void*)bufTxPingPong[init_count];
+#else
+        txFrame[txFrameIndex].addr = (void*)bufTx[init_count];
+#endif
+        txFrame[txFrameIndex].size = BUFSIZE;
+        txFrame[txFrameIndex].arg = (uint32_t)hMcbspTxChan;
+        txFrame[txFrameIndex].status = MCBSP_STATUS_COMPLETED;
+        txFrame[txFrameIndex].misc = 1;   /* reserved - used in callback to indicate asynch packet */
+
+        status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame[txFrameIndex]);
+        if (status != MCBSP_STATUS_PENDING)
+        {
+            System_printf ("Debug(Core %d): Error: TX buffer  #%d submission FAILED\n", coreNum, init_count);
+            retval = 1;
+        }
+        else
+        {
+#ifdef MCBSP_APP_VERBOSE
+            System_printf ("Debug(Core %d): TX buffer  #%d submission is submitted to MCBSP driver\n", coreNum, init_count);
+#endif
+        }
+        txFrameIndex++;
+        txFrameIndex = (txFrameIndex >=(NUM_OF_MCBSP_FRAMES)) ? 0 : txFrameIndex;
+
+        txSubmitCount++;
+    }
+
+    /* Wait for TX and RX processing to complete */
+    while (1)
+    {
+        if (edmaTxDone == 1)
+        {
+#ifdef MCBSP_APP_VERBOSE
+            System_printf ("Debug(Core %d): EDMA -> Iteration-%d frames are transmitted to TX path\n", coreNum, count);
+#endif
+            edmaTxDone = 0; /* Reset for next iteration */
+            mcbspTxDone = 1;
+        }
+        if (edmaRxDone == 1)
+        {
+#ifdef MCBSP_APP_VERBOSE
+            System_printf ("Debug(Core %d): EDMA -> Iteration-%d frames are received from RX path\n", coreNum, count);
+#endif
+            edmaRxDone = 0;  /* Reset for next iteration */
+            mcbspRxDone = 1;
+        }
+        if ((mcbspTxDone == 1) && (mcbspRxDone == 1))
+        {
+            mcbspTxDone = 0;  /* Reset for next iteration */
+            mcbspRxDone = 0;  /* Reset for next iteration */
+            break;
+        }
+    }
+#ifdef MCBSP_LOOP_PING_PONG
+    /* Change ping Pong Index */
+    init_count=0;
+#endif
+#endif /* MCBSP_EXTERNAL_CLOCK */
+
+    /* Start main loop to iterate through frames */
+    while(debugVar)
+    {
+        /* submit frames to the driver */
+        for (count = init_count; count < NUM_BUFS; count++)
+        {
+#ifdef MCBSP_EXTERNAL_CLOCK
+/*   With External clock the data coming from the RX side is copied to loop back to the Tx side */
+            memcpy((uint8_t *)bufTx[count], (uint8_t *)bufRx[count], BUFSIZE);
+#endif
+#ifdef MCBSP_LOOP_PING_PONG
+            memset((uint8_t *)bufRxPingPong[pingPongIndex], 0, BUFSIZE);
+#else
+            memset((uint8_t *)bufRx[count], 0, BUFSIZE);
+            /* RX frame processing */
+            rxFrame[rxFrameIndex].cmd = Mcbsp_IOBuf_Cmd_READ;
+            rxFrame[rxFrameIndex].addr = (void*)bufRx[count];
+            rxFrame[rxFrameIndex].size = BUFSIZE;
+            rxFrame[rxFrameIndex].arg = (uint32_t) hMcbspRxChan;
+            rxFrame[rxFrameIndex].status = MCBSP_STATUS_COMPLETED;
+            rxFrame[rxFrameIndex].misc = 1;   /* reserved - used in callback to indicate asynch packet */
+
+            status = mcbspSubmitChan(hMcbspRxChan, (void *)&rxFrame[rxFrameIndex]);
+            if (status != MCBSP_STATUS_PENDING)
+            {
+                System_printf ("Debug(Core %d): Error: RX buffer #%d submission FAILED\n", coreNum, count);
+                retval = 1;
+            }
+            else
+            {
+#ifdef MCBSP_APP_VERBOSE
+                System_printf ("Debug(Core %d): RX buffer #%d is submitted to MCBSP driver\n", coreNum, count);
+#endif
+            }
+            rxFrameIndex++;
+            rxFrameIndex = (rxFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : rxFrameIndex;
+#endif
+            rxSubmitCount++;
+#ifdef MCBSP_LOOP_PING_PONG
+            /* Copy buffer from buffer to ping pong buffer*/
+            memcpy((uint8_t *)bufTxPingPong[pingPongIndex], (uint8_t *)bufTx[count],BUFSIZE);
+#else
+            /* TX frame processing */
+            txFrame[txFrameIndex].cmd = Mcbsp_IOBuf_Cmd_WRITE;
+            txFrame[txFrameIndex].addr = (void*)bufTx[count];
+            txFrame[txFrameIndex].size = BUFSIZE;
+            txFrame[txFrameIndex].arg = (uint32_t)hMcbspTxChan;
+            txFrame[txFrameIndex].status = MCBSP_STATUS_COMPLETED;
+            txFrame[txFrameIndex].misc = 1;   /* reserved - used in callback to indicate asynch packet */
+
+            status = mcbspSubmitChan(hMcbspTxChan, (void *)&txFrame[txFrameIndex]);
+            if (status != MCBSP_STATUS_PENDING)
+            {
+                System_printf ("Debug(Core %d): Error: TX buffer  #%d submission FAILED\n", coreNum, count);
+                retval = 1;
+            }
+            else
+            {
+#ifdef MCBSP_APP_VERBOSE
+                System_printf ("Debug(Core %d): TX buffer  #%d is submitted to MCBSP driver\n", coreNum, count);
+#endif
+            }
+            txFrameIndex++;
+            txFrameIndex = (txFrameIndex >= (NUM_OF_MCBSP_FRAMES)) ? 0 : txFrameIndex;
+#endif
+            txSubmitCount++;
+
+            /* Wait for TX and RX processing to complete */
+            while (1)
+            {
+                if (edmaTxDone == 1)
+                {
+#ifdef MCBSP_APP_VERBOSE
+                    System_printf ("Debug(Core %d): EDMA -> Buffer #-%d is transmitted to TX path\n", coreNum, count);
+#endif
+                    edmaTxDone = 0; /* Reset for next iteration */
+                    mcbspTxDone = 1;
+                }
+                if (edmaRxDone == 1)
+                {
+#ifdef MCBSP_APP_VERBOSE
+                    System_printf ("Debug(Core %d): EDMA -> Buffer #-%d is received from RX path\n", coreNum, count);
+#endif
+                    edmaRxDone = 0;  /* Reset for next iteration */
+                    mcbspRxDone = 1;
+                }
+                if ((mcbspTxDone == 1) && (mcbspRxDone == 1))
+                {
+                    mcbspTxDone = 0;  /* Reset for next iteration */
+                                   mcbspRxDone = 0;  /* Reset for next iteration */
+                                   break;
+                }
+            }
+#ifdef MCBSP_LOOP_PING_PONG
+            /* Change ping Pong Index */
+            pingPongIndex=(pingPongIndex)?0:1;
+
+            /* Copy buffer from buffer to other buffer*/
+            memcpy((void*)bufRx[count], (uint8_t *)bufRxPingPong[pingPongIndex],BUFSIZE);
+#endif
+            /* compare buffer contents */
+            for (tempCount = 0; tempCount < BUFSIZE; tempCount++)
+            {
+                if (((char *)bufTx[count])[tempCount] != ((char *)bufRx[count])[tempCount])
+                {
+#ifdef MCBSP_APP_VERBOSE
+                    System_printf("Debug(Core %d): Error: TX and RX frame data DOES NOT match in Buffer #-%d\n",
+                        coreNum, count);
+                    System_printf("Debug(Core %d): Error: Buffer index = %d, Tx data = %d, Rx data = %d\n", coreNum,
+                        tempCount, ((char *)bufTx[count])[tempCount], ((char *)bufRx[count])[tempCount]);
+#endif
+                    errBuffCount++;
+                    break;
+                }
+            }
+            if (tempCount >= BUFSIZE)
+            {
+#ifdef MCBSP_APP_VERBOSE
+                System_printf("Debug(Core %d): TX and RX frames data match in iteration-%d !!!\n", coreNum, count);
+#endif
+            }
+        }
+        init_count=0;
+        num_iterations++;
+#ifndef   MCBSP_EXTERNAL_CLOCK
+        if(num_iterations >= NUM_OF_ITERATIONS)
+            break;
+#endif
+        switch(debugCommand)
+        {
+        case DEBUG_COMMAND_RESTART_CHANNELS:
+            debugCommand=0;
+            /* Close channel and reopen */
+            /* Delete  RX channel */
+            status = mcbspDeleteChan(hMcbspRxChan);
+            if (MCBSP_STATUS_COMPLETED != status)
+            {
+                System_printf ("Debug(Core %d): Error: Delete Channel (RX) failed\n", coreNum);
+                return;
+            }
+
+            /* Delete TX channel*/
+            status = mcbspDeleteChan(hMcbspTxChan);
+            if (MCBSP_STATUS_COMPLETED != status)
+            {
+                System_printf ("Debug(Core %d): Error: Delete Channel (TX) failed\n", coreNum);
+                return;
+            }
+            /* Create a RX channel for receiving */
+            status = mcbspCreateChan(&hMcbspRxChan, hMcbspDev, MCBSP_MODE_INPUT, &mcbspChanparamRx, mcbspAppCallback, &rxChanMode);
+            if (MCBSP_STATUS_COMPLETED != status)
+            {
+                System_printf ("Debug(Core %d): Error: Create Channel (RX) failed\n", coreNum);
+                return;
+            }
+
+            /* Create a TX channel for the transmission */
+            status = mcbspCreateChan(&hMcbspTxChan, hMcbspDev, MCBSP_MODE_OUTPUT, &mcbspChanparamTx, mcbspAppCallback, &txChanMode);
+            if (MCBSP_STATUS_COMPLETED != status)
+            {
+                System_printf ("Debug(Core %d): Error: Create Channel (TX) failed\n", coreNum);
+                return;
+            }
+            edmaTxDone = 0;   /* Reset for next iteration */
+            edmaRxDone = 0;   /* Reset for next iteration */
+            mcbspTxDone = 0;  /* Reset for next iteration */
+            mcbspRxDone = 0;  /* Reset for next iteration */
+            goto restart_mcbsp_point;
+
+        default:
+            debugCommand=0;
+            break;
+
+        }
+
+    }
+
+    if ((errBuffCount == 0 ) & (retval ==0))
+    {
+        System_printf("Debug(Core %d): MCBSP Digital Loopback Application completed successfully : "\
+            "Num iterations %d  Num buffers per iteration %d!!!\n",
+            coreNum, num_iterations, NUM_BUFS);
+    }
+    else
+    {
+        System_printf("Debug(Core %d): MCBSP Digital Loopback application FAILED :  "\
+            "Num iterations %d  Num buffers per iteration %d Failed buffers %d!!!\n",
+            coreNum, num_iterations, NUM_BUFS, errBuffCount);
+    }
+
+    /* Delete  RX channel */
+    status = mcbspDeleteChan(hMcbspRxChan);
+    if (MCBSP_STATUS_COMPLETED != status)
+    {
+        System_printf ("Debug(Core %d): Error: Delete Channel (RX) failed\n", coreNum);
+        return;
+    }
+
+    /* Delete TX channel*/
+    status = mcbspDeleteChan(hMcbspTxChan);
+    if (MCBSP_STATUS_COMPLETED != status)
+    {
+        System_printf ("Debug(Core %d): Error: Delete Channel (TX) failed\n", coreNum);
+        return;
+    }
+    return;
+}
+
+/*
+ * \brief  Void main(Void)
+ *
+ *         Main function of the sample application. This function calls the
+ *         function to configure the mcbsp instance.
+ *
+ * \param  None
+ *
+ * \return None
+ */
+#include "ti/sysbios/hal/Cache.h"
+
+Void main(Void)
+{
+    Task_Params taskParams;
+    EDMA3_DRV_Result edmaResult = 0;
+    uint8_t uchValue, uchReadValue;
+
+    /* Get the core number. */
+    coreNum = 0; //CSL_chipReadReg (CSL_CHIP_DNUM);
+
+#ifdef SIMULATOR_SUPPORT
+#warn MCBSP Digital Loopback example is not supported on SIMULATOR !!!
+    System_printf ("MCBSP Digital Loopback example is not supported on SIMULATOR. Exiting!\n");
+    return;
+#else
+    System_printf ("Debug(Core %d): Running MCBSP Digital Loopback example on the DEVICE\n", coreNum);
+#endif
+
+    /* Initialize the system only if the core was configured to do so. */
+    if (coreNum == CORE_SYS_INIT)
+    {
+#if 0
+        System_printf ("Debug(Core %d): System Initialization for MCBSP\n", coreNum);
+        /* Read FPGA register */
+        if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchReadValue)))
+        {
+            System_printf ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum);
+            return;
+        }
+        /* Clear field for configuration */
+        uchValue = (uchReadValue & (~0x3));
+#ifndef PLATFORM_FPGA_MCBSP_AMC_EN
+        uchValue |=  0x3;
+#endif
+        /* Drive McBSP_AMC_EN# high. Output SLCLKs, TxCLKs, RxCLKs, FSTs, FSRs as Hi-Z. 
+         * These clocks and syncs are tri-stated and McBSP is accessed over 80-pin header */
+        if (0 != (platform_fpgaWriteConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, (uchValue))))
+        {
+            System_printf ("Debug(Core %d): FPGA McBSP_AMC_EN# register WRITE failed \n", coreNum);
+            return;
+        }
+
+        /* DEBUG: Verify if FPGA register is configured correctly */
+        if (0 != (platform_fpgaReadConfigReg(MCBSP_FPGA_MISC_REG_OFFSET, &uchReadValue)))
+        {
+            System_printf ("Debug(Core %d): FPGA McBSP_AMC_EN# register READ failed \n", coreNum);
+            return;
+        }
+
+        if (uchValue != uchReadValue)
+        {
+            System_printf ("Debug(Core %d): FPGA McBSP_AMC_EN# register setting failed \n", coreNum);
+            return;
+        }
+        else
+        {
+            System_printf ("Debug(Core %d): FPGA McBSP_AMC_EN# register is set to %d \n", coreNum, uchValue);
+        }
+#endif
+        /* MCBSP Driver Initialization: This should always be called before
+         * invoking the MCBSP Driver. */
+        mcbspInit();
+
+        /* Device Specific MCBSP Initializations */
+        McbspDevice_init();
+        
+        /* MCBSP Driver is operational at this time. */
+        System_printf ("Debug(Core %d): MCBSP Driver Initialization Done\n", coreNum);
+
+        /* Write to the SHARED memory location at this point in time. The other cores cannot execute
+         * till the MCBSP Driver is up and running. */
+        isMCBSPInitialized[0] = 1;
+
+        /* The MCBSP IP block has been initialized. We need to writeback the cache here because it will
+         * ensure that the rest of the cores which are waiting for MCBSP to be initialized would now be
+         * woken up. */
+        //CACHE_wbL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT);
+        Cache_wb ((void *) &isMCBSPInitialized[0], MCBSP_CACHE_LENGTH,0x7fff, 1);
+    }
+    else
+    {
+        /* All other cores need to wait for the MCBSP to be initialized before they proceed with the test. */ 
+        System_printf ("Debug(Core %d): Waiting for MCBSP to be initialized.\n", coreNum);
+
+        /* All other cores loop around forever till the MCBSP is up and running. 
+         * We need to invalidate the cache so that we always read this from the memory. */
+        while (isMCBSPInitialized[0] == 0)
+            //CACHE_invL1d ((void *) &isMCBSPInitialized[0], MCBSP_MAX_CACHE_ALIGN, CACHE_FENCE_WAIT);
+               Cache_inv ((void *) &isMCBSPInitialized[0], MCBSP_CACHE_LENGTH, 0x7fff, 1);
+
+
+        System_printf ("Debug(Core %d): MCBSP can now be used.\n", coreNum);
+    }
+
+    /* Initialize EDMA3 library */
+    hEdma[0] = edma3init(0, &edmaResult);
+
+    if (edmaResult != EDMA3_DRV_SOK)
+    {
+        /* Report EDMA Error */
+        System_printf("Debug(Core %d): EDMA Driver Initialization FAILED\n", coreNum);
+    }
+    else
+    {
+        System_printf("Debug(Core %d): EDMA Driver Initialization Done\n", coreNum);
+    }
+
+    /* Create the Digital Loopback Application Task */
+    Task_Params_init(&taskParams);
+    Task_create(mcbspDigLpbkApp, &taskParams, NULL);
+
+    /* Start BIOS */
+    BIOS_start();
+
+    return;
+}
+
+/* ========================================================================== */
+/*                                END OF FILE                                 */
+/* ========================================================================== */
diff --git a/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg b/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg
new file mode 100644 (file)
index 0000000..59e4f37
--- /dev/null
@@ -0,0 +1,58 @@
+/*
+ *  Copyright 2012 by Texas Instruments Incorporated.
+ *
+ *  All rights reserved. Property of Texas Instruments Incorporated.
+ *  Restricted rights to use, duplicate or disclose this code are
+ *  granted through contract.
+ *
+ */
+
+/* THIS FILE WAS GENERATED BY ti.sysbios.genx */
+
+/*
+ *  ======== mcbspMasterDigLpbk.cfg ========
+ *
+ */
+
+/* Load and use the required BIOS packages */
+var BIOS    = xdc.useModule('ti.sysbios.BIOS');
+var Task    = xdc.useModule('ti.sysbios.knl.Task');
+var cache   = xdc.useModule('ti.sysbios.hal.Cache');
+var Idle    = xdc.useModule('ti.sysbios.knl.Idle');
+var Queue   = xdc.useModule('ti.sysbios.knl.Queue');
+var ECM     = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
+//var CpIntc  = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
+var Memory  = xdc.useModule('xdc.runtime.Memory');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+
+/* Load and use the System Package */
+var System = xdc.useModule('xdc.runtime.System');
+var SysStd    = xdc.useModule('xdc.runtime.SysStd');
+
+/* Create a default system heap using ti.bios.HeapMem. */
+var heapMemParams1         = new HeapMem.Params;
+heapMemParams1.size        = 32768;
+heapMemParams1.sectionName = "systemHeap";
+Program.global.heap0       = HeapMem.create(heapMemParams1);
+
+/* This is the default memory heap. */
+Memory.defaultHeapInstance = Program.global.heap0;
+
+/*
+ * Create and install logger for the whole system.
+ * Enable Event Groups here and registering of ISR for specific GEM INTC is done
+ * using EventCombiner_dispatchPlug() and Hwi_eventMap() APIs
+ */
+ECM.eventGroupHwiNum[0] = 7;
+ECM.eventGroupHwiNum[1] = 8;
+ECM.eventGroupHwiNum[2] = 9;
+ECM.eventGroupHwiNum[3] = 10;
+
+/* Load and use the CSL, EDMA, PlatformLib etc. packages */
+//var cslSettings = xdc.useModule ('ti.csl.Settings');
+var Edma = xdc.loadPackage('ti.sdo.edma3.drv');
+//var PlatformLib = xdc.loadPackage('ti.platform.evmc6657l');
+
+/* Circular buffer size for System_printf() */
+System.SupportProxy = SysStd;
+
diff --git a/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd b/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd
new file mode 100644 (file)
index 0000000..6021dd0
--- /dev/null
@@ -0,0 +1,9 @@
+SECTIONS
+{
+    .init_array:     load >> IRAM
+    .mcbsp:          load >> DDR
+    .mcbspSharedMem: load >> DDR
+     platform_lib:   load >> DDR
+     systemHeap:     load >> IRAM
+}
+
diff --git a/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c b/example/omapl138/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c
new file mode 100644 (file)
index 0000000..6cda422
--- /dev/null
@@ -0,0 +1,639 @@
+/**
+ *   @file  mcbspMasterDigLpbk_osal.c
+ *
+ *   @brief   
+ *      This is the OS abstraction layer and is used by the MCBSP
+ *      driver for the MCBSP Example Digital Loopback Application. 
+ *
+ *  \par
+ *  ============================================================================
+ *  @n   (C) Copyright 2012, Texas Instruments, Inc.
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  \par
+*/
+#include <xdc/std.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <xdc/runtime/IHeap.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/Memory.h>
+#include <xdc/runtime/Error.h>
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/knl/Queue.h>
+#include <ti/sysbios/heaps/HeapBuf.h>
+#include <ti/sysbios/heaps/HeapMem.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <xdc/cfg/global.h>
+#include <ti/drv/mcbsp/mcbsp_drv.h>
+#if 0
+/* CSL Include Files */
+#include <ti/csl/csl_chip.h>
+#include <ti/csl/csl_semAux.h>
+#include <ti/csl/csl_cacheAux.h>
+#include <ti/csl/csl_xmcAux.h>
+#endif
+/* IPC includes */ 
+#include <ti/ipc/GateMP.h>
+#include <ti/ipc/Ipc.h>
+#include <ti/ipc/ListMP.h>
+#include <ti/ipc/SharedRegion.h>
+
+/**********************************************************************
+ ************************** Local Definitions *************************
+ **********************************************************************/
+
+#define MCBSP_HW_SEM         1
+#define PLATFORM_SPI_HW_SEM     2   /**< SPI BUS arbitration - Used by platform library        */
+
+#ifdef MCBSP_LOOP_PING_PONG
+#define MAX_MEM_MGR_ENTRIES     8
+#else
+#define MAX_MEM_MGR_ENTRIES     4
+#endif
+
+typedef struct MEM_MGMT_ENTRY
+{
+    uint8_t*    ptrMemory;
+    uint32_t    isFree;
+}MEM_MGMT_ENTRY;
+
+MEM_MGMT_ENTRY     gDataBufferMemMgr[MAX_MEM_MGR_ENTRIES];
+int32_t            gDataBufferMemMgrMaxSize = 0;
+
+/**********************************************************************
+ ************************** Global Variables **************************
+ **********************************************************************/
+UInt32 malloc_counter = 0;
+UInt32 free_counter   = 0;
+
+/**********************************************************************
+ ************************** Extern Definitions ************************
+ **********************************************************************/
+
+
+/**********************************************************************
+ **************************** OSAL Functions **************************
+ **********************************************************************/
+
+/**
+ *  @b Description
+ *  @n  
+ *      Utility function which converts a local address to global.
+ *
+ *  @param[in]  addr
+ *      Local address to be converted
+ *
+ *  @retval
+ *      Global Address
+ */
+void *Osal_local2Global (void *addr)
+{
+       UInt32 corenum;
+
+       /* Get the core number. */
+       corenum = 0;//CSL_chipReadReg(CSL_CHIP_DNUM);
+       return addr;
+
+       if(((UInt32)addr & 0xff000000) == 0) {
+       /* Compute the global address. */
+               return ((void *)((UInt32)(addr) + (0x10000000 + (corenum*0x1000000))));
+       }
+       else
+               return(addr);
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used to allocate a memory block of the specified size.
+ *
+ *  @param[in]  numBytes
+ *      Number of bytes to be allocated.
+ *
+ *  @retval
+ *      Allocated block address
+ */
+Void* Osal_mcbspMalloc(UInt32 numBytes)
+{
+       Error_Block     errorBlock;
+    Void*       ptr;
+
+    /* Increment the allocation counter. */
+    malloc_counter++;  
+
+    /* Allocate the memory. */
+    ptr = Memory_alloc(NULL, numBytes, 0, &errorBlock);
+
+    /* Return the allocated memory block. */
+       return ptr;
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used to clean up a specific memory block and is called
+ *      from the MCBSP Driver. 
+ *
+ *  @param[in]  ptr
+ *      Pointer to the memory block to be cleaned up.
+ *  @param[in]  size
+ *      Size of the memory block being cleaned up.
+ *
+ *  @retval
+ *      Not Applicable
+ */
+Void Osal_mcbspFree (Void* ptr, UInt32 size)
+{
+    /* Increment the free counter. */
+    free_counter++;    
+       Memory_free(NULL, ptr, size);
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used to allocate a block of memory for all the data buffer
+ *      operations. This function is called by the application.
+ *
+ *  @param[in]  numBuffers
+ *      Number of data buffers
+ *  @param[in]  dataBufferSize
+ *      Size of each data buffer
+ *
+ *  @retval
+ *      Success -   0
+ *  @retval
+ *      Error   -   <0
+ */
+int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize)
+{
+       Error_Block     errorBlock;
+    uint8_t*    ptrMemory;
+    uint32_t    index;
+
+    /* Allocate memory for all the data buffers */
+    ptrMemory = (uint8_t*)Memory_alloc(NULL, MAX_MEM_MGR_ENTRIES*dataBufferSize, 128, &errorBlock);
+    if (ptrMemory == NULL)
+        return -1;
+
+    /* Convert to a global address */
+    ptrMemory = Osal_local2Global(ptrMemory);
+    /* Now we chop up the memory and add it to the memory manager. */
+    for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++)
+    {
+        /* Populate the data memory management entry. */
+        gDataBufferMemMgr[index].isFree    = 1;
+        gDataBufferMemMgr[index].ptrMemory = ptrMemory;
+
+        /* Increment the memory to the next address */
+        ptrMemory = ptrMemory + dataBufferSize;        
+    }
+
+    /* Remember the memory buffer size */
+    gDataBufferMemMgrMaxSize = dataBufferSize;
+
+    /* Memory Manager has been created. */
+    return 0;
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used to allocate a data buffer of the specified
+ *      size. Data buffers should always be allocated from the global
+ *      address space.
+ *
+ *  @param[in]  numBytes
+ *      Number of bytes to be allocated.
+ *
+ *  @retval
+ *      Allocated block address
+ */
+Void* Osal_mcbspDataBufferMalloc(UInt32 numBytes)
+{
+    uint32_t    index;
+    void*       ptrMemory = NULL;
+
+    /* Basic Validation: Ensure that the memory size requested is within range. */
+    if (numBytes > gDataBufferMemMgrMaxSize)
+        return NULL;
+
+    /* Increment the allocation counter. */
+    malloc_counter++;
+
+    /* Lock out interrupts */
+    Hwi_disable();
+
+    /* Cycle through for a free entry. */
+    for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++)
+    {
+        /* Check if the entry is free or not? */
+        if (gDataBufferMemMgr[index].isFree == 1) 
+        {
+            /* Entry was free. We can use it. */
+            ptrMemory = gDataBufferMemMgr[index].ptrMemory;
+
+            /* Mark the entry as used. */
+            gDataBufferMemMgr[index].isFree = 0;
+
+            /* We have found a match. */
+            break;
+        }
+    }
+
+    /* Unlock interrupts. */
+    Hwi_enable();
+
+    /* Return the allocated memory. */
+    return ptrMemory;  
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used to clean up a previously allocated data buffer 
+ *      block. All data buffers are in the global address space
+ *
+ *  @param[in]  ptr
+ *      Pointer to the data buffer block to be cleaned up
+ *  @param[in]  size
+ *      Size of the data buffer
+ *
+ *  @retval
+ *      Not Applicable
+ */
+void Osal_mcbspDataBufferFree(void* ptr, uint32_t numBytes)
+{
+    uint32_t    index;
+
+    /* Increment the free counter. */
+    free_counter++;    
+
+    /* Lock out interrupts */
+    Hwi_disable();
+
+    /* Cycle through and clean up */
+    for (index = 0; index < MAX_MEM_MGR_ENTRIES; index++)
+    {
+        /* Check if the entry is free or not? */
+        if (gDataBufferMemMgr[index].ptrMemory == (uint8_t*)ptr) 
+        {
+            /* Mark the entry as free. */
+            gDataBufferMemMgr[index].isFree = 1;
+
+            /* We have found a match. */
+            break;
+        }
+    }
+
+    /* Unlock interrupts. */
+    Hwi_enable();
+    return;
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is the MCBSP OSAL Logging API which logs 
+ *      the messages on the console.
+ *
+ *  @param[in]  fmt
+ *      Formatted String.
+ *
+ *  @retval
+ *      Not Applicable
+ */
+Void Osal_mcbspLog( String fmt, ... )
+{
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used to create a critical section.
+ *
+ *  @retval
+ *      Semaphore Handle created
+ */
+Void* Osal_mcbspCreateSem(Void)
+{
+    return (Void*)Semaphore_create(0, NULL, NULL);
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used to delete a critical section.
+ *
+ *  @param[in]  semHandle
+ *      Semaphore handle to be deleted
+ *
+ *  @retval
+ *      Not Applicable
+ */
+Void Osal_mcbspDeleteSem(Void* semHandle)
+{
+    Semaphore_delete(semHandle);
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used to pend on a semaphore
+ *
+ *  @param[in]  semHandle
+ *      Semaphore handle on which the API will pend
+ *
+ *  @retval
+ *      Not Applicable
+ */
+Void Osal_mcbspPendSem(Void* semHandle)
+{
+    Semaphore_pend(semHandle, BIOS_WAIT_FOREVER);
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used to post a semaphore
+ *
+ *  @param[in]  semHandle
+ *      Semaphore handle which will be posted
+ *
+ *  @retval
+ *      Not Applicable
+ */
+Void Osal_mcbspPostSem(Void* semHandle)
+{
+    Semaphore_post(semHandle);
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      This is the Multicore OSAL Implementation to protect the driver shared
+ *      resources across multiple cores.
+ *
+ *  @retval
+ *      Semaphore Opaque Handle
+ */
+void* Osal_mcbspEnterMultipleCoreCriticalSection(void)
+{
+    /* Get the hardware semaphore */
+   // while ((CSL_semAcquireDirect (MCBSP_HW_SEM)) == 0);
+    return NULL;
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is called to end the critical section which was protecting
+ *      shared resources from access across multiple cores.
+ *
+ *  @param[in]  critSectHandle
+ *      Semaphore opaque handle.
+ *
+ *  @retval
+ *      None
+ */
+Void  Osal_mcbspExitMultipleCoreCriticalSection(Void* critSectHandle)
+{
+    //CSL_semReleaseSemaphore (MCBSP_HW_SEM);
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used to provide critical section to prevent access of shared
+ *      resources from single core and multiple threads.  
+ *
+ *  @param[in]  drvHandle
+ *      Driver Handle which needs critical section to protect its resources.
+ *
+ *  @retval
+ *      Opaque handle
+ */
+Void* Osal_mcbspEnterSingleCoreCriticalSection()
+{
+    /* Disable interrupts */
+     return (Void*)Hwi_disable();
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is called to end the critical section access of shared resources
+ *      from single cores.
+ *
+ *  @param[in]  drvHandle
+ *      Driver Handle which needed critical section to protect its resources.
+ *  @param[in]  critSectHandle
+ *      Opaque handle retreived when the Single Core Protection Enter API was called
+ *
+ *  @retval
+ *      Not Applicable.
+ */
+Void Osal_mcbspExitSingleCoreCriticalSection(Void* critSectHandle)
+{
+    /* Driver Managed Configuration: We need to enable interrupts. */
+    Hwi_enable();
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used by the MCBSP driver to indicate that
+ *      its about to access a block of memory and we need to ensure
+ *      that the cache contents for this block are invalidated before
+ *      we try and use it.
+ *
+ *  @param[in]  ptr
+ *      Pointer to the buffer which is being accessed
+ *  @param[in]  size
+ *      Size of the buffer which is to be accessed.
+ *
+ *  @retval
+ *      None
+ */
+#include "ti/sysbios/hal/Cache.h"
+void Osal_mcbspBeginMemAccess(void* ptr, uint32_t size)
+{
+    UInt  key;
+
+    /* Disable Interrupts */
+    key = Hwi_disable();
+
+    /* Cleanup the prefetch buffer also. */
+    //CSL_XMC_invalidatePrefetchBuffer();
+
+    /* Invalidate the cache. */
+    //CACHE_invL1d (ptr, size, CACHE_FENCE_WAIT);
+
+    Cache_inv ((void *) ptr,size, 0x7fff, 1);
+
+    /* Reenable Interrupts. */
+    Hwi_restore(key);
+}
+
+/**
+ *  @b Description
+ *  @n  
+ *      The function is used by the MCBSP driver to indicate that its 
+ *      ending access to a block of memory. We need to ensure that the
+ *      contents of the cache are written back to the actual memory.
+ *
+ *  @param[in]  ptr
+ *      Pointer to the buffer 
+ *  @param[in]  size
+ *      Size of the buffer 
+ *
+ *  @retval
+ *      None
+ */
+void Osal_mcbspEndMemAccess(void* ptr, uint32_t size)
+{
+    UInt  key;
+
+    /* Disable Interrupts */
+    key = Hwi_disable();
+
+    /* Writeback the cache. */
+    //CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
+    Cache_wb ((void *) ptr,size, 0x7fff, 1);
+    /* Reenable Interrupts. */
+    Hwi_restore(key);
+}
+
+/**
+ * @brief   The function is used by the MCBSP driver to test for an 
+ *          empty queue.
+ *
+ *  <b> Parameter </b>
+ *  @n  handle - Handle of a previously created Queue instance object 
+ *
+ *  <b> Return Value </b>
+ *  @n  TRUE - If the queue is empty
+ */
+Bool Osal_mcbspQueueEmpty(void* handle)
+{
+    return Queue_empty(handle);
+}
+
+/**
+ * @brief   The macro is used by the MCBSP driver to get an 
+ *          element from the front of queue. The function 
+ *          removes the element from the front of queue and
+ *          returns a pointer to it.
+ *
+ *  <b> Parameter </b>
+ *  @n  handle - Handle of a previously created Queue instance object 
+ *
+ *  <b> Return Value </b>
+ *  @n  Handle (pointer) to former first element
+ */
+void* Osal_mcbspQueueGet(void* handle)
+{
+    return Queue_get(handle);
+}
+
+/**
+ * @brief   The macro is used by the MCBSP driver to put an 
+ *          element at the end of queue. 
+ *
+ *  <b> Parameter </b>
+ *  @n  handle - Handle of a previously created Queue instance object 
+ *  @n  elem - Pointer to new queue element 
+ *
+ *  <b> Return Value </b>
+ *  @n  None
+ */
+void  Osal_mcbspQueuePut(void* handle, Mcbsp_QueueElem* elem)
+{
+    Queue_put(handle, (Queue_Elem *)elem);
+    return;
+}
+
+/**
+ * @brief   The macro is used by the MCBSP driver to wait 'n' 
+ *          bit clocks to ensure proper synchronization internally. 
+ *
+ *  <b> Parameter </b>
+ *  @n  nticks - Number of bit clocks to wait 
+ *
+ *  <b> Return Value </b>
+ *  @n  None
+ */
+void  Osal_mcbspWaitNBitClocks(uint32_t nticks)
+{
+    Task_sleep(nticks);
+    return;
+}
+
+/* OSAL functions for Platform Library */
+uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment)
+{
+       return malloc(num_bytes);
+}
+
+void Osal_platformFree (uint8_t *dataPtr, uint32_t num_bytes)
+{
+    /* Free up the memory */
+    if (dataPtr)
+    {
+        free(dataPtr);
+    }
+}
+
+void Osal_platformSpiCsEnter(void)
+{
+    /* Get the hardware semaphore.
+     *
+     * Acquire Multi core CPPI synchronization lock
+     */
+    //while ((CSL_semAcquireDirect (PLATFORM_SPI_HW_SEM)) == 0);
+
+    return;
+}
+
+void Osal_platformSpiCsExit (void)
+{
+    /* Release the hardware semaphore
+     *
+     * Release multi-core lock.
+     */
+    //CSL_semReleaseSemaphore (PLATFORM_SPI_HW_SEM);
+
+    return;
+}
diff --git a/example/omapl138/MCBSPDigLpbk/sample_cs.c b/example/omapl138/MCBSPDigLpbk/sample_cs.c
new file mode 100644 (file)
index 0000000..92c20ab
--- /dev/null
@@ -0,0 +1,420 @@
+/*
+ * sample_cs.c
+ *
+ * Sample functions showing the implementation of critical section entry/exit
+ * routines and various semaphore related routines (all BIOS6 depenedent).
+ * These implementations MUST be provided by the user / application, using the
+ * EDMA3 driver, for its correct functioning.
+ *
+ * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/hal/Cache.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/knl/Semaphore.h>
+
+#include "bios6_edma3_drv_sample.h"
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+
+/**
+ * Shadow Region on which the executable is running. Its value is
+ * populated with the DSP Instance Number here in this case.
+ */
+extern unsigned int region_id;
+
+/**
+ * \brief   EDMA3 OS Protect Entry
+ *
+ *      This function saves the current state of protection in 'intState'
+ *      variable passed by caller, if the protection level is
+ *      EDMA3_OS_PROTECT_INTERRUPT. It then applies the requested level of
+ *      protection.
+ *      For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and
+ *      EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored,
+ *      and the requested interrupt is disabled.
+ *      For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, '*intState' specifies the
+ *      Transfer Controller number whose interrupt needs to be disabled.
+ *
+ * \param   level is numeric identifier of the desired degree of protection.
+ * \param   intState is memory location where current state of protection is
+ *      saved for future use while restoring it via edma3OsProtectExit() (Only
+ *      for EDMA3_OS_PROTECT_INTERRUPT protection level).
+ * \return  None
+ */
+void edma3OsProtectEntry (unsigned int edma3InstanceId,
+                                                       int level, unsigned int *intState)
+    {
+    if (((level == EDMA3_OS_PROTECT_INTERRUPT)
+        || (level == EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR))
+        && (intState == NULL))
+        {
+        return;
+        }
+    else
+        {
+        switch (level)
+            {
+            /* Disable all (global) interrupts */
+            case EDMA3_OS_PROTECT_INTERRUPT :
+                *intState = Hwi_disable();
+                break;
+
+            /* Disable scheduler */
+            case EDMA3_OS_PROTECT_SCHEDULER :
+                                       Task_disable();
+                break;
+
+            /* Disable EDMA3 transfer completion interrupt only */
+            case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION :
+                EventCombiner_disableEvent(ccXferCompInt[edma3InstanceId][region_id]);
+                break;
+
+            /* Disable EDMA3 CC error interrupt only */
+            case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR :
+                EventCombiner_disableEvent(ccErrorInt[edma3InstanceId]);
+                break;
+
+            /* Disable EDMA3 TC error interrupt only */
+            case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR :
+                switch (*intState)
+                    {
+                    case 0:
+                    case 1:
+                    case 2:
+                    case 3:
+                    case 4:
+                    case 5:
+                    case 6:
+                    case 7:
+                        /* Fall through... */
+                        /* Disable the corresponding interrupt */
+                        EventCombiner_disableEvent(tcErrorInt[edma3InstanceId][*intState]);
+                        break;
+
+                     default:
+                        break;
+                    }
+
+                break;
+
+            default:
+                break;
+            }
+        }
+    }
+
+
+/**
+ * \brief   EDMA3 OS Protect Exit
+ *
+ *      This function undoes the protection enforced to original state
+ *      as is specified by the variable 'intState' passed, if the protection
+ *      level is EDMA3_OS_PROTECT_INTERRUPT.
+ *      For EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION and
+ *      EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR, variable 'intState' is ignored,
+ *      and the requested interrupt is enabled.
+ *      For EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR, 'intState' specifies the
+ *      Transfer Controller number whose interrupt needs to be enabled.
+ * \param   level is numeric identifier of the desired degree of protection.
+ * \param   intState is original state of protection at time when the
+ *      corresponding edma3OsProtectEntry() was called (Only
+ *      for EDMA3_OS_PROTECT_INTERRUPT protection level).
+ * \return  None
+ */
+void edma3OsProtectExit (unsigned int edma3InstanceId,
+                        int level, unsigned int intState)
+    {
+    switch (level)
+        {
+        /* Enable all (global) interrupts */
+        case EDMA3_OS_PROTECT_INTERRUPT :
+            Hwi_restore(intState);
+            break;
+
+        /* Enable scheduler */
+        case EDMA3_OS_PROTECT_SCHEDULER :
+            Task_enable();
+            break;
+
+        /* Enable EDMA3 transfer completion interrupt only */
+        case EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION :
+            EventCombiner_enableEvent(ccXferCompInt[edma3InstanceId][region_id]);
+            break;
+
+        /* Enable EDMA3 CC error interrupt only */
+        case EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR :
+            EventCombiner_enableEvent(ccErrorInt[edma3InstanceId]);
+            break;
+
+        /* Enable EDMA3 TC error interrupt only */
+        case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR :
+            switch (intState)
+                {
+                case 0:
+                case 1:
+                case 2:
+                case 3:
+                case 4:
+                case 5:
+                case 6:
+                case 7:
+                    /* Fall through... */
+                    /* Enable the corresponding interrupt */
+                    EventCombiner_enableEvent(tcErrorInt[edma3InstanceId][intState]);
+                    break;
+
+                 default:
+                    break;
+                }
+
+            break;
+
+        default:
+            break;
+        }
+    }
+
+
+/**
+ *  \brief   EDMA3 Cache Invalidate
+ *
+ *  This function invalidates the D cache.
+ *
+ *  \param  mem_start_ptr [IN]      Starting address of memory.
+ *                                  Please note that this should be
+ *                                  aligned according to the cache line size.
+ *  \param  num_bytes [IN]          length of buffer
+ *  \return  EDMA3_DRV_SOK if success, else error code in case of error
+ *          or non-alignment of buffers.
+ *
+ * Note: This function is required if the buffer is in DDR.
+ * For other cases, where buffer is NOT in DDR, user
+ * may or may not require the below implementation and
+ * should modify it according to her need.
+ */
+EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr,
+                           unsigned int    num_bytes)
+    {
+    EDMA3_DRV_Result cacheInvResult = EDMA3_DRV_SOK;
+
+    /* Verify whether the start address is cache aligned or not */
+    if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1u))    !=    0)
+        {
+#ifdef EDMA3_DRV_DEBUG
+        EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n",
+                            EDMA3_CACHE_LINE_SIZE_IN_BYTES);
+#endif
+        cacheInvResult = EDMA3_NON_ALIGNED_BUFFERS_ERROR;
+        }
+    else
+        {
+               Cache_inv((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, TRUE);
+        }
+
+    return cacheInvResult;
+}
+
+
+
+/**
+ * \brief   EDMA3 Cache Flush
+ *
+ *  This function flushes (cleans) the Cache
+ *
+ *  \param  mem_start_ptr [IN]      Starting address of memory.
+ *                                  Please note that this should be
+ *                                  aligned according to the cache line size.
+ *  \param  num_bytes [IN]          length of buffer
+ *  \return  EDMA3_DRV_SOK if success, else error code in case of error
+ *          or non-alignment of buffers.
+ *
+ * Note: This function is required if the buffer is in DDR.
+ * For other cases, where buffer is NOT in DDR, user
+ * may or may not require the below implementation and
+ * should modify it according to her need.
+ */
+EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr,
+                      unsigned int num_bytes)
+    {
+    EDMA3_DRV_Result cacheFlushResult = EDMA3_DRV_SOK;
+
+    /* Verify whether the start address is cache aligned or not */
+    if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1u))    !=    0)
+        {
+#ifdef EDMA3_DRV_DEBUG
+        EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n",
+                            EDMA3_CACHE_LINE_SIZE_IN_BYTES);
+#endif
+        cacheFlushResult = EDMA3_NON_ALIGNED_BUFFERS_ERROR;
+        }
+    else
+        {
+               Cache_wb((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, TRUE);
+        }
+
+    return cacheFlushResult;
+}
+
+
+/**
+  * Counting Semaphore related functions (OS dependent) should be
+  * called/implemented by the application. A handle to the semaphore
+  * is required while opening the driver/resource manager instance.
+  */
+
+/**
+ * \brief   EDMA3 OS Semaphore Create
+ *
+ *      This function creates a counting semaphore with specified
+ *      attributes and initial value. It should be used to create a semaphore
+ *      with initial value as '1'. The semaphore is then passed by the user
+ *      to the EDMA3 driver/RM for proper sharing of resources.
+ * \param   initVal [IN] is initial value for semaphore
+ * \param   semParams [IN] is the semaphore attributes.
+ * \param   hSem [OUT] is location to recieve the handle to just created
+ *      semaphore
+ * \return  EDMA3_DRV_SOK if succesful, else a suitable error code.
+ */
+EDMA3_DRV_Result edma3OsSemCreate(int initVal,
+                                                       const Semaphore_Params *semParams,
+                               EDMA3_OS_Sem_Handle *hSem)
+    {
+    EDMA3_DRV_Result semCreateResult = EDMA3_DRV_SOK;
+
+    if(NULL == hSem)
+        {
+        semCreateResult = EDMA3_DRV_E_INVALID_PARAM;
+        }
+    else
+        {
+        *hSem = (EDMA3_OS_Sem_Handle)Semaphore_create(initVal, semParams, NULL);
+        if ( (*hSem) == NULL )
+            {
+            semCreateResult = EDMA3_DRV_E_SEMAPHORE;
+            }
+        }
+
+    return semCreateResult;
+    }
+
+
+/**
+ * \brief   EDMA3 OS Semaphore Delete
+ *
+ *      This function deletes or removes the specified semaphore
+ *      from the system. Associated dynamically allocated memory
+ *      if any is also freed up.
+ * \param   hSem [IN] handle to the semaphore to be deleted
+ * \return  EDMA3_DRV_SOK if succesful else a suitable error code
+ */
+EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem)
+    {
+    EDMA3_DRV_Result semDeleteResult = EDMA3_DRV_SOK;
+
+    if(NULL == hSem)
+        {
+        semDeleteResult = EDMA3_DRV_E_INVALID_PARAM;
+        }
+    else
+        {
+               Semaphore_delete((Semaphore_Handle *)&hSem);
+        }
+
+    return semDeleteResult;
+    }
+
+
+/**
+ * \brief   EDMA3 OS Semaphore Take
+ *
+ *      This function takes a semaphore token if available.
+ *      If a semaphore is unavailable, it blocks currently
+ *      running thread in wait (for specified duration) for
+ *      a free semaphore.
+ * \param   hSem [IN] is the handle of the specified semaphore
+ * \param   mSecTimeout [IN] is wait time in milliseconds
+ * \return  EDMA3_DRV_Result if successful else a suitable error code
+ */
+EDMA3_DRV_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int mSecTimeout)
+    {
+    EDMA3_DRV_Result semTakeResult = EDMA3_DRV_SOK;
+    unsigned short semPendResult;
+
+    if(NULL == hSem)
+        {
+        semTakeResult = EDMA3_DRV_E_INVALID_PARAM;
+        }
+    else
+        {
+        semPendResult = Semaphore_pend(hSem, mSecTimeout);
+        if (semPendResult == FALSE)
+            {
+            semTakeResult = EDMA3_DRV_E_SEMAPHORE;
+            }
+        }
+
+    return semTakeResult;
+    }
+
+
+/**
+ * \brief   EDMA3 OS Semaphore Give
+ *
+ *      This function gives or relinquishes an already
+ *      acquired semaphore token
+ * \param   hSem [IN] is the handle of the specified semaphore
+ * \return  EDMA3_DRV_Result if successful else a suitable error code
+ */
+EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem)
+    {
+    EDMA3_DRV_Result semGiveResult = EDMA3_DRV_SOK;
+
+    if(NULL == hSem)
+        {
+        semGiveResult = EDMA3_DRV_E_INVALID_PARAM;
+        }
+    else
+        {
+               Semaphore_post(hSem);
+        }
+
+    return semGiveResult;
+    }
+
+/* End of File */
+
diff --git a/example/omapl138/MCBSPDigLpbk/sample_init.c b/example/omapl138/MCBSPDigLpbk/sample_init.c
new file mode 100644 (file)
index 0000000..54fc955
--- /dev/null
@@ -0,0 +1,223 @@
+/*
+ * sample_init.c
+ *
+ * Sample Initialization for the EDMA3 Driver for BIOS 6 based applications.
+ * It should be MANDATORILY done once before EDMA3 usage.
+ *
+ * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+
+#include "bios6_edma3_drv_sample.h"
+
+/** @brief EDMA3 Driver Instance specific Semaphore handle */
+extern EDMA3_OS_Sem_Handle semHandle[];
+
+/**  To Register the ISRs with the underlying OS, if required. */
+extern void registerEdma3Interrupts (unsigned int edma3Id);
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+extern void unregisterEdma3Interrupts (unsigned int edma3Id);
+
+/* To find out the DSP# */
+extern unsigned short determineProcId();
+
+/**
+ * To check whether the global EDMA3 configuration is required or not.
+ * It should be done ONCE by any of the masters present in the system.
+ * This function checks whether the global configuration is required by the
+ * current master or not. In case of many masters, it should be done only
+ * by one of the masters. Hence this function will return TRUE only once
+ * and FALSE for all other masters. 
+ */
+extern unsigned short isGblConfigRequired(unsigned int dspNum);
+
+/**
+ * DSP instance number on which the executable is running. Its value is
+ * determined by reading the processor specific register DNUM.
+ */
+unsigned int dsp_num;
+
+/**
+ * Shadow Region on which the executable is runnig. Its value is populated
+ * with the DSP Instance Number here in this case.
+ */
+unsigned int region_id;
+
+/* Number of EDMA3 controllers present in the system */
+extern const unsigned int numEdma3Instances;
+
+/* External Global Configuration Structure */
+extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[];
+
+/* External Instance Specific Configuration Structure */
+extern EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[][EDMA3_MAX_REGIONS];
+
+#if defined (CHIP_TI814X)
+extern EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, unsigned int edma3Id);
+#endif
+
+/**
+ * \brief   EDMA3 Initialization
+ *
+ * This function initializes the EDMA3 Driver and registers the
+ * interrupt handlers.
+ *
+  * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode)
+    {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+    Semaphore_Params semParams;
+    EDMA3_DRV_GblConfigParams *globalConfig = NULL;
+       EDMA3_DRV_InitConfig initCfg;
+       EDMA3_RM_MiscParam miscParam;
+       EDMA3_DRV_Handle hEdma = NULL;
+
+       if ((edma3Id >= numEdma3Instances) || (errorCode == NULL))
+               return hEdma;
+
+    /* DSP instance number */
+    dsp_num = determineProcId();
+//    dsp_num = 0; /* selection of region ID */
+
+       globalConfig = &sampleEdma3GblCfgParams[edma3Id];
+
+       /* Configure it as master, if required */
+       miscParam.isSlave = isGblConfigRequired(dsp_num);
+       edma3Result = EDMA3_DRV_create (edma3Id, globalConfig ,
+                                                                       (void *)&miscParam);
+
+       if (edma3Result == EDMA3_DRV_SOK)
+               {
+               /**
+               * Driver Object created successfully.
+               * Create a semaphore now for driver instance.
+               */
+               Semaphore_Params_init(&semParams);
+
+               initCfg.drvSemHandle = NULL;
+               edma3Result = edma3OsSemCreate(1, &semParams, &initCfg.drvSemHandle);
+               }
+
+       if (edma3Result == EDMA3_DRV_SOK)
+               {
+               /* Save the semaphore handle for future use */
+               semHandle[edma3Id] = initCfg.drvSemHandle;
+
+        /* Driver instance specific config NULL */
+               initCfg.drvInstInitConfig = NULL;
+
+#ifndef EDMA3_DRV_USE_DEF_RM_CFG
+        /* Hook for running examples with default RM config */
+               /* configuration structure for the Driver */
+               initCfg.drvInstInitConfig = &sampleInstInitConfig[edma3Id][dsp_num];
+#endif
+
+               initCfg.isMaster = TRUE;
+               /* Choose shadow region according to the DSP# */
+               initCfg.regionId = (EDMA3_RM_RegionId)dsp_num;
+               /*Saving the regionId for using it in the sample_cs.c file */
+               region_id = (EDMA3_RM_RegionId)dsp_num;
+               /* Driver instance specific config NULL */
+
+               initCfg.gblerrCb = NULL;
+               initCfg.gblerrData = NULL;
+
+               /* Open the Driver Instance */
+               hEdma = EDMA3_DRV_open (edma3Id, (void *) &initCfg, &edma3Result);
+               }
+
+#if defined (CHIP_TI814X)
+       {
+       if(hEdma && (edma3Result == EDMA3_DRV_SOK))
+               {
+               edma3Result = sampleInitXbarEvt(hEdma, edma3Id);
+               }
+       }
+#endif
+       if(hEdma && (edma3Result == EDMA3_DRV_SOK))
+               {
+               /**
+               * Register Interrupt Handlers for various interrupts
+               * like transfer completion interrupt, CC error
+               * interrupt, TC error interrupts etc, if required.
+               */
+               registerEdma3Interrupts(edma3Id);
+               }
+
+       *errorCode = edma3Result;       
+       return hEdma;
+    }
+
+
+/**
+ * \brief   EDMA3 De-initialization
+ *
+ * This function removes the EDMA3 Driver instance and unregisters the
+ * interrupt handlers.
+ *
+  * \return  EDMA3_DRV_SOK if success, else error code
+ */
+EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma)
+    {
+    EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
+
+    /* Unregister Interrupt Handlers first */
+    unregisterEdma3Interrupts(edma3Id);
+
+    /* Delete the semaphore */
+    edma3Result = edma3OsSemDelete(semHandle[edma3Id]);
+
+    if (EDMA3_DRV_SOK == edma3Result )
+        {
+        /* Make the semaphore handle as NULL. */
+        semHandle[edma3Id] = NULL;
+
+        /* Now, close the EDMA3 Driver Instance */
+        edma3Result = EDMA3_DRV_close (hEdma, NULL);
+       }
+
+       if (EDMA3_DRV_SOK == edma3Result )
+        {
+        /* Now, delete the EDMA3 Driver Object */
+        edma3Result = EDMA3_DRV_delete (edma3Id, NULL);
+        }
+
+    return edma3Result;
+    }
+
+/* End of File */
+
diff --git a/example/omapl138/MCBSPDigLpbk/sample_omapl138_cfg.c b/example/omapl138/MCBSPDigLpbk/sample_omapl138_cfg.c
new file mode 100644 (file)
index 0000000..5e670ca
--- /dev/null
@@ -0,0 +1,1391 @@
+/*
+ * sample_omapl138_cfg.c
+ *
+ * SoC specific EDMA3 hardware related information like number of transfer
+ * controllers, various interrupt ids etc. It is used while interrupts
+ * enabling / disabling. It needs to be ported for different SoCs.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sdo/edma3/drv/edma3_drv.h>
+
+/* Number of EDMA3 controllers present in the system */
+#define NUM_EDMA3_INSTANCES         2u
+const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
+
+/* Number of DSPs present in the system */
+#define NUM_DSPS                    1u
+const unsigned int numDsps = NUM_DSPS;
+
+/* Determine the processor id by reading DNUM register. */
+unsigned short determineProcId()
+{
+    return 1;
+}
+
+signed char*  getGlobalAddr(signed char* addr)
+{
+     return (addr); /* The address is already a global address */
+}
+unsigned short isGblConfigRequired(unsigned int dspNum)
+{
+    (void) dspNum;
+
+    return 1;
+}
+
+/* Semaphore handles */
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL};
+
+/** Number of PaRAM Sets available */
+#define EDMA3_NUM_PARAMSET                              (128u)
+/** Number of TCCS available */
+#define EDMA3_NUM_TCC                                   (32u)
+
+/** Number of Event Queues available                                          */
+#define EDMA3_0_NUM_EVTQUE                              (2u)
+#define EDMA3_1_NUM_EVTQUE                              (1u)
+
+/** Number of Transfer Controllers available                                  */
+#define EDMA3_0_NUM_TC                                  (2u)
+#define EDMA3_1_NUM_TC                                  (1u)
+
+#ifdef __TMS470__  /* values for ARM */
+
+#else /* values for DSP */
+/** Interrupt no. for Transfer Completion                                     */
+#define EDMA3_0_CC_XFER_COMPLETION_INT                  (8u)
+#define EDMA3_1_CC_XFER_COMPLETION_INT                  (91u)
+
+/** Interrupt no. for CC Error                                                */
+#define EDMA3_0_CC_ERROR_INT                            (56u)
+#define EDMA3_1_CC_ERROR_INT                            (92u)
+
+/** Interrupt no. for TCs Error                                               */
+#define EDMA3_0_TC0_ERROR_INT                           (57u)
+#define EDMA3_0_TC1_ERROR_INT                           (58u)
+#define EDMA3_0_TC2_ERROR_INT                           (0u)
+#define EDMA3_0_TC3_ERROR_INT                           (0u)
+#define EDMA3_0_TC4_ERROR_INT                           (0u)
+#define EDMA3_0_TC5_ERROR_INT                           (0u)
+#define EDMA3_0_TC6_ERROR_INT                           (0u)
+#define EDMA3_0_TC7_ERROR_INT                           (0u)
+
+#define EDMA3_1_TC0_ERROR_INT                           (93u)
+#define EDMA3_1_TC1_ERROR_INT                           (0u)
+#define EDMA3_1_TC2_ERROR_INT                           (0u)
+#define EDMA3_1_TC3_ERROR_INT                           (0u)
+#define EDMA3_1_TC4_ERROR_INT                           (0u)
+#define EDMA3_1_TC5_ERROR_INT                           (0u)
+#define EDMA3_1_TC6_ERROR_INT                           (0u)
+#define EDMA3_1_TC7_ERROR_INT                           (0u)
+
+/**
+ * EDMA3 interrupts (transfer completion, CC error etc.) correspond to different
+ * ECM events (SoC specific). These ECM events come
+ * under ECM block XXX (handling those specific ECM events). Normally, block
+ * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+ * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+ * is mapped to a specific HWI_INT YYY in the tcf file.
+ * Define EDMA3_HWI_INT_XFER_COMP to specific HWI_INT, corresponding
+ * to transfer completion interrupt.
+ * Define EDMA3_HWI_INT_CC_ERR to specific HWI_INT, corresponding
+ * to CC error interrupts.
+ * Define EDMA3_HWI_INT_TC_ERR to specific HWI_INT, corresponding
+ * to TC error interrupts.
+ */
+/* EDMA 0 */
+#define EDMA3_0_HWI_INT_XFER_COMP                           (7u)
+#define EDMA3_0_HWI_INT_CC_ERR                              (8u)
+#define EDMA3_0_HWI_INT_TC0_ERR                             (8u)
+#define EDMA3_0_HWI_INT_TC1_ERR                             (8u)
+
+/* EDMA 1 */
+#define EDMA3_1_HWI_INT_XFER_COMP                           (9u)
+#define EDMA3_1_HWI_INT_CC_ERR                              (9u)
+#define EDMA3_1_HWI_INT_TC0_ERR                             (9u)
+
+#endif  /* __TMS470__ */
+
+/**
+ * \brief Mapping of DMA channels 0-31 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+                                                      /* 31     0 */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0xFF3FF3FFu)
+#define EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0       (0x3F07FFFFu)
+
+/**
+ * \brief Mapping of DMA channels 32-63 to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ * 1: Mapped
+ * 0: Not mapped
+ *
+ * This mapping will be used to allocate DMA channels when user passes
+ * EDMA3_DRV_DMA_CHANNEL_ANY as dma channel id (for eg to do memory-to-memory
+ * copy). The same mapping is used to allocate the TCC when user passes
+ * EDMA3_DRV_TCC_ANY as tcc id (for eg to do memory-to-memory copy).
+ *
+ * To allocate more DMA channels or TCCs, one has to modify the event mapping.
+ */
+/* DMA channels 32-63 DOES NOT exist in omapl138. */
+#define EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x0u)
+#define EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1       (0x0u)
+
+/* Variable which will be used internally for referring number of Event Queues*/
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] =  {
+                                                        EDMA3_0_NUM_EVTQUE,
+                                                        EDMA3_1_NUM_EVTQUE
+                                                    };
+
+/* Variable which will be used internally for referring number of TCs.        */
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] =  {
+                                                    EDMA3_0_NUM_TC,
+                                                    EDMA3_1_NUM_TC
+                                                };
+
+/**
+ * Variable which will be used internally for referring transfer completion
+ * interrupt.
+ */
+unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
+                {
+                    0u, EDMA3_0_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+                },
+                {
+                    0u, EDMA3_1_CC_XFER_COMPLETION_INT, 0u, 0u, 0u, 0u, 0u, 0u,
+                },
+            };
+
+/**
+ * Variable which will be used internally for referring channel controller's
+ * error interrupt.
+ */
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_CC_ERROR_INT,
+                                                    EDMA3_1_CC_ERROR_INT
+                                               };
+
+/**
+ * Variable which will be used internally for referring transfer controllers'
+ * error interrupts.
+ */
+unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][8] = {
+                               {
+                                   EDMA3_0_TC0_ERROR_INT, EDMA3_0_TC1_ERROR_INT,
+                                   EDMA3_0_TC2_ERROR_INT, EDMA3_0_TC3_ERROR_INT,
+                                   EDMA3_0_TC4_ERROR_INT, EDMA3_0_TC5_ERROR_INT,
+                                   EDMA3_0_TC6_ERROR_INT, EDMA3_0_TC7_ERROR_INT,
+                               },
+                               {
+                                   EDMA3_1_TC0_ERROR_INT, EDMA3_1_TC1_ERROR_INT,
+                                   EDMA3_1_TC2_ERROR_INT, EDMA3_1_TC3_ERROR_INT,
+                                   EDMA3_1_TC4_ERROR_INT, EDMA3_1_TC5_ERROR_INT,
+                                   EDMA3_1_TC6_ERROR_INT, EDMA3_1_TC7_ERROR_INT,
+                               }
+                            };
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+unsigned int hwIntXferComp[NUM_EDMA3_INSTANCES] = {
+                                                    EDMA3_0_HWI_INT_XFER_COMP,
+                                                    EDMA3_1_HWI_INT_XFER_COMP
+                                                  };
+
+unsigned int hwIntCcErr[NUM_EDMA3_INSTANCES] = {
+                                                   EDMA3_0_HWI_INT_CC_ERR,
+                                                   EDMA3_1_HWI_INT_CC_ERR
+                                               };
+
+unsigned int hwIntTcErr[NUM_EDMA3_INSTANCES][8] = {
+                                                     {
+                                                        EDMA3_0_HWI_INT_TC0_ERR,
+                                                        EDMA3_0_HWI_INT_TC1_ERR,
+                                                     },
+                                                     {
+                                                        EDMA3_1_HWI_INT_TC0_ERR,
+                                                     }
+                                               };
+
+/* Driver Object Initialization Configuration */
+EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
+{
+    {
+        /* EDMA3 INSTANCE# 0 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller    */
+        32u,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller   */
+        8u,
+        /** Total number of TCCs supported by the EDMA3 Controller            */
+        32u,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller      */
+        128u,
+        /** Total number of Event Queues in the EDMA3 Controller              */
+        2u,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller*/
+        2u,
+        /** Number of Regions on this EDMA3 controller                        */
+        4u,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        0u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        (void *)0x01C00000u,
+        /** Transfer Controller (TC) Registers */
+        {
+            (void *)0x01C08000u,
+            (void *)0x01C08400u,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+        },
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_0_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_0_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+        {
+            EDMA3_0_TC0_ERROR_INT,
+            EDMA3_0_TC1_ERROR_INT,
+            EDMA3_0_TC2_ERROR_INT,
+            EDMA3_0_TC3_ERROR_INT,
+            EDMA3_0_TC4_ERROR_INT,
+            EDMA3_0_TC5_ERROR_INT,
+            EDMA3_0_TC6_ERROR_INT,
+            EDMA3_0_TC7_ERROR_INT
+        },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+        {
+            0u,
+            1u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+            {
+            16u,
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+            {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+            },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+            {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u,
+            20u, 21u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+            },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+            {
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            }
+        },
+
+        {
+        /* EDMA3 INSTANCE# 1 */
+        /** Total number of DMA Channels supported by the EDMA3 Controller */
+        32u,
+        /** Total number of QDMA Channels supported by the EDMA3 Controller */
+        8u,
+        /** Total number of TCCs supported by the EDMA3 Controller */
+        32u,
+        /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+        128u,
+        /** Total number of Event Queues in the EDMA3 Controller */
+        1u,
+        /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+        1u,
+        /** Number of Regions on this EDMA3 controller */
+        4u,
+
+        /**
+         * \brief Channel mapping existence
+         * A value of 0 (No channel mapping) implies that there is fixed association
+         * for a channel number to a parameter entry number or, in other words,
+         * PaRAM entry n corresponds to channel n.
+         */
+        0u,
+
+        /** Existence of memory protection feature */
+        0u,
+
+        /** Global Register Region of CC Registers */
+        (void *)0x01E30000u,
+        /** Transfer Controller (TC) Registers */
+            {
+            (void *)0x01E38000u,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL,
+            (void *)NULL
+            },
+        /** Interrupt no. for Transfer Completion */
+        EDMA3_1_CC_XFER_COMPLETION_INT,
+        /** Interrupt no. for CC Error */
+        EDMA3_1_CC_ERROR_INT,
+        /** Interrupt no. for TCs Error */
+            {
+                EDMA3_1_TC0_ERROR_INT,
+                EDMA3_1_TC1_ERROR_INT,
+                EDMA3_1_TC2_ERROR_INT,
+                EDMA3_1_TC3_ERROR_INT,
+                EDMA3_1_TC4_ERROR_INT,
+                EDMA3_1_TC5_ERROR_INT,
+                EDMA3_1_TC6_ERROR_INT,
+                EDMA3_1_TC7_ERROR_INT,
+            },
+
+        /**
+         * \brief EDMA3 TC priority setting
+         *
+         * User can program the priority of the Event Queues
+         * at a system-wide level.  This means that the user can set the
+         * priority of an IO initiated by either of the TCs (Transfer Controllers)
+         * relative to IO initiated by the other bus masters on the
+         * device (ARM, DSP, USB, etc)
+         */
+            {
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+            },
+        /**
+         * \brief To Configure the Threshold level of number of events
+         * that can be queued up in the Event queues. EDMA3CC error register
+         * (CCERR) will indicate whether or not at any instant of time the
+         * number of events queued up in any of the event queues exceeds
+         * or equals the threshold/watermark value that is set
+         * in the queue watermark threshold register (QWMTHRA).
+         */
+        {
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief To Configure the Default Burst Size (DBS) of TCs.
+         * An optimally-sized command is defined by the transfer controller
+         * default burst size (DBS). Different TCs can have different
+         * DBS values. It is defined in Bytes.
+         */
+        {
+            16u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u,
+            0u
+        },
+
+        /**
+         * \brief Mapping from each DMA channel to a Parameter RAM set,
+         * if it exists, otherwise of no use.
+         */
+        {
+            0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+            16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+            24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+            EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+        },
+
+         /**
+          * \brief Mapping from each DMA channel to a TCC. This specific
+          * TCC code will be returned when the transfer is completed
+          * on the mapped channel.
+          */
+        {
+            0u, 1u, 2u, 3u,
+            4u, 5u, 6u, 7u,
+            8u, 9u, 10u, 11u,
+            12u, 13u, 14u, 15u,
+            16u, 17u, 18u, EDMA3_RM_CH_NO_TCC_MAP,
+            EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            24u, 25u, 26u, 27u,
+            28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+            /* DMA channels 32-63 DOES NOT exist in OMAPL138. */
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+            EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+        },
+
+        /**
+         * \brief Mapping of DMA channels to Hardware Events from
+         * various peripherals, which use EDMA for data transfer.
+         * All channels need not be mapped, some can be free also.
+         */
+        {
+            EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1
+        }
+    },
+};
+
+
+/* Driver Instance Initialization Configuration */
+EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+    /* EDMA3 INSTANCE# 0 */
+    {
+        /* Resources owned/reserved by region 0 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+        /* Resources owned/reserved by region 1 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* resvdDmaChannels */
+            /* 31       0 */
+            {0xFF3FF3FFu,
+            /* 63..32 */
+            0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31       0 */
+            {EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+            /* 63..32 */
+            EDMA3_0_DMA_CHANNEL_TO_EVENT_MAPPING_1},
+        },
+        /* Resources owned/reserved by region 2 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 3 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 4 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 5 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 6 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 7 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+    },
+    /* EDMA3 INSTANCE# 1 */
+    {
+        /* Resources owned/reserved by region 0 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+        /* Resources owned by Region 1 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0xFFFFFFFFu, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x000000FFu},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {
+                0xFFFFFFFFu,
+                0x00000000u
+            },
+
+            /* Resources reserved by Region 1 */
+            /* resvdPaRAMSets */
+                /* 31     0     63    32     95    64     127   96 */
+            {
+                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
+                /* 159  128     191  160     223  192     255  224 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                /* 287  256     319  288     351  320     383  352 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                /* 415  384     447  416     479  448     511  480 */
+                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            },
+
+            /* resvdDmaChannels */
+                /* 31      0  */
+            {
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_0,
+                /* 63..32   */
+                EDMA3_1_DMA_CHANNEL_TO_EVENT_MAPPING_1
+            },
+
+            /* resvdQdmaChannels */
+            /* 31     0  */
+            {
+                0x00000000u
+            },
+
+            /* resvdTccs */
+            /* 31      0 */
+            {
+                0x3F07FFFFu,
+                /* 63..32 */
+                0x00000000u
+            },
+        },
+        /* Resources owned/reserved by region 2 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 3 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 4 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 5 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 6 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        },
+
+        /* Resources owned/reserved by region 7 */
+        {
+            /* ownPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* ownDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* ownQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* ownTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdPaRAMSets */
+            /* 31     0     63    32     95    64     127   96 */
+            {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 159  128     191  160     223  192     255  224 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 287  256     319  288     351  320     383  352 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+            /* 415  384     447  416     479  448     511  480 */
+             0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+
+            /* resvdDmaChannels */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+
+            /* resvdQdmaChannels */
+            /* 31     0 */
+            {0x00000000u},
+
+            /* resvdTccs */
+            /* 31     0     63    32 */
+            {0x00000000u, 0x00000000u},
+        }
+    }
+};
+
+/* End of File */
+
diff --git a/example/omapl138/MCBSPDigLpbk/sample_omapl138_int_reg.c b/example/omapl138/MCBSPDigLpbk/sample_omapl138_int_reg.c
new file mode 100644 (file)
index 0000000..e82c939
--- /dev/null
@@ -0,0 +1,152 @@
+/*
+ * sample_omapl138_int_reg.c
+ *
+ * Platform specific interrupt registration and un-registration routines.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include <ti/sysbios/family/c64p/EventCombiner.h>
+#include <ti/sysbios/family/c64p/Hwi.h>
+
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
+
+/**
+  * EDMA3 TC ISRs which need to be registered with the underlying OS by the user
+  * (Not all TC error ISRs need to be registered, register only for the
+  * available Transfer Controllers).
+  */
+void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
+                                                {
+                                                &lisrEdma3TC0ErrHandler0,
+                                                &lisrEdma3TC1ErrHandler0,
+                                                &lisrEdma3TC2ErrHandler0,
+                                                &lisrEdma3TC3ErrHandler0,
+                                                &lisrEdma3TC4ErrHandler0,
+                                                &lisrEdma3TC5ErrHandler0,
+                                                &lisrEdma3TC6ErrHandler0,
+                                                &lisrEdma3TC7ErrHandler0,
+                                                };
+
+extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
+extern unsigned int ccErrorInt[];
+extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern unsigned int numEdma3Tc[];
+
+/**
+ * Variables which will be used internally for referring the hardware interrupt
+ * for various EDMA3 interrupts.
+ */
+extern unsigned int hwIntXferComp[];
+extern unsigned int hwIntCcErr[];
+extern unsigned int hwIntTcErr[];
+
+extern unsigned int dsp_num;
+
+/**  To Register the ISRs with the underlying OS, if required. */
+void registerEdma3Interrupts (unsigned int edma3Id)
+    {
+    static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Enable the Xfer Completion Event Interrupt */
+    EventCombiner_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
+                               edma3Id, 1);
+    EventCombiner_enableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Enable the CC Error Event Interrupt */
+    EventCombiner_dispatchPlug(ccErrorInt[edma3Id],
+                                               (EventCombiner_FuncPtr)(&lisrEdma3CCErrHandler0),
+                                               edma3Id, 1);
+    EventCombiner_enableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+           {
+        EventCombiner_dispatchPlug(tcErrorInt[edma3Id][numTc],
+                            (EventCombiner_FuncPtr)(ptrEdma3TcIsrHandler[numTc]),
+                            edma3Id, 1);
+        EventCombiner_enableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+   /**
+    * Enabling the HWI_ID.
+    * EDMA3 interrupts (transfer completion, CC error etc.)
+    * correspond to different ECM events (SoC specific). These ECM events come
+    * under ECM block XXX (handling those specific ECM events). Normally, block
+    * 0 handles events 4-31 (events 0-3 are reserved), block 1 handles events
+    * 32-63 and so on. This ECM block XXX (or interrupt selection number XXX)
+    * is mapped to a specific HWI_INT YYY in the tcf file. So to enable this
+    * mapped HWI_INT YYY, one should use the corresponding bitmask in the
+    * API C64_enableIER(), in which the YYY bit is SET.
+    */
+    Hwi_enableInterrupt(hwIntXferComp[edma3Id]);
+    Hwi_enableInterrupt(hwIntCcErr[edma3Id]);
+    Hwi_enableInterrupt(hwIntTcErr[edma3Id]);
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
+/**  To Unregister the ISRs with the underlying OS, if previously registered. */
+void unregisterEdma3Interrupts (unsigned int edma3Id)
+    {
+       static UInt32 cookie = 0;
+    unsigned int numTc = 0;
+
+    /* Disabling the global interrupts */
+    cookie = Hwi_disable();
+
+    /* Disable the Xfer Completion Event Interrupt */
+       EventCombiner_disableEvent(ccXferCompInt[edma3Id][dsp_num]);
+
+    /* Disable the CC Error Event Interrupt */
+       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
+
+    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
+    while (numTc < numEdma3Tc[edma3Id])
+       {
+        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
+        numTc++;
+       }
+
+    /* Restore interrupts */
+    Hwi_restore(cookie);
+    }
+
index c6259ef5d969e9159af51e4e0e5e8fcc1cf8ade7..c47853b9ca56e8059c2533553a21e292d5a4810c 100644 (file)
@@ -48,7 +48,9 @@ function getLibs(prog)
     /* Get target folder, if applicable */
     if ( java.lang.String(suffix).contains('66') )
         lib = lib + "/c66";
-
+       else if ( java.lang.String(suffix).contains('674') )
+        lib = lib + "/c674";
+               
     /* Get library name with path */
     lib = lib + "/" + name;
     if (java.io.File(this.packageBase + lib).exists()) {