Fixing the loopback test issue on C6657
authorMahesh Radhakrishnan <m-radhakrishnan2@ti.com>
Tue, 22 Mar 2016 22:38:27 +0000 (18:38 -0400)
committerMahesh Radhakrishnan <m-radhakrishnan2@ti.com>
Tue, 22 Mar 2016 22:38:27 +0000 (18:38 -0400)
Signed-off-by: Mahesh Radhakrishnan <m-radhakrishnan2@ti.com>
example/c6657/MCBSPDigLpbk/MCBSP_evmc6657_C66DigLpbkExampleProject.txt
example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.c
example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg
example/c6657/MCBSPDigLpbk/sample_c6657_cfg.c
example/c6657/MCBSPDigLpbk/sample_c6657_int_reg.c
example/c6657/MCBSPDigLpbk/sample_cs.c
example/c6657/MCBSPDigLpbk/sample_init.c

index 4a5b5e795a60528d8bc00a728ac61927f7d1f414..44464ebbf0403782bb0ac3d3d7e5d805f413d30d 100644 (file)
@@ -3,10 +3,6 @@
 -ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cmd" 
 -ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk.cfg" 
 -ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/mcbspMasterDigLpbk_osal.c" 
--ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_c6657_cfg.c" 
--ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_c6657_int_reg.c" 
--ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_cs.c" 
--ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/example/c6657/MCBSPDigLpbk/sample_init.c" 
 -ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/src/mcbsp_drv.c"
 -ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/src/mcbsp_edma.c"
 -ccs.linkFile "${PDK_INSTALL_PATH}/ti/drv/mcbsp/src/mcbsp_ioctl.c"
index ec0ec8bf36d7e87917429309d2e716baac2893fe..7281420d4e4d4f470d465c2a70c40d2ab6a78ff8 100644 (file)
@@ -71,6 +71,8 @@
 //#include <ti/platform/platform.h>
 
 
+extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[];
+extern EDMA3_RM_InstanceInitConfig sampleInstInitConfig[2][8];
 /* ========================================================================== */
 /*                        EXTERNAL FUNCTIONS                                  */
 /* ========================================================================== */
@@ -854,6 +856,7 @@ Void main(Void)
     EDMA3_DRV_Result edmaResult = 0;
     uint8_t uchValue, uchReadValue;
 
+    uint32_t temp;
     /* Get the core number. */
     coreNum = 0; //CSL_chipReadReg (CSL_CHIP_DNUM);
 
@@ -940,6 +943,17 @@ Void main(Void)
 
         System_printf ("Debug(Core %d): MCBSP can now be used.\n", coreNum);
     }
+    /* Enabling the dmaChannel MCBSP Events to EDMA (36-40) */
+    temp=sampleEdma3GblCfgParams[0].dmaChannelHwEvtMap[1];
+    sampleEdma3GblCfgParams[0].dmaChannelHwEvtMap[1]= temp | 0x000000F0;
+
+    /* Let RM Own the dmaChannels (36-40) */
+     temp=sampleInstInitConfig[0][0].ownDmaChannels[1];
+     sampleInstInitConfig[0][0].ownDmaChannels[1]=temp | 0x000000F0;
+
+     /* Let RM Own the TCCs (36-40) */
+     temp=sampleInstInitConfig[0][0].ownTccs[1];
+     sampleInstInitConfig[0][0].ownTccs[1]= temp | 0x000000F0;
 
     /* Initialize EDMA3 library */
     hEdma[0] = edma3init(0, &edmaResult);
index 8c7dfd3746c344bebf56d6a02c9dc7f5648542d7..68ba2a0ceb8cc3239965df774b8a89b432aace91 100644 (file)
@@ -50,7 +50,9 @@ ECM.eventGroupHwiNum[3] = 10;
 
 /* Load and use the CSL, EDMA, PlatformLib etc. packages */
 //var cslSettings = xdc.useModule ('ti.csl.Settings');
-var Edma = xdc.loadPackage('ti.sdo.edma3.drv');
+var Edma                       = xdc.loadPackage ("ti.sdo.edma3.drv.sample");
+var drv                        = xdc.loadPackage ("ti.sdo.edma3.drv");
+var rm                 = xdc.loadPackage ("ti.sdo.edma3.rm");
 //var PlatformLib = xdc.loadPackage('ti.platform.evmc6657l');
 
 /* Circular buffer size for System_printf() */
index 36e4e45b894b412debfc09a34ea6e96fedd0a16c..b698e98d206b678fb3b4e7f11bb723f8f7ebd640 100644 (file)
@@ -1,11 +1,11 @@
 /*
- * sample_galileo_cfg.c
+ * sample_c6657_cfg.c
  *
  * Platform specific EDMA3 hardware related information like number of transfer
  * controllers, various interrupt ids etc. It is used while interrupts
  * enabling / disabling. It needs to be ported for different SoCs.
  *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
  *
  *
  *  Redistribution and use in source and binary forms, with or without
 #include <ti/sdo/edma3/rm/edma3_rm.h>
 
 /* Number of EDMA3 controllers present in the system */
-#define NUM_EDMA3_INSTANCES                    2u
+#define NUM_EDMA3_INSTANCES                    1u
 const unsigned int numEdma3Instances = NUM_EDMA3_INSTANCES;
 
 /* Number of DSPs present in the system */
-#define NUM_DSPS                                       1u
+#define NUM_DSPS                                       2u
 //const unsigned int numDsps = NUM_DSPS;
 
 #define CGEM_REG_START                  (0x01800000)
@@ -85,7 +85,7 @@ signed char*  getGlobalAddr(signed char* addr)
  */
 unsigned int gblCfgReqdArray [NUM_DSPS] = {
                                                                        0,      /* DSP#0 is Master, will do the global init */
-
+                                                                       1,      /* DSP#1 is Slave, will not do the global init  */
                                                                        };
 
 unsigned short isGblConfigRequired(unsigned int dspNum)
@@ -94,14 +94,14 @@ unsigned short isGblConfigRequired(unsigned int dspNum)
        }
 
 /* Semaphore handles */
-EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL,NULL};
+EDMA3_OS_Sem_Handle semHandle[NUM_EDMA3_INSTANCES] = {NULL};
 
 
 /* Variable which will be used internally for referring number of Event Queues. */
-unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {2u, 2u};
+unsigned int numEdma3EvtQue[NUM_EDMA3_INSTANCES] = {4u};
 
 /* Variable which will be used internally for referring number of TCs. */
-unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 2u};
+unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {4u};
 
 /**
  * Variable which will be used internally for referring transfer completion
@@ -110,12 +110,8 @@ unsigned int numEdma3Tc[NUM_EDMA3_INSTANCES] = {2u, 2u};
  */
 unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
                                                                                                        {
-                                                                                                       0x88, 0x89, 0x8a, 0x8b,
-                                                                                                       0x8c, 0x8d, 0x8e, 0x8f,
-                                                                                                       },
-                                                                                                       {
-                                                                                                       0x90, 0x91, 0x92, 0x93,
-                                                                                                       0x94, 0x95, 0x96, 0x97,
+                                                                                                       24u, 25u, 26u, 27u,
+                                                                                                       28u, 29u, 30u, 31u,
                                                                                                        },
                                                                                                };
 
@@ -123,7 +119,7 @@ unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
  * Variable which will be used internally for referring channel controller's
  * error interrupt.
  */
-unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {0x99, 0x9c};
+unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {16u};
 
 /**
  * Variable which will be used internally for referring transfer controllers'
@@ -131,11 +127,7 @@ unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {0x99, 0x9c};
  */
 unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] =    {
                                                                                                        {
-                                                                                                       0xA0,0xA1, 0u, 0u,
-                                                                                                       0u, 0u, 0u, 0u,
-                                                                                                       },
-                                                                                                       {
-                                                                                                       0xA4, 0xA5, 0u, 0u,
+                                                                                                       18u, 19u, 20u, 21u,
                                                                                                        0u, 0u, 0u, 0u,
                                                                                                        },
                                                                                                };
@@ -154,9 +146,9 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                /** Total number of PaRAM Sets supported by the EDMA3 Controller */
                512u,
                /** Total number of Event Queues in the EDMA3 Controller */
-               2u,
+               4u,
                /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-               2u,
+               4u,
                /** Number of Regions on this EDMA3 controller */
                8u,
 
@@ -172,182 +164,28 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                1u,
 
                /** Global Register Region of CC Registers */
-               (void *)0x02700000u,
+               (void *)0x02740000u,
                /** Transfer Controller (TC) Registers */
                {
-               (void *)0x02760000u,
-               (void *)0x02768000u,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
+               (void *)0x02790000u,
+               (void *)0x02798000u,
+               (void *)0x027A0000u,
+               (void *)0x027A8000u,
                (void *)NULL,
                (void *)NULL,
                (void *)NULL,
+               (void *)NULL
                },
                /** Interrupt no. for Transfer Completion */
-               0x88,
+               24u,
                /** Interrupt no. for CC Error */
-               0x99,
-               /** Interrupt no. for TCs Error */
-               {
-               0xA0,
-               0xA1,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               },
-
-               /**
-                * \brief EDMA3 TC priority setting
-                *
-                * User can program the priority of the Event Queues
-                * at a system-wide level.  This means that the user can set the
-                * priority of an IO initiated by either of the TCs (Transfer Controllers)
-                * relative to IO initiated by the other bus masters on the
-                * device (ARM, DSP, USB, etc)
-                */
-               {
-               0u,
-               1u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               },
-               /**
-                * \brief To Configure the Threshold level of number of events
-                * that can be queued up in the Event queues. EDMA3CC error register
-                * (CCERR) will indicate whether or not at any instant of time the
-                * number of events queued up in any of the event queues exceeds
-                * or equals the threshold/watermark value that is set
-                * in the queue watermark threshold register (QWMTHRA).
-                */
-               {
-               16u,
                16u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               },
-
-               /**
-                * \brief To Configure the Default Burst Size (DBS) of TCs.
-                * An optimally-sized command is defined by the transfer controller
-                * default burst size (DBS). Different TCs can have different
-                * DBS values. It is defined in Bytes.
-                */
-               {
-               128u,
-               128u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               0u,
-               },
-
-               /**
-                * \brief Mapping from each DMA channel to a Parameter RAM set,
-                * if it exists, otherwise of no use.
-                */
-               {
-               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-               40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-               56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u,
-               },
-
-                /**
-                 * \brief Mapping from each DMA channel to a TCC. This specific
-                 * TCC code will be returned when the transfer is completed
-                 * on the mapped channel.
-                 */
-               {
-               0u, 1u, 2u, EDMA3_RM_CH_NO_TCC_MAP, 4u, 5u, 6u, EDMA3_RM_CH_NO_TCC_MAP,
-               8u, 9u, 10u, EDMA3_RM_CH_NO_TCC_MAP, 12u, 13u, 14u, EDMA3_RM_CH_NO_TCC_MAP,
-               16u, 17u, 18u, EDMA3_RM_CH_NO_TCC_MAP, 20u, 21u, 22u, EDMA3_RM_CH_NO_TCC_MAP,
-               24u, 25u, 26u, 27u, 28u, 29u, 30u, EDMA3_RM_CH_NO_TCC_MAP,
-               32u, 33u, 34u, 35u, 36u, 37u, 38u, EDMA3_RM_CH_NO_TCC_MAP,
-               40u, 41u, 42u, EDMA3_RM_CH_NO_TCC_MAP, 44u, 45u, 46u, EDMA3_RM_CH_NO_TCC_MAP,
-               48u, 49u, 50u, 51u, 52u, 53u, 54u, EDMA3_RM_CH_NO_TCC_MAP,
-               56u, 57u, 58u, 59u, 60u, 61u, 62u, EDMA3_RM_CH_NO_TCC_MAP
-               },
-
-               /**
-                * \brief Mapping of DMA channels to Hardware Events from
-                * various peripherals, which use EDMA for data transfer.
-                * All channels need not be mapped, some can be free also.
-                */
-               {
-               0x0F000000u,
-               0x0000000Fu
-               }
-               },
-
-               {
-               /* EDMA3 INSTANCE# 1 */
-               /** Total number of DMA Channels supported by the EDMA3 Controller */
-               64u,
-               /** Total number of QDMA Channels supported by the EDMA3 Controller */
-               8u,
-               /** Total number of TCCs supported by the EDMA3 Controller */
-               64u,
-               /** Total number of PaRAM Sets supported by the EDMA3 Controller */
-               512u,
-               /** Total number of Event Queues in the EDMA3 Controller */
-               2u,
-               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
-               2u,
-               /** Number of Regions on this EDMA3 controller */
-               8u,
-
-               /**
-                * \brief Channel mapping existence
-                * A value of 0 (No channel mapping) implies that there is fixed association
-                * for a channel number to a parameter entry number or, in other words,
-                * PaRAM entry n corresponds to channel n.
-                */
-               1u,
-
-               /** Existence of memory protection feature */
-               1u,
-
-               /** Global Register Region of CC Registers */
-               (void *)0x02728000U,
-               /** Transfer Controller (TC) Registers */
-               {
-               (void *)0x027b0000U,
-               (void *)0x027b8000U,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               (void *)NULL,
-               },
-               /** Interrupt no. for Transfer Completion */
-               0x90,
-               /** Interrupt no. for CC Error */
-               0x9c,
                /** Interrupt no. for TCs Error */
                {
-               0xA2,
-               0xA3,
-               0u,
-               0u,
+               18u,
+               19u,
+               20u,
+               21u,
                0u,
                0u,
                0u,
@@ -366,8 +204,8 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                {
                0u,
                1u,
-               0u,
-               0u,
+               2u,
+               3u,
                0u,
                0u,
                0u,
@@ -384,8 +222,8 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                {
                16u,
                16u,
-               0u,
-               0u,
+               16u,
+               16u,
                0u,
                0u,
                0u,
@@ -401,8 +239,8 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                {
                64u,
                64u,
-               0u,
-               0u,
+               64u,
+               64u,
                0u,
                0u,
                0u,
@@ -414,14 +252,38 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                 * if it exists, otherwise of no use.
                 */
                {
-               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
-               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
-               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-               40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
-               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-               56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
+                   EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
                },
 
                 /**
@@ -431,13 +293,15 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                  */
                {
                0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
-               8u, 9u, 10u, 11u, 12u, 13u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
                16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
-               24u, 25u, 26u, 27u, 28u, 29u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
                32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
-               40u, 41u, 42u, 43u, 44u, 45u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
-               48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
-               56u, 57u, 58u, 59u, 60u, 61u, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 
+    EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, 
+    EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+               56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
                },
 
                /**
@@ -446,148 +310,53 @@ EDMA3_RM_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
                 * All channels need not be mapped, some can be free also.
                 */
                {
-               0x00000000u,
-               0xFFF00000u
+               0xFFFFFFFFu,
+               0xFF0000FFu
                }
                },
-
        };
 
 EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] =
        {
                /* EDMA3 INSTANCE# 0 */
                {
-                       /* Resources owned/reserved by region 0 */
+               /* Resources owned/reserved by region 0 */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFF000Fu, 0x00000FFFu, 0x00000000u, 0x00000FFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x0f00000Fu, 0x0000000Fu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000003u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x0f00000Fu, 0x000000FFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000003u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 415  384     447  416     479  448     511  480 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 
-                               /* resvdDmaChannels */
-                               /* 31           0 */
-                               {0x00000003u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31           0 */
-                               {0x00000003u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 1 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x000000F0u, 0xFFFFF000u, 0x000000FFu, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x000000F0u, 0x00000000u},
+                               {0x00000000u, 0x0000FF00u},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x0000000Cu},
+                               {0x0000000Fu},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x000000F0u, 0x00000000u},
+                               {0x00000000u, 0x0000FFF0u},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00000030u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000030u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000030u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 2 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000F00u, 0x00000000u, 0xFFFFFF00u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000F00u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000030u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000F00u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000300u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00000300u, 0x00000000u},
+                               {0xFFFFFFFFu, 0xFF0000FFu},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -595,46 +364,46 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00000300u, 0x00000000u},
+                               {0xFFFFFFFFu, 0xFF0000FFu},
                        },
 
-               /* Resources owned/reserved by region 3 */
+               /* Resources owned/reserved by region 1 */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0xFFFFF000u,
+                               {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                                0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
 
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
-                               {0x0000F000u, 0x00000000u},
+                               {0x00000000u, 0x00FF0000u},
 
                                /* ownQdmaChannels */
                                /* 31     0 */
-                               {0x000000C0u},
+                               {0x000000F0u},
 
                                /* ownTccs */
                                /* 31     0     63    32 */
-                               {0x0000F000u, 0x00000000u},
+                               {0x00000000u, 0x00FF0000u},
 
                                /* resvdPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x00003000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                               {0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 287  256     319  288     351  320     383  352 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
+                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
 
                                /* resvdDmaChannels */
                                /* 31     0     63    32 */
-                               {0x00003000u, 0x00000000u},
+                               {0xFFFFFFFFu, 0xFF0000FFu},
 
                                /* resvdQdmaChannels */
                                /* 31     0 */
@@ -642,35 +411,13 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
 
                                /* resvdTccs */
                                /* 31     0     63    32 */
-                               {0x00003000u, 0x00000000u},
+                               {0xFFFFFFFFu, 0xFF0000FFu},
                        },
 
-               /* Resources owned/reserved by region 4 */
+               /* Resources owned/reserved by region 2 */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
                                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
@@ -679,31 +426,6 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                /* 415  384     447  416     479  448     511  480 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 5 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
                                {0x00000000u, 0x00000000u},
@@ -739,32 +461,10 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                {0x00000000u, 0x00000000u},
                        },
 
-               /* Resources owned/reserved by region 6 */
+               /* Resources owned/reserved by region 3 */
                        {
                                /* ownPaRAMSets */
                                /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
                                {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
                                /* 159  128     191  160     223  192     255  224 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
@@ -773,31 +473,6 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                /* 415  384     447  416     479  448     511  480 */
                                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
 
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 7 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000F000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
-
                                /* ownDmaChannels */
                                /* 31     0     63    32 */
                                {0x00000000u, 0x00000000u},
@@ -832,197 +507,6 @@ EDMA3_RM_InstanceInitConfig sampleInstInitConfig[NUM_EDMA3_INSTANCES][EDMA3_MAX_
                                /* 31     0     63    32 */
                                {0x00000000u, 0x00000000u},
                        },
-           },
-
-               /* EDMA3 INSTANCE# 1 */
-           {
-               /* Resources owned/reserved by region 0 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x0000FFFFu, 0x00F00000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0xFFFFFFFFu, 0x0000FFFFu, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x0000FFFFu, 0x00F00000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000003u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x0000FFFFu, 0x00F00000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00003FFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00003FFFu, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00003FFFu, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 1 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0xFFFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0xFFFF0000u, 0x00000000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x0000000Cu},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0xFFFF0000u, 0x00000000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x3FFF0000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x3FFF0000u, 0x00000000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x3FFF0000u, 0x00000000u},
-                       },
-
-               /* Resources owned/reserved by region 2 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x0000FFFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x0000FFFFu, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x0000FFFFu},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x00000030u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x0000FFFFu},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x00003FFFu, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00003FFFu},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x00003FFFu},
-                       },
-
-               /* Resources owned/reserved by region 3 */
-                       {
-                               /* ownPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0xFFFF0000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0xFFFF0000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu,},
-
-                               /* ownDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0xFFFF0000u},
-
-                               /* ownQdmaChannels */
-                               /* 31     0 */
-                               {0x000000C0u},
-
-                               /* ownTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0xFFFF0000u},
-
-                               /* resvdPaRAMSets */
-                               /* 31     0     63    32     95    64     127   96 */
-                               {0x00000000u, 0x3FFF0000u, 0x00000000u, 0x00000000u,
-                               /* 159  128     191  160     223  192     255  224 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 287  256     319  288     351  320     383  352 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
-                               /* 415  384     447  416     479  448     511  480 */
-                                0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,},
-
-                               /* resvdDmaChannels */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x3FFF0000u},
-
-                               /* resvdQdmaChannels */
-                               /* 31     0 */
-                               {0x00000000u},
-
-                               /* resvdTccs */
-                               /* 31     0     63    32 */
-                               {0x00000000u, 0x3FFF0000u},
-                       },
 
                /* Resources owned/reserved by region 4 */
                        {
index 47b68be7a8b0f9dea225ca4f701237943c16eedb..a727019c7d7d85cc72f13c4d3461e7f7b1b6b81d 100644 (file)
@@ -1,9 +1,9 @@
 /*
- * sample_tci6616_int_reg.c
+ * sample_c6657_int_reg.c
  *
  * Platform specific interrupt registration and un-registration routines.
  *
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
  *
  *
  *  Redistribution and use in source and binary forms, with or without
@@ -43,7 +43,6 @@
 
 #include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>
 
-#include <ti/csl/csl_edma3.h>
 extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
 extern unsigned int ccErrorInt[];
 extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
@@ -60,20 +59,16 @@ void (*ptrEdma3TcIsrHandler[EDMA3_MAX_TC])(unsigned int arg) =
                                                 &lisrEdma3TC6ErrHandler0,
                                                 &lisrEdma3TC7ErrHandler0,
                                                 };
-#if 0
+
 unsigned int hwiInterrupt = 8;
 
 /* Host interrupts for transfer completion */
 //unsigned int ccXferHostInt[NUM_EDMA3_INSTANCES][NUM_DSPS] = {
-unsigned int ccXferHostInt[3][4] = {
-                                                                               {32, 24u, 40u, 56u},
-                                                                               {9u, 25u, 41u, 57u},
-                                                                               {10u, 26u, 42u, 58u},
+unsigned int ccXferHostInt[1][2] = {
+                                                                               {0u, 20u},
                                                                                };
-unsigned int edma3ErrHostInt[3][4] = {
-                                                                               {33, 27u, 43u, 59u},
-                                                                               {12u, 28u, 44u, 60u},
-                                                                               {13u, 29u, 45u, 61u},
+unsigned int edma3ErrHostInt[1][2] = {
+                                                                               {1u, 21u},
                                                                                };
 
 
@@ -88,9 +83,8 @@ void registerEdma3Interrupts (unsigned int edma3Id)
 
     /* Disabling the global interrupts */
     cookie = Hwi_disable();
-#if 0
+
        /* Transfer completion ISR */
-#if 0
        CpIntc_dispatchPlug(ccXferCompInt[edma3Id][dsp_num],
                                                lisrEdma3ComplHandler0,
                                                edma3Id,
@@ -98,18 +92,7 @@ void registerEdma3Interrupts (unsigned int edma3Id)
        CpIntc_mapSysIntToHostInt(0, ccXferCompInt[edma3Id][dsp_num],
                                                                ccXferHostInt[edma3Id][dsp_num]);
        CpIntc_enableHostInt(0, ccXferHostInt[edma3Id][dsp_num]);
-#else
-       // Map system interrupt 15 to host interrupt 8
-       CpIntc_mapSysIntToHostInt(0, 0x88, 32);
-
-       // Plug the function for event #15
-       CpIntc_dispatchPlug(0x88, lisrEdma3ComplHandler0,edma3Id,TRUE);
-
-       // Enable host interrupt #8
-       CpIntc_enableHostInt(0,32); // enable host interrupt 8
-#endif
     eventId = CpIntc_getEventId(ccXferHostInt[edma3Id][dsp_num]);
-    eventId = 0x30;
     EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
                                 ccXferHostInt[edma3Id][dsp_num], TRUE);
        EventCombiner_enableEvent(eventId);
@@ -132,31 +115,15 @@ void registerEdma3Interrupts (unsigned int edma3Id)
        /* Enable the host interrupt which is common for both CC and TC error */
        CpIntc_enableHostInt(0, edma3ErrHostInt[edma3Id][dsp_num]);
     eventId = CpIntc_getEventId(edma3ErrHostInt[edma3Id][dsp_num]);
-    eventId = 0x31;
     EventCombiner_dispatchPlug (eventId, CpIntc_dispatch,
                                 edma3ErrHostInt[edma3Id][dsp_num], TRUE);
        EventCombiner_enableEvent(eventId);
 
     Hwi_enableInterrupt(hwiInterrupt);
-#else
 
     /* enable the 'global' switch */
     CpIntc_enableAllHostInts(0);
-    {
-        Hwi_Params params;
-       CpIntc_mapSysIntToHostInt(0, 0x88, 32);                 // I picked host int 32 for CPINTC #0.  CPINTC #1 is for cores 4-7
-           CpIntc_dispatchPlug(0x88, lisrEdma3ComplHandler0, 0, TRUE);   //  the 'arg' parameter could be anything, doesn't have to be 149
-           CpIntc_enableHostInt(0, 32);                                     // CPINT #0 is for cores 0-3, CPINTC #1 is for cores 4-7
-           eventId = CpIntc_getEventId(32);                               // this should return the GEM event 21 (This was a bug fixed in 6.32.04)
-           eventId = 0x30;
-           Hwi_Params_init(&params);
-           params.arg = 32;                                       // required to be the host interrupt #
-           params.eventId = eventId;
-           params.enableInt = TRUE;
-           Hwi_create(8, &CpIntc_dispatch, &params, NULL); // create ISR to handle this event in Hwi vector 8
 
-    }
-#endif
     /* Restore interrupts */
     Hwi_restore(cookie);
     }
@@ -184,127 +151,3 @@ void unregisterEdma3Interrupts (unsigned int edma3Id)
     Hwi_restore(cookie);
     }
 
-#else
-/**  To Register the ISRs with the underlying OS, if required. */
-void registerEdma3Interrupts (unsigned int edma3Id)
-    {
-    static UInt32 cookie = 0;
-    unsigned int eventId,numTc = 0;
-    Hwi_Params params;
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    /* Enable the Xfer Completion Event Interrupt */
-    EventCombiner_dispatchPlug(6,
-                                               (EventCombiner_FuncPtr)(&lisrEdma3ComplHandler0),
-                               edma3Id, 1);
-    EventCombiner_enableEvent(6);
-
-    Hwi_enableInterrupt(7);
-
-# if 0
-    /* Map the EDMA Region 0 transfer complete interrupt to the EDMA ISR Handler. */
-    CpIntc_dispatchPlug(0x88, (CpIntc_FuncPtr)lisrEdma3ComplHandler0, 0, TRUE);
-
-    /* The configuration is for CPINTC0. We map system interrupt 0x88 to Host Interrupt 32. */
-    CpIntc_mapSysIntToHostInt(0, 0x88, 32);
-
-    /* Enable the Host Interrupt. */
-    CpIntc_enableHostInt(0, 32);
-
-    /* Enable the System Interrupt */
-    CpIntc_enableSysInt(0, 0x88);
-
-    /* Get the event id associated with the host interrupt. */
-    eventId = 0x30;
-    /* enable the 'global' switch */
-
-   /* Enable the Xfer Completion Event Interrupt */
-        EventCombiner_dispatchPlug(0x30,
-                                                       (EventCombiner_FuncPtr)(&CpIntc_dispatch),
-                               32, 1);
-        EventCombiner_enableEvent(0x30);
-
-        /* Map the EDMA CC error interrupt to the EDMA ISR Handler. */
-            CpIntc_dispatchPlug(0x99, (CpIntc_FuncPtr)lisrEdma3ComplHandler0, 0, TRUE);
-
-            /* The configuration is for CPINTC0. We map system interrupt 0x99 to Host Interrupt 33. */
-            CpIntc_mapSysIntToHostInt(0, 0x99, 33);
-
-            /* Enable the Host Interrupt. */
-            CpIntc_enableHostInt(0, 33);
-
-            /* Enable the System Interrupt */
-            CpIntc_enableSysInt(0, 0x99);
-
-            /* Get the event id associated with the host interrupt. */
-            eventId = 0x31;
-            /* enable the 'global' switch */
-
-           /* Enable the Xfer Completion Event Interrupt */
-                EventCombiner_dispatchPlug(0x31,
-                                                               (EventCombiner_FuncPtr)(&CpIntc_dispatch),
-                                       33, 1);
-                EventCombiner_enableEvent(0x31);
-
-                /* Map the EDMA TC error  interrupt to the EDMA ISR Handler. */
-                           CpIntc_dispatchPlug(0x9e, (CpIntc_FuncPtr)lisrEdma3ComplHandler0, 0, TRUE);
-
-                           /* The configuration is for CPINTC0. We map system interrupt 0x9e to Host Interrupt 34. */
-                           CpIntc_mapSysIntToHostInt(0, 0x9e, 34);
-
-                           /* Enable the Host Interrupt. */
-                           CpIntc_enableHostInt(0, 34);
-
-                           /* Enable the System Interrupt */
-                           CpIntc_enableSysInt(0, 0x9e);
-
-                           /* Get the event id associated with the host interrupt. */
-                           eventId = 0x32;
-                           /* enable the 'global' switch */
-
-                          /* Enable the Xfer Completion Event Interrupt */
-                               EventCombiner_dispatchPlug(0x32,
-                                                                               (EventCombiner_FuncPtr)(&CpIntc_dispatch),
-                                                       34, 1);
-                               EventCombiner_enableEvent(0x32);
-
-
-
-        CpIntc_enableAllHostInts(0);
-        Hwi_enableInterrupt(8);
-
-
-#endif
-
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-
-/**  To Unregister the ISRs with the underlying OS, if previously registered. */
-void unregisterEdma3Interrupts (unsigned int edma3Id)
-    {
-       static UInt32 cookie = 0;
-    unsigned int numTc = 0;
-
-    /* Disabling the global interrupts */
-    cookie = Hwi_disable();
-
-    /* Disable the Xfer Completion Event Interrupt */
-       EventCombiner_disableEvent(ccXferCompInt[edma3Id][0]);
-
-    /* Disable the CC Error Event Interrupt */
-       EventCombiner_disableEvent(ccErrorInt[edma3Id]);
-
-    /* Enable the TC Error Event Interrupt, according to the number of TCs. */
-    while (numTc < numEdma3Tc[edma3Id])
-       {
-        EventCombiner_disableEvent(tcErrorInt[edma3Id][numTc]);
-        numTc++;
-       }
-
-    /* Restore interrupts */
-    Hwi_restore(cookie);
-    }
-#endif
index 92c20ab46b8be557d6a6f376aa6b211fab944adb..2cfcc4ca851843ca1f4ee58d092e17b524545fed 100644 (file)
@@ -6,7 +6,7 @@
  * These implementations MUST be provided by the user / application, using the
  * EDMA3 driver, for its correct functioning.
  *
- * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  *
  *
  *  Redistribution and use in source and binary forms, with or without
 #include <ti/sysbios/knl/Task.h>
 #include <ti/sysbios/knl/Semaphore.h>
 
-#include "bios6_edma3_drv_sample.h"
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
 
-extern unsigned int ccXferCompInt[][EDMA3_MAX_REGIONS];
-extern unsigned int ccErrorInt[];
-extern unsigned int tcErrorInt[][EDMA3_MAX_TC];
+extern uint32_t ccXferCompInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
+extern uint32_t ccErrorInt[EDMA3_MAX_EDMA3_INSTANCES];
+extern uint32_t tcErrorInt[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_TC];
 
 /**
  * Shadow Region on which the executable is running. Its value is
  * populated with the DSP Instance Number here in this case.
  */
-extern unsigned int region_id;
+extern uint32_t region_id;
 
 /**
  * \brief   EDMA3 OS Protect Entry
@@ -76,14 +76,14 @@ extern unsigned int region_id;
  *      for EDMA3_OS_PROTECT_INTERRUPT protection level).
  * \return  None
  */
-void edma3OsProtectEntry (unsigned int edma3InstanceId,
-                                                       int level, unsigned int *intState)
+void edma3OsProtectEntry (uint32_t edma3InstanceId,
+                                                       int32_t level, uint32_t *intState)
     {
     if (((level == EDMA3_OS_PROTECT_INTERRUPT)
         || (level == EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR))
         && (intState == NULL))
         {
-        return;
+            /* Nothing to be done here */
         }
     else
         {
@@ -136,7 +136,8 @@ void edma3OsProtectEntry (unsigned int edma3InstanceId,
                 break;
             }
         }
-    }
+        return;
+        }
 
 
 /**
@@ -156,8 +157,8 @@ void edma3OsProtectEntry (unsigned int edma3InstanceId,
  *      for EDMA3_OS_PROTECT_INTERRUPT protection level).
  * \return  None
  */
-void edma3OsProtectExit (unsigned int edma3InstanceId,
-                        int level, unsigned int intState)
+void edma3OsProtectExit (uint32_t edma3InstanceId,
+                        int32_t level, uint32_t intState)
     {
     switch (level)
         {
@@ -183,7 +184,7 @@ void edma3OsProtectExit (unsigned int edma3InstanceId,
 
         /* Enable EDMA3 TC error interrupt only */
         case EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR :
-            switch (intState)
+            switch ((int32_t)intState)
                 {
                 case 0:
                 case 1:
@@ -227,13 +228,13 @@ void edma3OsProtectExit (unsigned int edma3InstanceId,
  * may or may not require the below implementation and
  * should modify it according to her need.
  */
-EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr,
-                           unsigned int    num_bytes)
+EDMA3_DRV_Result Edma3_CacheInvalidate(uint32_t mem_start_ptr,
+                           uint32_t    num_bytes)
     {
     EDMA3_DRV_Result cacheInvResult = EDMA3_DRV_SOK;
 
     /* Verify whether the start address is cache aligned or not */
-    if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1u))    !=    0)
+    if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1U))    !=    0)
         {
 #ifdef EDMA3_DRV_DEBUG
         EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n",
@@ -243,7 +244,7 @@ EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr,
         }
     else
         {
-               Cache_inv((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, TRUE);
+               Cache_inv((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, (Bool)TRUE);
         }
 
     return cacheInvResult;
@@ -268,13 +269,13 @@ EDMA3_DRV_Result Edma3_CacheInvalidate(unsigned int mem_start_ptr,
  * may or may not require the below implementation and
  * should modify it according to her need.
  */
-EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr,
-                      unsigned int num_bytes)
+EDMA3_DRV_Result Edma3_CacheFlush(uint32_t mem_start_ptr,
+                      uint32_t num_bytes)
     {
     EDMA3_DRV_Result cacheFlushResult = EDMA3_DRV_SOK;
 
     /* Verify whether the start address is cache aligned or not */
-    if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1u))    !=    0)
+    if((mem_start_ptr & (EDMA3_CACHE_LINE_SIZE_IN_BYTES-1U))    !=    0)
         {
 #ifdef EDMA3_DRV_DEBUG
         EDMA3_DRV_PRINTF("\r\n Cache : Memory is not %d bytes alinged\r\n",
@@ -284,7 +285,7 @@ EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr,
         }
     else
         {
-               Cache_wb((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, TRUE);
+               Cache_wb((Ptr)mem_start_ptr, num_bytes, Cache_Type_ALL, (Bool)TRUE);
         }
 
     return cacheFlushResult;
@@ -310,7 +311,7 @@ EDMA3_DRV_Result Edma3_CacheFlush(unsigned int mem_start_ptr,
  *      semaphore
  * \return  EDMA3_DRV_SOK if succesful, else a suitable error code.
  */
-EDMA3_DRV_Result edma3OsSemCreate(int initVal,
+EDMA3_DRV_Result edma3OsSemCreate(int32_t initVal,
                                                        const Semaphore_Params *semParams,
                                EDMA3_OS_Sem_Handle *hSem)
     {
@@ -368,12 +369,11 @@ EDMA3_DRV_Result edma3OsSemDelete(EDMA3_OS_Sem_Handle hSem)
  *      a free semaphore.
  * \param   hSem [IN] is the handle of the specified semaphore
  * \param   mSecTimeout [IN] is wait time in milliseconds
- * \return  EDMA3_DRV_Result if successful else a suitable error code
+ * \return  EDMA3_Result if successful else a suitable error code
  */
-EDMA3_DRV_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int mSecTimeout)
+EDMA3_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int32_t mSecTimeout)
     {
-    EDMA3_DRV_Result semTakeResult = EDMA3_DRV_SOK;
-    unsigned short semPendResult;
+    EDMA3_Result semTakeResult = EDMA3_DRV_SOK;
 
     if(NULL == hSem)
         {
@@ -381,8 +381,7 @@ EDMA3_DRV_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int mSecTimeout)
         }
     else
         {
-        semPendResult = Semaphore_pend(hSem, mSecTimeout);
-        if (semPendResult == FALSE)
+        if((Semaphore_pend(hSem, (uint32_t)mSecTimeout)) == FALSE)
             {
             semTakeResult = EDMA3_DRV_E_SEMAPHORE;
             }
@@ -398,11 +397,11 @@ EDMA3_DRV_Result edma3OsSemTake(EDMA3_OS_Sem_Handle hSem, int mSecTimeout)
  *      This function gives or relinquishes an already
  *      acquired semaphore token
  * \param   hSem [IN] is the handle of the specified semaphore
- * \return  EDMA3_DRV_Result if successful else a suitable error code
+ * \return  EDMA3_Result if successful else a suitable error code
  */
-EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem)
+EDMA3_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem)
     {
-    EDMA3_DRV_Result semGiveResult = EDMA3_DRV_SOK;
+    EDMA3_Result semGiveResult = EDMA3_DRV_SOK;
 
     if(NULL == hSem)
         {
index 54fc9557401f6a43557f0c490e316ee5c91a6881..b8f0b6295423b30a6484ada92b28c3ffa008f187 100644 (file)
@@ -4,7 +4,7 @@
  * Sample Initialization for the EDMA3 Driver for BIOS 6 based applications.
  * It should be MANDATORILY done once before EDMA3 usage.
  *
- * Copyright (C) 2009-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  *
  *
  *  Redistribution and use in source and binary forms, with or without
 #include <ti/sysbios/knl/Semaphore.h>
 #include <ti/sysbios/family/c64p/EventCombiner.h>
 
-#include "bios6_edma3_drv_sample.h"
+#include <ti/sdo/edma3/drv/sample/bios6_edma3_drv_sample.h>
 
 /** @brief EDMA3 Driver Instance specific Semaphore handle */
-extern EDMA3_OS_Sem_Handle semHandle[];
+extern EDMA3_OS_Sem_Handle semHandle[EDMA3_MAX_EDMA3_INSTANCES];
 
 /**  To Register the ISRs with the underlying OS, if required. */
-extern void registerEdma3Interrupts (unsigned int edma3Id);
+extern void registerEdma3Interrupts (uint32_t edma3Id);
 /**  To Unregister the ISRs with the underlying OS, if previously registered. */
-extern void unregisterEdma3Interrupts (unsigned int edma3Id);
+extern void unregisterEdma3Interrupts (uint32_t edma3Id);
 
 /* To find out the DSP# */
-extern unsigned short determineProcId();
+extern uint16_t determineProcId(void);
 
 /**
  * To check whether the global EDMA3 configuration is required or not.
@@ -62,31 +62,31 @@ extern unsigned short determineProcId();
  * by one of the masters. Hence this function will return TRUE only once
  * and FALSE for all other masters. 
  */
-extern unsigned short isGblConfigRequired(unsigned int dspNum);
+extern uint16_t isGblConfigRequired(uint32_t dspNum);
 
 /**
  * DSP instance number on which the executable is running. Its value is
  * determined by reading the processor specific register DNUM.
  */
-unsigned int dsp_num;
+uint32_t dsp_num;
 
 /**
  * Shadow Region on which the executable is runnig. Its value is populated
  * with the DSP Instance Number here in this case.
  */
-unsigned int region_id;
+uint32_t region_id;
 
 /* Number of EDMA3 controllers present in the system */
-extern const unsigned int numEdma3Instances;
+extern const uint32_t numEdma3Instances;
 
 /* External Global Configuration Structure */
-extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[];
+extern EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[EDMA3_MAX_EDMA3_INSTANCES];
 
 /* External Instance Specific Configuration Structure */
-extern EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[][EDMA3_MAX_REGIONS];
+extern EDMA3_DRV_InstanceInitConfig sampleInstInitConfig[EDMA3_MAX_EDMA3_INSTANCES][EDMA3_MAX_REGIONS];
 
-#if defined (CHIP_TI814X)
-extern EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, unsigned int edma3Id);
+#ifdef DMA_XBAR_AVAILABLE
+extern EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, uint32_t edma3Id);
 #endif
 
 /**
@@ -97,7 +97,7 @@ extern EDMA3_DRV_Result sampleInitXbarEvt(EDMA3_DRV_Handle hEdma, unsigned int e
  *
   * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode)
+EDMA3_DRV_Handle edma3init (uint32_t edma3Id, EDMA3_DRV_Result *errorCode)
     {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;
     Semaphore_Params semParams;
@@ -107,11 +107,13 @@ EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode)
        EDMA3_DRV_Handle hEdma = NULL;
 
        if ((edma3Id >= numEdma3Instances) || (errorCode == NULL))
-               return hEdma;
-
+    {
+               hEdma = NULL;
+    }
+    else
+    {
     /* DSP instance number */
     dsp_num = determineProcId();
-//    dsp_num = 0; /* selection of region ID */
 
        globalConfig = &sampleEdma3GblCfgParams[edma3Id];
 
@@ -129,7 +131,7 @@ EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode)
                Semaphore_Params_init(&semParams);
 
                initCfg.drvSemHandle = NULL;
-               edma3Result = edma3OsSemCreate(1, &semParams, &initCfg.drvSemHandle);
+               edma3Result = edma3OsSemCreate((int32_t)1, &semParams, &initCfg.drvSemHandle);
                }
 
        if (edma3Result == EDMA3_DRV_SOK)
@@ -160,15 +162,15 @@ EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode)
                hEdma = EDMA3_DRV_open (edma3Id, (void *) &initCfg, &edma3Result);
                }
 
-#if defined (CHIP_TI814X)
+#ifdef DMA_XBAR_AVAILABLE
        {
-       if(hEdma && (edma3Result == EDMA3_DRV_SOK))
+       if((hEdma != NULL) && (edma3Result == EDMA3_DRV_SOK))
                {
                edma3Result = sampleInitXbarEvt(hEdma, edma3Id);
                }
        }
 #endif
-       if(hEdma && (edma3Result == EDMA3_DRV_SOK))
+       if((hEdma != NULL) && (edma3Result == EDMA3_DRV_SOK))
                {
                /**
                * Register Interrupt Handlers for various interrupts
@@ -178,8 +180,9 @@ EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode)
                registerEdma3Interrupts(edma3Id);
                }
 
-       *errorCode = edma3Result;       
-       return hEdma;
+       *errorCode = edma3Result;
+    }
+    return hEdma;
     }
 
 
@@ -191,7 +194,7 @@ EDMA3_DRV_Handle edma3init (unsigned int edma3Id, EDMA3_DRV_Result *errorCode)
  *
   * \return  EDMA3_DRV_SOK if success, else error code
  */
-EDMA3_DRV_Result edma3deinit (unsigned int edma3Id, EDMA3_DRV_Handle hEdma)
+EDMA3_DRV_Result edma3deinit (uint32_t edma3Id, EDMA3_DRV_Handle hEdma)
     {
     EDMA3_DRV_Result edma3Result = EDMA3_DRV_E_INVALID_PARAM;