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raw | patch | inline | side by side (parent: 3376243)
raw | patch | inline | side by side (parent: 3376243)
author | Sajesh Kumar Saran <sajesh@ti.com> | |
Thu, 1 Dec 2011 00:39:22 +0000 (19:39 -0500) | ||
committer | Sajesh Kumar Saran <sajesh@ti.com> | |
Thu, 1 Dec 2011 00:39:22 +0000 (19:39 -0500) |
evmc6670l/gel/evmc6670l.gel | patch | blob | history | |
evmc6678l/gel/evmc6678l.gel | patch | blob | history |
index b57ee6f166cc7a09672611a9acdf415fc77455b2..b0d2f7080f7ffc0e4472461011ac1a895457045f 100755 (executable)
// * KeyStone1 Emupack version __KEYSTONE1_EMUPACK_VERSION__
-#define GEL_VERSION 1.405
+#define GEL_VERSION 2.000
// Enable for when Manually using CCS and AVV Framework style memory map
#define SYSTEM_RESET_BEFORE_FILE_LOAD_ENABLE (0)
/*--------------------------------------------------------------*/
OnReset( int nErrorCode )
{
- if (ON_RESET_CODE_ENABLE == 1)
- {
- if (DNUM == 0)
- {
- // Setup DDR timing @ 533.3 MHz (ext clock * 8)
- //xmc_setup();
- //Set_DDR3_533_3_MHz();
-
- // Setup DDR
- //xmc_setup();
- //ddr3_setup_auto_lvl_1333(0);
-
- // Wait for DDR to be stable before continuing.
- //Wait_Soft(4000);
- }
- ddr3_setup_auto_lvl_1333(0);
- Wait_Soft(5000 + (DNUM * 15000));
- }
}
/*--------------------------------------------------------------*/
KICK0 = KICK0_UNLOCK;
KICK1 = KICK1_UNLOCK;
+ /* Wait for PLL to lock = min 500 ref clock cycles.
+ With refclk = 100MHz, = 5000 ns = 5us */
+ Delay_milli_seconds(1);
/***************** 3.2 DDR3 PLL Configuration ************/
/* Done before */
@@ -1246,16 +1231,7 @@ prog_pll1_values(unsigned int pll_multiplier, unsigned int pll_divider, unsigned
MAINPLLCTL0 &=~(0x0007F000); /*Clear PLLM field */
MAINPLLCTL0 |=((TEMP << 12) & 0x0007F000);
- /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
- PLL1_SECCTL &= ~(0x00780000); /* Clear the field */
- PLL1_SECCTL |= ((odiv << 19) & 0x00780000) ;
-
- /* Set the pll divider (6 bit field) *
- * PLLD[5:0] is located in MAINPLLCTL0 */
- MAINPLLCTL0 &= ~(0x0000003F); /* Clear the Field */
- MAINPLLCTL0 |= (pll_divider & 0x0000003F);
-
- /* Set the BWADJ (12 bit field) *
+ /* Set the BWADJ (12 bit field) *
* BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 *
* registers. BWADJ[11:0] should be programmed to a value equal to half of *
* PLLM[12:0] value (round down if PLLM has an odd value) *
@@ -1265,6 +1241,16 @@ prog_pll1_values(unsigned int pll_multiplier, unsigned int pll_divider, unsigned
MAINPLLCTL0 |= ((TEMP << 24) & 0xFF000000);
MAINPLLCTL1 &=~(0x0000000F); /* Clear the BWADJ field */
MAINPLLCTL1 |= ((TEMP >> 8) & 0x0000000F);
+
+ /* Set the pll divider (6 bit field) *
+ * PLLD[5:0] is located in MAINPLLCTL0 */
+ MAINPLLCTL0 &= ~(0x0000003F); /* Clear the Field */
+ MAINPLLCTL0 |= (pll_divider & 0x0000003F);
+
+ /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
+ PLL1_SECCTL &= ~(0x00780000); /* Clear the field */
+ PLL1_SECCTL |= ((odiv << 19) & 0x00780000) ;
+
}
menuitem "EVMC6670L HW Setup";
/* Wait for PLL Reset assertion Time (min: 50 us) *
* Minimum delay in GEL can be 1 milli seconds, so program to 1ms=1000us, *
* more than required, but should be Okay */
- Delay_milli_seconds(1);
+ //Delay_milli_seconds(1);
/* Program the necessary multipliers/dividers and BW adjustments */
prog_pll1_values(pll_mult, pll_div, 1);
DDR3PLLCTL0 |= 0x00800000; /* Set the Bit 23 */
/* Wait for the PLL Reset time (min: 5 us) */
- Delay_milli_seconds(1);
+ //Delay_milli_seconds(1);
/* In PLL Controller, reset the PLL (bit 13 in DDR3PLLCTL1 register) */
DDR3PLLCTL1 |= 0x00002000;
/* Program the necessary multipliers/dividers and BW adjustments */
- /* Set the Multipler values */
- DDR3PLLCTL0 &= ~(0x0007FFC0);
- DDR3PLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
-
/* Set the divider values */
DDR3PLLCTL0 &= ~(0x0000003F);
DDR3PLLCTL0 |= (divider & 0x0000003F);
+ /* Set the Multipler values */
+ DDR3PLLCTL0 &= ~(0x0007FFC0);
+ DDR3PLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
+
/* Set the BWADJ */
temp = ((multiplier + 1) >> 1) - 1;
DDR3PLLCTL0 &= ~(0xFF000000);
PAPLLCTL0 |= 0x00800000; /* Set the Bit 23 */
/* Wait for the PLL Reset time (min: 5 us) */
- Delay_milli_seconds(1);
+ //Delay_milli_seconds(1);
/* In PLL Controller, reset the PLL (bit 14 in PAPLLCTL1 register) */
PAPLLCTL1 |= 0x00004000;
/* Program the necessary multipliers/dividers and BW adjustments */
- /* Set the Multipler values */
- PAPLLCTL0 &= ~(0x0007FFC0);
- PAPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
-
/* Set the divider values */
PAPLLCTL0 &= ~(0x0000003F);
PAPLLCTL0 |= (divider & 0x0000003F);
+ /* Set the Multipler values */
+ PAPLLCTL0 &= ~(0x0007FFC0);
+ PAPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
+
/* Set the BWADJ */
temp = ((multiplier + 1) >> 1) - 1;
PAPLLCTL0 &= ~(0xFF000000);
index 1d170c94db2cb24ff8df95ac0bae85856f51ceaa..577a5928fe3fc9e6d2b06a5f21215ef4a0132d3e 100755 (executable)
// * KeyStone1 Emupack version __KEYSTONE1_EMUPACK_VERSION__
-#define GEL_VERSION 1.603
+#define GEL_VERSION 2.000
// The System PLL governs the device (CorePac) operating speed.
//
while (1);
}
- // Setup all Power Domains on
- Set_Psc_All_On( );
+ if (!count) {
+ // Setup all Power Domains on
+ Set_Psc_All_On( );
+ }
// Setup Pll3 pass clk @ 1050 MHz
Init_Pll3(PLLM_PASS, PLLD_PASS);
@@ -992,16 +994,7 @@ prog_pll1_values(unsigned int pll_multiplier, unsigned int pll_divider, unsigned
MAINPLLCTL0 &=~(0x0007F000); /*Clear PLLM field */
MAINPLLCTL0 |=((TEMP << 12) & 0x0007F000);
- /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
- PLL1_SECCTL &= ~(0x00780000); /* Clear the field */
- PLL1_SECCTL |= ((odiv << 19) & 0x00780000) ;
-
- /* Set the pll divider (6 bit field) *
- * PLLD[5:0] is located in MAINPLLCTL0 */
- MAINPLLCTL0 &= ~(0x0000003F); /* Clear the Field */
- MAINPLLCTL0 |= (pll_divider & 0x0000003F);
-
- /* Set the BWADJ (12 bit field) *
+ /* Set the BWADJ (12 bit field) *
* BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 *
* registers. BWADJ[11:0] should be programmed to a value equal to half of *
* PLLM[12:0] value (round down if PLLM has an odd value) *
@@ -1011,6 +1004,16 @@ prog_pll1_values(unsigned int pll_multiplier, unsigned int pll_divider, unsigned
MAINPLLCTL0 |= ((TEMP << 24) & 0xFF000000);
MAINPLLCTL1 &=~(0x0000000F); /* Clear the BWADJ field */
MAINPLLCTL1 |= ((TEMP >> 8) & 0x0000000F);
+
+ /* Set the pll divider (6 bit field) *
+ * PLLD[5:0] is located in MAINPLLCTL0 */
+ MAINPLLCTL0 &= ~(0x0000003F); /* Clear the Field */
+ MAINPLLCTL0 |= (pll_divider & 0x0000003F);
+
+ /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
+ PLL1_SECCTL &= ~(0x00780000); /* Clear the field */
+ PLL1_SECCTL |= ((odiv << 19) & 0x00780000) ;
+
}
menuitem "EVMC6678L HW Setup";
/* Wait for PLL Reset assertion Time (min: 50 us) *
* Minimum delay in GEL can be 1 milli seconds, so program to 1ms=1000us, *
* more than required, but should be Okay */
- Delay_milli_seconds(1);
+ //Delay_milli_seconds(1);
/* Program the necessary multipliers/dividers and BW adjustments */
prog_pll1_values(pll_mult, pll_div, 1);
KICK0 = KICK0_UNLOCK;
KICK1 = KICK1_UNLOCK;
+ /* Wait for PLL to lock = min 500 ref clock cycles.
+ With refclk = 100MHz, = 5000 ns = 5us */
+ Delay_milli_seconds(1);
/***************** 3.2 DDR3 PLL Configuration ************/
/* Done before */
DDR3PLLCTL0 |= 0x00800000; /* Set the Bit 23 */
/* Wait for the PLL Reset time (min: 5 us) */
- Delay_milli_seconds(1);
+ //Delay_milli_seconds(1);
/* In PLL Controller, reset the PLL (bit 13 in DDR3PLLCTL1 register) */
DDR3PLLCTL1 |= 0x00002000;
/* Program the necessary multipliers/dividers and BW adjustments */
- /* Set the Multipler values */
- DDR3PLLCTL0 &= ~(0x0007FFC0);
- DDR3PLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
-
/* Set the divider values */
DDR3PLLCTL0 &= ~(0x0000003F);
DDR3PLLCTL0 |= (divider & 0x0000003F);
+ /* Set the Multipler values */
+ DDR3PLLCTL0 &= ~(0x0007FFC0);
+ DDR3PLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
+
/* Set the BWADJ */
temp = ((multiplier + 1) >> 1) - 1;
DDR3PLLCTL0 &= ~(0xFF000000);
PAPLLCTL0 |= 0x00800000; /* Set the Bit 23 */
/* Wait for the PLL Reset time (min: 5 us) */
- Delay_milli_seconds(1);
+ //Delay_milli_seconds(1);
/* In PLL Controller, reset the PLL (bit 14 in PAPLLCTL1 register) */
PAPLLCTL1 |= 0x00004000;
/* Program the necessary multipliers/dividers and BW adjustments */
- /* Set the Multipler values */
- PAPLLCTL0 &= ~(0x0007FFC0);
- PAPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
-
/* Set the divider values */
PAPLLCTL0 &= ~(0x0000003F);
PAPLLCTL0 |= (divider & 0x0000003F);
+ /* Set the Multipler values */
+ PAPLLCTL0 &= ~(0x0007FFC0);
+ PAPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
+
/* Set the BWADJ */
temp = ((multiplier + 1) >> 1) - 1;
PAPLLCTL0 &= ~(0xFF000000);