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raw | patch | inline | side by side (parent: d9eba95)
raw | patch | inline | side by side (parent: d9eba95)
| author | Sam Nelson <sam.nelson@ti.com> | |
| Thu, 10 Apr 2014 16:45:12 +0000 (12:45 -0400) | ||
| committer | Sam Nelson <sam.nelson@ti.com> | |
| Thu, 10 Apr 2014 16:45:12 +0000 (12:45 -0400) |
Signed-off-by: Sam Nelson <sam.nelson@ti.com>
21 files changed:
diff --git a/evmk2e/platform_lib/include/platform_internal.h b/evmk2e/platform_lib/include/platform_internal.h
index 1a343db70fa9754141855218f16e26cba4bec933..4541fa9894d96e1772a9bfed2c075841f4eb7558 100755 (executable)
#include "csl_xmcAux.h"
#include "evmc66x_pllc.h"
-
+#include "csl_serdes_ethernet.h"
/********************************************************************************************
* Platform Specific Declarations *
*******************************************************************************************/
#define write_reg(v,a) (*(volatile uint32_t *)(a) = (v))
CSL_Status SetDDR3PllConfig(pll_init_data *data);
-
+int32_t init_ddr3param(uint8_t*);
#endif
index eaf0653a4755a877d24433a45c56d5157cda18f3..587ad14f47d4ed6fd6b0d8180cfe66113a476006 100644 (file)
crc_msb = (unsigned char)(csum16 >> 8);
if ((spd[126] == crc_lsb) && (spd[127] == crc_msb))
{
- printf("SPD checksum expected:");
+ printf("SPD checksum verified.. Ok\n");
return Platform_EOK;
}
else
@@ -465,7 +465,7 @@ int32_t readSPD(uint8_t uchEepromI2cAddress,uint8_t buf[],uint8_t i2cportnumber)
{
evmI2CInit(i2cportnumber);
- if (i2cEepromRead (0x80, 256, (uint8_t *)buf,uchEepromI2cAddress,i2cportnumber) != I2C_RET_OK) {
+ if (i2cEepromRead (0x00, 256, (uint8_t *)buf,uchEepromI2cAddress,i2cportnumber) != I2C_RET_OK) {
platform_write("platform_spd_eeprom_read: EEPROM read failed\n");
return ( (Platform_STATUS) Platform_EFAIL);
}
diff --git a/evmk2e/platform_lib/src/evmc66x_i2c_eeprom.c b/evmk2e/platform_lib/src/evmc66x_i2c_eeprom.c
index a0ae651dabb7ae71518b553afe5ef045e6b49c8e..1fd958020bd20d620b852c8c06e8387d2832bb69 100755 (executable)
i2cDelay (DELAY_CONST);\r
\r
/* Put the first byte into the transmit register, set the start bit */\r
- uiValue = (*puiData >> 8) & 0x00ff;\r
+ if (i2cportnumber == 1)\r
+ uiValue = (*puiData) & 0xff;\r
+ else\r
+ uiValue = (*puiData >> 8) & 0x00ff;\r
+\r
I2CR->ICDXR = uiValue;\r
uiByteType = I2C_BYTE_LSB;\r
\r
\r
\r
/* Write the byte address to the eeprom. Do not send a stop */\r
- uiReturnValue = i2cEepromWriteBlock ( uchEepromI2cAddress, &byte_addr, \r
- 2, I2C_DO_NOT_RELEASE_BUS,i2cportnumber);\r
+ if (i2cportnumber == 1)\r
+ uiReturnValue = i2cEepromWriteBlock ( uchEepromI2cAddress, &byte_addr,\r
+ 1, I2C_DO_NOT_RELEASE_BUS,i2cportnumber);\r
+ else\r
+ uiReturnValue = i2cEepromWriteBlock ( uchEepromI2cAddress, &byte_addr,\r
+ 2, I2C_DO_NOT_RELEASE_BUS,i2cportnumber);\r
if (uiReturnValue != I2C_RET_OK)\r
return (uiReturnValue);\r
\r
index a52388a2963c187b4290a61a6b505a2a644031c7..729e0a053fa2f966280556ecf938be4bec6bfb25 100644 (file)
******************************************************************************/\r
/* Chip Level definitions include */\r
#include "platform_internal.h"\r
-\r
-unsigned int pa_serdes_cfg_base = 0x0232A000;\r
-#define PASS_CFG_BASE 0x02000000\r
-#define SGMII0_OFFSET 0x00090100\r
-#define SGMII1_OFFSET 0x00090200\r
-#define SGMII2_OFFSET 0x00090400\r
-#define SGMII3_OFFSET 0x00090500\r
-#define SGMII0_STATUS *((volatile unsigned int *)(PASS_CFG_BASE + SGMII0_OFFSET + 0x14))\r
-#define SGMII1_STATUS *((volatile unsigned int *)(PASS_CFG_BASE + SGMII1_OFFSET + 0x14))\r
-#define SGMII2_STATUS *((volatile unsigned int *)(PASS_CFG_BASE + SGMII2_OFFSET + 0x14))\r
-#define SGMII3_STATUS *((volatile unsigned int *)(PASS_CFG_BASE + SGMII3_OFFSET + 0x14))\r
-\r
-\r
-#define mkptr(base,offset) ((volatile unsigned int *)((base)+(offset)))\r
-unsigned int reg_poll_to(unsigned int wdth, \r
- unsigned int addr, \r
- unsigned int poll_val, \r
- unsigned int masked_bits, \r
- unsigned int to_cycles)\r
-{\r
- unsigned int read_data, read_data_masked;\r
- unsigned int loop_count = 0;\r
- read_data = (*(unsigned int *) (addr));\r
- read_data_masked = read_data & masked_bits;\r
-\r
-\r
- while (read_data_masked != (poll_val & masked_bits))\r
- {\r
-\r
- read_data = (*(volatile unsigned int *) (addr));\r
- read_data_masked = read_data & masked_bits;\r
-\r
- loop_count++;\r
-\r
- if( loop_count == to_cycles )\r
- {\r
- printf("reg_poll_to max Limit reached \n");\r
- return 1;\r
- }\r
- }\r
-\r
- return 0;\r
-}\r
+#define NUM_MAC_PORTS 3\r
//#define SERDES_INTERNAL_LOOPBACK\r
void CSL_SgmiiDefSerdesSetup()\r
{\r
- unsigned int old_val;\r
- volatile unsigned int i;\r
-\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x000));\r
- (*mkptr(pa_serdes_cfg_base, 0x000)) = ((old_val & 0x0000FFFF)| 0x00800000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x014));\r
- (*mkptr(pa_serdes_cfg_base, 0x014)) = ((old_val & 0xFFFF0000)| 0x00008282);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x060));\r
- (*mkptr(pa_serdes_cfg_base, 0x060)) = ((old_val & 0xFF000000)| 0x00142438);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x064));\r
- (*mkptr(pa_serdes_cfg_base, 0x064)) = ((old_val & 0xFF0000FF)| 0x00C3C700);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x078));\r
- (*mkptr(pa_serdes_cfg_base, 0x078)) = ((old_val & 0xFFFF00FF)| 0x0000C000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x204));\r
- (*mkptr(pa_serdes_cfg_base, 0x204)) = ((old_val & 0x00FFFF00)| 0x38000080);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x208));\r
- (*mkptr(pa_serdes_cfg_base, 0x208)) = ((old_val & 0xFFFFFF00)| 0x00000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x20C));\r
- (*mkptr(pa_serdes_cfg_base, 0x20C)) = ((old_val & 0x00FFFFFF)| 0x02000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x210));\r
- (*mkptr(pa_serdes_cfg_base, 0x210)) = ((old_val & 0x00FFFFFF)| 0x1B000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x214));\r
- (*mkptr(pa_serdes_cfg_base, 0x214)) = ((old_val & 0xFFFF0000)| 0x00006FB8);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x218));\r
- (*mkptr(pa_serdes_cfg_base, 0x218)) = ((old_val & 0x0000FF00)| 0x758000E4);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x2AC));\r
- (*mkptr(pa_serdes_cfg_base, 0x2AC)) = ((old_val & 0xFFFF00FF)| 0x00004400);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x22C));\r
- (*mkptr(pa_serdes_cfg_base, 0x22C)) = ((old_val & 0xFF0000FF)| 0x00100800);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x280));\r
- (*mkptr(pa_serdes_cfg_base, 0x280)) = ((old_val & 0xFF00FF00)| 0x00820082);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x284));\r
- (*mkptr(pa_serdes_cfg_base, 0x284)) = ((old_val & 0x00000000)| 0x1D0F0385);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x404));\r
- (*mkptr(pa_serdes_cfg_base, 0x404)) = ((old_val & 0x00FFFF00)| 0x38000080);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x408));\r
- (*mkptr(pa_serdes_cfg_base, 0x408)) = ((old_val & 0xFFFFFF00)| 0x00000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x40C));\r
- (*mkptr(pa_serdes_cfg_base, 0x40C)) = ((old_val & 0x00FFFFFF)| 0x02000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x410));\r
- (*mkptr(pa_serdes_cfg_base, 0x410)) = ((old_val & 0x00FFFFFF)| 0x1B000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x414));\r
- (*mkptr(pa_serdes_cfg_base, 0x414)) = ((old_val & 0xFFFF0000)| 0x00006FB8);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x418));\r
- (*mkptr(pa_serdes_cfg_base, 0x418)) = ((old_val & 0x0000FF00)| 0x758000E4);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x4AC));\r
- (*mkptr(pa_serdes_cfg_base, 0x4AC)) = ((old_val & 0xFFFF00FF)| 0x00004400);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x42C));\r
- (*mkptr(pa_serdes_cfg_base, 0x42C)) = ((old_val & 0xFF0000FF)| 0x00100800);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x480));\r
- (*mkptr(pa_serdes_cfg_base, 0x480)) = ((old_val & 0xFF00FF00)| 0x00820082);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x484));\r
- (*mkptr(pa_serdes_cfg_base, 0x484)) = ((old_val & 0x00000000)| 0x1D0F0385);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x604));\r
- (*mkptr(pa_serdes_cfg_base, 0x604)) = ((old_val & 0x00FFFF00)| 0x38000080);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x608));\r
- (*mkptr(pa_serdes_cfg_base, 0x608)) = ((old_val & 0xFFFFFF00)| 0x00000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x60C));\r
- (*mkptr(pa_serdes_cfg_base, 0x60C)) = ((old_val & 0x00FFFFFF)| 0x02000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x610));\r
- (*mkptr(pa_serdes_cfg_base, 0x610)) = ((old_val & 0x00FFFFFF)| 0x1B000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x614));\r
- (*mkptr(pa_serdes_cfg_base, 0x614)) = ((old_val & 0xFFFF0000)| 0x00006FB8);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x618));\r
- (*mkptr(pa_serdes_cfg_base, 0x618)) = ((old_val & 0x0000FF00)| 0x758000E4);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x6AC));\r
- (*mkptr(pa_serdes_cfg_base, 0x6AC)) = ((old_val & 0xFFFF00FF)| 0x00004400);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x62C));\r
- (*mkptr(pa_serdes_cfg_base, 0x62C)) = ((old_val & 0xFF0000FF)| 0x00100800);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x680));\r
- (*mkptr(pa_serdes_cfg_base, 0x680)) = ((old_val & 0xFF00FF00)| 0x00820082);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x684));\r
- (*mkptr(pa_serdes_cfg_base, 0x684)) = ((old_val & 0x00000000)| 0x1D0F0385);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x804));\r
- (*mkptr(pa_serdes_cfg_base, 0x804)) = ((old_val & 0x00FFFF00)| 0x38000080);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x808));\r
- (*mkptr(pa_serdes_cfg_base, 0x808)) = ((old_val & 0xFFFFFF00)| 0x00000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x80C));\r
- (*mkptr(pa_serdes_cfg_base, 0x80C)) = ((old_val & 0x00FFFFFF)| 0x02000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x810));\r
- (*mkptr(pa_serdes_cfg_base, 0x810)) = ((old_val & 0x00FFFFFF)| 0x1B000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x814));\r
- (*mkptr(pa_serdes_cfg_base, 0x814)) = ((old_val & 0xFFFF0000)| 0x00006FB8);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x818));\r
- (*mkptr(pa_serdes_cfg_base, 0x818)) = ((old_val & 0x0000FF00)| 0x758000E4);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x8AC));\r
- (*mkptr(pa_serdes_cfg_base, 0x8AC)) = ((old_val & 0xFFFF00FF)| 0x00004400);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x82C));\r
- (*mkptr(pa_serdes_cfg_base, 0x82C)) = ((old_val & 0xFF0000FF)| 0x00100800);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x880));\r
- (*mkptr(pa_serdes_cfg_base, 0x880)) = ((old_val & 0xFF00FF00)| 0x00820082);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x884));\r
- (*mkptr(pa_serdes_cfg_base, 0x884)) = ((old_val & 0x00000000)| 0x1D0F0385);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa00));\r
- (*mkptr(pa_serdes_cfg_base, 0xa00)) = ((old_val & 0xFFFF00FF)| 0x00000800);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa08));\r
- (*mkptr(pa_serdes_cfg_base, 0xa08)) = ((old_val & 0x0000FFFF)| 0X38A20000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa30));\r
- (*mkptr(pa_serdes_cfg_base, 0xa30)) = ((old_val & 0xFF0000FF)| 0x008A8A00);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa84));\r
- (*mkptr(pa_serdes_cfg_base, 0xa84)) = ((old_val & 0xFFFF00FF)| 0x00000600);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa94));\r
- (*mkptr(pa_serdes_cfg_base, 0xa94)) = ((old_val & 0x00FFFFFF)| 0x10000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xaa0));\r
- (*mkptr(pa_serdes_cfg_base, 0xaa0)) = ((old_val & 0x00FFFFFF)| 0x81000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xabc));\r
- (*mkptr(pa_serdes_cfg_base, 0xabc)) = ((old_val & 0x00FFFFFF)| 0xFF000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xac0));\r
- (*mkptr(pa_serdes_cfg_base, 0xabc)) = ((old_val & 0xFFFFFF00)| 0x0000008B);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xb08));\r
- (*mkptr(pa_serdes_cfg_base, 0xb08)) = ((old_val & 0x0000FFFF)| 0x583F0000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xb0c));\r
- (*mkptr(pa_serdes_cfg_base, 0xb0c)) = ((old_val & 0xFFFFFF00)| 0x0000004e);\r
-\r
- #ifdef SERDES_INTERNAL_LOOPBACK\r
- /*Beginning of SERDES LOOPBACK Configuration*/\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x200));\r
- (*mkptr(pa_serdes_cfg_base, 0x200)) = ((old_val & 0x00FFFFFF)| 0x40000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x400));\r
- (*mkptr(pa_serdes_cfg_base, 0x400)) = ((old_val & 0x00FFFFFF)| 0x40000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x600));\r
- (*mkptr(pa_serdes_cfg_base, 0x600)) = ((old_val & 0x00FFFFFF)| 0x40000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x800));\r
- (*mkptr(pa_serdes_cfg_base, 0x800)) = ((old_val & 0x00FFFFFF)| 0x40000000);\r
- /*End of Serdes loopback configuration*/\r
- #endif\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x000));\r
- (*mkptr(pa_serdes_cfg_base, 0x000)) = ((old_val & 0xFFFFFF00)| 0x00000003);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa00));\r
- (*mkptr(pa_serdes_cfg_base, 0xa00)) = ((old_val & 0xFFFFFF00)| 0x0000005F);\r
-\r
-\r
- /*Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */\r
- *mkptr(pa_serdes_cfg_base, 0x1fe0) = 0xF800F8C0;\r
- *mkptr(pa_serdes_cfg_base, 0x1fe4) = 0xF800F8C0;\r
- *mkptr(pa_serdes_cfg_base, 0x1fe8) = 0xF800F8C0;\r
- *mkptr(pa_serdes_cfg_base, 0x1fec) = 0xF800F8C0;\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval;\r
+ CSL_SERDES_STATUS pllstat;\r
+ int numPort1 = (NUM_MAC_PORTS > 2)?2:NUM_MAC_PORTS;\r
+ int numPort2 = (NUM_MAC_PORTS > 2)?NUM_MAC_PORTS - 2:0;\r
+\r
+\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(CSL_NETCP_SERDES_0_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch1 */\r
+\r
+ if (numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(CSL_NETCP_SERDES_1_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* 4 port switch2 */\r
+ }\r
+\r
+ //SB Lane Enable\r
+ for(i=0; i < numPort1; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_0_CFG_REGS,\r
+ i,\r
+ CSL_SERDES_LOOPBACK_DISABLED,\r
+ CSL_SERDES_LANE_QUARTER_RATE); /* 4 port switch1 */\r
+ }\r
\r
- /*Enable pll via the pll_ctrl 0x0014*/\r
- *mkptr(pa_serdes_cfg_base, 0x1ff4) = 0xe0000000;\r
+ for(i=0; i < numPort2; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_NETCP_SERDES_1_CFG_REGS,\r
+ i,\r
+ CSL_SERDES_LOOPBACK_DISABLED,\r
+ CSL_SERDES_LANE_QUARTER_RATE); /* 4 port switch2 */\r
+ }\r
\r
- /*Waiting for SGMII Serdes PLL lock.*/\r
- reg_poll_to(32, SGMII0_STATUS, 0x10, 0x10, 10000);\r
- reg_poll_to(32, SGMII1_STATUS, 0x10, 0x10, 10000);\r
- reg_poll_to(32, SGMII2_STATUS, 0x10, 0x10, 10000);\r
- reg_poll_to(32, SGMII3_STATUS, 0x10, 0x10, 10000);\r
+ /* SB PLL Enable */\r
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_0_CFG_REGS); /* 4 port switch1 */\r
+ if(numPort2)\r
+ CSL_EthernetSerdesPllEnable(CSL_NETCP_SERDES_1_CFG_REGS); /* 4 port switch2 */\r
\r
+ /* SB PLL Status Poll */\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_0_CFG_REGS, numPort1); /* 4 port switch1 */\r
+ if(numPort2)\r
+ pllstat &= CSL_EthernetSerdesGetStatus(CSL_NETCP_SERDES_1_CFG_REGS, numPort2); /* 4 port switch2 */\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
\r
- for(i = 0; i < 5000; i++);\r
- for(i = 0; i < 40000; i++);\r
}\r
\r
\r
index 947c9ad4ea46442e761f087e876b350d1b2f338b..4c5ea0ed2b3a6d96703c404009a576b264a90f8c 100755 (executable)
};\r
\r
#if (PLATFORM_EXTMEMTEST_IN)\r
-static inline int32_t platform_memory_test (uint32_t start_address, uint32_t end_address);\r
+static inline int32_t platform_memory_test (uint32_t start_address, uint32_t end_address);
#endif\r
\r
/******************************************************************************\r
platform_errno = 0;\r
#endif\r
\r
+ PowerUpDomains();\r
+\r
/* PLLC module handle structure */\r
if (p_flags->pll)\r
{\r
return ( (Platform_STATUS) Platform_EFAIL);\r
}\r
\r
-
-\r
/* Set the DDR3 PLL */\r
status = SetDDR3PllConfig(&ddr_pll_data);\r
if (status != CSL_SOK)\r
status = DDR3Init();\r
#endif\r
\r
-\r
if (status != CSL_SOK) {\r
platform_errno = PLATFORM_ERRNO_GENERIC;\r
return ( (Platform_STATUS) Platform_EFAIL);\r
}\r
#endif\r
\r
- PowerUpDomains();\r
-\r
/* Enable Error Correction for memory */\r
if (p_flags->ecc) {\r
enableL1PEDC();\r
index 39cb24f3d16d211d71871b4fd10671dd68268054..3006968af3fc77f9fd21877e1513488407f4f380 100755 (executable)
<listOptionValue builtIn="false" value=""${PROJECT_ROOT}/../../../..""/>
<listOptionValue builtIn="false" value=""${PROJECT_ROOT}/../..""/>
</option>
- <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE.1481853604" name="Mode" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE" value="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE.manual" valueType="enumerated"/>
+ <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE.1481853604" name="Mode" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE" value="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE.automatic" valueType="enumerated"/>\r
<option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.DEFINE.1740639170" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.DEFINE" valueType="definedSymbols">
<listOptionValue builtIn="false" value="DEVICE_K2E"/>
</option>
<listOptionValue builtIn="false" value=""${PROJECT_ROOT}/../platform_lib/lib/debug""/>
<listOptionValue builtIn="false" value=""${PROJECT_ROOT}/../../../csl/lib/k2e/c66""/>
</option>
- <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.XML_LINK_INFO.255106532" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.XML_LINK_INFO" value=""platform_test_evmk2e_linkInfo.xml"" valueType="string"/>
+ <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.XML_LINK_INFO.255106532" name="Detailed link information data-base into <file> (--xml_link_info, -xml_link_info)" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.XML_LINK_INFO" value=""platform_test_evmk2e_linkInfo.xml"" valueType="string"/>\r
<inputType id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__CMD_SRCS.17572325" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__CMD_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__CMD2_SRCS.1895228935" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__CMD2_SRCS"/>
<inputType id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__GEN_CMDS.1781659870" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__GEN_CMDS"/>
diff --git a/evmk2e/platform_test/testconfig/platform_test_input.txt b/evmk2e/platform_test/testconfig/platform_test_input.txt
index db006b9f9d54133e55a4235e2be5a1eb8f2da09f..5aafc014e4baf8886340c2ff6b7d06e46fc51f10 100755 (executable)
test_nand = 1
test_nor = 1
test_led = 1
-test_uart = 1
+test_uart = 0
run_external_memory_test = 1
run_internal_memory_test = 1
diff --git a/evmk2l/platform_lib/include/evmc66x_fpga.h b/evmk2l/platform_lib/include/evmc66x_fpga.h
--- /dev/null
@@ -0,0 +1,119 @@
+/******************************************************************************
+ * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name: evmc66x_fpga.h
+ *
+ * Description: This is the header file for FPGA interface
+ *
+ ******************************************************************************/
+
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+/************************
+ * Defines and Macros
+ ************************/
+#define SPI_FPGA_MAX_FREQ (25000000) /* SPI FPGA Max frequency in Hz */
+
+/* ------------------------------------------------------------------------ *
+ * FPGA Error Status *
+ * ------------------------------------------------------------------------ */
+#define FPGA_STATUS Uint32 /* NOR status error code */
+#define FPGA_EFAIL (FPGA_STATUS)-1 /* General failure code */
+#define FPGA_EOK 0 /* General success code */
+
+#define FPGA_RD_CMD (1 << 7)
+#define FPGA_WR_CMD (0 << 7)
+
+
+/* FPGA Configuration Register offsets */
+#define FPGA_DEV_ID_LO_OFFSET (0x00)
+#define FPGA_DEV_ID_HI_OFFSET (0x01)
+#define FPGA_REV_ID_LO_OFFSET (0x02)
+#define FPGA_REV_ID_HI_OFFSET (0x03)
+#define FPGA_BM_GPI_LO_OFFSET (0x04)
+#define FPGA_BM_GPI_HI_OFFSET (0x05)
+#define FPGA_DBG_LED_OFFSET (0x1D)
+#define FPGA_MMC_CTL_OFFSET (0x09)
+#define FPGA_RSTBST_REG_OFFSET (0x0B)
+#define FPGA_MISC_REG_OFFSET (0x0C)
+#define FPGA_MAX_ADDR_OFFSET (0x3F)
+
+// Macros for errors
+#define INVALID_FPGA_CMD (5)
+#define INVALID_FPGA_ADDR (6)
+
+/************************
+ * Structures and Enums
+ ************************/
+typedef enum _FPGA_LedStatus
+{
+ FPGA_LED_OFF = 0,
+ FPGA_LED_ON = 1
+}FPGA_LedStatus;
+
+typedef enum _FPGA_UserLed
+{
+ FPGA_USER_LED0 = 0,
+ FPGA_USER_LED1 = 1,
+ FPGA_USER_LED2 = 2,
+ FPGA_USER_LED3 = 3
+}FPGA_UserLed;
+
+/************************
+ * Function declarations
+ ************************/
+uint32_t getBoardVersion(void);
+uint32_t getFpgaDevID(void);
+uint32_t fpgaGetAMCDetect(void);
+void fpgaEnableNandWriteProtect(void);
+void fpgaDisableNandWriteProtect(void);
+void fpgaEnableNorWriteProtect(void);
+void fpgaDisableNorWriteProtect(void);
+void fpgaEnableEepromWriteProtect(void);
+void fpgaDisableEepromWriteProtect(void);
+void fpgaControlUserLEDs(FPGA_UserLed uchUserLEDNum,
+ FPGA_LedStatus uchStatus);
+uint32_t fpgaGetUserSwitch(uint32_t uiSwitchNum);
+uint32_t fpgaWriteConfigurationRegister(uint8_t uchAddress,
+ uint8_t uchValue);
+uint32_t fpgaReadConfigurationRegister(uint8_t uchAddress,
+ uint8_t *puchValue);
+#endif // _FPGA_H_
+
+
+
+
+
diff --git a/evmk2l/platform_lib/include/evmc66x_gpio.h b/evmk2l/platform_lib/include/evmc66x_gpio.h
index 118007f0dce16103a3dc2e6510ceee227cd9e252..a0ed10064a06d6a81494296e54dce063f5a1588b 100755 (executable)
#define INVALID_GPIO_DIRECTION (3) /* Invalid GPIO direction error */
#define INVALID_GPIO_STATE (4)
+/* Debug LED GPIO Moved to platform_internal.h
/* Debug LED GPIO */
-#define LED0_RED GPIO_12
-#define LED0_GREEN GPIO_13
-#define LED1_BLUE GPIO_14
-#define LED2_BLUE GPIO_15
-#define led_gpio(x) (LED0_RED + (x))
+#define LED0_RED 1
+#define LED0_GREEN 2
+#define LED1_BLUE 4
+#define LED2_BLUE 8
+#define led_fpga(x) (LED0_RED + (x))
+#define SPI_FPGA_CMD 0x1D
typedef enum _GpioDirection
{
index e5a5a849fa4db323f1a956bb1d548551e7e1be21..97e0651c592af5d7bc848446a8f1941aa4569a3b 100755 (executable)
/* ------------------------------------------------------------------------ *
* SPI Controller *
* ------------------------------------------------------------------------ */
-#define SPI_BASE CSL_SPI_0_SLV_REGS
+#define SPI_PORT (spiportnumber == 0)
+#define SPI_BASE0 CSL_SPI_0_SLV_REGS
+#define SPI_BASE1 CSL_SPI_1_SLV_REGS
+#define SPI_BASE ((SPI_PORT) ? (SPI_BASE0) : (SPI_BASE1))
+
#define SPI_SPIGCR0 *( volatile Uint32* )( SPI_BASE + 0x0 )
#define SPI_SPIGCR1 *( volatile Uint32* )( SPI_BASE + 0x4 )
#define SPI_SPIINT0 *( volatile Uint32* )( SPI_BASE + 0x8 )
#define SPI_NOR_CHAR_LENTH 8 /* Number of bits per SPI trasfered data element for NOR flash */
#define SPI_FPGA_CHAR_LENTH 16 /* Number of bits per SPI trasfered data element for FPGA */
+#define SPI0 0
+#define SPI1 1
/* SPI error status */
#define SPI_STATUS Uint32 /* SPI error status type */
SPI_STATUS
spi_claim
(
+ uint8_t spiportnumber,
Uint32 cs,
Uint32 freq
);
void
spi_release
(
- void
+ uint8_t spiportnumber
);
SPI_STATUS
spi_xfer
(
+ uint8_t spiportnumber,
Uint32 bitlen,
Uint8* dout,
Uint8* din,
SPI_STATUS
spi_cmd
(
+ uint8_t spiportnumber,
Uint8 cmd,
Uint8* response,
Uint32 len
-);
+ );
SPI_STATUS
spi_cmd_read
(
+ uint8_t spiportnumber,
Uint8* cmd,
Uint32 cmd_len,
Uint8* data,
SPI_STATUS
spi_cmd_write
(
+ uint8_t spiportnumber,
Uint8* cmd,
Uint32 cmd_len,
Uint8* data,
SPI_STATUS
spi_read_word
(
+ uint8_t spiportnumber,
Uint16* cmd_buf,
Uint32 cmd_len,
Uint16* data_buf,
SPI_STATUS
spi_write_word
(
+ uint8_t spiportnumber,
Uint16* cmd_buf,
Uint32 cmd_len,
Uint16* data_buf,
Uint32 data_len
+
);
#endif /* SPI_H_ */
diff --git a/evmk2l/platform_lib/include/platform_internal.h b/evmk2l/platform_lib/include/platform_internal.h
index 5d51689325a452002a7109daaeadf30addeebf06..b44acc4208123e4169b5d291d6e98c82f1d2eadc 100755 (executable)
#include "evmc66x_nor.h"
#include "evmc66x_spi.h"
#include "cslr_spi.h"
+#include "evmc66x_fpga.h"
#include "csl_xmcAux.h"
#include "evmc66x_pllc.h"
-
+#include "csl_serdes_ethernet.h"
/********************************************************************************************
* Platform Specific Declarations *
*******************************************************************************************/
#define PLATFORM_L1D_BASE_ADDRESS 0x10F00000
#define PLATFORM_L1D_SIZE 0x8000 /* 32K bytes */
#define PLATFORM_DDR3_SDRAM_START 0x80000000
-#define PLATFORM_DDR3_SDRAM_END 0x3FFFFFFF /* DDR3A 1024 MB */
+#define PLATFORM_DDR3_SDRAM_END 0x9FFFFFFF /* DDR3A 1024 MB */
/* 24AA1025 EEPROM */
#define PLATFORM_EEPROM_MANUFACTURER_ID (0x01)
#define PLATFORM_EEPROM_DEVICE_ID_1 (0x50)
#define PLATFORM_EEPROM_DEVICE_ID_2 (0x51)
+
+
/********************************************************************************************
* General Declarations *
*******************************************************************************************/
extern void Init_SGMII(uint32_t macport);
extern void PowerUpDomains (void);
extern void xmc_setup();
-
+uint8_t fpga_led_set(uint32_t uiLed);
+uint8_t fpga_led_set(uint32_t uiLed);
/********************************************************************************************
* PLL control local Declarations *
*******************************************************************************************/
#define write_reg(v,a) (*(volatile uint32_t *)(a) = (v))
CSL_Status SetDDR3PllConfig(pll_init_data *data);
-
+int32_t init_ddr3param(uint8_t *);
#endif
index f915e3fb2253db7a0373f131a00f9aaa4bd75735..e4396b901b45f0c7bd253150642f7b92b50ebff1 100755 (executable)
DDR3PLLCTL1_REG(data->pll) |= 0x00000040;
/* Wait for the PLL Reset time (min: 1000 ns) */
- /*pll_delay(1400);*/
+ pll_delay(1200);
/* Put the PLL in Bypass Mode *
* DDR3PLLCTL0_REG Bit map *
}
-static ddr3_emif_config ddr3_1600_32 = {
- 0x6200DE62,
+static ddr3_emif_config ddr3_1600 = {
+ 0x6200CE62,
0x166C9855,
0x00001D4A,
- 0x321DFF53,
- 0x543F07FF,
+ 0x435DFF53,
+ 0x543F0CFF,
0x70073200,
0x00001869,
};
-static ddr3_phy_config ddr3phy_1600_32 = {
+
+static ddr3_phy_config ddr3phy_1600 = {
0x1C000,
(IODDRM_MASK | ZCKSEL_MASK | ZCKSEL_MASK),
((1 << 2) | (1 << 7) | (1 << 23)),
- 0x426213CF,
- 0xCFC712B3,
+ 0x42C21590,
+ 0xD05612C0,
0, /* not set in gel */
- 0x08861A80,
+ 0x0D861A80,
0x0C827100,
- (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK),
- ((1 << 10) | (1 << 27)),
- 0x019CBB66,
- 0x1284040C,
- 0x5002CE00,
+ (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ ((1 << 10)),
+ 0x9D5CBB66,
+ 0x12868300,
+ 0x5002D200,
0x00001C70,
0x00000006,
- 0x00000058,
+ 0x00000018,
0x710035C7,
0x00F07A12,
- 0x0000007B,
- 0x0000007B,
- 0x0000007B,
+ 0x0001005D,
+ 0x0001005B,
+ 0x0001005B,
0x00000033,
0x0000FF81,
};
-
-
void init_ddrphy(uint32_t base, ddr3_phy_config *phy_cfg)
{
uint32_t tmp;
CSL_BootCfgUnlockKicker();
- init_ddrphy(TCI6630_DDR3A_DDRPHYC, &ddr3phy_1600_32);
- init_ddremif(TCI6630_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32);
+ init_ddrphy(TCI6630_DDR3A_DDRPHYC, &ddr3phy_1600);
+ init_ddremif(TCI6630_DDR3A_EMIF_CTRL_BASE, &ddr3_1600);
return (status);
}
diff --git a/evmk2l/platform_lib/src/evmc66x_fpga.c b/evmk2l/platform_lib/src/evmc66x_fpga.c
--- /dev/null
@@ -0,0 +1,517 @@
+/******************************************************************************
+ * Copyright (c) 2011-2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name: evmc665x_fpga.c
+ *
+ * Description: This file contains the function definitions for accessing
+ * fpga device registers
+ *
+ ******************************************************************************/
+
+/************************
+ * Include Files
+ ************************/
+#include "platform_internal.h"
+
+#if 0
+/******************************************************************************
+ *
+ * Function: getBoardVersion
+ *
+ * Description: Gets the board version
+ *
+ * Parameters: void
+ *
+ * Return Value: Board version
+ ******************************************************************************/
+uint32_t getBoardVersion(void)
+{
+ uint8_t uchValue_lo = 0;
+ uint8_t uchValue_hi = 0;
+ uint32_t ret;
+
+ /* Read the lo REV ID */
+ ret = fpgaReadConfigurationRegister(FPGA_REV_ID_LO_OFFSET, &uchValue_lo);
+
+ IFPRINT(platform_write ("FPGA_REV_ID_LO_OFFSET = %d\n", uchValue_lo & 0xff));
+
+ if (ret != SUCCESS) {
+ IFPRINT(platform_write ( "getBoardVersion: Error in reading the fpga config reg lo\n"));
+ }
+
+ /* Read the hi REV ID */
+ ret = fpgaReadConfigurationRegister(FPGA_REV_ID_HI_OFFSET, &uchValue_hi);
+
+ IFPRINT (platform_write("FPGA_REV_ID_HI_OFFSET = %d\n", uchValue_hi & 0xff));
+
+ if (ret != SUCCESS) {
+ IFPRINT( platform_write ( "getBoardVersion: Error in reading the fpga config reg hi\n"));
+ }
+
+ return (uchValue_hi << 8 | uchValue_lo);
+}
+#endif
+/******************************************************************************
+ *
+ * Function: getFpgaDevID
+ *
+ * Description: Gets the fpga device ID
+ *
+ * Parameters: void
+ *
+ * Return Value: fpga device ID
+ ******************************************************************************/
+uint32_t getFpgaDevID(void)
+{
+ uint8_t uchValue_lo = 0;
+ uint8_t uchValue_hi = 0;
+ uint32_t ret;
+
+ /* Read the lo REV ID */
+ ret = fpgaReadConfigurationRegister(FPGA_DEV_ID_LO_OFFSET, &uchValue_lo);
+
+ IFPRINT (platform_write("FPGA_DEV_ID_LO_OFFSET = %d\n", uchValue_lo & 0xff));
+
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "getBoardVersion: Error in reading the fpga config reg lo\n"));
+ }
+
+
+ /* Read the hi REV ID */
+ ret = fpgaReadConfigurationRegister(FPGA_DEV_ID_HI_OFFSET, &uchValue_hi);
+
+ IFPRINT (platform_write("FPGA_DEV_ID_HI_OFFSET = %d\n", uchValue_hi & 0xff));
+
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "getBoardVersion: Error in reading the fpga config reg hi\n"));
+ }
+
+ return (uchValue_hi << 8 | uchValue_lo);
+}
+
+/******************************************************************************
+ *
+ * Function: fpgaControlUserLEDs
+ *
+ * Description: This function enable/disables user LEDs
+ *
+ * Parameters: uchUserLEDNum - User LED number (0, 1, 2, 3)
+ * uchStatus - User LED status
+ *
+ * Return Value: void
+ *
+ ******************************************************************************/
+void fpgaControlUserLEDs(FPGA_UserLed uchUserLEDNum,
+ FPGA_LedStatus uchStatus)
+{
+ uint8_t uchValue = 0; /* Default value */
+ uint8_t temp;
+ uint32_t ret;
+
+ if ( (FPGA_USER_LED0 > uchUserLEDNum) ||
+ (FPGA_USER_LED3 < uchUserLEDNum)) {
+ /* No action for the invalid LED numbers */
+ return;
+ }
+
+ /* Read the current LED status */
+ ret = fpgaReadConfigurationRegister(FPGA_DBG_LED_OFFSET, &uchValue);
+
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "fpgaControlUserLEDs: Error in reading the fpga config reg\n"));
+ }
+
+ /* Turn on/off the corresponding LED bit number */
+ switch (uchStatus) {
+ case FPGA_LED_ON:
+ temp = (FPGA_LED_ON << uchUserLEDNum);
+ uchValue |= temp;
+ break;
+ case FPGA_LED_OFF:
+ temp = ~(FPGA_LED_ON << uchUserLEDNum);
+ uchValue &= temp;
+ break;
+ default: /* No action */
+ break;
+ }
+
+ /* Send command to turn on/off the Corresponding LED */
+ ret = fpgaWriteConfigurationRegister(FPGA_DBG_LED_OFFSET, uchValue);
+
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "fpgaControlUserLEDs: Error in writing the fpga config reg\n"));
+ }
+
+
+ return;
+
+}
+
+/******************************************************************************
+ *
+ * Function: fpgaDisableNandWriteProtect
+ *
+ * Description: This function enables the write protect in NAND
+ *
+ * Parameters: void
+ *
+ * Return Value: void
+ *
+ ******************************************************************************/
+void fpgaDisableNandWriteProtect(void)
+{
+ uint8_t uchValue = 0x14; /* default misc reg value */
+ uint32_t ret;
+
+ /* Read the current Misc Register status */
+ ret = fpgaReadConfigurationRegister(FPGA_MISC_REG_OFFSET, &uchValue);
+
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "fpgaDisableNandWriteProtect: Error in Reading the NAND WP\n"));
+ }
+
+ uchValue &= ~(1 << 2);
+
+ /* Send command to disable the NandWrite Protect */
+ ret = fpgaWriteConfigurationRegister(FPGA_MISC_REG_OFFSET, uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "fpgaDisableNandWriteProtect: Error in writing the NAND WP\n"));
+ }
+
+ return;
+
+}
+
+/******************************************************************************
+ *
+ * Function: fpgaEnableNandWriteProtect
+ *
+ * Description: This function enables the write protect in NAND
+ *
+ * Parameters: void
+ *
+ * Return Value: void
+ *
+ ******************************************************************************/
+void fpgaEnableNandWriteProtect(void)
+{
+ uint8_t uchValue = 0x14; /* default misc reg value */
+ uint32_t ret;
+
+ /* Read the current Misc Register status */
+ ret = fpgaReadConfigurationRegister(FPGA_MISC_REG_OFFSET, &uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write("fpgaEnableNandWriteProtect: Error in Reading the NAND WP\n"));
+ }
+
+ uchValue |= (1 << 2);
+
+ /* Send command to enable the NandWrite Protect */
+ fpgaWriteConfigurationRegister(FPGA_MISC_REG_OFFSET, uchValue);
+
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "fpgaEnableNandWriteProtect: Error in Writing the NAND WP\n"));
+ }
+
+ return;
+}
+
+/******************************************************************************
+ *
+ * Function: fpgaDisableNorWriteProtect
+ *
+ * Description: This function enables the write protect in NAND
+ *
+ * Parameters: void
+ *
+ * Return Value: void
+ *
+ ******************************************************************************/
+void fpgaDisableNorWriteProtect(void)
+{
+ uint8_t uchValue = 0x14; /* default misc reg value */
+ uint32_t ret;
+
+ /* Read the current Misc Register status */
+ ret = fpgaReadConfigurationRegister(FPGA_MISC_REG_OFFSET, &uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "fpgaDisableNorWriteProtect: Error in Reading the NOR WP\n"));
+ }
+
+ uchValue |= (1 << 4);
+
+ /* Send command to disable the Nor Write Protect */
+ ret = fpgaWriteConfigurationRegister(FPGA_MISC_REG_OFFSET, uchValue);
+
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write("fpgaDisableNorWriteProtect: Error in writing the NOR WP\n"));
+ }
+
+ return;
+}
+
+/******************************************************************************
+ *
+ * Function: fpgaEnableNorWriteProtect
+ *
+ * Description: This function enables the write protect in NAND
+ *
+ * Parameters: void
+ *
+ * Return Value: void
+ *
+ ******************************************************************************/
+void fpgaEnableNorWriteProtect(void)
+{
+ uint8_t uchValue = 0x14; /* default misc reg value */
+ uint32_t ret;
+
+ /* Read the current Misc Register status */
+ ret = fpgaReadConfigurationRegister(FPGA_MISC_REG_OFFSET, &uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write("fpgaEnableNorWriteProtect: Error in Reading the NOR WP\n"));
+ }
+
+ uchValue |= (1 << 4);
+
+ /* Send command to enable the Nor Write Protect */
+ ret = fpgaWriteConfigurationRegister(FPGA_MISC_REG_OFFSET, uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write("fpgaEnableNorWriteProtect: Error in Writing the NOR WP\n"));
+ }
+
+ return;
+}
+/******************************************************************************
+ *
+ * Function: fpgaDisableEepromWriteProtect
+ *
+ * Description: This function enables the write protect in NAND
+ *
+ * Parameters: void
+ *
+ * Return Value: void
+ *
+ ******************************************************************************/
+void fpgaDisableEepromWriteProtect(void)
+{
+ uint8_t uchValue = 0x14; /* default misc reg value */
+ uint32_t ret;
+
+ /* Read the current Misc Register status */
+ ret = fpgaReadConfigurationRegister(FPGA_MISC_REG_OFFSET, &uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write("fpgaDisableEepromWriteProtect: Error in Reading the EEPROM WP\n"));
+ }
+ uchValue |= (1 << 5);
+
+ /* Send command to disable the EEPROMWrite Protect */
+ ret = fpgaWriteConfigurationRegister(FPGA_MISC_REG_OFFSET, uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "fpgaDisableEepromWriteProtect: Error in Writing the EEPROM WP\n"));
+ }
+
+ return;
+}
+/******************************************************************************
+ *
+ * Function: fpgaEnableEepromWriteProtect
+ *
+ * Description: This function enables the write protect in NAND
+ *
+ * Parameters: void
+ *
+ * Return Value: void
+ *
+ ******************************************************************************/
+void fpgaEnableEepromWriteProtect(void)
+{
+ uint8_t uchValue = 0x14; /* default misc reg value */
+ uint32_t ret;
+
+ /* Read the current Misc Register status */
+ ret = fpgaReadConfigurationRegister(FPGA_MISC_REG_OFFSET, &uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write("fpgaEnableEepromWriteProtect: Error in Reading the EEPROM WP\n"));
+ }
+
+ uchValue &= ~(1 << 5);
+
+ /* Send command to enable the EEPROM Write Protect */
+ ret = fpgaWriteConfigurationRegister(FPGA_MISC_REG_OFFSET, uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "fpgaEnableEepromWriteProtect: Error in Writing the EEPROM WP\n"));
+ }
+
+ return;
+}
+/******************************************************************************
+ *
+ * Function: fpgaGetUserSwitch
+ *
+ * Description: This function gets the status of user switch
+ *
+ * Parameters: uint8_t* - address of byte location
+ *
+ * Return Value: status 0 = switch off, 1 = switch on
+ *
+ ******************************************************************************/
+uint32_t fpgaGetUserSwitch(uint32_t uiSwitchNum)
+{
+ uint8_t uchValue = 0;
+ uint32_t ret;
+
+ /* Read the current Reset Button Status Register */
+ ret = fpgaReadConfigurationRegister(FPGA_RSTBST_REG_OFFSET, &uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write("fpgaGetUserSwitch: Error in Reading the USER SWITCH\n"));
+ }
+
+ /* Check if BIT 7 is high or low for the user switch */
+ uchValue &= (0x80);
+
+ if (uchValue == 0)
+ return 1;
+ else
+ return 0;
+}
+
+/******************************************************************************
+ *
+ * Function: fpgaGetAMCDetect
+ *
+ * Description: This function gets the status, whether AMC is detected or not
+ *
+ * Parameters: uint8_t* - address of byte location
+ *
+ * Return Value: status 0 = AMC not detected
+ * 1 = AMC Detected
+ *
+ ******************************************************************************/
+uint32_t fpgaGetAMCDetect(void)
+{
+ uint8_t uchValue = 0;
+ uint32_t ret;
+
+ /* Read the current BM_GPIO Switch */
+ ret = fpgaReadConfigurationRegister(FPGA_MMC_CTL_OFFSET, &uchValue);
+ if (ret != SUCCESS) {
+ IFPRINT (platform_write( "fpgaGetAMCDetect: Error in Reading the AMC switch\n"));
+ }
+
+ uchValue &= (1);
+
+ if (uchValue == 0)
+ return 1;
+ else
+ return 0;
+}
+/******************************************************************************
+ *
+ * Function: fpgaWriteConfigurationRegister
+ *
+ * Description: This function writes to spicified FPGA configuration reg.
+ *
+ * Parameters: uchAddress - Address of configuration reg
+ * uchValue - Value to be written
+ *
+ * Return Value: status
+ ******************************************************************************/
+uint32_t fpgaWriteConfigurationRegister(uint8_t uchAddress, uint8_t uchValue)
+{
+ uint16_t cmd;
+ uint32_t ret;
+ uint16_t value = (uint16_t) uchValue;
+
+ value = value & 0x00FF;
+
+ if(uchAddress > FPGA_MAX_ADDR_OFFSET )
+ return INVALID_FPGA_ADDR;
+
+ /* Open the SPI controller for FPGA */
+ spi_claim(SPI1,SPI_FPGA_CS, SPI_FPGA_MAX_FREQ);
+
+ /* Get the current state of the debug LEDs */
+ cmd = (FPGA_WR_CMD | uchAddress)<< 8;
+ cmd |= uchValue;
+ ret = spi_write_word(SPI1,&cmd, (Uint32 )1, &value, (Uint32)1);
+ if (ret)
+ {
+ spi_release(SPI1);
+ return FAIL;
+ }
+
+ spi_release(SPI1);
+ return SUCCESS;
+}
+
+/******************************************************************************
+ *
+ * Function: fpgaReadConfigurationRegister
+ *
+ * Description: This function reads spicified FPGA configuration reg.
+ *
+ * Parameters: uchAddress - Address of configuration reg
+ * puchValue - pointer to store the read value
+ *
+ * Return Value: status
+ ******************************************************************************/
+uint32_t fpgaReadConfigurationRegister(uint8_t uchAddress, uint8_t* puchValue)
+{
+ uint16_t cmd;
+ uint32_t ret;
+ uint16_t value;
+
+ if(uchAddress > FPGA_MAX_ADDR_OFFSET )
+ return INVALID_FPGA_ADDR;
+
+ /* Open the SPI controller for FPGA */
+ spi_claim(SPI1,SPI_FPGA_CS, SPI_FPGA_MAX_FREQ);
+
+ /* Get the current state of the debug LEDs */
+ cmd = (FPGA_RD_CMD | uchAddress) << 8;
+ ret = spi_read_word(SPI1,&cmd, 1, &value, 1);
+
+ *puchValue = value & 0xFF;
+
+ if (ret)
+ {
+ spi_release(SPI1);
+ return FAIL;
+ }
+
+ spi_release(SPI1);
+ return SUCCESS;
+}
diff --git a/evmk2l/platform_lib/src/evmc66x_i2c_eeprom.c b/evmk2l/platform_lib/src/evmc66x_i2c_eeprom.c
index 3327e25fddadbdb91ad02b1923b80646a38baec5..11ccc9bb71ed64c8c7968b1f3b76a9b846d828ee 100755 (executable)
i2cDelay (DELAY_CONST);\r
\r
/* Put the first byte into the transmit register, set the start bit */\r
- uiValue = (*puiData >> 8) & 0x00ff;\r
- I2CR->ICDXR = uiValue;\r
+ if (i2cportnumber == 1)\r
+ uiValue = (*puiData) & 0xff;\r
+ else\r
+ uiValue = (*puiData >> 8) & 0x00ff;\r
+\r
+ I2CR->ICDXR = uiValue;\r
uiByteType = I2C_BYTE_LSB;\r
\r
/* Set the start bit */\r
\r
\r
/* Write the byte address to the eeprom. Do not send a stop */\r
- uiReturnValue = i2cEepromWriteBlock ( uchEepromI2cAddress, &byte_addr, \r
- 2, I2C_DO_NOT_RELEASE_BUS,i2cportnumber);\r
+ if (i2cportnumber == 1)\r
+ uiReturnValue = i2cEepromWriteBlock ( uchEepromI2cAddress, &byte_addr,\r
+ 1, I2C_DO_NOT_RELEASE_BUS,i2cportnumber);\r
+ else\r
+ uiReturnValue = i2cEepromWriteBlock ( uchEepromI2cAddress, &byte_addr,\r
+ 2, I2C_DO_NOT_RELEASE_BUS,i2cportnumber);\r
+\r
if (uiReturnValue != I2C_RET_OK)\r
return (uiReturnValue);\r
\r
{\r
\r
/* Send Read Status command */\r
- ret = spi_xfer(1, &cmd, NULL, FALSE);\r
+ ret = spi_xfer(SPI0,1, &cmd, NULL, FALSE);\r
if (ret)\r
{\r
return ret;\r
}\r
\r
/* Read status value */\r
- ret = spi_xfer(1, NULL, &status, TRUE);\r
+ ret = spi_xfer(SPI0,1, NULL, &status, TRUE);\r
if (ret)\r
{\r
return ret;\r
uint8_t idcode[3]; /* Initialize the SPI interface */\r
\r
/* Claim the SPI controller */\r
- spi_claim(SPI_NOR_CS, SPI_MAX_FREQ);\r
+ spi_claim(SPI0,SPI_NOR_CS, SPI_MAX_FREQ);\r
\r
/* Read the ID codes */\r
- ret = spi_cmd(SPI_NOR_CMD_RDID, idcode, sizeof(idcode));\r
+ ret = spi_cmd(SPI0,SPI_NOR_CMD_RDID, idcode, sizeof(idcode));\r
if (ret) {\r
- spi_release();\r
+ spi_release(SPI0);\r
platform_errno = PLATFORM_ERRNO_NOR;\r
return FAIL;\r
}\r
/* No blocks are bad for NOR.. for now */\r
nor_info->bblist = NULL;\r
\r
- spi_release();\r
+ spi_release(SPI0);\r
\r
return uiStatus; \r
}\r
uint8_t idcode[3]; /* Initialize the SPI interface */\r
\r
/* Claim the SPI controller */\r
- spi_claim(SPI_NOR_CS, SPI_MAX_FREQ);\r
+ spi_claim(SPI0,SPI_NOR_CS, SPI_MAX_FREQ);\r
\r
/* Read the ID codes */\r
- ret = spi_cmd(SPI_NOR_CMD_RDID, idcode, sizeof(idcode));\r
+ ret = spi_cmd(SPI0,SPI_NOR_CMD_RDID, idcode, sizeof(idcode));\r
if (ret) \r
{\r
IFPRINT (platform_write( "nor_init: Error in reading the idcode\n"));\r
- spi_release();\r
+ spi_release(SPI0);\r
platform_errno = PLATFORM_ERRNO_NOR;\r
return NOR_EFAIL;\r
}\r
\r
if (idcode[0] != SPI_NOR_MANUFACTURE_ID) {\r
/* Expected Manufacturer ID does not match */\r
- spi_release();\r
+ spi_release(SPI0);\r
platform_errno = PLATFORM_ERRNO_BADFLASHDEV;\r
return NOR_EFAIL;\r
}\r
\r
- spi_release();\r
+ spi_release(SPI0);\r
return NOR_EOK; \r
}\r
\r
NOR_STATUS ret_val;\r
\r
/* Claim the SPI controller */\r
- spi_claim(SPI_NOR_CS, SPI_MAX_FREQ);\r
+ spi_claim(SPI0,SPI_NOR_CS, SPI_MAX_FREQ);\r
\r
/* Validate address input */\r
if(addr + len > SPI_NOR_MAX_FLASH_SIZE) \r
{\r
platform_errno = PLATFORM_ERRNO_FLASHADDR;\r
- spi_release();\r
+ spi_release(SPI0);\r
return NOR_EFAIL;\r
}\r
\r
cmd[2] = (uint8_t)(addr>>8);\r
cmd[3] = (uint8_t)addr;\r
\r
- ret_val = (spi_cmd_read(cmd, 4, buf, len)); \r
+ ret_val = (spi_cmd_read(SPI0,cmd, 4, buf, len));\r
\r
- spi_release();\r
+ spi_release(SPI0);\r
return (ret_val);\r
}\r
#endif\r
uint8_t cmd[4];\r
\r
/* Claim the SPI controller */\r
- spi_claim(SPI_NOR_CS, SPI_MAX_FREQ);\r
+ spi_claim(SPI0,SPI_NOR_CS, SPI_MAX_FREQ);\r
\r
/* Validate address input */\r
if(addr + len > SPI_NOR_MAX_FLASH_SIZE) \r
{\r
platform_errno = PLATFORM_ERRNO_NOFREEBLOCKS;\r
- spi_release();\r
+ spi_release(SPI0);\r
return NOR_EFAIL;\r
}\r
\r
for (actual = 0; actual < len; actual += chunk_len) \r
{\r
/* Send Write Enable command */\r
- ret = spi_cmd(SPI_NOR_CMD_WREN, NULL, 0);\r
+ ret = spi_cmd(SPI0,SPI_NOR_CMD_WREN, NULL, 0);\r
if (ret) \r
{\r
platform_errno = PLATFORM_ERRNO_DEV_FAIL;\r
- spi_release();\r
+ spi_release(SPI0);\r
return NOR_EFAIL;\r
}\r
\r
cmd[2] = (uint8_t)(addr>>8);\r
cmd[3] = (uint8_t)addr;\r
\r
- ret = spi_cmd_write(cmd, 4, buf + actual, chunk_len);\r
+ ret = spi_cmd_write(SPI0,cmd, 4, buf + actual, chunk_len);\r
if (ret) \r
{\r
platform_errno = PLATFORM_ERRNO_DEV_FAIL;\r
- spi_release(); \r
+ spi_release(SPI0);\r
return NOR_EFAIL;\r
}\r
\r
if (ret) \r
{\r
platform_errno = PLATFORM_ERRNO_DEV_TIMEOUT;\r
- spi_release();\r
+ spi_release(SPI0);\r
return NOR_EFAIL;\r
}\r
\r
\r
}\r
\r
- spi_release(); \r
+ spi_release(SPI0);\r
return ((NOR_STATUS) ret);\r
}\r
#endif\r
uint32_t address;\r
\r
/* Claim the SPI controller */\r
- spi_claim(SPI_NOR_CS, SPI_MAX_FREQ);\r
+ spi_claim(SPI0,SPI_NOR_CS, SPI_MAX_FREQ);\r
\r
/*\r
* This function currently uses sector erase only.\r
}\r
\r
/* Send Write Enable command */\r
- ret = spi_cmd(SPI_NOR_CMD_WREN, NULL, 0);\r
+ ret = spi_cmd(SPI0,SPI_NOR_CMD_WREN, NULL, 0);\r
if (ret) \r
{\r
platform_errno = PLATFORM_ERRNO_DEV_FAIL;\r
- spi_release();\r
+ spi_release(SPI0);\r
return NOR_EFAIL;\r
}\r
\r
- ret = spi_cmd_write(cmd, cmd_len, NULL, 0);\r
+ ret = spi_cmd_write(SPI0,cmd, cmd_len, NULL, 0);\r
if (ret) \r
{\r
platform_errno = PLATFORM_ERRNO_DEV_FAIL;\r
- spi_release();\r
+ spi_release(SPI0);\r
return NOR_EFAIL;\r
}\r
\r
if (ret) \r
{\r
platform_errno = PLATFORM_ERRNO_DEV_TIMEOUT;\r
- spi_release();\r
+ spi_release(SPI0);\r
return NOR_EFAIL;\r
}\r
- spi_release();\r
+ spi_release(SPI0);\r
return ret;\r
}\r
#endif\r
index a52388a2963c187b4290a61a6b505a2a644031c7..7a711e1d6173c6d739faa52162b55f1e6e4c6049 100755 (executable)
******************************************************************************/\r
/* Chip Level definitions include */\r
#include "platform_internal.h"\r
-\r
+#if 0\r
unsigned int pa_serdes_cfg_base = 0x0232A000;\r
#define PASS_CFG_BASE 0x02000000\r
#define SGMII0_OFFSET 0x00090100\r
\r
return 0;\r
}\r
-//#define SERDES_INTERNAL_LOOPBACK\r
+#endif\r
+#define NUM_MAC_PORTS 2\r
void CSL_SgmiiDefSerdesSetup()\r
{\r
- unsigned int old_val;\r
- volatile unsigned int i;\r
-\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x000));\r
- (*mkptr(pa_serdes_cfg_base, 0x000)) = ((old_val & 0x0000FFFF)| 0x00800000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x014));\r
- (*mkptr(pa_serdes_cfg_base, 0x014)) = ((old_val & 0xFFFF0000)| 0x00008282);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x060));\r
- (*mkptr(pa_serdes_cfg_base, 0x060)) = ((old_val & 0xFF000000)| 0x00142438);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x064));\r
- (*mkptr(pa_serdes_cfg_base, 0x064)) = ((old_val & 0xFF0000FF)| 0x00C3C700);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x078));\r
- (*mkptr(pa_serdes_cfg_base, 0x078)) = ((old_val & 0xFFFF00FF)| 0x0000C000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x204));\r
- (*mkptr(pa_serdes_cfg_base, 0x204)) = ((old_val & 0x00FFFF00)| 0x38000080);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x208));\r
- (*mkptr(pa_serdes_cfg_base, 0x208)) = ((old_val & 0xFFFFFF00)| 0x00000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x20C));\r
- (*mkptr(pa_serdes_cfg_base, 0x20C)) = ((old_val & 0x00FFFFFF)| 0x02000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x210));\r
- (*mkptr(pa_serdes_cfg_base, 0x210)) = ((old_val & 0x00FFFFFF)| 0x1B000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x214));\r
- (*mkptr(pa_serdes_cfg_base, 0x214)) = ((old_val & 0xFFFF0000)| 0x00006FB8);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x218));\r
- (*mkptr(pa_serdes_cfg_base, 0x218)) = ((old_val & 0x0000FF00)| 0x758000E4);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x2AC));\r
- (*mkptr(pa_serdes_cfg_base, 0x2AC)) = ((old_val & 0xFFFF00FF)| 0x00004400);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x22C));\r
- (*mkptr(pa_serdes_cfg_base, 0x22C)) = ((old_val & 0xFF0000FF)| 0x00100800);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x280));\r
- (*mkptr(pa_serdes_cfg_base, 0x280)) = ((old_val & 0xFF00FF00)| 0x00820082);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x284));\r
- (*mkptr(pa_serdes_cfg_base, 0x284)) = ((old_val & 0x00000000)| 0x1D0F0385);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x404));\r
- (*mkptr(pa_serdes_cfg_base, 0x404)) = ((old_val & 0x00FFFF00)| 0x38000080);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x408));\r
- (*mkptr(pa_serdes_cfg_base, 0x408)) = ((old_val & 0xFFFFFF00)| 0x00000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x40C));\r
- (*mkptr(pa_serdes_cfg_base, 0x40C)) = ((old_val & 0x00FFFFFF)| 0x02000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x410));\r
- (*mkptr(pa_serdes_cfg_base, 0x410)) = ((old_val & 0x00FFFFFF)| 0x1B000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x414));\r
- (*mkptr(pa_serdes_cfg_base, 0x414)) = ((old_val & 0xFFFF0000)| 0x00006FB8);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x418));\r
- (*mkptr(pa_serdes_cfg_base, 0x418)) = ((old_val & 0x0000FF00)| 0x758000E4);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x4AC));\r
- (*mkptr(pa_serdes_cfg_base, 0x4AC)) = ((old_val & 0xFFFF00FF)| 0x00004400);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x42C));\r
- (*mkptr(pa_serdes_cfg_base, 0x42C)) = ((old_val & 0xFF0000FF)| 0x00100800);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x480));\r
- (*mkptr(pa_serdes_cfg_base, 0x480)) = ((old_val & 0xFF00FF00)| 0x00820082);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x484));\r
- (*mkptr(pa_serdes_cfg_base, 0x484)) = ((old_val & 0x00000000)| 0x1D0F0385);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x604));\r
- (*mkptr(pa_serdes_cfg_base, 0x604)) = ((old_val & 0x00FFFF00)| 0x38000080);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x608));\r
- (*mkptr(pa_serdes_cfg_base, 0x608)) = ((old_val & 0xFFFFFF00)| 0x00000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x60C));\r
- (*mkptr(pa_serdes_cfg_base, 0x60C)) = ((old_val & 0x00FFFFFF)| 0x02000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x610));\r
- (*mkptr(pa_serdes_cfg_base, 0x610)) = ((old_val & 0x00FFFFFF)| 0x1B000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x614));\r
- (*mkptr(pa_serdes_cfg_base, 0x614)) = ((old_val & 0xFFFF0000)| 0x00006FB8);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x618));\r
- (*mkptr(pa_serdes_cfg_base, 0x618)) = ((old_val & 0x0000FF00)| 0x758000E4);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x6AC));\r
- (*mkptr(pa_serdes_cfg_base, 0x6AC)) = ((old_val & 0xFFFF00FF)| 0x00004400);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x62C));\r
- (*mkptr(pa_serdes_cfg_base, 0x62C)) = ((old_val & 0xFF0000FF)| 0x00100800);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x680));\r
- (*mkptr(pa_serdes_cfg_base, 0x680)) = ((old_val & 0xFF00FF00)| 0x00820082);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x684));\r
- (*mkptr(pa_serdes_cfg_base, 0x684)) = ((old_val & 0x00000000)| 0x1D0F0385);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x804));\r
- (*mkptr(pa_serdes_cfg_base, 0x804)) = ((old_val & 0x00FFFF00)| 0x38000080);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x808));\r
- (*mkptr(pa_serdes_cfg_base, 0x808)) = ((old_val & 0xFFFFFF00)| 0x00000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x80C));\r
- (*mkptr(pa_serdes_cfg_base, 0x80C)) = ((old_val & 0x00FFFFFF)| 0x02000000);\r
+ uint32_t i;\r
+ CSL_SERDES_RESULT csl_retval;\r
+ CSL_SERDES_LANE_ENABLE_STATUS lane_retval = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+ CSL_SERDES_STATUS pllstat;\r
+ uint32_t serdes_mux_ethernet_sel;\r
+ int numPort1 = (NUM_MAC_PORTS > 2)?2:NUM_MAC_PORTS;\r
+ int numPort2 = (NUM_MAC_PORTS > 2)?NUM_MAC_PORTS - 2:0;\r
\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x810));\r
- (*mkptr(pa_serdes_cfg_base, 0x810)) = ((old_val & 0x00FFFFFF)| 0x1B000000);\r
\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x814));\r
- (*mkptr(pa_serdes_cfg_base, 0x814)) = ((old_val & 0xFFFF0000)| 0x00006FB8);\r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (CSL_FEXTR(*(volatile uint32_t *)(CSL_BOOT_CFG_REGS + 0x20), 28, 28) == 0)\r
+ serdes_mux_ethernet_sel = 1;\r
\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x818));\r
- (*mkptr(pa_serdes_cfg_base, 0x818)) = ((old_val & 0x0000FF00)| 0x758000E4);\r
+ /* SB CMU and COMLANE and Lane Setup */\r
+ csl_retval = CSL_EthernetSerdesInit(CSL_CSISC2_2_SERDES_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 0 and Lane 1 */\r
\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x8AC));\r
- (*mkptr(pa_serdes_cfg_base, 0x8AC)) = ((old_val & 0xFFFF00FF)| 0x00004400);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x82C));\r
- (*mkptr(pa_serdes_cfg_base, 0x82C)) = ((old_val & 0xFF0000FF)| 0x00100800);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x880));\r
- (*mkptr(pa_serdes_cfg_base, 0x880)) = ((old_val & 0xFF00FF00)| 0x00820082);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x884));\r
- (*mkptr(pa_serdes_cfg_base, 0x884)) = ((old_val & 0x00000000)| 0x1D0F0385);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa00));\r
- (*mkptr(pa_serdes_cfg_base, 0xa00)) = ((old_val & 0xFFFF00FF)| 0x00000800);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa08));\r
- (*mkptr(pa_serdes_cfg_base, 0xa08)) = ((old_val & 0x0000FFFF)| 0X38A20000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa30));\r
- (*mkptr(pa_serdes_cfg_base, 0xa30)) = ((old_val & 0xFF0000FF)| 0x008A8A00);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa84));\r
- (*mkptr(pa_serdes_cfg_base, 0xa84)) = ((old_val & 0xFFFF00FF)| 0x00000600);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa94));\r
- (*mkptr(pa_serdes_cfg_base, 0xa94)) = ((old_val & 0x00FFFFFF)| 0x10000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xaa0));\r
- (*mkptr(pa_serdes_cfg_base, 0xaa0)) = ((old_val & 0x00FFFFFF)| 0x81000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xabc));\r
- (*mkptr(pa_serdes_cfg_base, 0xabc)) = ((old_val & 0x00FFFFFF)| 0xFF000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xac0));\r
- (*mkptr(pa_serdes_cfg_base, 0xabc)) = ((old_val & 0xFFFFFF00)| 0x0000008B);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xb08));\r
- (*mkptr(pa_serdes_cfg_base, 0xb08)) = ((old_val & 0x0000FFFF)| 0x583F0000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xb0c));\r
- (*mkptr(pa_serdes_cfg_base, 0xb0c)) = ((old_val & 0xFFFFFF00)| 0x0000004e);\r
-\r
- #ifdef SERDES_INTERNAL_LOOPBACK\r
- /*Beginning of SERDES LOOPBACK Configuration*/\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x200));\r
- (*mkptr(pa_serdes_cfg_base, 0x200)) = ((old_val & 0x00FFFFFF)| 0x40000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x400));\r
- (*mkptr(pa_serdes_cfg_base, 0x400)) = ((old_val & 0x00FFFFFF)| 0x40000000);\r
-\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x600));\r
- (*mkptr(pa_serdes_cfg_base, 0x600)) = ((old_val & 0x00FFFFFF)| 0x40000000);\r
+ if (serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ csl_retval |= CSL_EthernetSerdesInit(CSL_CSISC2_3_SERDES_CFG_REGS,\r
+ CSL_SERDES_REF_CLOCK_156p25M,\r
+ CSL_SERDES_LINK_RATE_1p25G); /* SGMII Lane 2 and Lane 3 */\r
+ }\r
\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x800));\r
- (*mkptr(pa_serdes_cfg_base, 0x800)) = ((old_val & 0x00FFFFFF)| 0x40000000);\r
- /*End of Serdes loopback configuration*/\r
- #endif\r
+ if (csl_retval != 0)\r
+ {\r
+ //System_printf ("Invalid Serdes Init Params\n");\r
+ }\r
\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0x000));\r
- (*mkptr(pa_serdes_cfg_base, 0x000)) = ((old_val & 0xFFFFFF00)| 0x00000003);\r
+ //SB Lane Enable\r
+ for(i=0; i < numPort1; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_2_SERDES_CFG_REGS,\r
+ i,\r
+ CSL_SERDES_LOOPBACK_DISABLED,\r
+ CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 0 and Lane 1 */\r
+ }\r
\r
- old_val = (*mkptr(pa_serdes_cfg_base, 0xa00));\r
- (*mkptr(pa_serdes_cfg_base, 0xa00)) = ((old_val & 0xFFFFFF00)| 0x0000005F);\r
+ if (serdes_mux_ethernet_sel && numPort2)\r
+ {\r
+ for(i=0; i < numPort1; i++)\r
+ {\r
+ lane_retval |= CSL_EthernetSerdesLaneEnable(CSL_CSISC2_3_SERDES_CFG_REGS,\r
+ i,\r
+ CSL_SERDES_LOOPBACK_DISABLED,\r
+ CSL_SERDES_LANE_QUARTER_RATE); /* SGMII Lane 2 and Lane 3 */\r
+ }\r
+ }\r
\r
+ if (lane_retval != 0)\r
+ {\r
+ //System_printf ("Invalid Serdes Lane Rate\n");\r
+ }\r
\r
- /*Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */\r
- *mkptr(pa_serdes_cfg_base, 0x1fe0) = 0xF800F8C0;\r
- *mkptr(pa_serdes_cfg_base, 0x1fe4) = 0xF800F8C0;\r
- *mkptr(pa_serdes_cfg_base, 0x1fe8) = 0xF800F8C0;\r
- *mkptr(pa_serdes_cfg_base, 0x1fec) = 0xF800F8C0;\r
+ /* SB PLL Enable */\r
+ CSL_EthernetSerdesPllEnable(CSL_CSISC2_2_SERDES_CFG_REGS); /* SGMII Lane 0 and Lane 1 */\r
\r
- /*Enable pll via the pll_ctrl 0x0014*/\r
- *mkptr(pa_serdes_cfg_base, 0x1ff4) = 0xe0000000;\r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (serdes_mux_ethernet_sel)\r
+ CSL_EthernetSerdesPllEnable(CSL_CSISC2_3_SERDES_CFG_REGS); /* SGMII Lane 2 and Lane 3 */\r
\r
- /*Waiting for SGMII Serdes PLL lock.*/\r
- reg_poll_to(32, SGMII0_STATUS, 0x10, 0x10, 10000);\r
- reg_poll_to(32, SGMII1_STATUS, 0x10, 0x10, 10000);\r
- reg_poll_to(32, SGMII2_STATUS, 0x10, 0x10, 10000);\r
- reg_poll_to(32, SGMII3_STATUS, 0x10, 0x10, 10000);\r
+ /* SB PLL Status Poll */\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetStatus(CSL_CSISC2_2_SERDES_CFG_REGS, numPort1); /* SGMII Lane 0 and Lane 1 */\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
\r
+ /* Check CSISC2_3_MUXSEL bit */\r
+ if (serdes_mux_ethernet_sel)\r
+ {\r
+ do\r
+ {\r
+ pllstat = CSL_EthernetSerdesGetMuxStatus(CSL_CSISC2_3_SERDES_CFG_REGS, numPort2); /* SGMII Lane 2 and Lane 3 */\r
+ }while(pllstat == CSL_SERDES_STATUS_PLL_NOT_LOCKED);\r
+ }\r
\r
- for(i = 0; i < 5000; i++);\r
- for(i = 0; i < 40000; i++);\r
}\r
\r
\r
*/\r
CSL_SGMII_startRxTxSoftReset (macPortNum);\r
CSL_SGMII_disableMasterMode (macPortNum);\r
- CSL_SGMII_enableAutoNegotiation (macPortNum);\r
- CSL_SGMII_endRxTxSoftReset (macPortNum);\r
+\r
\r
/* Setup the Advertised Ability register for this port:\r
* (1) Enable Full duplex mode\r
sgmiiCfg.duplexMode = CSL_SGMII_FULL_DUPLEX;\r
CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);\r
\r
+ CSL_SGMII_enableAutoNegotiation (macPortNum);\r
+ CSL_SGMII_endRxTxSoftReset (macPortNum);\r
do\r
{\r
CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
*/\r
CSL_SGMII_startRxTxSoftReset (macPortNum);\r
CSL_SGMII_disableMasterMode (macPortNum);\r
- CSL_SGMII_enableAutoNegotiation (macPortNum);\r
- CSL_SGMII_endRxTxSoftReset (macPortNum);\r
\r
/* Setup the Advertised Ability register for this port:\r
* (1) Enable Full duplex mode\r
sgmiiCfg.bLinkUp = 1;\r
CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);\r
\r
+ CSL_SGMII_enableAutoNegotiation (macPortNum);\r
+ CSL_SGMII_endRxTxSoftReset (macPortNum);\r
+\r
do\r
{\r
CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);\r
*\r
* Description: This function claims the SPI bus in the SPI controller\r
*\r
- * Parameters: Uint32 cs - Chip Select number for the slave SPI device\r
+ * Parameters: uint8_t spiportnumber - spi port number\r
+ * Uint32 cs - Chip Select number for the slave SPI device\r
* Uint32 freq - SPI clock frequency\r
*\r
* Return Value: error status\r
SPI_STATUS\r
spi_claim\r
(\r
+ uint8_t spiportnumber,\r
uint32_t cs,\r
uint32_t freq\r
+\r
)\r
{\r
uint32_t scalar;\r
}else if ( cs == 1) {\r
SPI_SPIFMT0 = (16 << CSL_SPI_SPIFMT_CHARLEN_SHIFT) |\r
(scalar << CSL_SPI_SPIFMT_PRESCALE_SHIFT) |\r
- (CSL_SPI_SPIFMT_PHASE_NO_DELAY << CSL_SPI_SPIFMT_PHASE_SHIFT) |\r
+ (CSL_SPI_SPIFMT_PHASE_DELAY << CSL_SPI_SPIFMT_PHASE_SHIFT) |\r
(CSL_SPI_SPIFMT_POLARITY_LOW << CSL_SPI_SPIFMT_POLARITY_SHIFT) |\r
(CSL_SPI_SPIFMT_SHIFTDIR_MSB << CSL_SPI_SPIFMT_SHIFTDIR_SHIFT);\r
}\r
/* enable SPI */\r
SPI_SPIGCR1 |= ( CSL_SPI_SPIGCR1_ENABLE_ENABLE << CSL_SPI_SPIGCR1_ENABLE_SHIFT );\r
\r
- if (cs == 1) {\r
- SPI_SPIDAT0 = 1 << 15;\r
- spi_delay (10000);\r
- /* Read SPIFLG, wait untill the RX full interrupt */\r
- if ( (SPI_SPIFLG & (CSL_SPI_SPIFLG_RXINTFLG_FULL<<CSL_SPI_SPIFLG_RXINTFLG_SHIFT)) ) {\r
- /* Read one byte data */\r
- scalar = SPI_SPIBUF & 0xFF;\r
- /* Clear the Data */\r
- SPI_SPIBUF = 0;\r
- }\r
- else {\r
- /* Read one byte data */\r
- scalar = SPI_SPIBUF & 0xFF;\r
- return SPI_EFAIL;\r
- }\r
- }\r
return SPI_EOK;\r
}\r
\r
*\r
* Description: This function releases the bus in SPI controller\r
*\r
- * Parameters: None\r
+ * Parameters: uint8_t spiportnumber - spi port number\r
*\r
* Return Value: None\r
*\r
void\r
spi_release\r
(\r
- void\r
+ uint8_t spiportnumber\r
)\r
{\r
/* Disable the SPI hardware */\r
*\r
* Description: This function sends and receives 8-bit data serially\r
*\r
- * Parameters: uint32_t nbytes - Number of bytes of the TX data\r
+ * Parameters: uint8_t spiportnumber - spi port number\r
+ * uint32_t nbytes - Number of bytes of the TX data\r
* uint8_t* data_out - Pointer to the TX data\r
* uint8_t* data_in - Pointer to the RX data\r
* Bool terminate - TRUE: terminate the transfer, release the CS\r
SPI_STATUS\r
spi_xfer\r
(\r
+ uint8_t spiportnumber,\r
uint32_t nbytes,\r
uint8_t* data_out,\r
uint8_t* data_in,\r
Bool terminate\r
+\r
)\r
{\r
uint32_t i, buf_reg;\r
*\r
* Description: This function sends a single byte command and receives response data\r
*\r
- * Parameters: uint8_t cmd - Command sent to the NOR flash\r
+ * Parameters: uint8_t spiportnumber - spi port number\r
+ * uint8_t cmd - Command sent to the NOR flash\r
* uint8_t* response - Pointer to the RX response data\r
* uint32_t len - Lenght of the response in bytes\r
*\r
SPI_STATUS\r
spi_cmd\r
(\r
+ uint8_t spiportnumber,\r
uint8_t cmd,\r
uint8_t* response,\r
uint32_t len\r
+\r
)\r
{\r
Bool flags = FALSE;\r
}\r
\r
/* Send the command byte */\r
- ret = spi_xfer(1, &cmd, NULL, flags);\r
+ ret = spi_xfer(spiportnumber,1, &cmd, NULL, flags);\r
if (ret)\r
{\r
IFPRINT (platform_write("SF: Failed to send command %02x: %d\n", cmd, ret));\r
/* Receive the response */\r
if (len)\r
{\r
- ret = spi_xfer(len, NULL, response, TRUE);\r
+ ret = spi_xfer(spiportnumber,len, NULL, response, TRUE);\r
if (ret)\r
{\r
IFPRINT (platform_write("SF: Failed to read response (%zu bytes): %d\n", len, ret));\r
*\r
* Description: This function sends a read command and reads data from the flash\r
*\r
- * Parameters: uint8_t cmd - Command sent to the NOR flash\r
+ * Parameters: uint8_t spiportnumber - spi port number\r
+ * uint8_t cmd - Command sent to the NOR flash\r
* uint32_t cmd_len - Length of the command in bytes\r
* uint8_t* dat - Pointer to the data read\r
* uint32_t data_len - Lenght of the data read in bytes\r
SPI_STATUS\r
spi_cmd_read\r
(\r
- uint8_t* cmd,\r
+ uint8_t spiportnumber,\r
+ uint8_t* cmd,\r
uint32_t cmd_len,\r
uint8_t* data,\r
uint32_t data_len\r
+\r
)\r
{\r
Bool flags = FALSE;\r
}\r
\r
/* Send read command */\r
- ret = spi_xfer(cmd_len, cmd, NULL, flags);\r
+ ret = spi_xfer(spiportnumber,cmd_len, cmd, NULL, flags);\r
if (ret)\r
{\r
IFPRINT (platform_write("SF: Failed to send read command (%zu bytes): %d\n",\r
else if (data_len != 0)\r
{\r
/* Read data */\r
- ret = spi_xfer(data_len, NULL, data, TRUE);\r
+ ret = spi_xfer(spiportnumber,data_len, NULL, data, TRUE);\r
if (ret)\r
{\r
IFPRINT (platform_write("SF: Failed to read %zu bytes of data: %d\n",\r
*\r
* Description: This function sends a write command and writes data to the flash\r
*\r
- * Parameters: uint8_t cmd - Command sent to the NOR flash\r
+ * Parameters: uint8_t spiportnumber - spi port number\r
+ * uint8_t cmd - Command sent to the NOR flash\r
* uint32_t cmd_len - Length of the command in bytes\r
* uint8_t* dat - Pointer to the data to be written\r
* uint32_t data_len - Lenght of the data in bytes\r
SPI_STATUS\r
spi_cmd_write\r
(\r
- uint8_t* cmd,\r
+ uint8_t spiportnumber,\r
+ uint8_t* cmd,\r
uint32_t cmd_len,\r
uint8_t* data,\r
uint32_t data_len\r
+\r
)\r
{\r
Bool flags = FALSE;\r
}\r
\r
/* Send write command */\r
- ret = spi_xfer(cmd_len, cmd, NULL, flags);\r
+ ret = spi_xfer(spiportnumber,cmd_len, cmd, NULL, flags);\r
if (ret)\r
{\r
IFPRINT (platform_write("SF: Failed to send write command (%zu bytes): %d\n",\r
else if (data_len != 0)\r
{\r
/* Write data */\r
- ret = spi_xfer(data_len, data, NULL, TRUE);\r
+ ret = spi_xfer(spiportnumber,data_len, data, NULL, TRUE);\r
if (ret)\r
{\r
IFPRINT (platform_write("SF: Failed to write %zu bytes of data: %d\n",\r
*\r
* Description: This function sends a read command and reads data in 16-bit data format\r
*\r
- * Parameters: uint16_t* cmd_buf - Pointer to the command sent\r
+ * Parameters: uint8_t spiportnumber - spi port number\r
+ * uint16_t* cmd_buf - Pointer to the command sent\r
* uint32_t cmd_len - Length of the command in words\r
* uint16_t* data_buf - Pointer to the data read\r
* uint32_t data_len - Lenght of the data read in words\r
SPI_STATUS\r
spi_read_word\r
(\r
- uint16_t* cmd_buf,\r
+ uint8_t spiportnumber,\r
+ uint16_t* cmd_buf,\r
uint32_t cmd_len,\r
uint16_t* data_buf,\r
uint32_t data_len\r
+\r
)\r
{\r
uint32_t data1_reg;\r
*\r
* Description: This function sends a write command and writes data in 16-bit data format\r
*\r
- * Parameters: uint16_t* cmd_buf - Pointer to the command sent\r
+ * Parameters: uint8_t spiportnumber - spi port number\r
+ * uint16_t* cmd_buf - Pointer to the command sent\r
* uint32_t cmd_len - Length of the command in bytes\r
* uint16_t* data_buf - Pointer to the data read\r
* uint32_t data_len - Lenght of the data read in bytes\r
SPI_STATUS\r
spi_write_word\r
(\r
- uint16_t* cmd_buf,\r
+ uint8_t spiportnumber,\r
+ uint16_t* cmd_buf,\r
uint32_t cmd_len,\r
uint16_t* data_buf,\r
uint32_t data_len\r
+\r
)\r
{\r
uint32_t data1_reg;\r
index 39443ac65ff0de55c83c23769112ec95986ba7a8..b082417a9a7dc1b3f9c0a9c475df6341eeeae67e 100755 (executable)
*****************************************************************************/\r
#include "platform_internal.h"\r
\r
+//#define SODIMM_CONFIG\r
+\r
/* Errno value */\r
uint32_t platform_errno = 0;\r
uint32_t platform_init_return_code = 0;\r
platform_errno = 0;\r
#endif\r
\r
+ PowerUpDomains();\r
/* PLLC module handle structure */\r
if (p_flags->pll)\r
{\r
}\r
#endif\r
\r
- PowerUpDomains();\r
\r
/* Enable Error Correction for memory */\r
if (p_flags->ecc) {\r
@@ -754,10 +756,12 @@ Platform_STATUS platform_led(uint32_t led_id, PLATFORM_LED_OP operation, LED_CLA
\r
switch (led_class) {\r
case PLATFORM_USER_LED_CLASS:\r
- if (operation == BMC_LED_OFF)\r
- gpioClearOutput(led_gpio(led_id)); /* Turn off LED */\r
+ if (operation == FPGA_LED_OFF)\r
+ //gpioClearOutput(led_gpio(led_id)); /* Turn off LED */\r
+ fpgaControlUserLEDs((FPGA_UserLed)(led_id),(FPGA_LedStatus) operation);\r
else\r
- gpioSetOutput(led_gpio(led_id)); /* Turn on LED */\r
+ //gpioSetOutput(led_gpio(led_id)); /* Turn on LED */\r
+ fpgaControlUserLEDs((FPGA_UserLed)(led_id),(FPGA_LedStatus) operation);\r
break;\r
case PLATFORM_SYSTEM_LED_CLASS:\r
return ( (Platform_STATUS) Platform_EUNSUPPORTED);\r
index 427667fbac8f74adc2e0b1830301607fa15211c7..0ed37c43136bb942c4360b1d02660142a9fab0f0 100755 (executable)
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<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
<listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
- <listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.1.0.01"/>
+ <listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.5.0"/>\r
<listOptionValue builtIn="false" value="LINKER_COMMAND_FILE=platform_utils.cmd"/>
<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
<listOptionValue builtIn="false" value="PROJECT_KIND=com.ti.ccstudio.managedbuild.core.ProjectKind_Executable"/>
<listOptionValue builtIn="false" value=""${PROJECT_ROOT}/../../../..""/>
<listOptionValue builtIn="false" value=""${PROJECT_ROOT}/../..""/>
</option>
- <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE.1481853604" name="Mode" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE" value="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE.manual" valueType="enumerated"/>
+ <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE.1481853604" name="Mode" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE" value="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.PREPROC_MODE.automatic" valueType="enumerated"/>\r
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<listOptionValue builtIn="false" value="DEVICE_K2L"/>
</option>
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<listOptionValue builtIn="false" value=""${PROJECT_ROOT}/../../../csl/lib/k2h/c66""/>
</option>
+ <option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.XML_LINK_INFO.1750054766" name="Detailed link information data-base into <file> (--xml_link_info, -xml_link_info)" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.linkerID.XML_LINK_INFO" value=""platform_test_evmk2l_linkInfo.xml"" valueType="string"/>\r
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<inputType id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__GEN_CMDS.1781659870" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exeLinker.inputType__GEN_CMDS"/>
index d2cdcc38a6e25bd6e110f7ff928c9a380059df0e..a98665ef16ac98ca0d033a532de6d386dfbdf1fe 100755 (executable)
*/
-c
--heap 0x41000
+-heap 0x71000
-stack 0xa000
/* Memory Map 1 - the default */
diff --git a/resource_mgr.h b/resource_mgr.h
index 09a558374a22561772532a609f7b0297ec76d17a..898f09b44cb72890d82aea9d56b7aa5619fc4a27 100644 (file)
--- a/resource_mgr.h
+++ b/resource_mgr.h
*/
/*@{*/
-
+#ifndef NSS_GEN2
/**
* @brief Number of PA Tx queues available
*/
* @brief Number of PA Rx queues available
*/
#define NUM_PA_RX_CHANNELS 24
+#else
+
+/** Number of PA Tx queues available */
+#define NUM_PA_TX_QUEUES 21
+/** Number of PA Rx channels available */
+#define NUM_PA_RX_CHANNELS 91
+
+#define TF_PA_Q_CONFIG_BASE 8
+#endif
/**
* @brief Maximum number of L2 handles
*/