1 /*
2 * file otp_pvt.h
3 *
4 * Private API and data structures for OTP driver.
5 *
6 * ============================================================================
7 * (C) Copyright 2012, Texas Instruments, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * \par
38 */
40 #ifndef OTP_PVT_H_
41 #define OTP_PVT_H_
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
47 #include "otp.h"
49 /* EFUSE defines */
50 #define EFUSE_JTAG_BLOCK ((Uint16) 0)
51 #define EFUSE_JTAG_ROW ((Uint16) 0xA)
52 #define EFUSE_JTAG_SIZE_32BIT_WORDS ((Uint16) 1)
53 #define EFUSE_PUBLIC_PRIVATE_ENABLE_BLOCK ((Uint16) 0)
54 #define EFUSE_PUBLIC_PRIVATE_ENABLE_ROW ((Uint16) 0x9)
55 #define EFUSE_PUBLIC_PRIVATE_ENABLE_SIZE_32BIT_WORDS ((Uint16) 1)
56 #define EFUSE_SMEK_BLOCK ((Uint16) 0)
57 #define EFUSE_SMEK_ROW ((Uint16) 0x15)
58 #define EFUSE_SMPK_BLOCK ((Uint16) 0)
59 #define EFUSE_SMPK_ROW ((Uint16) 0x1F)
60 /* FuseROM 0 contains the first 17.5 OTP keys: Key Mgr 0, Key 0 - Key Mgr 1, Key 0
61 * Half of Key Mgr 1, Key 1 is contained in FuseROM 0 and the other half in FurseROM 1
62 * FuseROM 1 contains the last 14.5 keys: Key Mgr 1, Key 2 - Key Mgr 1, Key 15 */
63 #define EFUSE_OTP_1_BLOCK ((Uint16) 0)
64 #define EFUSE_OTP_1_BASE_ROW ((Uint16) 0x65) /* Key Mgr 0, Key 0 - half of
65 * Key Mgr 1, Key 1 */
66 #define EFUSE_OTP_2_BLOCK ((Uint16) 1)
67 #define EFUSE_OTP_2_BASE_ROW ((Uint16) 0x3E) /* half of Key Mgr 1, Key 1 -
68 * Key Mgr 1, Key 15 */
69 #define EFUSE_OTP_SIZE_32BIT_WORDS ((Uint16) 4) /* 4 key words */
71 /* EFUSE JTAG defines */
72 #define EFUSE_JTAG_OPEN ((Uint32) 0x00000000)
73 #define EFUSE_JTAG_PROTECTED ((Uint32) 0x00000001)
74 #define EFUSE_JTAG_DISABLED ((Uint32) 0x00000003)
76 /* eFuse controller instructions */
77 #define EFUSE_INSTRUCTION_NOOP ((Uint32) 0x00000000)
78 #define EFUSE_INSTRUCTION_READ ((Uint32) 0x04000000)
79 #define EFUSE_INSTRUCTION_PROGRAM ((Uint32) 0x07000000)
81 /* eFuse Address register block defines */
82 #define EFUSE_ADDRESS_FUSEROM_BLOCK_0 ((Uint32) 0x00000000)
83 #define EFUSE_ADDRESS_FUSEROM_BLOCK_1 ((Uint32) 0x00000800)
85 /* eFuse key code */
86 #define EFUSE_KEY_CODE ((Uint32) 0x96969696)
88 /* eFuse data register upper defines */
89 #define EFUSE_DATA_UPPER_NO_REP_NO_PROT ((Uint32) 0x00000000)
90 #define EFUSE_DATA_UPPER_NO_REP_WR_PROT ((Uint32) 0x00000001)
91 #define EFUSE_DATA_UPPER_NO_REP_WR_RD_PROT ((Uint32) 0x00000002)
92 #define EFUSE_DATA_UPPER_ROW_REP ((Uint32) 0x00000003)
94 /* eFuse read register defines */
95 #define EFUSE_READ_READ_DATA_BIT ((Uint32) 0x00000004)
96 #define EFUSE_CLOCK_READ_PULSE_WIDTH ((Uint32) 0x000000E0) /* Currently set to 14*sys_clk_period */
98 /* eFuse program register defines */
99 /* Current program write configuration sets:
100 * Bits 10:0 - 113 (0x71) for the strobe pulse width
101 * Bits 14:11 - write iterations is cleared, will be OR'd in from write API parameter
102 * Bit 15 - program signal
103 * Bits 31:17 - 64 clock pulse stall width */
104 #define EFUSE_PROGRAM_WRITE_CONFIG ((Uint32) 0x00808071)
105 /* Current program read configuration sets:
106 * Bits 10:0 - 14 (0x0E) for the strobe pulse width
107 * Bits 14:11 - write iterations is cleared, will be OR'd in from write API parameter
108 * Bit 15 - program signal
109 * Bits 31:17 - 64 clock pulse stall width */
110 #define EFUSE_PROGRAM_READ_CONFIG ((Uint32) 0x0080800E)
111 #define EFUSE_PROGRAM_WR_ATTEMPT_SHIFT ((Uint16) 11)
113 /* eFuse error status register defines */
114 #define EFUSE_ERROR_STATUS_NUM_FUSE_CHAINS ((Uint16) 4)
115 #define EFUSE_ERROR_STATUS_MASK ((Uint32) 0x1F) /* all errors are 5 bits */
116 /* Macro for extracting each fuse chain's status on a write operation.
117 * There are 8 bits between fuse chain error status fields */
118 #define EFUSE_ERROR_STATUS_WRITE(errorStatus, fuseChain) ( \
119 (errorStatus >> (fuseChain * 8)) & EFUSE_ERROR_STATUS_MASK)
120 /* Macro for extracting each fuse chain's status on a read operation.
121 * There are 6 bits between fuse chain error status fields */
122 #define EFUSE_ERROR_STATUS_READ(errorStatus, fuseChain) ( \
123 (errorStatus >> (fuseChain * 6)) & EFUSE_ERROR_STATUS_MASK)
125 /* OTP Key Boundaries */
126 #define EFUSE_MAX_KEY_MGRS 2
127 #define EFUSE_MAX_KEYS_PER_MGR 16
129 #define EFUSE_OTP_KEY_CHECK(mgr, key) ((mgr >= EFUSE_MAX_KEY_MGRS) || \
130 (key >= EFUSE_MAX_KEYS_PER_MGR))
132 /* OTP control register overlay structure */
133 typedef struct {
134 Uint32 otpSysStatus_Instruction;
135 Uint32 otpInstructionDumpword;
136 Uint32 otpAddress;
137 Uint32 otpDataLower;
138 Uint32 otpSysConfig;
139 Uint32 otpDataUpper;
140 Uint32 otpAccumulator;
141 Uint32 otpBoundary;
142 Uint32 otpKeyFlag;
143 Uint32 otpKey;
144 Uint32 otpRelease;
145 Uint32 otpPins;
146 Uint32 otpCra;
147 Uint32 otpRead;
148 Uint32 otpProgram;
149 Uint32 otpErrorStatus;
150 } Otp_ControlOverlay;
152 Otp_Status Otp_write (Uint32 *data, Uint16 size, Uint16 fuseRomBlock,
153 Uint16 fuseRomRow, Otp_writeCfg *otpWrCfg);
155 #ifdef __cplusplus
156 }
157 #endif
159 #endif /* OTP_PVT_H_ */