2 --args 0x0
3 -heap 0x0
4 -stack 0x1000
6 MEMORY
7 {
8 L2SRAM (RWX) : org = 0x800000, len = 0x100000
9 MSMCSRAM (RWX) : org = 0xc000000, len = 0x200000
10 DDR3 : org = 0xa0000000, len = 0x20000000
11 }
13 SECTIONS
14 {
15 .text: load >> L2SRAM
16 .ti.decompress: load > L2SRAM
17 .stack: load > L2SRAM
18 GROUP: load > L2SRAM
19 {
20 .bss:
21 .neardata:
22 .rodata:
23 }
24 .cinit: load > L2SRAM
25 .pinit: load >> L2SRAM
26 .init_array: load > L2SRAM
27 .const: load >> L2SRAM
28 .data: load >> L2SRAM
29 .fardata: load >> L2SRAM
30 .switch: load >> L2SRAM
31 .sysmem: load > L2SRAM
32 .far: load >> L2SRAM
33 .args: load > L2SRAM align = 0x4, fill = 0 {_argsize = 0x0; }
34 .cio: load >> L2SRAM
35 .ti.handler_table: load > L2SRAM
36 .testtoc: load >> MSMCSRAM
37 }