1 /*
2 *
3 * Copyright (C) 2011-12 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
36 #ifndef __PHYREGS_H__
37 #define __PHYREGS_H__
39 /* Marvell Phy Registers */
40 #define PHY_PAGE0 0
41 #define PHY_PAGE1 1
42 #define PHY_PAGE2 2
43 #define PHY_PAGE3 3
44 #define PHY_PAGE4 4
45 #define PHY_PAGE5 5
46 #define PHY_PAGE6 6
47 #define PHY_PAGE7 7
48 #define PHY_PAGE8 8
49 #define PHY_PAGE9 9
50 #define PHY_PAGE12 12
51 #define PHY_PAGE14 14
52 #define PHY_PAGE16 16
54 /* Any Page or Page 0 for 1340*/
55 #define PHY_REG_CONTROL 0
56 #define PHY_REG_STATUS 1
57 #define PHY_REG_PHY_ID_1 2
58 #define PHY_REG_PHY_ID_2 3
59 #define PHY_REG_AUTO_AD 4
60 #define PHY_REG_PARTNER_AD 5
61 #define PHY_REG_AUTO_EXP 6
62 #define PHY_REG_NEXT_PAGE 7
63 #define PHY_REG_PARTNER_NEXT_PAGE 8
64 #define PHY_REG_1000_CONTROL 9
65 #define PHY_REG_1000_STATUS 10
66 #define PHY_REG_EXT_STATUS 15
67 #define PHY_REG_EXT_PHY_SPEC_CONTROL 20
68 #define PHY_REG_PAGE_ADDR 22
69 #define PHY_REG_PAGE_ADDR_2 29
70 #define PHY_REG_PAGE_ACCESS 30 /* Mult-functions access register, which page is on Reg 29 */
72 /* Page 0 */
73 #define PHY_REG_COPPER_CONTROL_1 16
74 #define PHY_REG_COPPER_STATUS_1 17
75 #define PHY_REG_COPPER_INT_ENABLE 18
76 #define PHY_REG_COPPER_STATUS_2 19
77 #define PHY_REG_COPPER_CONTROL_2 20
78 #define PHY_REG_COPPER_RX_ERROR_COUNTER 21
79 #define PHY_REG_GLOBAL_INT_STATUS 23
80 #define PHY_REG_COPPER_CONTROL_3 26
82 /* Page 1 */
83 #define PHY_REG_FIBER_CONTROL 0
84 #define PHY_REG_FIBER_STATUS 1
85 #define PHY_REG_FIBER_AUTO_AD 4
86 #define PHY_REG_FIBER_PARTNER_AD 5
87 #define PHY_REG_FIBER_AUTO_EXP 6
88 #define PHY_REG_FIBER_NEXT_PAGE 7
89 #define PHY_REG_FIBER_PARTNER_NEXT_PAGE 8
90 #define PHY_REG_FIBER_EXT_STATUS 15
92 #define PHY_REG_FIBER_CONTROL_1 16
93 #define PHY_REG_FIBER_STATUS_1 17
94 #define PHY_REG_FIBER_INT_ENABLE 18
95 #define PHY_REG_FIBER_STATUS_2 19
96 #define PHY_REG_FIBER_RX_ERROR_COUNTER 21
98 #define PHY_REG_FIBER_PRBS_CTRL 23
99 #define PHY_REG_FIBER_PRBS_ERR_COUNT_LSB 24
100 #define PHY_REG_FIBER_PRBS_ERR_COUNT_MSB 25
101 #define PHY_REG_FIBER_SPEC_CTRL_2 26
103 /* Page 2 */
104 #define PHY_REG_MAC_CONTROL_1 16
105 #define PHY_REG_MAC_STATUS_1 17
106 #define PHY_REG_MAC_INT_ENABLE 18
107 #define PHY_REG_MAC_STATUS_2 19
108 #define PHY_REG_NAC_RX_ER_BYTE_CAPT 20
109 #define PHY_REG_MAC_CONTROL 21
110 #define PHY_REG_MAC_CONTROL_2 26
111 #define PHY_REG_MAC_CO_SERDES_RX_ER_BYTE_CTRL_2 20
112 #define PHY_REG_MAC_CONTROL_2_1340 21
114 /* Page 3 */
115 #define PHY_REG_LED_FUNC_CTRL 16
116 #define PHY_REG_LED_POLAR_CTRL 17
117 #define PHY_REG_LED_TIMER_CTRL 18
118 #define PHY_REG_LED_FUNC_POLAR_CTRL 19
120 /* Page 4 */
121 #define PHY_REG_QSGMII_CONTROL 0
122 #define PHY_REG_QSGMII_STATUS 1
123 #define PHY_REG_QSGMII_AUTO_AD 4
124 #define PHY_REG_QSGMII_PARTNER_AD 5
125 #define PHY_REG_QSGMII_AUTO_EXP 6
126 #define PHY_REG_QSGMII_CONTROL_1 16
127 #define PHY_REG_QSGMII_STATUS_1 17
128 #define PHY_REG_QSGMII_INT_ENABLE 18
129 #define PHY_REG_QSGMII_STATUS_2 19
130 #define PHY_REG_QSGMII_RX_ER_BYTE_CAPT 20
131 #define PHY_REG_QSGMII_RX_ER_COUNTER 21
132 #define PHY_REG_QSGMII_PRBS_CTRL 23
133 #define PHY_REG_QSGMII_PRBS_ERR_COUNT_LSB 24
134 #define PHY_REG_QSGMII_PRBS_ERR_COUNT_MSB 25
135 #define PHY_REG_QSGMII_GLOBAL_CTRL_1 26
136 #define PHY_REG_QSGMII_GLOBAL_CTRL_2 27
138 /* Page 5 */
139 #define PHY_REG_MDI0_VCT_STATUS 16
140 #define PHY_REG_MDI1_VCT_STATUS 17
141 #define PHY_REG_MDI2_VCT_STATUS 18
142 #define PHY_REG_MDI3_VCT_STATUS 19
143 #define PHY_REG_PAIR_SKEW_STATUS 20
144 #define PHY_REG_PAIR_SWAP_STATUS 21
145 #define PHY_REG_ADV_VCT_CONTROL_5 23
146 #define PHY_REG_ADV_VCT_SMPL_DIST 24
147 #define PHY_REG_ADV_VCT_X_PAIR_PTHR 25
148 #define PHY_REG_ADV_VCT_SMPAIR_PTHR_01 26
149 #define PHY_REG_ADV_VCT_SMPAIR_PTHR_23 27
150 #define PHY_REG_ADV_VCT_SMPAIR_PTHR_4_P 28
152 /* Page 6 */
153 #define PHY_REG_PACKET_GENERATION 16
154 #define PHY_REG_CRC_COUNTERS 17
155 #define PHY_REG_CHECK_CONTROL 18
156 #define PHY_REG_GENERAL_CONTROL 20
157 #define PHY_REG_LATE_COLIS_CNT_12 23
158 #define PHY_REG_LATE_COLIS_CNT_34 24
159 #define PHY_REG_LATE_COLIS_WIN_ADJ 25
160 #define PHY_REG_MISC_TEST 26
162 /* Page 7 */
163 #define PHY_REG_PHY_CBL_DIAG_0_LEN 16
164 #define PHY_REG_PHY_CBL_DIAG_1_LEN 17
165 #define PHY_REG_PHY_CBL_DIAG_2_LEN 18
166 #define PHY_REG_PHY_CBL_DIAG_3_LEN 19
167 #define PHY_REG_PHY_CBL_DIAG_RESULT 20
168 #define PHY_REG_PHY_CBL_DIAG_CTRL 21
169 #define PHY_REG_ADV_VCT_XPAIR_NTHR 25
170 #define PHY_REG_ADV_VCT_SMPAIR_NTHR_01 26
171 #define PHY_REG_ADV_VCT_SMPAIR_NTHR_23 27
172 #define PHY_REG_ADV_VCT_SMPAIR_NTHR_4_P 28
174 /* Page 8, PTP */
175 #define PHY_REG_PTP_PORT_CONFIG_0 0
176 #define PHY_REG_PTP_PORT_CONFIG_1 1
177 #define PHY_REG_PTP_PORT_CONFIG_2 2
178 #define PHY_REG_PTP_ARR0_PORT_STATUS 8
179 #define PHY_REG_PTP_TIME_ARR0_01 9
180 #define PHY_REG_PTP_TIME_ARR0_23 10
181 #define PHY_REG_PTP_TIME_ARR0_SEQID 11
182 #define PHY_REG_PTP_ARR1_PORT_STATUS 12
183 #define PHY_REG_PTP_TIME_ARR1_01 13
184 #define PHY_REG_PTP_TIME_ARR1_23 14
185 #define PHY_REG_PTP_TIME_ARR1_SEQID 15
187 /* Page 8, Advanced VCT */
188 #define PHY_REG_ADV_VCT_CONTROL_8 20
190 /* Page 9, PTP */
191 #define PHY_REG_PTP_DEP_PORT_STATUS 0
192 #define PHY_REG_PTP_TIME_DEP_01 1
193 #define PHY_REG_PTP_TIME_DEP_23 2
194 #define PHY_REG_PTP_TIME_DEP_SEQID 3
195 #define PHY_REG_PTP_PORT_STATUS 5
197 /* Page 11, LinkCript */
198 #define PHY_REG_LINKCRYPT_READ_ADDR 0
199 #define PHY_REG_LINKCRYPT_WRITE_ADDR 1
200 #define PHY_REG_LINKCRYPT_DATA_LO 2
201 #define PHY_REG_LINKCRYPT_DATA_HI 3
203 /* Page 12, TAI Global Config */
204 #define PHY_REG_TAI_CONFIG_0 0
205 #define PHY_REG_TAI_CONFIG_1 1
206 #define PHY_REG_TAI_CONFIG_2 2
207 #define PHY_REG_TAI_CONFIG_3 3
208 #define PHY_REG_TAI_CONFIG_4 4
209 #define PHY_REG_TAI_CONFIG_5 5
210 #define PHY_REG_TAI_CONFIG_8 8
211 #define PHY_REG_TAI_CONFIG_9 9
212 #define PHY_REG_TAI_CONFIG_10 10
213 #define PHY_REG_TAI_CONFIG_11 11
214 #define PHY_REG_TAI_CONFIG_12 12
215 #define PHY_REG_TAI_CONFIG_13 13
216 #define PHY_REG_TAI_CONFIG_14 14
217 #define PHY_REG_TAI_CONFIG_15 15
219 /* Bit Definition for PHY_REG_CONTROL */
220 #define PHY_REG_CTRL_RESET 0x8000
221 #define PHY_REG_CTRL_LOOPBACK 0x4000
222 #define PHY_REG_CTRL_SPEED 0x2000
223 #define PHY_REG_CTRL_AUTONEGO 0x1000
224 #define PHY_REG_CTRL_POWER 0x800
225 #define PHY_REG_CTRL_ISOLATE 0x400
226 #define PHY_REG_CTRL_RESTART_AUTONEGO 0x200
227 #define PHY_REG_CTRL_DUPLEX 0x100
228 #define PHY_REG_CTRL_SPEED_MSB 0x40
230 #define PHY_REG_CTRL_POWER_BIT 11
231 #define PHY_REG_CTRL_RESTART_AUTONEGO_BIT 9
233 /* Bit Definition for PHY_REG_AUTO_AD */
234 #define PHY_REG_AUTO_AD_NEXTPAGE 0x8000
235 #define PHY_REG_AUTO_AD_REMOTEFAULT 0x4000
236 #define PHY_REG_AUTO_AD_ASYM_PAUSE 0x800
237 #define PHY_REG_AUTO_AD_PAUSE 0x400
238 #define PHY_REG_AUTO_AD_100_FULL 0x100
239 #define PHY_REG_AUTO_AD_100_HALF 0x80
240 #define PHY_REG_AUTO_AD_10_FULL 0x40
241 #define PHY_REG_AUTO_AD_10_HALF 0x20
243 /* Bit Definition for PHY_REG_1000_CONTROL */
244 #define PHY_REG_MS_MANUAL_CONFIG 0x1000
245 #define PHY_REG_MS_CONFIG_VALUE 0x800
246 #define PHY_REG_MS_PORT_TYPE 0x400
247 #define PHY_REG_1000T_FULL 0x200
248 #define PHY_REG_1000T_HALF 0x100
250 /* Bit definition for PHY_REG_COPPER_INT_ENABLE */
251 #define PHY_REG_INT_AUTO_NEGO_ERROR 0x8000
252 #define PHY_REG_INT_SPEED_CHANGED 0x4000
253 #define PHY_REG_INT_DUPLEX_CHANGED 0x2000
254 #define PHY_REG_INT_PAGE_RECEIVED 0x1000
255 #define PHY_REG_INT_AUTO_NEG_COMPLETED 0x800
256 #define PHY_REG_INT_LINK_STATUS_CHANGED 0x400
257 #define PHY_REG_INT_SYMBOL_ERROR 0x200
258 #define PHY_REG_INT_FALSE_CARRIER 0x100
259 #define PHY_REG_INT_CROSSOVER_CHANGED 0x40
260 #define PHY_REG_INT_DOWNSHIFT 0x20
261 #define PHY_REG_INT_ENERGY_DETECT 0x10
262 #define PHY_REG_INT_DTE_DETECT_CHANGED 0x4
263 #define PHY_REG_INT_POLARITY_CHANGED 0x2
264 #define PHY_REG_INT_JABBER 0x1
266 /* Bit definition for PHY_REG_MAC_INT_ENABLE */
267 #define PHY_REG_MAC_INT_FIFO_ERROR 0x80
269 #endif /* __PHYREGS_H__ */