Add NAND/NOR writer support and update POST for C6670
[keystone-rtos/mcsdk-tools.git] / post / include / post.h
1 /******************************************************************************
2  * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com
3  *
4  *  Redistribution and use in source and binary forms, with or without
5  *  modification, are permitted provided that the following conditions
6  *  are met:
7  *
8  *    Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  *
11  *    Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the
14  *    distribution.
15  *
16  *    Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
19  *
20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  *****************************************************************************/
34 /******************************************************************************
35  * POST version definitions
36  ******************************************************************************/
37 #define POST_EVM_VERSION_MSG        " POST Version "
38 #define POST_VERSION                "01.00.00.02"
40 /******************************************************************************
41  * PLL Controller Reset Type Status register
42  *
43  * Bit 31-29    28   27-16  15-8     7-3      2         1     0
44  *     Rsvd  EMU-RST Rsvd  WDRST[N]  Rsvd PLLCTRLRST /RESET  POR
45  ******************************************************************************/
46 #define PLL_BASE                    0x02310000
47 #define PLL_CTRL_REG_RSTYPE         *( volatile uint32_t* )( PLL_BASE + 0xe4 )
49 /******************************************************************************
50  * UART Baud Rate
51  ******************************************************************************/
52 #define POST_UART_BAUDRATE         115200
54 /******************************************************************************
55  * FPGA debug LED definitions
56  ******************************************************************************/
57 typedef enum
58 {
59     POST_LED_OFF     = 0,       /* LED is steady off */
60     POST_LED_ON,                /* LED is steady on */
61     POST_LED_BLINK              /* LED is blinking */
62 } POST_LED_STATE;
64 typedef enum
65 {
66     POST_TEST_IN_PROGRESS = 0,      /* POST running in progress */
67     POST_TEST_COMPLETE,             /* POST done successfully */
68     POST_TEST_DDR,                  /* POST external memory test */
69     POST_TEST_EEPROM,               /* POST I2C EEPROM read test */
70     POST_TEST_NAND,                 /* POST EMIF16 NAND read test */
71     POST_TEST_NOR,                  /* POST SPI NOR read test */
72     POST_TEST_UART,                 /* POST UART write test */
73     POST_TEST_EMAC,                 /* POST EMAC loopback test */
74     POST_TEST_PLL_INIT,             /* POST PLL initialization */
75     POST_TEST_NAND_INIT,            /* POST NAND initialization */
76     POST_TEST_NOR_INIT,             /* POST NOR initialization  */
77     POST_TEST_GENERAL,              /* POST test general */
78     POST_MAX_TEST_NUM               /* Maximum number of POST LED tests */
79 } POST_TEST_ID;
81 #define POST_MAX_NUM_LED        4   /* Total number of LEDs on the EVM */
82 static uint8_t post_led_status[POST_MAX_TEST_NUM][POST_MAX_NUM_LED] =
83 {
84     {POST_LED_ON, POST_LED_ON, POST_LED_ON, POST_LED_ON},           /* POST running in progress */
85     {POST_LED_OFF, POST_LED_OFF, POST_LED_OFF, POST_LED_OFF},       /* POST done successfully */
86     {POST_LED_BLINK, POST_LED_OFF, POST_LED_OFF, POST_LED_OFF},     /* POST external memory test failed */
87     {POST_LED_OFF, POST_LED_BLINK, POST_LED_OFF, POST_LED_OFF},     /* POST I2C EEPROM read test failed */
88     {POST_LED_OFF, POST_LED_OFF, POST_LED_BLINK, POST_LED_OFF},     /* POST EMIF16 NAND read test failed */
89     {POST_LED_OFF, POST_LED_OFF, POST_LED_OFF, POST_LED_BLINK},     /* POST SPI NOR read test failed */
90     {POST_LED_BLINK, POST_LED_BLINK, POST_LED_OFF, POST_LED_OFF},   /* POST UART write test failed */
91     {POST_LED_OFF, POST_LED_BLINK, POST_LED_BLINK, POST_LED_OFF},   /* POST EMAC loopback test failed */
92     {POST_LED_OFF, POST_LED_OFF, POST_LED_BLINK, POST_LED_BLINK},   /* POST PLL initialization failed */
93     {POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK, POST_LED_OFF}, /* POST NAND initialization failed */
94     {POST_LED_OFF, POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK}, /* POST NOR initialization failed */
95     {POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK} /* POST general failure */
96 };
98 #define POST_STATUS_MAX_NUM_CHAR            25      /* Maximum char length of the POST status string */
99 static char post_status[POST_MAX_TEST_NUM][POST_STATUS_MAX_NUM_CHAR] =
101     "running in progress ...",
102     "done successfully!",
103     "external memory",
104     "I2C EEPROM read",
105 #if (defined(_EVMC6678L_))
106     "EMIF16 NAND read",
107 #endif
108 #if (defined(_EVMC6670L_))
109     "GPIO NAND read",
110 #endif
111     "SPI NOR read",
112     "UART write",
113     "EMAC loopback",
114     "PLL initialization",
115     "NAND initialization",
116     "NOR initialization",
117     "general ",
118 };
120 #define POST_LED_BLINK_DELAY    500000  /* 500,000 usec blinking delay */
122 /******************************************************************************
123  * I2C EEPROM test definitions
124  ******************************************************************************/
125 #define POST_EEPROM_TEST_DEVICE_ID      PLATFORM_DEVID_EEPROM50     /* I2C slave bus address 0x50 */
126 #define POST_EEPROM_TEST_READ_ADDRESS   0                           /* Byte address */
127 #define POST_EEPROM_TEST_READ_LENGTH    12                          /* Read length in Bytes */
129 /******************************************************************************
130  * NAND test definitions
131  ******************************************************************************/
132 #if (defined(_EVMC6678L_) || defined(_EVMC6670L_))
133 #define POST_NAND_TEST_DEVICE_ID        PLATFORM_DEVID_NAND512R3A2D /* NAND device ID */
134 #endif
135 #define POST_NAND_TEST_READ_BLOCK_NUM   0       /* NAND read block number */
136 #define POST_NAND_TEST_READ_PAGE_NUM    0       /* NAND read page number */
137 #define POST_NAND_TEST_READ_LENGTH      512     /* Read length in bytes (one page) */
139 /******************************************************************************
140  * NOR test definitions
141  ******************************************************************************/
142 #if (defined(_EVMC6678L_) || defined(_EVMC6670L_))
143 #define POST_NOR_TEST_DEVICE_ID         PLATFORM_DEVID_NORN25Q128   /* NOR device ID */
144 #endif
145 #define POST_NOR_TEST_READ_ADDR         0       /* Byte address of 0 */
146 #define POST_NOR_TEST_READ_LENGTH       256     /* Read length in bytes (one page) */
148 /******************************************************************************
149  * EMAC test definitions
150  ******************************************************************************/
152 #define POST_EMAC_TEST_PKT_LENGTH   256     /* Ethernet packet payload size in bytes */