Added POST and EEPROM writer for C6670
[keystone-rtos/mcsdk-tools.git] / post / include / post.h
1 /******************************************************************************
2  * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com
3  *
4  *  Redistribution and use in source and binary forms, with or without
5  *  modification, are permitted provided that the following conditions
6  *  are met:
7  *
8  *    Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  *
11  *    Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the
14  *    distribution.
15  *
16  *    Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
19  *
20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  *****************************************************************************/
34 /******************************************************************************
35  * POST version definitions
36  ******************************************************************************/
37 #if (defined(_EVMC6678L_))
38 #define POST_DEVICE                 "\r\n\r\nC6678 "
39 #endif
40 #if (defined(_EVMC6670L_))
41 #define POST_DEVICE                 "\r\n\r\nC6670 "
42 #endif
43 #define POST_EVM_VERSION_MSG        "EVM POST Version "
44 #define POST_VERSION                "01.00.00.01"
46 /******************************************************************************
47  * PLL Controller Reset Type Status register
48  *
49  * Bit 31-29    28   27-16  15-8     7-3      2         1     0
50  *     Rsvd  EMU-RST Rsvd  WDRST[N]  Rsvd PLLCTRLRST /RESET  POR
51  ******************************************************************************/
52 #define PLL_BASE                    0x02310000
53 #define PLL_CTRL_REG_RSTYPE         *( volatile uint32_t* )( PLL_BASE + 0xe4 )
55 /******************************************************************************
56  * UART Baud Rate
57  ******************************************************************************/
58 #define POST_UART_BAUDRATE         115200
60 /******************************************************************************
61  * FPGA debug LED definitions
62  ******************************************************************************/
63 typedef enum
64 {
65     POST_LED_OFF     = 0,       /* LED is steady off */
66     POST_LED_ON,                /* LED is steady on */
67     POST_LED_BLINK              /* LED is blinking */
68 } POST_LED_STATE;
70 typedef enum
71 {
72     POST_TEST_IN_PROGRESS = 0,      /* POST running in progress */
73     POST_TEST_COMPLETE,             /* POST done successfully */
74     POST_TEST_DDR,                  /* POST external memory test */
75     POST_TEST_EEPROM,               /* POST I2C EEPROM read test */
76     POST_TEST_NAND,                 /* POST EMIF16 NAND read test */
77     POST_TEST_NOR,                  /* POST SPI NOR read test */
78     POST_TEST_UART,                 /* POST UART write test */
79     POST_TEST_EMAC,                 /* POST EMAC loopback test */
80     POST_TEST_PLL_INIT,             /* POST PLL initialization */
81     POST_TEST_NAND_INIT,            /* POST NAND initialization */
82     POST_TEST_NOR_INIT,             /* POST NOR initialization  */
83     POST_TEST_GENERAL,              /* POST test general */
84     POST_MAX_TEST_NUM               /* Maximum number of POST LED tests */
85 } POST_TEST_ID;
87 #define POST_MAX_NUM_LED        4   /* Total number of LEDs on the EVM */
88 static uint8_t post_led_status[POST_MAX_TEST_NUM][POST_MAX_NUM_LED] =
89 {
90     {POST_LED_ON, POST_LED_ON, POST_LED_ON, POST_LED_ON},           /* POST running in progress */
91     {POST_LED_OFF, POST_LED_OFF, POST_LED_OFF, POST_LED_OFF},       /* POST done successfully */
92     {POST_LED_BLINK, POST_LED_OFF, POST_LED_OFF, POST_LED_OFF},     /* POST external memory test failed */
93     {POST_LED_OFF, POST_LED_BLINK, POST_LED_OFF, POST_LED_OFF},     /* POST I2C EEPROM read test failed */
94     {POST_LED_OFF, POST_LED_OFF, POST_LED_BLINK, POST_LED_OFF},     /* POST EMIF16 NAND read test failed */
95     {POST_LED_OFF, POST_LED_OFF, POST_LED_OFF, POST_LED_BLINK},     /* POST SPI NOR read test failed */
96     {POST_LED_BLINK, POST_LED_BLINK, POST_LED_OFF, POST_LED_OFF},   /* POST UART write test failed */
97     {POST_LED_OFF, POST_LED_BLINK, POST_LED_BLINK, POST_LED_OFF},   /* POST EMAC loopback test failed */
98     {POST_LED_OFF, POST_LED_OFF, POST_LED_BLINK, POST_LED_BLINK},   /* POST PLL initialization failed */
99     {POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK, POST_LED_OFF}, /* POST NAND initialization failed */
100     {POST_LED_OFF, POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK}, /* POST NOR initialization failed */
101     {POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK} /* POST general failure */
102 };
104 #define POST_STATUS_MAX_NUM_CHAR            20      /* Maximum char length of the POST status string */
105 static char post_status[POST_MAX_TEST_NUM][POST_STATUS_MAX_NUM_CHAR] =
107     "running in progress",
108     "done successfully",
109     "external memory",
110     "I2C EEPROM read",
111 #if (defined(_EVMC6678L_))
112     "EMIF16 NAND read",
113 #endif
114 #if (defined(_EVMC6670L_))
115     "GPIO NAND read",
116 #endif
117     "SPI NOR read",
118     "UART write",
119     "EMAC loopback",
120     "PLL initialization",
121     "NAND initialization",
122     "NOR initialization",
123     "general ",
124 };
126 #define POST_LED_BLINK_DELAY    500000  /* 500,000 usec blinking delay */
128 /******************************************************************************
129  * I2C EEPROM test definitions
130  ******************************************************************************/
131 #define POST_EEPROM_TEST_DEVICE_ID      PLATFORM_DEVID_EEPROM50     /* I2C slave bus address 0x50 */
132 #define POST_EEPROM_TEST_READ_ADDRESS   0                           /* Byte address */
133 #define POST_EEPROM_TEST_READ_LENGTH    12                          /* Read length in Bytes */
135 /******************************************************************************
136  * NAND test definitions
137  ******************************************************************************/
138 #if (defined(_EVMC6678L_) || defined(_EVMC6670L_))
139 #define POST_NAND_TEST_DEVICE_ID        PLATFORM_DEVID_NAND512R3A2D /* NAND device ID */
140 #endif
141 #define POST_NAND_TEST_READ_BLOCK_NUM   0       /* NAND read block number */
142 #define POST_NAND_TEST_READ_PAGE_NUM    0       /* NAND read page number */
143 #define POST_NAND_TEST_READ_LENGTH      512     /* Read length in bytes (one page) */
145 /******************************************************************************
146  * NOR test definitions
147  ******************************************************************************/
148 #if (defined(_EVMC6678L_) || defined(_EVMC6670L_))
149 #define POST_NOR_TEST_DEVICE_ID         PLATFORM_DEVID_NORN25Q128   /* NOR device ID */
150 #endif
151 #define POST_NOR_TEST_READ_ADDR         0       /* Byte address of 0 */
152 #define POST_NOR_TEST_READ_LENGTH       256     /* Read length in bytes (one page) */
154 /******************************************************************************
155  * EMAC test definitions
156  ******************************************************************************/
158 #define POST_EMAC_TEST_PKT_LENGTH   256     /* Ethernet packet payload size in bytes */