55d8c7ddeacf810f772425a60fad7561c3e3bab3
1 /*
2 *
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the
16 * distribution.
17 *
18 * Neither the name of Texas Instruments Incorporated nor the names of
19 * its contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
38 /**************************************************************************
39 * FILE PURPOSE: Target specific definitions
40 **************************************************************************
41 * FILE NAME: target.h
42 *
43 * DESCRIPTION: This file defines target specific values used by low level
44 * drivers.
45 *
46 * @file target.h
47 *
48 * @brief
49 * Low level target specific values are defined
50 *
51 ***************************************************************************/
52 #ifndef _TARGET_H
53 #define _TARGET_H
54 #include "types.h"
57 /**
58 * @brief
59 * Device EMAC definitions
60 */
63 /**
64 * @brief
65 * Device Timer definitions
66 */
67 #define TIMER0_BASE 0x02200000u
69 #define TIMER_INPUT_DIVIDER 6 /* Timer driven from cpu clock / 6 */
72 /**
73 * @def MAIN_PLL
74 */
75 #define MAIN_PLL 0 /**< The index to the main PLL */
77 /**
78 * @def NET_PLL
79 */
80 #define NET_PLL 1 /**< The index to the network PLL */
82 /**
83 * @def DDR_PLL
84 */
85 #define DDR_PLL 2 /**< The index to the DDR PLL */
88 /**
89 * @brief
90 * Device PLL definitions
91 */
92 #if defined(SOC_K2K) || defined(SOC_K2H)
93 #define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x2310000 : ((x) == NET_PLL ? 0x2620338 : 0x2620330))
94 #define DEVICE_MAIN_PLL_CTL_0 0x2620328
95 #define DEVICE_MAIN_PLL_CTL_1 0x262032c
96 #elif defined(SOC_K2L) || defined(SOC_K2E)
97 #define DEVICE_PLL_BASE(x) ((x) == MAIN_PLL ? 0x2310000 : ((x) == NET_PLL ? 0x2620338 : 0x2620330))
98 #define DEVICE_MAIN_PLL_CTL_0 0x2620350
99 #define DEVICE_MAIN_PLL_CTL_1 0x2620354
100 #endif
102 /**
103 * @brief
104 * The c661x devices use a register external to the PLL controller for prediv configuration
105 */
106 #define chipPllExternalPrediv(x) TRUE
108 /**
109 * @brief
110 * Device PSC definitions
111 */
112 #define DEVICE_PSC_BASE 0x02350000u
114 /**
115 * @brief
116 * The SPI module base and module divider
117 */
118 #define DEVICE_SPI_BASE(x) 0x20bf0000u
119 #define DEVICE_SPI_MOD_DIVIDER 6
120 #define DEVICE_SPI_MAX_DIVIDER 0xff
122 /**
123 * @brief
124 * The PSC number for the PA sub-system */
125 #define TARGET_PWR_PA 7
127 /**
128 * @brief
129 * The PSC number for the SGMII */
130 #define TARGET_PWR_ETH(x) 8
132 /**
133 * @brief
134 * The PSC numbers for EMIF16 and SPI vary between devices. The devices are run time
135 * identified by reading the JTAG ID register
136 */
137 #define DEVICE_C6616_JTAG_ID_VAL 0x9d02f
138 #define DEVICE_C6618_JTAG_ID_VAL 0x9e02f
139 #define DEVICE_JTAG_ID_REG 0x2620018
142 /**
143 * @brief
144 * The PSC number for NAND depends on the device
145 */
146 #define TARGET_PWR_EMIF deviceEmifPscNum()
147 #define TARGET_PWR_EMIF_C6618 3
149 /*
150 * @brief
151 * The PSC number for SPI depends on the device
152 */
153 #define TARGET_PWR_SPI deviceSpiPscNum()
155 /**
156 * @brief
157 * The PSC number for GPIO. GPIO is in the always on domain
158 */
159 #define TARGET_PWR_GPIO -1
161 /**
162 * @brief
163 * Flag to indicate timer 0 power up requested. The time is always on in the 6472
164 */
165 #define TARGET_PWR_TIMER_0 -1
167 /**
168 * @brief
169 * Device DDR controller definitions
170 */
171 #define DEVICE_EMIF4_BASE 0x21000000
172 #define targetEmifType() ibl_EMIF_TYPE_40
174 /**
175 * @brief
176 * Device EMIF 2.5 controller definitions
177 */
178 #define DEVICE_EMIF25_BASE 0x20c00000
180 /**
181 * @brief
182 * NAND memory regions
183 */
184 #define TARGET_MEM_NAND_CS_2 0x70000000
185 #define TARGET_MEM_NAND_CS_3 0x74000000
186 #define TARGET_MEM_NAND_CS_4 0x78000000
187 #define TARGET_MEM_NAND_CS_5 0x7c000000
188 uint32_t deviceNandMemBase (int32_t cs);
189 #define TARGET_SHFL(x) _shfl(x) /* The shuffle intrinsic */
192 /**
193 * @brief
194 * The highest module number. The value for nyquist is used
195 */
196 #define TARGET_PWR_MAX_MOD 30
199 /**
200 * @brief
201 * The base address of MDIO
202 */
203 #if defined(SOC_K2K) || defined(SOC_K2H)
204 #define TARGET_MDIO_BASE 0x2090300
205 #elif defined(SOC_K2E)
206 #define TARGET_MDIO_BASE 0x24200F00
207 #elif defined(SOC_K2L)
208 #define TARGET_MDIO_BASE 0x26200F00
209 #endif
211 /**
212 * @brief
213 * The number of external ethernet ports
214 */
215 #define TARGET_EMAC_N_PORTS 2
219 /**
220 * @brief
221 * The base address of the I2C peripheral, and the module divisor of the cpu clock
222 */
223 #define DEVICE_I2C_BASE 0x02530000
224 #define DEVICE_I2C_MODULE_DIVISOR 6
226 /**
227 * @brief
228 * Prototypes for the PLL functions handled outside the main PLL registers
229 */
230 int16_t chipPllSetExternalPrediv(uint16_t pllNum, int32_t predivRegVal);
231 int16_t chipPllExternalBwAdj (uint16_t pllNum, uint16_t mult);
232 int32_t chipPllExternalMult (uint16_t pllNum, uint16_t mult);
235 /**
236 * @brief
237 * Hardware network subsystem support, ethernet switch
238 */
239 #define DEVICE_CPSW
240 #define DEVICE_CPSW_NUM_PORTS 3 /* 3 switch ports */
241 #if defined(SOC_K2L)
242 #define DEVICE_CPSW_BASE (0x26200000)
243 #elif defined(SOC_K2K) || (SOC_K2H)
244 #define DEVICE_CPSW_BASE (0x02090800)
245 #elif defined(SOC_K2E)
246 #define DEVICE_CPSW_BASE 0x24200000
247 #endif
248 #define targetGetSwitchCtl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
249 #define targetGetSwitchMaxPktSize() 9000
251 #define DEVICE_QM
252 #if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2E) || defined(SOC_K2L))
253 #define DEVICE_QM_MANAGER_BASE 0x02A02000
254 #define DEVICE_QM_DESC_SETUP_BASE 0x02A03000
255 #define DEVICE_QM_MANAGER_QUEUES_BASE 0x02A80000
256 #define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02AC0000
257 #define DEVICE_QM_QUEUE_STATUS_BASE 0x02A40000
259 /* QM base address register */
260 #define DEVICE_QM1_QUEUE_MANAGEMENT_REGS(x) (0x23A00000 + 0x80000 + 0x10000*(x))
261 #define DEVICE_QM2_QUEUE_MANAGEMENT_REGS(x) (0x23A00000 + 0xA0000 + 0x10000*(x))
262 #else
263 #define DEVICE_QM_MANAGER_BASE 0x02a68000
264 #define DEVICE_QM_DESC_SETUP_BASE 0x02a6a000
265 #define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a20000
266 #define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02a40000
267 #define DEVICE_QM_QUEUE_STATUS_BASE 0x02a00000
268 #endif
270 #define DEVICE_QM_NUM_LINKRAMS 2
271 #define DEVICE_QM_NUM_MEMREGIONS 20
272 void *targetGetQmConfig(void);
273 void targetInitQs (void);
275 #define chipLmbd(x,y) _lmbd(x,y)
277 #define DEVICE_CPDMA
278 #if defined(SOC_K2K) || (SOC_K2H)
279 #define DEVICE_NETCP_CFG_BASE 0x02000000
280 #elif defined(SOC_K2L)
281 #define DEVICE_NETCP_CFG_BASE 0x26000000
282 #elif defined(SOC_K2E)
283 #define DEVICE_NETCP_CFG_BASE 0x24000000
284 #endif
286 //Corrected
287 #if defined(SOC_K2K) || (SOC_K2H)
288 #define DEVICE_PA_CDMA_GLOBAL_CFG_BASE DEVICE_NETCP_CFG_BASE+0x4000
289 #define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE DEVICE_NETCP_CFG_BASE+0x4400
290 #define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE DEVICE_NETCP_CFG_BASE+0x4800
291 #define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE DEVICE_NETCP_CFG_BASE+0x5000
292 #elif defined(SOC_K2L) || defined(SOC_K2E)
293 #define DEVICE_PA_CDMA_GLOBAL_CFG_BASE DEVICE_NETCP_CFG_BASE+0x186000
294 #define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE DEVICE_NETCP_CFG_BASE+0x187000
295 #define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE DEVICE_NETCP_CFG_BASE+0x188000
296 #define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE DEVICE_NETCP_CFG_BASE+0x189000
297 #endif
299 #if defined(SOC_K2K) || defined(SOC_K2H)
300 #define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
301 #define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
302 #define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
303 #elif defined(SOC_K2L) || defined(SOC_K2E)
304 #define DEVICE_PA_CDMA_RX_NUM_CHANNELS 91
305 #define DEVICE_PA_CDMA_RX_NUM_FLOWS 96
306 #define DEVICE_PA_CDMA_TX_NUM_CHANNELS 21
307 #endif
308 //Corrected Over
309 #if defined(SOC_K2K) || defined(SOC_K2H)
310 #define DEVICE_QM_FREE_Q 910
311 #define DEVICE_QM_LNK_BUF_Q 911
312 #define DEVICE_QM_RCV_Q 912
313 #define DEVICE_QM_TX_Q 913
314 #define DEVICE_QM_PA_CFG_Q 640
315 #define DEVICE_QM_ETH_TX_Q 648
316 #elif defined(SOC_K2L) || defined(SOC_K2E)
317 #define DEVICE_QM_FREE_Q 1034
318 #define DEVICE_QM_LNK_BUF_Q 1035
319 #define DEVICE_QM_RCV_Q 1036
320 #define DEVICE_QM_TX_Q 1037
321 #define DEVICE_QM_PA_CFG_Q 640
322 #define DEVICE_QM_ETH_TX_Q 896
323 #endif
324 #define DEVICE_RX_CDMA_TIMEOUT_COUNT 1000
328 #define DEVICE_PA
329 #if defined(SOC_K2K) || defined(SOC_K2H)
330 #define DEVICE_PA_BASE 0x02000000
331 #define DEVICE_PA_NUM_PDSPS 6
332 #elif defined(SOC_K2L)
333 #define DEVICE_PA_BASE 0x26000000
334 #define DEVICE_PA_NUM_PDSPS 6
335 #elif defined(SOC_K2E)
336 #define DEVICE_PA_BASE 0x24000000
337 #define DEVICE_PA_NUM_PDSPS 6
338 #endif
340 #define DEVICE_PA_RUN_CHECK_COUNT 100 /* Number of loops to verify PA firmware is running */
341 #define DEVICE_PA_PLL_BASE 0x02620338
342 #define chipLower8(x) ((x) & 0x00ff)
345 #define TARGET_SGMII_EXTERNAL_SERDES
346 #if defined(SOC_K2K) || defined(SOC_K2H)
347 #define TARGET_SGMII_TYPE_2 /* Use second sgmii setup sequence */
348 #define TARGET_SGMII_BASE_ADDRESSES { 0x02090100, 0x02090200 }
349 #define TARGET_SGMII_SERDES_BASE 0x2620340
350 #define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
351 #elif defined(SOC_K2L)
352 #define TARGET_SGMII_TYPE_2 /* Use second sgmii setup sequence */
353 #define TARGET_SGMII_BASE_ADDRESSES { 0x26200100,0x26200200 }
354 #define TARGET_SGMII_SERDES_BASE 0x2620340
355 #define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
356 #elif defined(SOC_K2E)
357 #define TARGET_SGMII_TYPE_2 /* Use second sgmii setup sequence */
358 #define TARGET_SGMII_BASE_ADDRESSES { 0x24200100,0x24200200 }
359 #define TARGET_SGMII_SERDES_BASE 0x2620340
360 #define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
362 #endif
363 #define TARGET_SGMII_SOFT_RESET 0x04
364 #define TARGET_SGMII_CONTROL 0x10
365 #define TARGET_SGMII_MR_ADV_ABILITY 0x18
366 void targetSgmiiSerdesConfig (int32_t port, void *cfg);
367 #define chipKickOpenSerdes(x) *((uint32_t *)0x2620038) = 0x83e70b13; *((uint32_t *)0x262003c) = 0x95a4f1e0
368 #define chipKickClosedSerdes(x) ; /* never lock the registers */
369 #define TARGET_SERDES_LOCK_DELAY (1600*1000)
371 #if defined(SOC_K2H) || defined(SOC_K2K)
372 #define DEVICE_EMACSL_BASE(x) (0x02090900 + (x)*0x040)
373 #elif defined(SOC_K2L)
374 #define DEVICE_EMACSL_BASE(x) (0x26220000 + (x)*0x040)
375 #elif defined(SOC_K2E)
376 #define DEVICE_EMACSL_BASE(x) (0x24220000 + (x)*0x040)
377 #endif
379 #define DEVICE_N_GMACSL_PORTS 2
380 #define DEVICE_EMACSL_RESET_POLL_COUNT 100
381 int32_t targetMacSend (void *ptr_device, uint8_t* buffer, int32_t num_bytes);
382 int32_t targetMacRcv (void *ptr_device, uint8_t *buffer);
384 #define DEVICE_SS
386 #if defined(SOC_K2H) || defined(SOC_K2K)
387 #define DEVICE_PSTREAM_CFG_REG_ADDR 0x2000604
388 #elif defined(SOC_K2L)
389 #define DEVICE_PSTREAM_CFG_REG_ADDR 0x26000604
390 #elif defined(SOC_K2E)
391 #define DEVICE_PSTREAM_CFG_REG_ADDR 0x240000604
392 #endif
393 #define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0 0
394 #define hwConfigStreamingSwitch() DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0);
397 /**
398 * @brief
399 * Register access macros
400 */
401 #define DEVICE_REG32_W(x,y) *(volatile unsigned int *)(x)=(y)
402 #define DEVICE_REG32_R(x) (*(volatile unsigned int *)(x))
404 #define BOOTBITMASK(x,y) ( ( ( ((int32_t)1 << (((int32_t)x)-((int32_t)y)+(int32_t)1) ) - (int32_t)1 ) ) << ((int32_t)y) )
405 #define BOOT_READ_BITFIELD(z,x,y) (((int32_t)z) & BOOTBITMASK(x,y)) >> (y)
406 #define BOOT_SET_BITFIELD(z,f,x,y) (((int32_t)z) & ~BOOTBITMASK(x,y)) | ( (((int32_t)f) << (y)) & BOOTBITMASK(x,y) )
408 /**
409 * @brief
410 * Mpax configuration registers
411 */
412 #define DEVICE_REG_XMPAX_L(x) *((volatile unsigned int *)(0x08000000 + (8*(x))))
413 #define DEVICE_REG_XMPAX_H(x) *((volatile unsigned int *)(0x08000004 + (8*(x))))
416 /**
417 * @brief
418 * ROM boot loader boot modes and table locations
419 */
420 #define BOOT_MODE_I2C 40
421 #define BOOT_MODE_SPI 50
424 #define ROM_BOOT_PARAMS_ADDR_C6618 0x873680
425 #define ROM_BOOT_PARAMS_ADDR_C6616 0x8f3680
427 /**
428 * @brief
429 * No device specific configuration required for NOR boot, so
430 * the function call is defined to return success.
431 */
432 #define deviceConfigureForNor() 0
434 extern void chipDelay32 (uint32_t del);
435 extern void targetPaConfig (uint8_t *macAddr);
436 extern void *targetGetCpdmaRxConfig (void);
437 extern void *targetGetCpdmaTxConfig (void);
438 extern uint32_t deviceLocalAddrToGlobal (uint32_t addr);
440 #define MAX_SIZE_STREAM_BUFFER 1024
443 #endif /* _TARGET_H */