1 /****************************************************************************************************
2 * FILE PURPOSE: The boot loader packet accelerator driver
3 ****************************************************************************************************
4 * FILE NAME: pa.c
5 *
6 * DESCRIPTION: The driver for the packet accelerator during boot
7 *
8 ****************************************************************************************************/
9 #include "types.h"
10 #include "platform.h"
11 #include "pa_loc.h"
12 #include "pa_api.h"
13 #include "target.h"
14 #include "hwpafw_bin.h"
15 #include <string.h>
17 /****************************************************************************************************
18 * FUNCTION PURPOSE: Initialize the PA sub-system
19 ****************************************************************************************************
20 * DESCRIPTION: Only PDSP 0 is used. All other PDSPs are put into reset. PDSP0 is downloaded
21 * and started, then provided with the mac address configuration.
22 ****************************************************************************************************/
23 int16_t hwPaEnable (const paConfig_t *cfg)
24 {
25 uint32_t i;
26 uint32_t v;
27 BOOL done;
29 /* Disable all PDSPs */
30 for (i = 0; i < DEVICE_PA_NUM_PDSPS; i++)
31 DEVICE_REG32_W (DEVICE_PA_BASE + PA_REG_PDSP_CTL(i), PA_REG_VAL_PDSP_CTL_DISABLE_PDSP);
33 /* Clear the mailbox registers for PDSP 0 */
34 for (i = 0; i < PA_NUM_MAILBOX_SLOTS; i++)
35 DEVICE_REG32_W (DEVICE_PA_BASE + PA_REG_MAILBOX_SLOT(0, i), 0);
38 /* Give a few cycles for the disable */
39 chipDelay32 (100);
41 /* download the firmware */
42 memcpy ((uint32_t *)(DEVICE_PA_BASE + PA_MEM_PDSP_IRAM(0)), PDSPcode, sizeof(PDSPcode));
44 /* Reset the PC and enable PDSP0 */
45 DEVICE_REG32_W (DEVICE_PA_BASE + PA_REG_PDSP_CTL(0), PA_REG_VAL_PDSP_CTL_ENABLE_PDSP(0));
48 /* Copy the two destination mac addresses to the mail box slots.
49 * Mailbox 4 must be written last since this write triggers the firmware to
50 * update the match information */
51 cfg->cmdBuf[0] = BOOT_READ_BITFIELD(cfg->mac0ms, 31, 24);
52 cfg->cmdBuf[1] = BOOT_READ_BITFIELD(cfg->mac0ms, 23, 16);
53 cfg->cmdBuf[2] = BOOT_READ_BITFIELD(cfg->mac0ms, 15, 8);
54 /* Cant use BOOT_READ_BITFIELD for 8 LSBs because it compiles with endian dependency */
55 cfg->cmdBuf[3] = chipLower8 (cfg->mac0ms);
56 cfg->cmdBuf[4] = BOOT_READ_BITFIELD(cfg->mac0ls, 31, 24);
57 cfg->cmdBuf[5] = BOOT_READ_BITFIELD(cfg->mac0ls, 23, 16);
58 cfg->cmdBuf[6] = cfg->cmdBuf[7] = 0;
60 cfg->cmdBuf[8] = BOOT_READ_BITFIELD(cfg->mac1ms, 31, 24);
61 cfg->cmdBuf[9] = BOOT_READ_BITFIELD(cfg->mac1ms, 23, 16);
62 cfg->cmdBuf[10] = BOOT_READ_BITFIELD(cfg->mac1ms, 15, 8);
63 /* Cant use BOOT_READ_BITFIELD for 8 LSBs because it compiles with endian dependency */
64 cfg->cmdBuf[11] = chipLower8 (cfg->mac1ms);
65 cfg->cmdBuf[12] = BOOT_READ_BITFIELD(cfg->mac1ls, 31, 24);
66 cfg->cmdBuf[13] = BOOT_READ_BITFIELD(cfg->mac1ls, 23, 16);
68 cfg->cmdBuf[14] = BOOT_READ_BITFIELD(cfg->rxQnum, 15, 8);
69 cfg->cmdBuf[15] = chipLower8 (cfg->rxQnum);
72 /* Give some delay then verify that the mailboxes have been cleared */
73 for (i = 0, done = FALSE; ((i < DEVICE_PA_RUN_CHECK_COUNT) && (done == FALSE)); i++) {
74 chipDelay32 (100);
75 v = DEVICE_REG32_R (DEVICE_PA_BASE + PA_REG_MAILBOX_SLOT(0, 3));
76 if (v == 0)
77 done = TRUE;
78 }
80 if (done == FALSE)
81 return (-1);
83 return (0);
85 } /* hwPaEnable */
88 /***********************************************************************************************
89 * FUNCTION PURPOSE: Disable the PA firmware
90 ***********************************************************************************************
91 * DESCRIPTION: All PDSPs are disabled and all mailbox slots cleared
92 ***********************************************************************************************/
93 int16_t hwPaDisable (void)
94 {
95 uint32_t i, j;
97 /* Disable all pdsps, clear all mailboxes */
98 for (i = 0; i < DEVICE_PA_NUM_PDSPS; i++) {
100 DEVICE_REG32_W (DEVICE_PA_BASE + PA_REG_PDSP_CTL(i), PA_REG_VAL_PDSP_CTL_DISABLE_PDSP);
102 for (j = 0; j < PA_NUM_MAILBOX_SLOTS; j++)
103 DEVICE_REG32_W (DEVICE_PA_BASE + PA_REG_MAILBOX_SLOT(i, j), 0);
105 }
107 return (0);
109 } /* hwPaDisable */