diff --git a/post/include/post.h b/post/include/post.h
index 8a5b8fe10864ff38c2102227b82d40db6e655aa9..0dec4399896c3ad8898fda8bddd13777d1357c58 100644 (file)
--- a/post/include/post.h
+++ b/post/include/post.h
/******************************************************************************
* POST version definitions
******************************************************************************/
-#if (defined(_EVMC6678L_))
-#define POST_DEVICE "\r\n\r\nC6678 "
-#endif
-#if (defined(_EVMC6670L_))
-#define POST_DEVICE "\r\n\r\nC6670 "
-#endif
-#define POST_EVM_VERSION_MSG "EVM POST Version "
-#define POST_VERSION "01.00.00.00"
+#define POST_EVM_VERSION_MSG " POST Version "
+#define POST_VERSION "01.00.00.04"
/******************************************************************************
* PLL Controller Reset Type Status register
#define PLL_CTRL_REG_RSTYPE *( volatile uint32_t* )( PLL_BASE + 0xe4 )
/******************************************************************************
- * UART Baud Rate
+ * UART definitions
******************************************************************************/
#define POST_UART_BAUDRATE 115200
+#define POST_UART_READ_TIMEOUT (30 * 1000000) /* in usec */
/******************************************************************************
* FPGA debug LED definitions
POST_LED_BLINK /* LED is blinking */
} POST_LED_STATE;
+typedef enum
+{
+ POST_TEST_RESULT_STARTED = 0, /* POST Test Result Started */
+ POST_TEST_RESULT_PASSED, /* POST Test Result Passed */
+ POST_TEST_RESULT_FAILED /* POST Test Result Failed */
+} POST_TEST_RESULT;
+
typedef enum
{
POST_TEST_IN_PROGRESS = 0, /* POST running in progress */
POST_TEST_NAND_INIT, /* POST NAND initialization */
POST_TEST_NOR_INIT, /* POST NOR initialization */
POST_TEST_GENERAL, /* POST test general */
+ POST_TEST_EMAC_LOOPBACK, /* POST test PA Loopback */
POST_MAX_TEST_NUM /* Maximum number of POST LED tests */
} POST_TEST_ID;
{POST_LED_OFF, POST_LED_OFF, POST_LED_BLINK, POST_LED_BLINK}, /* POST PLL initialization failed */
{POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK, POST_LED_OFF}, /* POST NAND initialization failed */
{POST_LED_OFF, POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK}, /* POST NOR initialization failed */
- {POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK} /* POST general failure */
+ {POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK}, /* POST general failure */
+ {POST_LED_ON, POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK} /* POST PA loopback failure */
};
-#define POST_STATUS_MAX_NUM_CHAR 20 /* Maximum char length of the POST status string */
+#define POST_STATUS_MAX_NUM_CHAR 25 /* Maximum char length of the POST status string */
static char post_status[POST_MAX_TEST_NUM][POST_STATUS_MAX_NUM_CHAR] =
{
- "running in progress",
- "done successfully",
+ "running in progress ...",
+ "done successfully!",
"external memory",
"I2C EEPROM read",
-#if (defined(_EVMC6678L_))
+#if (!defined(_EVMC6670L_))
"EMIF16 NAND read",
-#endif
-#if (defined(_EVMC6670L_))
+#else
"GPIO NAND read",
#endif
"SPI NOR read",
"NAND initialization",
"NOR initialization",
"general ",
+ "EMAC loopback ",
};
#define POST_LED_BLINK_DELAY 500000 /* 500,000 usec blinking delay */
/******************************************************************************
* NAND test definitions
******************************************************************************/
-#if (defined(_EVMC6678L_) || defined(_EVMC6670L_))
-#define POST_NAND_TEST_DEVICE_ID PLATFORM_DEVID_NAND512R3A2D /* NAND device ID */
+#if (defined(_EVMC6657L_))
+ #define POST_NAND_TEST_DEVICE_ID PLATFORM_DEVID_MT29F1G08ABCHC /* NAND device ID */
+ #define POST_NAND_TEST_READ_BLOCK_NUM 0 /* NAND read block number */
+ #define POST_NAND_TEST_READ_PAGE_NUM 0 /* NAND read page number */
+ #define POST_NAND_TEST_READ_LENGTH 2048 /* Read length in bytes (one page) */
+#else
+ #define POST_NAND_TEST_DEVICE_ID PLATFORM_DEVID_NAND512R3A2D
+ #define POST_NAND_TEST_READ_BLOCK_NUM 0 /* NAND read block number */
+ #define POST_NAND_TEST_READ_PAGE_NUM 0 /* NAND read page number */
+ #define POST_NAND_TEST_READ_LENGTH 512 /* Read length in bytes (one page) */
#endif
-#define POST_NAND_TEST_READ_BLOCK_NUM 0 /* NAND read block number */
-#define POST_NAND_TEST_READ_PAGE_NUM 0 /* NAND read page number */
-#define POST_NAND_TEST_READ_LENGTH 512 /* Read length in bytes (one page) */
-
/******************************************************************************
* NOR test definitions
******************************************************************************/
-#if (defined(_EVMC6678L_) || defined(_EVMC6670L_))
-#define POST_NOR_TEST_DEVICE_ID PLATFORM_DEVID_NORN25Q128 /* NOR device ID */
+#if (defined(_EVMC6657L_))
+ #define POST_NOR_TEST_DEVICE_ID PLATFORM_DEVID_NORN25Q032A /* NOR device ID */
+ #define POST_NOR_TEST_READ_ADDR 0 /* Byte address of 0 */
+ #define POST_NOR_TEST_READ_LENGTH 256 /* Read length in bytes (one page) */
+#else
+ #define POST_NOR_TEST_DEVICE_ID PLATFORM_DEVID_NORN25Q128 /* NOR device ID */
+ #define POST_NOR_TEST_READ_ADDR 0 /* Byte address of 0 */
+ #define POST_NOR_TEST_READ_LENGTH 256 /* Read length in bytes (one page) */
#endif
-#define POST_NOR_TEST_READ_ADDR 0 /* Byte address of 0 */
-#define POST_NOR_TEST_READ_LENGTH 256 /* Read length in bytes (one page) */
-
/******************************************************************************
* EMAC test definitions
******************************************************************************/
-
#define POST_EMAC_TEST_PKT_LENGTH 256 /* Ethernet packet payload size in bytes */
+
+/******************************************************************************
+ * Serial Number definitions
+ ******************************************************************************/
+#define POST_MAX_SN_SIZE 10 /* Maximum number of the chars of Serial Number for the EVM */
+#define POST_SERIAL_NUM_ADDR (65536-128) /* Last 128 bytes of EEPROM 0x50 stores the S/N */
+
+extern POST_TEST_RESULT
+post_test_emac_loopback
+(
+ void
+);