diff --git a/post/src/post.c b/post/src/post.c
index 0b8ec0b9aa71bc1ec96f36be793e7580f709875b..f90473873ad465fc18b2e2b45061d4ef4304ab74 100644 (file)
--- a/post/src/post.c
+++ b/post/src/post.c
#include <ti/csl/cslr_cpsgmii.h>
#include <ti/csl/csl_mdioAux.h>
#else
- #include <ti/csl/csl_cpsgmii.h>
- #include <ti/csl/cslr_cpsgmii.h>
+ #include <ti/csl/csl_sgmii.h>
+ #include <ti/csl/cslr_sgmii.h>
#endif
#include <ti/csl/csl_mdio.h>
#pragma DATA_ALIGN(post_version, 16)
char post_version[] = POST_VERSION;
+#if (defined(SOC_K2K) || defined(SOC_K2H))
+/*
+ * Holds the base address of ports.
+ */
+void *cpswPortBaseAddr[4] = {
+ &hCpsw5gfRegs->PORT1_INFO,
+ &hCpsw5gfRegs->PORT2_INFO,
+ &hCpsw5gfRegs->PORT3_INFO,
+ &hCpsw5gfRegs->PORT4_INFO
+};
+#endif
+
/* OSAL functions for Platform Library */
uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment)
{
{
POST_TEST_RESULT test_result = POST_TEST_RESULT_PASSED;
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2E) || defined(SOC_K2L))
+ /* DDR3A test */
+ if(platform_external_memory_test(0x80000000, 0x88000000) != Platform_EOK)
+ {
+ test_result = POST_TEST_RESULT_FAILED;
+ }
+#if (defined(SOC_K2K) || defined(SOC_K2H))
+ /* DDR3B test */
+ if(platform_external_memory_test(0x60000000, 0x68000000) != Platform_EOK)
+ {
+ test_result = POST_TEST_RESULT_FAILED;
+ }
+#endif
+#else
if(platform_external_memory_test(0, 0) != Platform_EOK)
{
test_result = POST_TEST_RESULT_FAILED;
}
-
+#endif
return test_result;
}
#endif
int32_t cpswEvm6678 = 0;
-#if !(defined(_EVMC6657L_)) && !(defined(_EVMC6678L_))
+#if !(defined(_EVMC6657L_))
/** ============================================================================
* @n@b Init_SGMII
*
CSL_CPGMAC_SL_enableExtControl (macPortNum);
/* Configure the MAC address for this port */
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ CSL_CPSW_setPortMACAddress (macPortNum, macAddress);
+#else
CSL_CPSW_3GF_setPortMACAddress (macPortNum, macAddress);
+#endif
/* Configure VLAN ID/CFI/Priority.
*
* For now, we are not using VLANs so just configure them
* to all zeros.
*/
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ CSL_CPSW_setPortVlanReg (macPortNum, 0, 0, 0);
+#else
CSL_CPSW_3GF_setPortVlanReg (macPortNum, 0, 0, 0);
+#endif
/* Configure the Receive Maximum length on this port,
* i.e., the maximum size the port can receive without
void Init_Switch (uint32_t mtu)
{
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ CSL_CPSW_PORTSTAT portStatCfg;
+#else
CSL_CPSW_3GF_PORTSTAT portStatCfg;
+#endif
/* Enable the CPPI port, i.e., port 0 that does all
* the data streaming in/out of EMAC.
*/
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ CSL_CPSW_enablePort0 ();
+ CSL_CPSW_disableVlanAware ();
+ CSL_CPSW_setPort0VlanReg (0, 0, 0);
+ CSL_CPSW_setPort0RxMaxLen (mtu);
+#else
CSL_CPSW_3GF_enablePort0 ();
CSL_CPSW_3GF_disableVlanAware ();
CSL_CPSW_3GF_setPort0VlanReg (0, 0, 0);
CSL_CPSW_3GF_setPort0RxMaxLen (mtu);
+#endif
/* Enable statistics on both the port groups:
*
* MAC Sliver ports - Port 1, Port 2
* CPPI Port - Port 0
*/
+#if (defined(SOC_K2K) || defined(SOC_K2H))
portStatCfg.p0AStatEnable = 1;
portStatCfg.p0BStatEnable = 1;
portStatCfg.p1StatEnable = 1;
portStatCfg.p2StatEnable = 1;
+#elif (defined(SOC_K2L) || defined(SOC_K2E))
+ portStatCfg.p0StatEnable = 1;
+ portStatCfg.p1StatEnable = 1;
+ portStatCfg.p2StatEnable = 1;
+ portStatCfg.p3StatEnable = 1;
+ portStatCfg.p4StatEnable = 1;
+ portStatCfg.p5StatEnable = 1;
+ portStatCfg.p6StatEnable = 1;
+ portStatCfg.p7StatEnable = 1;
+ portStatCfg.p8StatEnable = 1;
+#endif
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ CSL_CPSW_setPortStatsEnableReg (&portStatCfg);
+#else
CSL_CPSW_3GF_setPortStatsEnableReg (&portStatCfg);
+#endif
/* Setup the Address Lookup Engine (ALE) Configuration:
* (1) Enable ALE.
* properties for the switch, i.e., which
* ports to send the packets to.
*/
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ CSL_CPSW_enableAle ();
+ CSL_CPSW_clearAleTable ();
+
+ CSL_CPSW_disableAleVlanAware ();
+ CSL_CPSW_disableAleTxRateLimit ();
+ CSL_CPSW_setAlePrescaleReg (125000000u/1000u);
+ CSL_CPSW_setAleUnkownVlanReg (7, 3, 3, 7);
+#else
CSL_CPSW_3GF_enableAle ();
CSL_CPSW_3GF_clearAleTable ();
CSL_CPSW_3GF_disableAleTxRateLimit ();
CSL_CPSW_3GF_setAlePrescaleReg (125000000u/1000u);
CSL_CPSW_3GF_setAleUnkownVlanReg (7, 3, 3, 7);
+#endif
if(cpswLpbkMode != CPSW_LOOPBACK_NONE)
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ CSL_CPSW_enableAleBypass();
+#else
CSL_CPSW_3GF_enableAleBypass();
+#endif
/* Done with switch configuration */
return;
int Switch_update_addr (uint32_t portNum, uint8_t macAddress[6], Uint16 add)
{
uint32_t i;
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ CSL_CPSW_ALE_PORTCONTROL alePortControlCfg;
+ CSL_CPSW_ALE_UNICASTADDR_ENTRY ucastAddrCfg;
+#else
CSL_CPSW_3GF_ALE_PORTCONTROL alePortControlCfg;
CSL_CPSW_3GF_ALE_UNICASTADDR_ENTRY ucastAddrCfg;
-
+#endif
/* Configure the address in "Learning"/"Forward" state */
alePortControlCfg.portState = ALE_PORTSTATE_FORWARD;
alePortControlCfg.mcastLimit = 0;
alePortControlCfg.bcastLimit = 0;
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ CSL_CPSW_setAlePortControlReg (portNum, &alePortControlCfg);
+#else
CSL_CPSW_3GF_setAlePortControlReg (portNum, &alePortControlCfg);
+#endif
if (cpswLpbkMode != CPSW_LOOPBACK_NONE)
{
* matching received packet must be forwarded to.
*/
/* Get the next free ALE entry to program */
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ for (i = 0; i < CSL_CPSW_NUMALE_ENTRIES; i++)
+#else
for (i = 0; i < CSL_CPSW_3GF_NUMALE_ENTRIES; i++)
+#endif
{
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ if (CSL_CPSW_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)
+#else
if (CSL_CPSW_3GF_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)
+#endif
{
/* Found a free entry */
break;
}
}
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ if (i == CSL_CPSW_NUMALE_ENTRIES)
+#else
if (i == CSL_CPSW_3GF_NUMALE_ENTRIES)
+#endif
{
/* No free ALE entry found. return error. */
return -1;
ucastAddrCfg.portNumber = portNum; // Add the ALE entry for this port
/* Setup the ALE entry for this port's MAC address */
+#if (defined(SOC_K2K) || defined(SOC_K2H) || defined(SOC_K2L) || defined(SOC_K2E))
+ CSL_CPSW_setAleUnicastAddrEntry (i, &ucastAddrCfg);
+#else
CSL_CPSW_3GF_setAleUnicastAddrEntry (i, &ucastAddrCfg);
+#endif
}
}
{
if (cpswSimTest)
{
+#if (!defined(SOC_K2K) && !defined(SOC_K2H) && !defined(SOC_K2L) && !defined(SOC_K2E))
/* Unlock the chip configuration registers to allow SGMII SERDES registers to
* be written */
/* Re-lock the chip configuration registers to prevent unintentional writes */
CSL_BootCfgLockKicker();
-
+#endif
}
/* SGMII SERDES Configuration complete. Return. */
#endif
-#if !(defined(_EVMC6678L_))
/******************************************************************************
* Function: post_test_emac_loopback
******************************************************************************/
{
return POST_TEST_RESULT_FAILED;
}
-
+
platform_delay(100);
-
+
/* Receive the loopback packet */
if (ret = cpmac_drv_receive (&nDevice, test_buf) <= 0)
{
#endif
return POST_TEST_RESULT_PASSED;
}
-#endif
void
post_hex_to_string
post_hex_to_string(reg_val, 8, msg);
msg[8] = ' ';
msg[9] = 0;
- post_write_uart(msg);
+ post_write_uart(msg);
}
/******************************************************************************
memset(&init_config, 0, sizeof(platform_init_config));
memset(&init_flags, 0x01, sizeof(platform_init_flags));
- init_flags.phy = 1;
+ init_flags.phy = 0;
acc_fail = 0;
/* Initialize the platform */
post_write_uart("\r\n\r------------------------------------------");
post_write_uart("\r\n\rSOC Information");
post_hex_to_string(info.board_rev, 4, msg);
- post_write_uart("\r\n\r\nFPGA Version: ");
+ post_write_uart("\r\n\r\nBMC Version: ");
post_write_uart(msg);
if (info.serial_nbr[0] != 0)
msg[3] = 0;
post_write_uart(msg);
}
-#if !(defined(_EVMC6657L_)||defined(_EVMC6655L_))
+#if !(defined(_EVMC6657L_)||defined(_EVMC6655L_) || defined(SOC_K2L) || defined(SOC_K2E))
sa_enable = *(volatile uint32_t *)0x20c0004;
+#elif defined(SOC_K2L)
+ sa_enable = *(volatile uint32_t *)0x260c0004;
+#elif defined(SOC_K2E)
+ sa_enable = *(volatile uint32_t *)0x240c0004;
+#endif
+#if !(defined(_EVMC6657L_)||defined(_EVMC6655L_))
sa_enable &= 0x1;
if (sa_enable)
/* Dump Additional Information */
post_dump_register_val ((uint32_t)&platform_init_return_code, "\r\n\rPlatform init return code: 0x");
+#if (!defined(SOC_K2K) && !defined(SOC_K2H))
post_write_uart("\r\n\rAdditional Information: ");
post_dump_register_val (0x02350014, "\r\n\r (0x02350014) :");
post_dump_register_val (0x02350624, "\r\n\r (0x02350624) :");
post_dump_register_val (0x02620180, "\r\n\r (0x02620180) :");
post_write_uart("\r\n\r------------------------------------------");
+#endif
}
post_write_uart("\r\n\r\nPower On Self Test\n");
acc_fail++;
}
post_display_status(POST_TEST_NAND, test_result);
-
-#if !(defined(_EVMC6678L_))
+#if 0
post_display_status(POST_TEST_EMAC_LOOPBACK, POST_TEST_RESULT_STARTED);
test_result = post_test_emac_loopback();
if (test_result == POST_TEST_RESULT_FAILED)
{
acc_fail++;
}
+
post_display_status(POST_TEST_EMAC_LOOPBACK, test_result);
#endif
-
post_display_status(POST_TEST_DDR, POST_TEST_RESULT_STARTED);
test_result = post_test_external_memory();
if (test_result == POST_TEST_RESULT_FAILED)
post_write_uart("\r\n\r\nPOST result: FAIL");
}
+#if (!defined(SOC_K2K) && !defined(SOC_K2H) && !defined(SOC_K2L) && !defined(SOC_K2E) )
post_write_serial_no();
+#endif
}