Added support for 6657 post
authorIvan Pang <i-pang@ti.com>
Thu, 10 May 2012 18:58:53 +0000 (14:58 -0400)
committerIvan Pang <i-pang@ti.com>
Thu, 10 May 2012 18:58:53 +0000 (14:58 -0400)
post/include/post.h

index d58875b3fc3b5d0ed33532d9a8ce4511fd0d837a..0dec4399896c3ad8898fda8bddd13777d1357c58 100644 (file)
@@ -35,7 +35,7 @@
  * POST version definitions
  ******************************************************************************/
 #define POST_EVM_VERSION_MSG        " POST Version "
-#define POST_VERSION                "01.00.00.05"
+#define POST_VERSION                "01.00.00.04"
 
 /******************************************************************************
  * PLL Controller Reset Type Status register
@@ -112,10 +112,9 @@ static char post_status[POST_MAX_TEST_NUM][POST_STATUS_MAX_NUM_CHAR] =
     "done successfully!",
     "external memory",
     "I2C EEPROM read",
-#if (defined(_EVMC6678L_))
+#if (!defined(_EVMC6670L_))
     "EMIF16 NAND read",
-#endif
-#if (defined(_EVMC6670L_))
+#else
     "GPIO NAND read",
 #endif
     "SPI NOR read",
@@ -140,22 +139,29 @@ static char post_status[POST_MAX_TEST_NUM][POST_STATUS_MAX_NUM_CHAR] =
 /******************************************************************************
  * NAND test definitions
  ******************************************************************************/
-#if (defined(_EVMC6678L_) || defined(_EVMC6670L_))
-#define POST_NAND_TEST_DEVICE_ID        PLATFORM_DEVID_NAND512R3A2D /* NAND device ID */
+#if (defined(_EVMC6657L_))
+       #define POST_NAND_TEST_DEVICE_ID        PLATFORM_DEVID_MT29F1G08ABCHC /* NAND device ID */
+       #define POST_NAND_TEST_READ_BLOCK_NUM   0       /* NAND read block number */
+       #define POST_NAND_TEST_READ_PAGE_NUM    0       /* NAND read page number */
+       #define POST_NAND_TEST_READ_LENGTH      2048     /* Read length in bytes (one page) */
+#else
+       #define POST_NAND_TEST_DEVICE_ID                PLATFORM_DEVID_NAND512R3A2D
+       #define POST_NAND_TEST_READ_BLOCK_NUM   0       /* NAND read block number */
+       #define POST_NAND_TEST_READ_PAGE_NUM    0       /* NAND read page number */
+       #define POST_NAND_TEST_READ_LENGTH      512     /* Read length in bytes (one page) */
 #endif
-#define POST_NAND_TEST_READ_BLOCK_NUM   0       /* NAND read block number */
-#define POST_NAND_TEST_READ_PAGE_NUM    0       /* NAND read page number */
-#define POST_NAND_TEST_READ_LENGTH      512     /* Read length in bytes (one page) */
-
 /******************************************************************************
  * NOR test definitions
  ******************************************************************************/
-#if (defined(_EVMC6678L_) || defined(_EVMC6670L_))
-#define POST_NOR_TEST_DEVICE_ID         PLATFORM_DEVID_NORN25Q128   /* NOR device ID */
+#if (defined(_EVMC6657L_))
+       #define POST_NOR_TEST_DEVICE_ID         PLATFORM_DEVID_NORN25Q032A   /* NOR device ID */
+       #define POST_NOR_TEST_READ_ADDR         0       /* Byte address of 0 */
+       #define POST_NOR_TEST_READ_LENGTH       256     /* Read length in bytes (one page) */
+#else
+       #define POST_NOR_TEST_DEVICE_ID         PLATFORM_DEVID_NORN25Q128   /* NOR device ID */
+       #define POST_NOR_TEST_READ_ADDR         0       /* Byte address of 0 */
+       #define POST_NOR_TEST_READ_LENGTH       256     /* Read length in bytes (one page) */
 #endif
-#define POST_NOR_TEST_READ_ADDR         0       /* Byte address of 0 */
-#define POST_NOR_TEST_READ_LENGTH       256     /* Read length in bytes (one page) */
-
 /******************************************************************************
  * EMAC test definitions
  ******************************************************************************/