Updating POST .h/.c files for keystone1 only. Keystone2 references removed
authorIvan Pang <i-pang@ti.com>
Fri, 9 May 2014 16:09:57 +0000 (11:09 -0500)
committerIvan Pang <i-pang@ti.com>
Fri, 9 May 2014 16:09:57 +0000 (11:09 -0500)
post/include/cpdma_loc.h
post/include/post.h
post/include/target.h
post/src/cpdma.c
post/src/post.c

index 80b7b12c35c586462d743a79af3d4200b33aad5e..49d78cb1a6acc3fa5089a2dfe24ed697bd30c106 100755 (executable)
@@ -11,7 +11,6 @@
 
 /* Emulation control register */
 #define CPDMA_REG_EMU_CTL   0x08
-#define CPDMA_REG_QM_BASE_ADDR(x)   (0x10 + (x)*0x4)
 
 /* CPPI Tx DMA channel control registers */
 #define CPDMA_REG_TCHAN_CFG_REG_A(x)   (0x00 + (x)*0x20)
index 2b5562b96724fc93da609b9c3a7d6be5ff021a30..8863ecb139685d4b2a3172ecbf302cd36e2b6a4d 100755 (executable)
@@ -35,7 +35,7 @@
  * POST version definitions
  ******************************************************************************/
 #define POST_EVM_VERSION_MSG        " POST Version "
-#define POST_VERSION                "01.00.00.08"
+#define POST_VERSION                "01.00.00.06"
 
 /******************************************************************************
  * PLL Controller Reset Type Status register
@@ -88,25 +88,6 @@ typedef enum
 } POST_TEST_ID;
 
 #define POST_MAX_NUM_LED        4   /* Total number of LEDs on the EVM */
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2E) || defined(DEVICE_K2L))
-static uint8_t post_led_status[POST_MAX_TEST_NUM][POST_MAX_NUM_LED] =
-{
-       /* LED0: red   LED0: green   LED1: blue   LED2: blue */
-    {POST_LED_OFF, POST_LED_OFF, POST_LED_ON, POST_LED_ON},        /* POST running in progress */
-    {POST_LED_OFF, POST_LED_ON, POST_LED_OFF, POST_LED_OFF},       /* POST done successfully */
-    {POST_LED_ON, POST_LED_OFF, POST_LED_OFF, POST_LED_OFF},       /* POST external memory test failed */
-    {POST_LED_ON, POST_LED_OFF, POST_LED_ON, POST_LED_OFF},        /* POST I2C EEPROM read test failed */
-    {POST_LED_ON, POST_LED_OFF, POST_LED_OFF, POST_LED_ON},        /* POST EMIF16 NAND read test failed */
-    {POST_LED_ON, POST_LED_OFF, POST_LED_ON, POST_LED_ON},         /* POST SPI NOR read test failed */
-    {POST_LED_ON, POST_LED_OFF, POST_LED_BLINK, POST_LED_OFF},     /* POST UART write test failed */
-    {POST_LED_ON, POST_LED_OFF, POST_LED_OFF, POST_LED_BLINK},     /* POST EMAC loopback test failed */
-    {POST_LED_ON, POST_LED_OFF, POST_LED_BLINK, POST_LED_ON},      /* POST PLL initialization failed */
-    {POST_LED_ON, POST_LED_OFF, POST_LED_ON, POST_LED_BLINK},      /* POST NAND initialization failed */
-    {POST_LED_ON, POST_LED_OFF, POST_LED_BLINK, POST_LED_BLINK},   /* POST NOR initialization failed */
-    {POST_LED_BLINK, POST_LED_OFF, POST_LED_OFF, POST_LED_OFF},    /* POST general failure */
-    {POST_LED_BLINK, POST_LED_OFF, POST_LED_ON, POST_LED_OFF}      /* POST PA loopback failure */
-};
-#else
 static uint8_t post_led_status[POST_MAX_TEST_NUM][POST_MAX_NUM_LED] =
 {
     {POST_LED_ON, POST_LED_ON, POST_LED_ON, POST_LED_ON},           /* POST running in progress */
@@ -123,7 +104,6 @@ static uint8_t post_led_status[POST_MAX_TEST_NUM][POST_MAX_NUM_LED] =
     {POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK}, /* POST general failure */
     {POST_LED_ON, POST_LED_BLINK, POST_LED_BLINK, POST_LED_BLINK}   /* POST PA loopback failure */
 };
-#endif
 
 #define POST_STATUS_MAX_NUM_CHAR            25      /* Maximum char length of the POST status string */
 static char post_status[POST_MAX_TEST_NUM][POST_STATUS_MAX_NUM_CHAR] =
@@ -159,21 +139,11 @@ static char post_status[POST_MAX_TEST_NUM][POST_STATUS_MAX_NUM_CHAR] =
 /******************************************************************************
  * NAND test definitions
  ******************************************************************************/
-#if (defined(_EVMC6657L_) || defined(DEVICE_K2K) || defined(DEVICE_K2H))
+#if (defined(_EVMC6657L_))
        #define POST_NAND_TEST_DEVICE_ID        PLATFORM_DEVID_MT29F1G08ABCHC /* NAND device ID */
        #define POST_NAND_TEST_READ_BLOCK_NUM   0       /* NAND read block number */
        #define POST_NAND_TEST_READ_PAGE_NUM    0       /* NAND read page number */
        #define POST_NAND_TEST_READ_LENGTH      2048     /* Read length in bytes (one page) */
-#elif (defined(DEVICE_K2E))
-       #define POST_NAND_TEST_DEVICE_ID        PLATFORM_DEVID_MT29F4G08ABADA /* NAND device ID */
-       #define POST_NAND_TEST_READ_BLOCK_NUM   0       /* NAND read block number */
-       #define POST_NAND_TEST_READ_PAGE_NUM    0       /* NAND read page number */
-       #define POST_NAND_TEST_READ_LENGTH      2048     /* Read length in bytes (one page) */
-#elif (defined(DEVICE_K2L))
-       #define POST_NAND_TEST_DEVICE_ID        PLATFORM_DEVID_MT29F16G08ADBCAH4C /* NAND device ID */
-       #define POST_NAND_TEST_READ_BLOCK_NUM   0       /* NAND read block number */
-       #define POST_NAND_TEST_READ_PAGE_NUM    0       /* NAND read page number */
-       #define POST_NAND_TEST_READ_LENGTH      4096     /* Read length in bytes (one page) */
 #else
        #define POST_NAND_TEST_DEVICE_ID                PLATFORM_DEVID_NAND512R3A2D
        #define POST_NAND_TEST_READ_BLOCK_NUM   0       /* NAND read block number */
index cc3167c298245055ed9d30ff58a6b330355c6507..7ec9543b4b9abd62b0972de992ab0f5217248bb2 100755 (executable)
  *  @brief
  *    Device PLL definitions
  */
-#if defined(DEVICE_K2K) || defined(DEVICE_K2H)
 #define DEVICE_PLL_BASE(x)      ((x) == MAIN_PLL ? 0x2310000 : ((x) == NET_PLL ? 0x2620338 : 0x2620330))
 #define DEVICE_MAIN_PLL_CTL_0       0x2620328
 #define DEVICE_MAIN_PLL_CTL_1       0x262032c
-#elif defined(DEVICE_K2L) || defined(DEVICE_K2E)
-#define DEVICE_PLL_BASE(x)      ((x) == MAIN_PLL ? 0x2310000 : ((x) == NET_PLL ? 0x2620338 : 0x2620330))
-#define DEVICE_MAIN_PLL_CTL_0       0x2620350
-#define DEVICE_MAIN_PLL_CTL_1       0x2620354
-#endif
+
 
 /**
  *  @brief
@@ -200,13 +195,7 @@ uint32_t deviceNandMemBase (int32_t cs);
  * @brief
  *   The base address of MDIO
  */
-#if defined(DEVICE_K2K) || defined(DEVICE_K2H)
 #define TARGET_MDIO_BASE    0x2090300
-#elif defined(DEVICE_K2E)
-#define TARGET_MDIO_BASE    0x24200F00
-#elif defined(DEVICE_K2L)
-#define TARGET_MDIO_BASE    0x26200F00
-#endif
 
 /**
  * @brief
@@ -238,35 +227,16 @@ int32_t chipPllExternalMult (uint16_t pllNum, uint16_t mult);
  */
 #define DEVICE_CPSW
 #define DEVICE_CPSW_NUM_PORTS       3                    /* 3 switch ports */
-#if defined(DEVICE_K2L)
-#define DEVICE_CPSW_BASE (0x26200000)
-#elif defined(DEVICE_K2K) || (DEVICE_K2H)
 #define DEVICE_CPSW_BASE            (0x02090800)
-#elif defined(DEVICE_K2E)
-#define DEVICE_CPSW_BASE                       0x24200000
-#endif
 #define targetGetSwitchCtl()        CPSW_CTL_P0_ENABLE   /* Enable port 0 */
 #define targetGetSwitchMaxPktSize() 9000
 
 #define DEVICE_QM
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2E) || defined(DEVICE_K2L))
-#define DEVICE_QM_MANAGER_BASE          0x02A02000
-#define DEVICE_QM_DESC_SETUP_BASE       0x02A03000
-#define DEVICE_QM_MANAGER_QUEUES_BASE   0x02A80000
-#define DEVICE_QM_MANAGER_Q_PROXY_BASE  0x02AC0000
-#define DEVICE_QM_QUEUE_STATUS_BASE            0x02A40000
-
-/* QM base address register */
-#define DEVICE_QM1_QUEUE_MANAGEMENT_REGS(x)  (0x23A00000 + 0x80000 + 0x10000*(x))
-#define DEVICE_QM2_QUEUE_MANAGEMENT_REGS(x)  (0x23A00000 + 0xA0000 + 0x10000*(x))
-#else
 #define DEVICE_QM_MANAGER_BASE          0x02a68000
 #define DEVICE_QM_DESC_SETUP_BASE       0x02a6a000
 #define DEVICE_QM_MANAGER_QUEUES_BASE   0x02a20000
 #define DEVICE_QM_MANAGER_Q_PROXY_BASE  0x02a40000
 #define DEVICE_QM_QUEUE_STATUS_BASE            0x02a00000
-#endif
-
 #define DEVICE_QM_NUM_LINKRAMS          2
 #define DEVICE_QM_NUM_MEMREGIONS        20
 void    *targetGetQmConfig(void);
@@ -274,92 +244,45 @@ void     targetInitQs (void);
 
 #define chipLmbd(x,y) _lmbd(x,y)
 
+
+
+
 #define DEVICE_CPDMA
-#if defined(DEVICE_K2K) || (DEVICE_K2H)
-#define DEVICE_NETCP_CFG_BASE 0x02000000
-#elif defined(DEVICE_K2L)
-#define DEVICE_NETCP_CFG_BASE  0x26000000
-#elif defined(DEVICE_K2E)
-#define DEVICE_NETCP_CFG_BASE  0x24000000
-#endif
-
-//Corrected
-#if defined(DEVICE_K2K) || (DEVICE_K2H)
-#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE   DEVICE_NETCP_CFG_BASE+0x4000
-#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE  DEVICE_NETCP_CFG_BASE+0x4400
-#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE  DEVICE_NETCP_CFG_BASE+0x4800
-#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE  DEVICE_NETCP_CFG_BASE+0x5000
-#elif defined(DEVICE_K2L) || defined(DEVICE_K2E)
-#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE   DEVICE_NETCP_CFG_BASE+0x186000
-#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE  DEVICE_NETCP_CFG_BASE+0x187000
-#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE  DEVICE_NETCP_CFG_BASE+0x188000
-#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE  DEVICE_NETCP_CFG_BASE+0x189000
-#endif
-
-#if defined(DEVICE_K2K) || defined(DEVICE_K2H)
+
+#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE   0x02004000
+#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE  0x02004400
+#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE  0x02004800
+#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE  0x02005000
+
 #define DEVICE_PA_CDMA_RX_NUM_CHANNELS   24
 #define DEVICE_PA_CDMA_RX_NUM_FLOWS      32
 #define DEVICE_PA_CDMA_TX_NUM_CHANNELS   9
-#elif defined(DEVICE_K2L) || defined(DEVICE_K2E)
-#define DEVICE_PA_CDMA_RX_NUM_CHANNELS   91
-#define DEVICE_PA_CDMA_RX_NUM_FLOWS      96
-#define DEVICE_PA_CDMA_TX_NUM_CHANNELS   21
-#endif
-//Corrected Over
-#if defined(DEVICE_K2K) || defined(DEVICE_K2H)
+
+
 #define DEVICE_QM_FREE_Q                910
 #define DEVICE_QM_LNK_BUF_Q             911
 #define DEVICE_QM_RCV_Q                 912
 #define DEVICE_QM_TX_Q                  913
 #define DEVICE_QM_PA_CFG_Q              640
 #define DEVICE_QM_ETH_TX_Q              648
-#elif defined(DEVICE_K2L) || defined(DEVICE_K2E)
-#define DEVICE_QM_FREE_Q                1034
-#define DEVICE_QM_LNK_BUF_Q             1035
-#define DEVICE_QM_RCV_Q                 1036
-#define DEVICE_QM_TX_Q                  1037
-#define DEVICE_QM_PA_CFG_Q              640
-#define DEVICE_QM_ETH_TX_Q              896
-#endif
+
 #define DEVICE_RX_CDMA_TIMEOUT_COUNT    1000
 
 
 
 #define DEVICE_PA
-#if defined(DEVICE_K2K) || defined(DEVICE_K2H)
 #define DEVICE_PA_BASE                  0x02000000
 #define DEVICE_PA_NUM_PDSPS             6
-#elif defined(DEVICE_K2L)
-#define DEVICE_PA_BASE                  0x26000000
-#define DEVICE_PA_NUM_PDSPS             6
-#elif defined(DEVICE_K2E)
-#define DEVICE_PA_BASE                  0x24000000
-#define DEVICE_PA_NUM_PDSPS             6
-#endif
-
 #define DEVICE_PA_RUN_CHECK_COUNT       100         /* Number of loops to verify PA firmware is running */
 #define DEVICE_PA_PLL_BASE              0x02620338
 #define chipLower8(x)                   ((x) & 0x00ff)
 
 
 #define TARGET_SGMII_EXTERNAL_SERDES
-#if defined(DEVICE_K2K) || defined(DEVICE_K2H)
 #define TARGET_SGMII_TYPE_2             /* Use second sgmii setup sequence */
 #define TARGET_SGMII_BASE_ADDRESSES    { 0x02090100, 0x02090200 }
 #define TARGET_SGMII_SERDES_BASE        0x2620340
 #define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
-#elif defined(DEVICE_K2L)
-#define TARGET_SGMII_TYPE_2             /* Use second sgmii setup sequence */
-#define TARGET_SGMII_BASE_ADDRESSES    { 0x26200100,0x26200200 }
-#define TARGET_SGMII_SERDES_BASE        0x2620340
-#define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
-#elif defined(DEVICE_K2E)
-#define TARGET_SGMII_TYPE_2             /* Use second sgmii setup sequence */
-#define TARGET_SGMII_BASE_ADDRESSES    { 0x24200100,0x24200200 }
-#define TARGET_SGMII_SERDES_BASE        0x2620340
-#define TARGET_SGMII_SERDES_STATUS_BASE 0x2620158
-
-#endif
 #define TARGET_SGMII_SOFT_RESET         0x04
 #define TARGET_SGMII_CONTROL            0x10
 #define TARGET_SGMII_MR_ADV_ABILITY     0x18
@@ -368,28 +291,14 @@ void targetSgmiiSerdesConfig (int32_t port, void *cfg);
 #define chipKickClosedSerdes(x)         ;       /* never lock the registers */
 #define TARGET_SERDES_LOCK_DELAY        (1600*1000)
 
-#if defined(DEVICE_K2H) || defined(DEVICE_K2K)
 #define DEVICE_EMACSL_BASE(x)           (0x02090900 + (x)*0x040)
-#elif defined(DEVICE_K2L)
-#define DEVICE_EMACSL_BASE(x)           (0x26220000 + (x)*0x040)
-#elif defined(DEVICE_K2E)
-#define DEVICE_EMACSL_BASE(x)           (0x24220000 + (x)*0x040)
-#endif
-
 #define DEVICE_N_GMACSL_PORTS           2
 #define DEVICE_EMACSL_RESET_POLL_COUNT  100
 int32_t targetMacSend (void *ptr_device, uint8_t* buffer, int32_t num_bytes);
 int32_t targetMacRcv (void *ptr_device, uint8_t *buffer);
 
 #define DEVICE_SS
-
-#if defined(DEVICE_K2H) || defined(DEVICE_K2K)
 #define DEVICE_PSTREAM_CFG_REG_ADDR                 0x2000604
-#elif defined(DEVICE_K2L)
-#define DEVICE_PSTREAM_CFG_REG_ADDR                 0x26000604
-#elif defined(DEVICE_K2E)
-#define DEVICE_PSTREAM_CFG_REG_ADDR                 0x240000604
-#endif
 #define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0      0
 #define hwConfigStreamingSwitch()                   DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_PDSP0);
 
index bbccb2b63223e2aecf9845f7c2a7632eed5fa176..9f444a85a4d7bd3ca7a7d9c0a7ada7da97ffcb62 100755 (executable)
@@ -148,11 +148,6 @@ int16_t hwCpdmaTxConfig (const cpdmaTxCfg_t *cfg)
     /* Disable loopback in the tx direction */
     DEVICE_REG32_W (cfg->gblCtlBase + CPDMA_REG_EMU_CTL, CPDMA_REG_VAL_EMU_CTL_NO_LOOPBACK);
 
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2E) || defined(DEVICE_K2L))
-    /* Set QM base address, only for K2x devices */
-    DEVICE_REG32_W (cfg->gblCtlBase + CPDMA_REG_QM_BASE_ADDR(0), DEVICE_QM1_QUEUE_MANAGEMENT_REGS(0));
-#endif
-
     /* Enable all channels. The current state isn't important */
     for (i = 0; i < cfg->nTxChans; i++)  {
         DEVICE_REG32_W (cfg->txBase + CPDMA_REG_TCHAN_CFG_REG_B(i), 0);  /* Priority */
index 3131ad258af859f2122036279d069c5e4cd1f274..417e7df5bbae2ad8d437919d638a1f6c4c5b1701 100755 (executable)
 #pragma DATA_ALIGN(post_version, 16)
 char post_version[] = POST_VERSION;
 
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H))
-/*
- *  Holds the base address of ports.
- */
-void *cpswPortBaseAddr[4] = {
-  &hCpsw5gfRegs->PORT1_INFO,
-  &hCpsw5gfRegs->PORT2_INFO,
-  &hCpsw5gfRegs->PORT3_INFO,
-  &hCpsw5gfRegs->PORT4_INFO
-};
-#endif
-
 /* OSAL functions for Platform Library */
 uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment)
 {
@@ -240,25 +228,11 @@ post_test_external_memory
 {
     POST_TEST_RESULT    test_result = POST_TEST_RESULT_PASSED;
 
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2E) || defined(DEVICE_K2L))
-    /* DDR3A test */
-    if(platform_external_memory_test(0x80000000, 0x88000000) != Platform_EOK)
-    {
-        test_result = POST_TEST_RESULT_FAILED;
-    }
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H))
-    /* DDR3B test */
-    if(platform_external_memory_test(0x60000000, 0x68000000) != Platform_EOK)
-    {
-        test_result = POST_TEST_RESULT_FAILED;
-    }
-#endif
-#else
     if(platform_external_memory_test(0, 0) != Platform_EOK)
     {
         test_result = POST_TEST_RESULT_FAILED;
     }
-#endif
+
     return test_result;
 }
 
@@ -530,22 +504,14 @@ int Init_MAC (uint32_t macPortNum, uint8_t macAddress[6], uint32_t mtu)
     CSL_CPGMAC_SL_enableExtControl (macPortNum);
 
     /* Configure the MAC address for this port */
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-    CSL_CPSW_setPortMACAddress (macPortNum, macAddress);
-#else
     CSL_CPSW_3GF_setPortMACAddress (macPortNum, macAddress);
-#endif
 
     /* Configure VLAN ID/CFI/Priority.
      *
      * For now, we are not using VLANs so just configure them
      * to all zeros.
      */
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-       CSL_CPSW_setPortVlanReg (macPortNum, 0, 0, 0);
-#else
     CSL_CPSW_3GF_setPortVlanReg (macPortNum, 0, 0, 0);
-#endif
 
     /* Configure the Receive Maximum length on this port,
      * i.e., the maximum size the port can receive without
@@ -562,53 +528,26 @@ int Init_MAC (uint32_t macPortNum, uint8_t macAddress[6], uint32_t mtu)
 
 void Init_Switch (uint32_t mtu)
 {
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-       CSL_CPSW_PORTSTAT               portStatCfg;
-#else
     CSL_CPSW_3GF_PORTSTAT               portStatCfg;
-#endif
 
     /* Enable the CPPI port, i.e., port 0 that does all
      * the data streaming in/out of EMAC.
      */
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-       CSL_CPSW_enablePort0 ();
-    CSL_CPSW_disableVlanAware ();
-    CSL_CPSW_setPort0VlanReg (0, 0, 0);
-    CSL_CPSW_setPort0RxMaxLen (mtu);
-#else
     CSL_CPSW_3GF_enablePort0 ();
     CSL_CPSW_3GF_disableVlanAware ();
     CSL_CPSW_3GF_setPort0VlanReg (0, 0, 0);
     CSL_CPSW_3GF_setPort0RxMaxLen (mtu);
-#endif
 
     /* Enable statistics on both the port groups:
      *
      * MAC Sliver ports -   Port 1, Port 2
      * CPPI Port        -   Port 0
      */
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H))
     portStatCfg.p0AStatEnable   =   1;
     portStatCfg.p0BStatEnable   =   1;
     portStatCfg.p1StatEnable    =   1;
     portStatCfg.p2StatEnable    =   1;
-#elif (defined(DEVICE_K2L) || defined(DEVICE_K2E))
-       portStatCfg.p0StatEnable    =   1;
-       portStatCfg.p1StatEnable    =   1;
-       portStatCfg.p2StatEnable    =   1;
-       portStatCfg.p3StatEnable    =   1;
-       portStatCfg.p4StatEnable    =   1;
-       portStatCfg.p5StatEnable    =   1;
-       portStatCfg.p6StatEnable    =   1;
-       portStatCfg.p7StatEnable    =   1;
-       portStatCfg.p8StatEnable    =   1;
-#endif
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-       CSL_CPSW_setPortStatsEnableReg (&portStatCfg);
-#else
     CSL_CPSW_3GF_setPortStatsEnableReg (&portStatCfg);
-#endif
 
     /* Setup the Address Lookup Engine (ALE) Configuration:
      *      (1) Enable ALE.
@@ -620,15 +559,6 @@ void Init_Switch (uint32_t mtu)
      *          properties for the switch, i.e., which
      *          ports to send the packets to.
      */
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-       CSL_CPSW_enableAle ();
-       CSL_CPSW_clearAleTable ();
-
-       CSL_CPSW_disableAleVlanAware ();
-       CSL_CPSW_disableAleTxRateLimit ();
-       CSL_CPSW_setAlePrescaleReg (125000000u/1000u);
-       CSL_CPSW_setAleUnkownVlanReg (7, 3, 3, 7);
-#else
     CSL_CPSW_3GF_enableAle ();
     CSL_CPSW_3GF_clearAleTable ();
 
@@ -636,14 +566,9 @@ void Init_Switch (uint32_t mtu)
     CSL_CPSW_3GF_disableAleTxRateLimit ();
     CSL_CPSW_3GF_setAlePrescaleReg (125000000u/1000u);
     CSL_CPSW_3GF_setAleUnkownVlanReg (7, 3, 3, 7);
-#endif
 
     if(cpswLpbkMode != CPSW_LOOPBACK_NONE)
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-       CSL_CPSW_enableAleBypass();
-#else
         CSL_CPSW_3GF_enableAleBypass();
-#endif
 
     /* Done with switch configuration */
     return;
@@ -652,13 +577,9 @@ void Init_Switch (uint32_t mtu)
 int Switch_update_addr (uint32_t portNum, uint8_t macAddress[6], Uint16 add)
 {
     uint32_t                              i;
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-       CSL_CPSW_ALE_PORTCONTROL        alePortControlCfg;
-       CSL_CPSW_ALE_UNICASTADDR_ENTRY  ucastAddrCfg;
-#else
     CSL_CPSW_3GF_ALE_PORTCONTROL        alePortControlCfg;
     CSL_CPSW_3GF_ALE_UNICASTADDR_ENTRY  ucastAddrCfg;
-#endif
+
 
     /* Configure the address in "Learning"/"Forward" state */
     alePortControlCfg.portState             =   ALE_PORTSTATE_FORWARD;
@@ -668,11 +589,7 @@ int Switch_update_addr (uint32_t portNum, uint8_t macAddress[6], Uint16 add)
     alePortControlCfg.mcastLimit            =   0;
     alePortControlCfg.bcastLimit            =   0;
 
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-       CSL_CPSW_setAlePortControlReg (portNum, &alePortControlCfg);
-#else
     CSL_CPSW_3GF_setAlePortControlReg (portNum, &alePortControlCfg);
-#endif
 
     if (cpswLpbkMode != CPSW_LOOPBACK_NONE)
     {
@@ -682,27 +599,15 @@ int Switch_update_addr (uint32_t portNum, uint8_t macAddress[6], Uint16 add)
         * matching received packet must be forwarded to.
         */
         /* Get the next free ALE entry to program */
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-        for (i = 0; i < CSL_CPSW_NUMALE_ENTRIES; i++)
-#else
         for (i = 0; i < CSL_CPSW_3GF_NUMALE_ENTRIES; i++)
-#endif
         {
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-            if (CSL_CPSW_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)
-#else
             if (CSL_CPSW_3GF_getALEEntryType (i) == ALE_ENTRYTYPE_FREE)
-#endif
             {
                 /* Found a free entry */
                 break;
             }
         }
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-       if (i == CSL_CPSW_NUMALE_ENTRIES)
-#else
         if (i == CSL_CPSW_3GF_NUMALE_ENTRIES)
-#endif
         {
             /* No free ALE entry found. return error. */
             return -1;
@@ -717,11 +622,7 @@ int Switch_update_addr (uint32_t portNum, uint8_t macAddress[6], Uint16 add)
             ucastAddrCfg.portNumber     =      portNum;   // Add the ALE entry for this port
 
             /* Setup the ALE entry for this port's MAC address */
-#if (defined(DEVICE_K2K) || defined(DEVICE_K2H) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-            CSL_CPSW_setAleUnicastAddrEntry (i, &ucastAddrCfg);
-#else
             CSL_CPSW_3GF_setAleUnicastAddrEntry (i, &ucastAddrCfg);
-#endif
         }
     }
 
@@ -733,7 +634,6 @@ int32_t Init_SGMII_SERDES(void)
 {
     if (cpswSimTest)
     {
-#if (!defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E))
 
            /* Unlock the chip configuration registers to allow SGMII SERDES registers to
            * be written */
@@ -747,7 +647,7 @@ int32_t Init_SGMII_SERDES(void)
 
            /* Re-lock the chip configuration registers to prevent unintentional writes */
            CSL_BootCfgLockKicker();
-#endif
+
     }
 
        /* SGMII SERDES Configuration complete. Return. */
@@ -870,9 +770,9 @@ post_test_emac_loopback
     {
         return POST_TEST_RESULT_FAILED;
     }
-
+    
     platform_delay(100);
-
+    
     /* Receive the loopback packet */
     if (ret = cpmac_drv_receive (&nDevice, test_buf) <= 0)
     {
@@ -1062,7 +962,7 @@ post_dump_register_val
    post_hex_to_string(reg_val, 8, msg);
    msg[8] = ' ';
    msg[9] = 0;
-   post_write_uart(msg);
+   post_write_uart(msg);   
 }
 
 /******************************************************************************
@@ -1093,6 +993,7 @@ main
     memset(&init_config, 0, sizeof(platform_init_config));
     memset(&init_flags, 0x01, sizeof(platform_init_flags));
 
+    init_flags.phy = 1;
     acc_fail = 0;
 
     /* Initialize the platform */
@@ -1140,7 +1041,7 @@ main
         post_write_uart("\r\n\r------------------------------------------");
         post_write_uart("\r\n\rSOC Information");
         post_hex_to_string(info.board_rev, 4, msg);
-        post_write_uart("\r\n\r\nBMC Version: ");
+        post_write_uart("\r\n\r\nFPGA Version: ");
         post_write_uart(msg);
 
         if (info.serial_nbr[0] != 0)
@@ -1159,14 +1060,8 @@ main
             msg[3] = 0;
             post_write_uart(msg);
         }
-#if !(defined(_EVMC6657L_)||defined(_EVMC6655L_) || defined(DEVICE_K2L) || defined(DEVICE_K2E))
-        sa_enable = *(volatile uint32_t *)0x20c0004;
-#elif defined(DEVICE_K2L)
-        sa_enable = *(volatile uint32_t *)0x260c0004;
-#elif defined(DEVICE_K2E)
-        sa_enable = *(volatile uint32_t *)0x240c0004;
-#endif
 #if !(defined(_EVMC6657L_)||defined(_EVMC6655L_))
+        sa_enable = *(volatile uint32_t *)0x20c0004;
         sa_enable &= 0x1;
 
         if (sa_enable)
@@ -1186,7 +1081,6 @@ main
 
         /* Dump Additional Information */
          post_dump_register_val ((uint32_t)&platform_init_return_code, "\r\n\rPlatform init return code: 0x");
-#if (!defined(DEVICE_K2K) && !defined(DEVICE_K2H))
          post_write_uart("\r\n\rAdditional Information: ");
          post_dump_register_val (0x02350014, "\r\n\r   (0x02350014) :");
          post_dump_register_val (0x02350624, "\r\n\r   (0x02350624) :");
@@ -1212,7 +1106,6 @@ main
          post_dump_register_val (0x02620180, "\r\n\r   (0x02620180) :");
 
          post_write_uart("\r\n\r------------------------------------------");
-#endif
     }
 
     post_write_uart("\r\n\r\nPower On Self Test\n");
@@ -1243,16 +1136,15 @@ main
        acc_fail++;
     }
     post_display_status(POST_TEST_NAND, test_result);
-#if 0
+
     post_display_status(POST_TEST_EMAC_LOOPBACK, POST_TEST_RESULT_STARTED);
     test_result = post_test_emac_loopback();
     if (test_result == POST_TEST_RESULT_FAILED)
     {
        acc_fail++;
     }
-
     post_display_status(POST_TEST_EMAC_LOOPBACK, test_result);
-#endif
+
     post_display_status(POST_TEST_DDR, POST_TEST_RESULT_STARTED);
     test_result = post_test_external_memory();
     if (test_result == POST_TEST_RESULT_FAILED)
@@ -1272,8 +1164,6 @@ main
        post_write_uart("\r\n\r\nPOST result: FAIL");
     }
 
-#if (!defined(DEVICE_K2K) && !defined(DEVICE_K2H) && !defined(DEVICE_K2L) && !defined(DEVICE_K2E) )
     post_write_serial_no();
-#endif
 }