Added defines for 6657

diff --git a/post/include/evmc665x_emac.h b/post/include/evmc665x_emac.h
new file mode 100644 (file)
index 0000000..0706c89
--- /dev/null
+++ b/post/include/evmc665x_emac.h
@@ -0,0 +1,105 @@
+/******************************************************************************
+ * Copyright (c) 2010 Texas Instruments Incorporated - http://www.ti.com
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *****************************************************************************/
+ 
+/******************************************************************************
+ *
+ * File Name:          evmc665x_emac.h
+ *
+ * Description:        This file contains typdedefs and macros for EMACSS.
+ *
+ * History:
+ *             FEB/15/2012, Ajay Bhargav               File created
+ *
+ ******************************************************************************/
+#ifndef _EVMC665x_EMAC_H_
+#define _EVMC665x_EMAC_H_
+
+/****************
+ * Include Files
+ ****************/
+#include <ti/csl/tistdtypes.h>
+#ifdef _EVMC6657L_
+#include <ti/csl/csl_emac.h>
+
+
+typedef struct EMAC_MCB
+{
+       EMAC_Desc *rx_desc;
+       EMAC_Desc *tx_desc;
+       Uint32 lastrxhdp;
+} EMAC_MCB;
+
+#endif
+/************************
+ * Defines and Macros
+ ************************/
+#ifndef CSL_EMAC_0_REGS
+#define CSL_EMAC_0_REGS                        (CSL_EMAC_SS_CFG_REGS)
+#endif
+
+#ifndef CSL_MDIO_0_REGS1
+#define CSL_MDIO_0_REGS                        (CSL_EMAC_SS_CFG_REGS + 0x0800)
+#endif
+
+#ifndef CSL_SGMII_0_REGS
+#define CSL_SGMII_0_REGS               (CSL_EMAC_SS_CFG_REGS + 0x0900)
+#endif
+
+#define EMAC_RAM_BASE                  (CSL_EMAC_SS_CFG_REGS + 0x2000)
+#define EMAC_RAM_LEN                   (0x00002000u)
+
+/* MTU Size */
+#define MAX_MTU_SIZE   1536
+
+/* TX & RX Descriptor setup */
+#define DESC_SIZE              sizeof(EMAC_Desc)
+#define TX_DESC_START  EMAC_RAM_BASE
+#define TX_DESC_COUNT  1
+#define TX_DESC_ADD(x) (TX_DESC_START + (DESC_SIZE * x))
+#define TX_DESC_END            (TX_DESC_START + (DESC_SIZE * TX_DESC_COUNT))
+#define RX_DESC_START  TX_DESC_END
+#define RX_DESC_COUNT  1
+#define RX_DESC_ADD(x) (RX_DESC_START + (DESC_SIZE * x))
+#define RX_DESC_END            (RX_DESC_START + (DESC_SIZE * RX_DESC_COUNT))
+#define RX_BUFF_SIZE   MAX_MTU_SIZE
+#define RX_BUFF_START  RX_DESC_END
+#define RX_BUFF_ADD(x) (RX_BUFF_START + (RX_BUFF_SIZE * x))
+#define RX_BUFF_END            (RX_BUFF_START + (RX_BUFF_SIZE * RX_DESC_COUNT))
+#define TX_BUFF_ADD            RX_BUFF_END
+
+Uint32 EMAC_init();
+Uint32 sgmii_init();
+Int32 EMAC_Send(Uint8 *buff, int len);
+Int32 EMAC_Recv(Uint8 *buff);
+
+#endif /* _EVMC665x_EMAC_H_ */

diff --git a/post/include/evmc665x_phy.h b/post/include/evmc665x_phy.h
new file mode 100644 (file)
index 0000000..4954ca0
--- /dev/null
+++ b/post/include/evmc665x_phy.h
@@ -0,0 +1,85 @@
+/*
+ *
+ * Copyright (C) 2011-12 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef _EVMC6657_PHY_H_
+#define _EVMC6657_PHY_H_
+
+#include <stdint.h>
+
+enum PHY_ERR {
+       PHY_OK = 0,
+       EPHY_FAIL,
+       EPHY_INVALID_PARM,
+       EPHY_WR_FAILED,
+       EPHY_RD_FAILED,
+       ENO_SPEED
+};
+
+/* operation */
+#define LOOPBACK_MASK                  0x1F
+#define MAC_LOOPBACK                   (1 << 0)
+#define LINE_COPPER_LOOPBACK           (1 << 1)        /* Not Available */
+#define LINE_FIBER_LOOPBACK            (1 << 2)        /* Not Available */
+#define EXT_COPPER_LOOPBACK            (1 << 3)
+#define EXT_FIBER_LOOPBACK             (1 << 4)
+
+/* negotiation (copper) */
+#define PHY_SPEED_MASK                 (0xF << 5)
+#define PHY_MODE_1000MBPS              (1 << 5)
+#define PHY_MODE_100MBPS               (1 << 6)
+#define PHY_MODE_10MBPS                        (1 << 7)
+#define PHY_MODE_AUTO                  (1 << 8)
+
+/* Preferred Media (copper default) */
+#define PHY_PREF_MASK                  (7 << 9)
+#define PHY_PREF_COPPER                        (1 << 9)
+#define PHY_PREF_FIBER                         (1 << 10)
+#define PHY_PREF_AUTO                  (1 << 11)
+
+/* media select */
+#define PHY_MEDIA_MASK                 (7 << 12)
+#define PHY_MEDIA_MAC                  (1 << 12)
+#define PHY_MEDIA_COPPER               (1 << 13)
+#define PHY_MEDIA_FIBER                        (1 << 14)
+
+#define PHY_CALC_MASK(fieldOffset, fieldLen, mask)     \
+               if ((fieldLen + fieldOffset) >= 16)                     \
+                       mask = (0 - (1 << fieldOffset));                \
+               else                                                                            \
+                       mask = (((1 << (fieldLen + fieldOffset))) - (1 << fieldOffset))
+
+int phy_init(int phyaddr, uint32_t mode);
+
+#endif /* _EVMC6657_PHY_H_ */

diff --git a/post/include/phyregs.h b/post/include/phyregs.h
new file mode 100644 (file)
index 0000000..8a009e6
--- /dev/null
+++ b/post/include/phyregs.h
@@ -0,0 +1,269 @@
+/*
+ *
+ * Copyright (C) 2011-12 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __PHYREGS_H__
+#define __PHYREGS_H__
+
+/* Marvell Phy Registers */
+#define PHY_PAGE0      0
+#define PHY_PAGE1      1
+#define PHY_PAGE2      2
+#define PHY_PAGE3      3
+#define PHY_PAGE4      4
+#define PHY_PAGE5      5
+#define PHY_PAGE6      6
+#define PHY_PAGE7      7
+#define PHY_PAGE8      8
+#define PHY_PAGE9      9
+#define PHY_PAGE12     12
+#define PHY_PAGE14     14
+#define PHY_PAGE16     16
+
+/* Any Page or Page 0 for 1340*/
+#define PHY_REG_CONTROL         0
+#define PHY_REG_STATUS          1
+#define PHY_REG_PHY_ID_1        2
+#define PHY_REG_PHY_ID_2        3
+#define PHY_REG_AUTO_AD         4
+#define PHY_REG_PARTNER_AD      5
+#define PHY_REG_AUTO_EXP        6
+#define PHY_REG_NEXT_PAGE       7
+#define PHY_REG_PARTNER_NEXT_PAGE   8
+#define PHY_REG_1000_CONTROL    9
+#define PHY_REG_1000_STATUS     10
+#define PHY_REG_EXT_STATUS      15
+#define PHY_REG_EXT_PHY_SPEC_CONTROL      20
+#define PHY_REG_PAGE_ADDR       22
+#define PHY_REG_PAGE_ADDR_2     29
+#define PHY_REG_PAGE_ACCESS     30  /* Mult-functions access register, which page is on Reg 29 */
+
+/* Page 0 */
+#define PHY_REG_COPPER_CONTROL_1                       16
+#define PHY_REG_COPPER_STATUS_1                                17
+#define PHY_REG_COPPER_INT_ENABLE                      18
+#define PHY_REG_COPPER_STATUS_2                                19
+#define PHY_REG_COPPER_CONTROL_2                       20
+#define PHY_REG_COPPER_RX_ERROR_COUNTER                21
+#define PHY_REG_GLOBAL_INT_STATUS                      23
+#define PHY_REG_COPPER_CONTROL_3                       26
+
+/* Page 1 */
+#define PHY_REG_FIBER_CONTROL                          0
+#define PHY_REG_FIBER_STATUS                           1
+#define PHY_REG_FIBER_AUTO_AD                          4
+#define PHY_REG_FIBER_PARTNER_AD                       5
+#define PHY_REG_FIBER_AUTO_EXP                         6
+#define PHY_REG_FIBER_NEXT_PAGE                                7
+#define PHY_REG_FIBER_PARTNER_NEXT_PAGE                8
+#define PHY_REG_FIBER_EXT_STATUS                       15
+
+#define PHY_REG_FIBER_CONTROL_1                                16
+#define PHY_REG_FIBER_STATUS_1                         17
+#define PHY_REG_FIBER_INT_ENABLE                       18
+#define PHY_REG_FIBER_STATUS_2                         19
+#define PHY_REG_FIBER_RX_ERROR_COUNTER         21
+
+#define PHY_REG_FIBER_PRBS_CTRL                                23
+#define PHY_REG_FIBER_PRBS_ERR_COUNT_LSB    24
+#define PHY_REG_FIBER_PRBS_ERR_COUNT_MSB    25
+#define PHY_REG_FIBER_SPEC_CTRL_2                      26
+
+/* Page 2 */
+#define PHY_REG_MAC_CONTROL_1                          16
+#define PHY_REG_MAC_STATUS_1                           17
+#define PHY_REG_MAC_INT_ENABLE                         18
+#define PHY_REG_MAC_STATUS_2                           19
+#define PHY_REG_NAC_RX_ER_BYTE_CAPT                    20
+#define PHY_REG_MAC_CONTROL                                    21
+#define PHY_REG_MAC_CONTROL_2                          26
+#define PHY_REG_MAC_CO_SERDES_RX_ER_BYTE_CTRL_2       20
+#define PHY_REG_MAC_CONTROL_2_1340                     21
+
+/* Page 3 */
+#define PHY_REG_LED_FUNC_CTRL         16
+#define PHY_REG_LED_POLAR_CTRL        17
+#define PHY_REG_LED_TIMER_CTRL        18
+#define PHY_REG_LED_FUNC_POLAR_CTRL   19
+
+/* Page 4 */
+#define PHY_REG_QSGMII_CONTROL         0
+#define PHY_REG_QSGMII_STATUS          1
+#define PHY_REG_QSGMII_AUTO_AD         4
+#define PHY_REG_QSGMII_PARTNER_AD      5
+#define PHY_REG_QSGMII_AUTO_EXP        6
+#define PHY_REG_QSGMII_CONTROL_1                       16
+#define PHY_REG_QSGMII_STATUS_1                                17
+#define PHY_REG_QSGMII_INT_ENABLE                      18
+#define PHY_REG_QSGMII_STATUS_2                                19
+#define PHY_REG_QSGMII_RX_ER_BYTE_CAPT         20
+#define PHY_REG_QSGMII_RX_ER_COUNTER           21
+#define PHY_REG_QSGMII_PRBS_CTRL                       23
+#define PHY_REG_QSGMII_PRBS_ERR_COUNT_LSB   24
+#define PHY_REG_QSGMII_PRBS_ERR_COUNT_MSB   25
+#define PHY_REG_QSGMII_GLOBAL_CTRL_1           26
+#define PHY_REG_QSGMII_GLOBAL_CTRL_2           27
+
+/* Page 5 */
+#define PHY_REG_MDI0_VCT_STATUS     16
+#define PHY_REG_MDI1_VCT_STATUS     17
+#define PHY_REG_MDI2_VCT_STATUS     18
+#define PHY_REG_MDI3_VCT_STATUS     19
+#define PHY_REG_PAIR_SKEW_STATUS    20
+#define PHY_REG_PAIR_SWAP_STATUS    21
+#define PHY_REG_ADV_VCT_CONTROL_5      23
+#define PHY_REG_ADV_VCT_SMPL_DIST      24
+#define PHY_REG_ADV_VCT_X_PAIR_PTHR    25
+#define PHY_REG_ADV_VCT_SMPAIR_PTHR_01 26
+#define PHY_REG_ADV_VCT_SMPAIR_PTHR_23 27
+#define PHY_REG_ADV_VCT_SMPAIR_PTHR_4_P        28
+
+/* Page 6 */
+#define PHY_REG_PACKET_GENERATION   16
+#define PHY_REG_CRC_COUNTERS        17
+#define PHY_REG_CHECK_CONTROL       18
+#define PHY_REG_GENERAL_CONTROL                20
+#define PHY_REG_LATE_COLIS_CNT_12   23
+#define PHY_REG_LATE_COLIS_CNT_34   24
+#define PHY_REG_LATE_COLIS_WIN_ADJ  25
+#define PHY_REG_MISC_TEST           26
+
+/* Page 7 */
+#define PHY_REG_PHY_CBL_DIAG_0_LEN   16
+#define PHY_REG_PHY_CBL_DIAG_1_LEN   17
+#define PHY_REG_PHY_CBL_DIAG_2_LEN   18
+#define PHY_REG_PHY_CBL_DIAG_3_LEN   19
+#define PHY_REG_PHY_CBL_DIAG_RESULT  20
+#define PHY_REG_PHY_CBL_DIAG_CTRL    21
+#define PHY_REG_ADV_VCT_XPAIR_NTHR             25
+#define PHY_REG_ADV_VCT_SMPAIR_NTHR_01 26
+#define PHY_REG_ADV_VCT_SMPAIR_NTHR_23 27
+#define PHY_REG_ADV_VCT_SMPAIR_NTHR_4_P        28
+
+/* Page 8, PTP */
+#define PHY_REG_PTP_PORT_CONFIG_0              0
+#define PHY_REG_PTP_PORT_CONFIG_1              1
+#define PHY_REG_PTP_PORT_CONFIG_2              2
+#define PHY_REG_PTP_ARR0_PORT_STATUS   8
+#define PHY_REG_PTP_TIME_ARR0_01               9
+#define PHY_REG_PTP_TIME_ARR0_23               10
+#define PHY_REG_PTP_TIME_ARR0_SEQID            11
+#define PHY_REG_PTP_ARR1_PORT_STATUS   12
+#define PHY_REG_PTP_TIME_ARR1_01               13
+#define PHY_REG_PTP_TIME_ARR1_23               14
+#define PHY_REG_PTP_TIME_ARR1_SEQID            15
+
+/* Page 8, Advanced VCT */
+#define PHY_REG_ADV_VCT_CONTROL_8              20
+
+/* Page 9, PTP */
+#define PHY_REG_PTP_DEP_PORT_STATUS            0
+#define PHY_REG_PTP_TIME_DEP_01                        1
+#define PHY_REG_PTP_TIME_DEP_23                        2
+#define PHY_REG_PTP_TIME_DEP_SEQID             3
+#define PHY_REG_PTP_PORT_STATUS                        5
+
+/* Page 11, LinkCript  */
+#define PHY_REG_LINKCRYPT_READ_ADDR            0
+#define PHY_REG_LINKCRYPT_WRITE_ADDR   1
+#define PHY_REG_LINKCRYPT_DATA_LO              2
+#define PHY_REG_LINKCRYPT_DATA_HI              3
+
+/* Page 12, TAI Global Config  */
+#define PHY_REG_TAI_CONFIG_0                   0
+#define PHY_REG_TAI_CONFIG_1                   1
+#define PHY_REG_TAI_CONFIG_2                   2
+#define PHY_REG_TAI_CONFIG_3                   3
+#define PHY_REG_TAI_CONFIG_4                   4
+#define PHY_REG_TAI_CONFIG_5                   5
+#define PHY_REG_TAI_CONFIG_8                   8
+#define PHY_REG_TAI_CONFIG_9                   9
+#define PHY_REG_TAI_CONFIG_10                  10
+#define PHY_REG_TAI_CONFIG_11                  11
+#define PHY_REG_TAI_CONFIG_12                  12
+#define PHY_REG_TAI_CONFIG_13                  13
+#define PHY_REG_TAI_CONFIG_14                  14
+#define PHY_REG_TAI_CONFIG_15                  15
+
+/* Bit Definition for PHY_REG_CONTROL */
+#define PHY_REG_CTRL_RESET          0x8000
+#define PHY_REG_CTRL_LOOPBACK       0x4000
+#define PHY_REG_CTRL_SPEED          0x2000
+#define PHY_REG_CTRL_AUTONEGO       0x1000
+#define PHY_REG_CTRL_POWER          0x800
+#define PHY_REG_CTRL_ISOLATE        0x400
+#define PHY_REG_CTRL_RESTART_AUTONEGO   0x200
+#define PHY_REG_CTRL_DUPLEX         0x100
+#define PHY_REG_CTRL_SPEED_MSB      0x40
+
+#define PHY_REG_CTRL_POWER_BIT              11
+#define PHY_REG_CTRL_RESTART_AUTONEGO_BIT   9
+
+/* Bit Definition for PHY_REG_AUTO_AD */
+#define PHY_REG_AUTO_AD_NEXTPAGE        0x8000
+#define PHY_REG_AUTO_AD_REMOTEFAULT     0x4000
+#define PHY_REG_AUTO_AD_ASYM_PAUSE      0x800
+#define PHY_REG_AUTO_AD_PAUSE           0x400
+#define PHY_REG_AUTO_AD_100_FULL        0x100
+#define PHY_REG_AUTO_AD_100_HALF        0x80
+#define PHY_REG_AUTO_AD_10_FULL         0x40
+#define PHY_REG_AUTO_AD_10_HALF         0x20
+
+/* Bit Definition for PHY_REG_1000_CONTROL */
+#define PHY_REG_MS_MANUAL_CONFIG    0x1000
+#define PHY_REG_MS_CONFIG_VALUE     0x800
+#define PHY_REG_MS_PORT_TYPE        0x400
+#define PHY_REG_1000T_FULL          0x200
+#define PHY_REG_1000T_HALF          0x100
+
+/* Bit definition for PHY_REG_COPPER_INT_ENABLE */
+#define PHY_REG_INT_AUTO_NEGO_ERROR     0x8000
+#define PHY_REG_INT_SPEED_CHANGED       0x4000
+#define PHY_REG_INT_DUPLEX_CHANGED      0x2000
+#define PHY_REG_INT_PAGE_RECEIVED       0x1000
+#define PHY_REG_INT_AUTO_NEG_COMPLETED  0x800
+#define PHY_REG_INT_LINK_STATUS_CHANGED 0x400
+#define PHY_REG_INT_SYMBOL_ERROR        0x200
+#define PHY_REG_INT_FALSE_CARRIER       0x100
+#define PHY_REG_INT_CROSSOVER_CHANGED   0x40
+#define PHY_REG_INT_DOWNSHIFT           0x20
+#define PHY_REG_INT_ENERGY_DETECT       0x10
+#define PHY_REG_INT_DTE_DETECT_CHANGED  0x4
+#define PHY_REG_INT_POLARITY_CHANGED    0x2
+#define PHY_REG_INT_JABBER              0x1
+
+/* Bit definition for PHY_REG_MAC_INT_ENABLE */
+#define PHY_REG_MAC_INT_FIFO_ERROR      0x80
+
+#endif /* __PHYREGS_H__ */

diff --git a/post/src/evmc665x_emac.c b/post/src/evmc665x_emac.c
new file mode 100644 (file)
index 0000000..96ec9ec
--- /dev/null
+++ b/post/src/evmc665x_emac.c
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * Copyright (c) 2011-2012 Texas Instruments Incorporated - http://www.ti.com
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:          evm665x_emac.c
+ *
+ * Description:        This file contains the EMAC initialization API
+ * 
+ ******************************************************************************/
+
+/************************
+ * Include Files
+ ************************/
+#ifdef _EVMC6657L_
+#include <stdio.h>
+#include <stdint.h>
+#include <evmc665x_emac.h>
+#include <cslr_psc.h>
+#include <csl_bootCfgAux.h>
+#include <csl_pscAux.h>
+#include <string.h>
+
+
+EMAC_MCB emac_mcb;
+volatile Uint8 rxbuff[RX_BUFF_SIZE];
+
+
+Uint32 EMAC_init()
+{
+       volatile Uint32* pRegAddr;
+       uint32_t i = 0;
+       uint32_t mac_addr2, mac_addr1;
+#if 0
+    uint32_t     power_domain_num          = 0;
+    uint32_t     mdctl_emac_module_num     = 3;
+    uint32_t     mdstat_emac_module_num    = 3;
+    CSL_PSC_MODSTATE mdstat;
+
+       /* EMAC clock domain enable */
+       CSL_PSC_enablePowerDomain(power_domain_num);
+       CSL_PSC_setModuleNextState (mdctl_emac_module_num, PSC_MODSTATE_ENABLE);
+
+       /* start the process and wait. but timeout in 1000 loops. */
+       CSL_PSC_startStateTransition(power_domain_num);
+       while(((CSL_PSC_isStateTransitionDone (power_domain_num)) != 0) && (i < 1000)) {
+               i++;
+       }
+
+       mdstat = CSL_PSC_getModuleState(mdstat_emac_module_num);
+       /* report result. */
+       if (mdstat != PSC_MODSTATE_ENABLE) {
+          return 1; /* Could not enable the PSC Module */
+       }
+#endif
+       CSL_BootCfgGetMacIdentifier(&mac_addr1, &mac_addr2);
+
+       /* Reset MAC */
+       EMAC_REGS->SOFTRESET = 0x01;
+       while(EMAC_REGS->SOFTRESET != 0);
+
+       /* Reset MAC Control */
+       EMAC_REGS->MACCONTROL = 0x0;
+
+       /* Init HDPs to NULL */
+       pRegAddr = &EMAC_REGS->TX0HDP;
+       for(i = 0; i < 8; i++)
+               *pRegAddr++ = 0;
+
+       pRegAddr = &EMAC_REGS->RX0HDP;
+       for(i = 0; i < 8; i++)
+               *pRegAddr++ = 0;
+
+       /* Init CPs to NULL */
+       pRegAddr = &EMAC_REGS->TX0CP;
+       for(i = 0; i < 8; i++)
+               *pRegAddr++ = 0;
+
+       pRegAddr = &EMAC_REGS->RX0CP;
+       for(i = 0; i < 8; i++)
+               *pRegAddr++ = 0;
+
+       /* Init MAC Addresses */
+       for(i = 0; i < 32; i++)
+       {
+               EMAC_REGS->MACINDEX = i;
+               EMAC_REGS->MACADDRHI = 0;
+               EMAC_REGS->MACADDRLO = 0;
+       }
+
+       /* Setup MAC Address for Channel 0 */
+       EMAC_REGS->MACINDEX = 0;
+       EMAC_REGS->MACADDRHI = ((mac_addr1 & 0x00ff0000) << 8)
+                       | ((mac_addr1 & 0xff000000) >> 8)
+                       | ((mac_addr2 & 0x000000ff) << 8)
+                       | ((mac_addr2 & 0x0000ff00) >> 8);
+
+       EMAC_REGS->MACADDRLO = CSL_FMK(EMAC_MACADDRLO_VALID, 1)
+                       | CSL_FMK(EMAC_MACADDRLO_MATCHFILT, 1)
+                       | ((mac_addr1 & 0x000000ff) << 8)
+                       | ((mac_addr1 & 0x0000ff00) >> 8);
+
+       /* Setup MAC Address for Channel 0 */
+       EMAC_REGS->MACINDEX = 0;
+       EMAC_REGS->MACADDRHI = ((mac_addr1 & 0x00ff0000) << 8)
+                       | ((mac_addr1 & 0xff000000) >> 8)
+                       | ((mac_addr2 & 0x000000ff) << 8)
+                       | ((mac_addr2 & 0x0000ff00) >> 8);
+
+       EMAC_REGS->MACADDRLO = CSL_FMK(EMAC_MACADDRLO_VALID, 1)
+                       | CSL_FMK(EMAC_MACADDRLO_MATCHFILT, 1)
+                       | ((mac_addr1 & 0x000000ff) << 8)
+                       | ((mac_addr1 & 0x0000ff00) >> 8);
+
+       printf("macaddress: %02X:%02X:%02X:%02X:%02X:%02X\n",
+                       ((mac_addr2 & 0x0000ff00) >> 8),
+                       (mac_addr2 & 0x000000ff),
+                       ((mac_addr1 & 0xff000000) >> 24),
+                       ((mac_addr1 & 0x00ff0000) >> 16),
+                       ((mac_addr1 & 0x0000ff00) >> 8),
+                       (mac_addr1 & 0x000000ff));
+
+       EMAC_REGS->RXBUFFEROFFSET = 0;
+
+       EMAC_REGS->RXMBPENABLE = 0;
+       EMAC_REGS->MACHASH1 = 0;
+       EMAC_REGS->MACHASH2 = 0;
+
+       /* Clear Unicast RX on channel 0-7 */
+       EMAC_REGS->RXUNICASTCLEAR = 0xff;
+
+       /* Disable all interrupts */
+       EMAC_REGS->RXINTMASKCLEAR = 0xFF;
+       EMAC_REGS->TXINTMASKCLEAR = 0xFF;
+       EMAC_REGS->MACINTMASKCLEAR = 0x0;
+
+       /* Set TX descriptor address */
+       /* Use CPPI Ram for buffer descriptor and buffer */
+       emac_mcb.tx_desc = (EMAC_Desc *)TX_DESC_ADD(0);
+       /* setup TX descriptor */
+       emac_mcb.tx_desc->pNext = 0;
+       emac_mcb.tx_desc->pBuffer = 0;
+       emac_mcb.tx_desc->BufOffLen = 0;
+       emac_mcb.tx_desc->PktFlgLen = 0;
+
+       /* Set RX descriptor address */
+       /* Use CPPI Ram for buffer descriptor and buffer */
+       emac_mcb.rx_desc = (EMAC_Desc *)RX_DESC_ADD(0);
+       /* setup RX descriptor */
+       emac_mcb.rx_desc->pNext = 0;
+       emac_mcb.rx_desc->pBuffer = (Uint8 *)RX_BUFF_ADD(0);
+       emac_mcb.rx_desc->BufOffLen = RX_BUFF_SIZE;
+       emac_mcb.rx_desc->PktFlgLen = EMAC_DSC_FLAG_OWNER;
+
+       /* Enable RX and TX for channel 0 */
+       EMAC_REGS->TXCONTROL = 0x01;
+       EMAC_REGS->RXCONTROL = 0x01;
+
+       EMAC_REGS->MACCONTROL = ( 1 << 18)      /* EXT_EN */
+                       | ( 0 << 9 )                    /* Round robin */
+                       | ( 1 << 7 )            /* GIG */
+                       | ( 0 << 6 )            /* TX pacing disabled */
+                       | ( 1 << 5 )            /* GMII RX & TX */
+                       | ( 0 << 4 )            /* TX flow disabled */
+                       | ( 0 << 3 )            /* RX flow disabled */
+                       | ( 0 << 1 )            /* Loopback enabled */
+                       | ( 1 << 0 );           /* full duplex */
+
+       /* Start RX for channel 0 */
+       EMAC_REGS->RX0HDP = (Uint32) emac_mcb.rx_desc;
+       emac_mcb.lastrxhdp = (Uint32) emac_mcb.rx_desc;
+
+       /* Enable RX Filter for Channel 0 */
+       EMAC_REGS->RXUNICASTSET = 0x01;
+
+       /* Enable receive for all broadcast packet */
+       EMAC_REGS->RXMBPENABLE = CSL_FMK(EMAC_RXMBPENABLE_RXBROADEN, 1);
+
+       return 0;
+}
+
+Int32 EMAC_Send(Uint8 *buff, int len)
+{
+       volatile EMAC_Desc *pDesc;
+
+       /* minimum 64 bytes required */
+       if (len < 64)
+               len = 64;
+
+       /* setup descriptor for transmission */
+       emac_mcb.tx_desc->pNext = 0;
+       emac_mcb.tx_desc->BufOffLen = len;
+       emac_mcb.tx_desc->pBuffer = (Uint8 *)TX_BUFF_ADD;
+       memcpy(emac_mcb.tx_desc->pBuffer, buff, len);
+       emac_mcb.tx_desc->PktFlgLen = EMAC_DSC_FLAG_SOP | EMAC_DSC_FLAG_EOP | EMAC_DSC_FLAG_OWNER | len;
+
+       /* send packet */
+       EMAC_REGS->TX0HDP = (Uint32)emac_mcb.tx_desc;
+
+       /* wait for TX complete */
+       do {
+               pDesc = (EMAC_Desc *)EMAC_REGS->TX0CP;
+       } while(pDesc->PktFlgLen & EMAC_DSC_FLAG_OWNER);
+
+       /* return no. of bytes transmitted */
+       return len;
+}
+
+Int32 EMAC_Recv(Uint8 *buff)
+{
+       EMAC_Desc *pDesc;
+       int recv_bytes = 0;
+
+       /* check for new packet */
+       if(emac_mcb.lastrxhdp == (Uint32)EMAC_REGS->RX0HDP)
+               return 0;
+
+       pDesc = (EMAC_Desc *)EMAC_REGS->RX0CP;
+       if (pDesc->PktFlgLen & EMAC_DSC_FLAG_SOP) {
+               /* Acknowledge recevied packet */
+               EMAC_REGS->RX0CP = (Uint32)pDesc;
+
+               /* store bytes recevied */
+               recv_bytes = pDesc->PktFlgLen & 0xFFFF;
+
+               /* copy data to output buffer */
+               memcpy(buff, pDesc->pBuffer, recv_bytes);
+
+               /* re-initalize descriptor to recevie more data */
+               pDesc->BufOffLen = RX_BUFF_SIZE;
+               pDesc->PktFlgLen = EMAC_DSC_FLAG_OWNER;
+
+               /* assign descriptor to HDP */
+               EMAC_REGS->RX0HDP = (Uint32)pDesc;
+       }
+
+       /* return number of bytes received */
+       return recv_bytes;
+}
+#endif

diff --git a/post/src/evmc665x_sgmii.c b/post/src/evmc665x_sgmii.c
new file mode 100644 (file)
index 0000000..fc88e56
--- /dev/null
+++ b/post/src/evmc665x_sgmii.c
@@ -0,0 +1,228 @@
+/******************************************************************************
+ * Copyright (c) 2011-2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/******************************************************************************
+ *
+ * File Name:          evm665x_sgmii.c
+ *
+ * Description:        This file contains the SGMII initialization API
+ *
+ ******************************************************************************/
+
+#ifdef _EVMC6657L_
+#include "platform.h"
+#include <csl_sgmii.h>
+/************************
+ * Defines and Macros
+ ************************/
+
+#ifndef CSL_EMAC_0_REGS
+#define CSL_EMAC_0_REGS                        (CSL_EMAC_SS_CFG_REGS)
+#endif
+
+#ifndef CSL_MDIO_0_REGS
+#define CSL_MDIO_0_REGS                        (CSL_EMAC_SS_CFG_REGS + 0x0800)
+#endif
+
+#ifndef CSL_SGMII_0_REGS
+#define CSL_SGMII_0_REGS               (CSL_EMAC_SS_CFG_REGS + 0x0900)
+#endif
+
+#define EMAC_RAM_BASE                  (CSL_EMAC_SS_CFG_REGS + 0x2000)
+#define EMAC_RAM_LEN                   (0x00002000u)
+
+/* MTU Size */
+#define MAX_MTU_SIZE   1536
+
+/* TX & RX Descriptor setup */
+#define DESC_SIZE              sizeof(EMAC_Desc)
+#define TX_DESC_START  EMAC_RAM_BASE
+#define TX_DESC_COUNT  1
+#define TX_DESC_ADD(x) (TX_DESC_START + (DESC_SIZE * x))
+#define TX_DESC_END            (TX_DESC_START + (DESC_SIZE * TX_DESC_COUNT))
+#define RX_DESC_START  TX_DESC_END
+#define RX_DESC_COUNT  1
+#define RX_DESC_ADD(x) (RX_DESC_START + (DESC_SIZE * x))
+#define RX_DESC_END            (RX_DESC_START + (DESC_SIZE * RX_DESC_COUNT))
+#define RX_BUFF_SIZE   MAX_MTU_SIZE
+#define RX_BUFF_START  RX_DESC_END
+#define RX_BUFF_ADD(x) (RX_BUFF_START + (RX_BUFF_SIZE * x))
+#define RX_BUFF_END            (RX_BUFF_START + (RX_BUFF_SIZE * RX_DESC_COUNT))
+#define TX_BUFF_ADD            RX_BUFF_END
+
+
+#define SGMII_SERDES_STS                       (*(unsigned int*)(CSL_BOOT_CFG_REGS + 0x158))
+
+
+static SGMII_delay(int delay)
+{
+       while(--delay);
+}
+
+Uint32 SGMII_reset ()
+{
+       int timeout = 10000;
+       CSL_FINS(SGMII_REGS->SOFT_RESET, SGMII_SOFT_RESET_SOFT_RESET, 1);
+
+       while(--timeout && CSL_FEXT(SGMII_REGS->SOFT_RESET, SGMII_SOFT_RESET_SOFT_RESET));
+
+       return 0;
+}
+
+Uint32 SGMII_config (SGMII_Config *config)
+{
+       int timeout;
+
+       if(!config)
+               return SGMII_ERROR_INVALID;
+
+       timeout = 10000;
+       while(--timeout && !(SGMII_REGS->STATUS & SGMII_STATUS_LOCK))
+               SGMII_delay(1000);
+
+       SGMII_REGS->CONTROL = 0;
+       if(config->loopbackEn) {
+               CSL_FINS(SGMII_REGS->CONTROL, SGMII_CONTROL_MR_AN_ENABLE, 0);
+               CSL_FINS(SGMII_REGS->CONTROL, SGMII_CONTROL_MASTER, 1);
+               CSL_FINS(SGMII_REGS->CONTROL, SGMII_CONTROL_LOOPBACK, config->loopbackEn);
+       } else {
+               CSL_FINS(SGMII_REGS->SOFT_RESET, SGMII_SOFT_RESET_RT_SOFT_RESET, 1);
+               if((config->masterEn) && (config->modeOfOperation == SGMII_MODE_OF_OPERATION_WITH_AN)) {
+                       CSL_FINS(SGMII_REGS->CONTROL, SGMII_CONTROL_MASTER, 1);
+                       CSL_FINS(SGMII_REGS->CONTROL, SGMII_CONTROL_MR_AN_ENABLE, 1);
+                       SGMII_REGS->MR_ADV_ABILITY = 0x01;
+               } else if((config->masterEn) && (config->modeOfOperation == SGMII_MODE_OF_OPERATION_WITHOUT_AN)) {
+                       CSL_FINS(SGMII_REGS->CONTROL, SGMII_CONTROL_MASTER, 1);
+                       CSL_FINS(SGMII_REGS->CONTROL, SGMII_CONTROL_MR_AN_ENABLE, 0);
+                       SGMII_REGS->MR_ADV_ABILITY = 0x9801;
+               } else {
+                       CSL_FINS(SGMII_REGS->CONTROL, SGMII_CONTROL_MASTER, 0);
+                       CSL_FINS(SGMII_REGS->CONTROL, SGMII_CONTROL_MR_AN_ENABLE, 1);
+                       SGMII_REGS->MR_ADV_ABILITY = 0x1;
+               }
+               CSL_FINS(SGMII_REGS->SOFT_RESET, SGMII_SOFT_RESET_RT_SOFT_RESET, 0);
+       }
+
+       SGMII_REGS->TX_CFG = config->txConfig;
+       SGMII_REGS->RX_CFG = config->rxConfig;
+       SGMII_REGS->AUX_CFG = config->auxConfig;
+
+       return 0;
+}
+
+Uint32 SGMII_getStatus (SGMII_Status *pStatus)
+{
+       if(!pStatus)
+               return SGMII_ERROR_INVALID;
+
+       pStatus->txCfgStatus = SGMII_REGS->TX_CFG;
+       pStatus->rxCfgStatus = SGMII_REGS->RX_CFG;
+       pStatus->auxCfgStatus = SGMII_REGS->AUX_CFG;
+
+       return 0;
+}
+
+Uint32 SGMII_getLinkStatus ()
+{
+       int timeout = 1000;
+       while(--timeout && !(SGMII_REGS->STATUS & SGMII_STATUS_LOCK))
+               SGMII_delay(1000);
+       if(!timeout)
+               return SGMII_ERROR_DEVICE;
+
+       timeout = 1000;
+       while(--timeout && !(timeout & SGMII_STATUS_LINK)) {
+               SGMII_delay(1000);
+       }
+
+       if(SGMII_REGS->STATUS & SGMII_STATUS_LINK)
+               return 1;
+       else
+               return 0;
+}
+
+Uint32 SGMII_getLinkPartnerStatus ()
+{
+       int timeout = 1000;
+       while(--timeout && !(SGMII_REGS->STATUS & SGMII_STATUS_LOCK))
+               SGMII_delay(1000);
+       if(!timeout)
+               return SGMII_ERROR_DEVICE;
+
+       if(SGMII_REGS->STATUS & SGMII_STATUS_MR_AN_COMPLTE)
+               return 1;
+       else
+               return 0;
+}
+
+Uint32 SGMII_getAnErrorStatus ()
+{
+       int timeout = 1000;
+       while(--timeout && !(SGMII_REGS->STATUS & SGMII_STATUS_LOCK))
+               SGMII_delay(1000);
+       if(!timeout)
+               return SGMII_ERROR_DEVICE;
+
+       if(SGMII_REGS->STATUS & SGMII_STATUS_AN_ERROR)
+               return 1;
+       else
+               return 0;
+}
+
+Uint32 SGMII_getStatusReg ()
+{
+       return SGMII_REGS->STATUS;
+}
+
+Uint32 sgmii_init()
+{
+       SGMII_Config sgmii_config;
+
+       sgmii_config.loopbackEn = 0;
+       sgmii_config.masterEn = 0;
+       sgmii_config.modeOfOperation = SGMII_MODE_OF_OPERATION_WITH_AN;
+
+       sgmii_config.txConfig = 0x108A1;
+       sgmii_config.rxConfig = 0x00700611;
+       sgmii_config.auxConfig = 0x51;
+
+       SGMII_reset();
+
+       SGMII_REGS->CONTROL = 0;
+
+       SGMII_config(&sgmii_config);
+
+       /* link status */
+       return !SGMII_getLinkStatus();
+}
+#endif

diff --git a/post/src/post.c b/post/src/post.c
index d607ac200441a7171bc0ed38fa43c4c6f4180690..cfa6c494a8d9f28857fe4a71c439bdb91fec3aee 100644 (file)
--- a/post/src/post.c
+++ b/post/src/post.c
@@ -1,5 +1,5 @@
 /******************************************************************************
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2011-12 Texas Instruments Incorporated - http://www.ti.com
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions
@@ -35,20 +35,32 @@
 #include "platform.h"
 #include "types.h"
 #include "post.h"
-#include "net.h"
-#include "cpmacdrv.h"
 #include "target.h"
-#include "qm_api.h"
-#include "cpdma_api.h"
 #include "pscapi.h"
 
+#if !(defined(_EVMC6657L_))
+  #include "net.h"
+  #include "cpmacdrv.h"
+  #include "qm_api.h"
+  #include "cpdma_api.h"
+#else
+  #include "evmc665x_phy.h"
+  #include "evmc665x_emac.h"
+#endif
+
 /* CSL EMAC include */
-#include <ti/csl/csl_cpsw.h>
-#include <ti/csl/csl_cpsgmii.h>
-#include <ti/csl/csl_cpsgmiiAux.h>
-#include <ti/csl/cslr_cpsgmii.h>
+#if !(defined(_EVMC6657L_))
+  #include <ti/csl/csl_cpsw.h>
+  #include <ti/csl/csl_cpsgmii.h>
+  #include <ti/csl/csl_cpsgmiiAux.h>
+  #include <ti/csl/cslr_cpsgmii.h>
+  #include <ti/csl/csl_mdioAux.h>
+#else
+  #include <ti/csl/csl_sgmii.h>
+  #include <ti/csl/cslr_sgmii.h>
+#endif
+
 #include <ti/csl/csl_mdio.h>
-#include <ti/csl/csl_mdioAux.h>
 
 /* BootCfg module include */
 #include <ti/csl/csl_bootcfg.h>
@@ -318,14 +330,29 @@ post_test_nor
     platform_device_close(p_device->handle);
     return test_result;
 }
+#if !(defined(_EVMC6657L_))
+  /** Number of ports in the ethernet subsystem */
+  #define         NUM_PORTS                   3u
+
+  /** Number of MAC/GMII ports in the ethernet switch */
+  #define         NUM_MAC_PORTS               2u
+
+
+#else
+  /** Number of ports in the ethernet subsystem */
+  #define         NUM_PORTS                   1u
+
+  /** Number of MAC/GMII ports in the ethernet switch */
+  #define         NUM_MAC_PORTS               1u
 
-/** Number of ports in the ethernet subsystem */
-#define         NUM_PORTS                   3u
+#endif
 
-/** Number of MAC/GMII ports in the ethernet switch */
-#define         NUM_MAC_PORTS               2u
+/*Define LoopBack Mode for C6657*/
+#define MAC_LOOPBACK                    (1 << 0)
+#define EXT_COPPER_LOOPBACK             (1 << 3)
+#define EXT_FIBER_LOOPBACK              (1 << 4)
 
-/* Define LoopBack modes */
+/* Define LoopBack modes for C6678 & C6670*/
 #define CPSW_LOOPBACK_NONE           0
 #define CPSW_LOOPBACK_INTERNAL       1
 #define CPSW_LOOPBACK_EXTERNAL       2
@@ -334,11 +361,13 @@ post_test_nor
 int32_t cpswSimTest = 1;
 int32_t cpswLpbkMode = CPSW_LOOPBACK_EXTERNAL;
 #else
+int32_t LpbkMode = EXT_COPPER_LOOPBACK;
 int32_t cpswSimTest = 0;
 int32_t cpswLpbkMode = CPSW_LOOPBACK_INTERNAL;
 #endif
 int32_t cpswEvm6678 = 0;
 
+#if !(defined(_EVMC6657L_))
 /** ============================================================================
  *   @n@b Init_SGMII
  *
@@ -660,6 +689,7 @@ int32_t Init_Cpsw (void)
     return 0;
 }
 
+#endif
 
 /******************************************************************************
  * Function:    post_test_emac_loopback
@@ -671,25 +701,30 @@ post_test_emac_loopback
 )
 {
     uint8_t   test_buf[POST_EMAC_TEST_PKT_LENGTH+14];
+#if (defined(_EVMC6657L_))
+    SGMII_Config config;
+    uint8_t mac_address[6];
+#endif
+
+#if !(defined(_EVMC6657L_))
     uint8_t   sw_port0_mac_addr[6] = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15};
     uint8_t   mac_address[6];
+    uint8_t            ret;
     NET_DRV_DEVICE nDevice;
-    uint32_t modNum;
-    int32_t  ret;
+#endif
+
 
-    /* Note that if the sgmii power enable is requested the PA must be
-     * powered up first */
-    modNum = 8;
+#if !(defined(_EVMC6657L_))
+    int modNum = 8;
     if (modNum == TARGET_PWR_ETH(x))  {
         ret = (int32_t)pscEnableModule (TARGET_PWR_PA);
         if (ret != 0)
             return (POST_TEST_RESULT_FAILED);
     }
+#endif
 
-    ret = (int32_t)pscEnableModule(modNum);
-    if (ret != 0)
-        return (POST_TEST_RESULT_FAILED);
 
+#if !(defined(_EVMC6657L_))
     Init_Cpsw();
 
     /* Queue manager configuration */
@@ -744,6 +779,35 @@ post_test_emac_loopback
         return POST_TEST_RESULT_FAILED;
     }
 
+#else
+    sgmii_init();
+    EMAC_init();
+    config.loopbackEn = 1;
+    SGMII_config(&config);
+
+    platform_get_macaddr(PLATFORM_MAC_TYPE_EFUSE, mac_address);
+
+    /* Set the dest MAC address to be broadcast, so that PA firmware will not filter out */
+    memset(test_buf, 0xff, 6);
+    memcpy(&test_buf[6], mac_address, 6);
+
+    /* set the payload length to 256 bytes */
+    test_buf[12] = 0x01;
+    test_buf[13] = 0x00;
+
+    if(EMAC_Send(test_buf, POST_EMAC_TEST_PKT_LENGTH+14) < 0)
+    {
+        return POST_TEST_RESULT_FAILED;
+    }
+
+    platform_delay(1000);
+
+    if(EMAC_Recv(test_buf) < 0)
+    {
+        return POST_TEST_RESULT_FAILED;
+    }
+
+#endif
     return POST_TEST_RESULT_PASSED;
 }
 
@@ -909,7 +973,7 @@ main
 (
     void
 )
-{
+ {
     platform_init_flags     init_flags;
     platform_init_config    init_config;
     POST_TEST_ID            test_id = POST_TEST_IN_PROGRESS;
@@ -919,7 +983,9 @@ main
     char                    msg[9];
     uint8_t                 mac_addr[6];
     platform_info           info;
+#if !(defined(_EVMC6657L_)||defined(_EVMC6655L_))
     uint32_t                sa_enable;
+#endif
     uint32_t                acc_fail;
     extern uint32_t platform_init_return_code;
 
@@ -927,7 +993,7 @@ main
     memset(&init_config, 0, sizeof(platform_init_config));
     memset(&init_flags, 0x01, sizeof(platform_init_flags));
 
-    init_flags.phy = 0;
+    init_flags.phy = 1;
     acc_fail = 0;
 
     /* Initialize the platform */
@@ -994,7 +1060,7 @@ main
             msg[3] = 0;
             post_write_uart(msg);
         }
-
+#if !(defined(_EVMC6657L_)||defined(_EVMC6655L_))
         sa_enable = *(volatile uint32_t *)0x20c0004;
         sa_enable &= 0x1;
 
@@ -1006,6 +1072,7 @@ main
         {
             post_write_uart("\r\n\rSA is disabled on this board.");
         }
+#endif
         /* Read the PLL Reset Type Status register and display on UART */
         reset_type = PLL_CTRL_REG_RSTYPE;
         post_hex_to_string(reset_type, 8, msg);

diff --git a/writer/nand/include/types.h b/writer/nand/include/types.h
index 6fc66481c44deaac1575e0a82a2559181ef3ad44..b8bd85c7eaa34f2231a41eede683438633269795 100644 (file)
--- a/writer/nand/include/types.h
+++ b/writer/nand/include/types.h
@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
  *
  *
  *  Redistribution and use in source and binary forms, with or without

diff --git a/writer/nand/src/nandwriter.c b/writer/nand/src/nandwriter.c
index 69f3fc086548021e0716b5c8914baa329ea73cde..09897f25d9a133657a436967b9a7f13ac7c2503a 100644 (file)
--- a/writer/nand/src/nandwriter.c
+++ b/writer/nand/src/nandwriter.c
@@ -1,5 +1,5 @@
 /******************************************************************************
- * Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com
+ * Copyright (c) 2011-2012 Texas Instruments Incorporated - http://www.ti.com
  * 
  *  Redistribution and use in source and binary forms, with or without 
  *  modification, are permitted provided that the following conditions 
@@ -47,7 +47,7 @@
 #include "types.h"
 
 /* NAND writer utility version */
-char version[] = "01.00.00.04";
+char version[] = "01.00.00.00";
 
 /* The input file name is hard coded */
 char *input_file = "nand_writer_input.txt";
@@ -530,8 +530,11 @@ void main ()
         print_platform_errno();
         return;
     }
-
+#if !(defined(_EVMC6657L_))
     p_device = platform_device_open(PLATFORM_DEVID_NAND512R3A2D, 0);
+#else
+    p_device = platform_device_open(PLATFORM_DEVID_MT29F1G08ABCHC, 0);
+#endif
     if (p_device == NULL) 
     {
         printf ("NAND device open failed!\n");

diff --git a/writer/nor/include/types.h b/writer/nor/include/types.h
index 6fc66481c44deaac1575e0a82a2559181ef3ad44..b8bd85c7eaa34f2231a41eede683438633269795 100644 (file)
--- a/writer/nor/include/types.h
+++ b/writer/nor/include/types.h
@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
  *
  *
  *  Redistribution and use in source and binary forms, with or without

diff --git a/writer/nor/src/norwriter.c b/writer/nor/src/norwriter.c
index 271b4bcb1fd15d7763c14dfee42a3f4535d63a5c..e095030e1c6dc84ffa3b6de66ef5d64d449f5b5e 100644 (file)
--- a/writer/nor/src/norwriter.c
+++ b/writer/nor/src/norwriter.c
@@ -439,8 +439,11 @@ void main ()
         print_platform_errno();
         return;
     }
-
+#if !(defined(_EVMC6657L_))
     p_device = platform_device_open(PLATFORM_DEVID_NORN25Q128, 0);
+#else
+    p_device = platform_device_open(PLATFORM_DEVID_NORN25Q032A, 0);
+#endif
     if (p_device == NULL)
     {
         printf ("NOR device open failed!\n");