1 /************************************************
2 * FILE: netapi_init.c
3 * Global, local initialization of NETAPI
4 *
5 * DESCRIPTION: Functions to initialize framework resources for running NETAPI
6 *
7 * REVISION HISTORY:
8 *
9 * Copyright (c) Texas Instruments Incorporated 2010-2011
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the
21 * distribution.
22 *
23 * Neither the name of Texas Instruments Incorporated nor the names of
24 * its contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ***********************************************/
40 #include <stdint.h>
41 #include <stdio.h>
42 #include <string.h>
43 #include <sys/types.h>
44 #include <sys/stat.h>
45 #include <fcntl.h>
46 #include <sys/mman.h>
47 #include <errno.h>
48 #include <unistd.h>
50 #include <ti/drv/nwal/nwal.h>
51 #include "netapi.h"
52 #include "netapi_vm.h"
53 #include "netapi_loc.h"
54 #include "ti/drv/nwal/nwal.h"
56 /* CSL RL includes */
57 #include <ti/csl/cslr_device.h>
58 #include <ti/csl/cslr_qm_config.h>
59 #include <ti/csl/cslr_qm_descriptor_region_config.h>
60 #include <ti/csl/cslr_qm_queue_management.h>
61 #include <ti/csl/cslr_qm_queue_status_config.h>
62 #include <ti/csl/cslr_qm_intd.h>
63 #include <ti/csl/cslr_pdsp.h>
64 #include <ti/csl/csl_qm_queue.h>
65 #include <ti/csl/cslr_cppidma_global_config.h>
66 #include <ti/csl/cslr_cppidma_rx_channel_config.h>
67 #include <ti/csl/cslr_cppidma_rx_flow_config.h>
68 #include <ti/csl/cslr_cppidma_tx_channel_config.h>
69 #include <ti/csl/cslr_cppidma_tx_scheduler_config.h>
70 #include <ti/csl/csl_cppi.h>
71 #include <ti/csl/csl_pscAux.h>
72 #include <ti/csl/csl_semAux.h>
73 #include <ti/csl/csl_cacheAux.h>
74 #include <ti/csl/csl_xmcAux.h>
75 #include <ti/csl/csl_cpsw_3gfAux.h>
76 #include <ti/csl/csl_cpsw.h>
77 #include <ti/csl/csl_cpsgmiiAux.h>
78 #include <ti/drv/qmss/qmss_qm.h>
79 //pull in device config for qmss, cppi
80 #include <ti/drv/qmss/device/qmss_device.c>
81 #include <ti/drv/cppi/device/cppi_device.c>
83 /* TODO verify: */
84 #define CACHE_LINESZ 64
86 #define System_printf printf
87 #define ALIGN(x) __attribute__((aligned (x)))
89 /*****************************************************************************
90 * Global Resources shared by all Cores
91 *****************************************************************************/
92 uint8_t *QMemGlobDescRam = 0;
93 uint8_t *cppiMemPaSaLinkBuf = 0;
94 uint8_t *cppiMemSaPaLinkBuf = 0;
96 /*****************************************************************************
97 * Local Resource allocated at each Core
98 *****************************************************************************/
99 /* Descriptors in global shared */
100 uint8_t *QMemLocDescRam = NULL;
101 uint8_t *cppiMemRxPktLinkBuf = NULL;
102 uint8_t *cppiMemTxPktLinkBuf = NULL;
103 uint8_t *cppiMemRxCtlLinkBuf = NULL;
104 uint8_t *cppiMemTxCtlLinkBuf = NULL;
107 //****************************************************
108 // initialize CPSW (switch) [per SOC]
109 //***************************************************
110 int netapi_init_cpsw(void)
111 {
112 CSL_CPSW_3GF_ALE_PORTCONTROL alePortControlCfg;
114 CSL_CPSW_3GF_clearAleTable();
116 alePortControlCfg.dropUntaggedEnable = 0;
117 alePortControlCfg.vidIngressCheckEnable = 0;
119 alePortControlCfg.mcastLimit = 0;
120 alePortControlCfg.bcastLimit = 0;
122 /* Disable learning mode for Port 0 */
123 alePortControlCfg.noLearnModeEnable = 1;
124 alePortControlCfg.portState = ALE_PORTSTATE_FORWARD;
125 CSL_CPSW_3GF_setAlePortControlReg (0, &alePortControlCfg);
127 /* Enable learning mode for Port 1 */
128 alePortControlCfg.noLearnModeEnable = 0;
129 alePortControlCfg.portState = ALE_PORTSTATE_FORWARD;
130 CSL_CPSW_3GF_setAlePortControlReg (1, &alePortControlCfg);
132 /* Enable learning mode for Port 2 */
133 alePortControlCfg.noLearnModeEnable = 0;
134 alePortControlCfg.portState = ALE_PORTSTATE_FORWARD;
135 CSL_CPSW_3GF_setAlePortControlReg (2, &alePortControlCfg);
137 return 1;
138 }
140 //****************************************************
141 // initialize QM (per SOC)
142 //***************************************************
143 int netapi_init_qm(void)
144 {
145 Qmss_InitCfg qmssInitConfig;
146 int32_t result;
147 Qmss_GlobalConfigParams nwalTest_qmssGblCfgParams;
149 memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));
151 /* Use Internal Linking RAM for optimal performance */
152 qmssInitConfig.linkingRAM0Base = 0;
153 qmssInitConfig.linkingRAM0Size = 0;
154 qmssInitConfig.linkingRAM1Base = 0;
155 qmssInitConfig.maxDescNum = TUNE_NETAPI_QM_CONFIG_MAX_DESC_NUM;
156 qmssInitConfig.qmssHwStatus =QMSS_HW_INIT_COMPLETE; //bypass some of the hw init
157 nwalTest_qmssGblCfgParams = qmssGblCfgParams[0];
159 nwalTest_qmssGblCfgParams.qmConfigReg = (void *)((uint8_t *)netapi_VM_qmssCfgVaddr +
160 (CSL_QM_SS_CFG_CONFIG_STARVATION_COUNTER_REGS - CSL_QM_SS_CFG_QUE_PEEK_REGS));
161 nwalTest_qmssGblCfgParams.qmDescReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
162 ((uint32_t)CSL_QM_SS_CFG_DESCRIPTION_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
163 nwalTest_qmssGblCfgParams.qmQueMgmtReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
164 ((uint32_t)CSL_QM_SS_CFG_QM_QUEUE_DEQUEUE_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
165 nwalTest_qmssGblCfgParams.qmQueMgmtProxyReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
166 ((uint32_t)CSL_QM_SS_CFG_PROXY_QUEUE_DEQUEUE_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
167 nwalTest_qmssGblCfgParams.qmQueStatReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
168 ((uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
169 nwalTest_qmssGblCfgParams.qmQueIntdReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
170 ((uint32_t)CSL_QM_SS_CFG_INTD_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
171 nwalTest_qmssGblCfgParams.qmPdspCmdReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
172 ((uint32_t)CSL_QM_SS_CFG_SCRACH_RAM1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
173 nwalTest_qmssGblCfgParams.qmPdspCmdReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
174 ((uint32_t)CSL_QM_SS_CFG_SCRACH_RAM2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
175 nwalTest_qmssGblCfgParams.qmPdspCtrlReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
176 ((uint32_t)CSL_QM_SS_CFG_ADSP1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
177 nwalTest_qmssGblCfgParams.qmPdspCtrlReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
178 ((uint32_t)CSL_QM_SS_CFG_ADSP2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
179 nwalTest_qmssGblCfgParams.qmPdspIRamReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
180 ((uint32_t)CSL_QM_SS_CFG_APDSP1_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
181 nwalTest_qmssGblCfgParams.qmPdspIRamReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
182 ((uint32_t)CSL_QM_SS_CFG_APDSP2_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
183 nwalTest_qmssGblCfgParams.qmStatusRAM = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
184 ((uint32_t)CSL_QM_SS_CFG_QM_STATUS_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
185 nwalTest_qmssGblCfgParams.qmLinkingRAMReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
186 ((uint32_t)CSL_QM_SS_CFG_LINKING_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
187 nwalTest_qmssGblCfgParams.qmMcDMAReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
188 ((uint32_t)CSL_QM_SS_CFG_MCDMA_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
189 nwalTest_qmssGblCfgParams.qmTimer16Reg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
190 ((uint32_t)CSL_QM_SS_CFG_TIMER1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
191 nwalTest_qmssGblCfgParams.qmTimer16Reg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
192 ((uint32_t)CSL_QM_SS_CFG_TIMER2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
193 nwalTest_qmssGblCfgParams.qmQueMgmtDataReg = (void *)((uint32_t)netapi_VM_qmssDataVaddr);
194 nwalTest_qmssGblCfgParams.qmQueMgmtProxyDataReg =
195 (void *)((uint32_t)netapi_VM_qmssDataVaddr + ((uint32_t)(0x44040000) - (uint32_t)(0x44020000)));
197 result = Qmss_init (&qmssInitConfig, &nwalTest_qmssGblCfgParams);
198 if (result != QMSS_SOK) {
199 System_printf ("function init_qm: qmss_Init failed with error code %d\n", result);
200 return (nwal_FALSE);
201 }
203 return 1;
204 }
206 //****************************************************
207 // Set up QM memory region (per SOC)
208 //***************************************************
209 int netapi_qm_setup_mem_region(
210 uint32_t numDesc,
211 uint32_t descSize,
212 uint32_t* pDescMemBase,
213 Qmss_MemRegion memRegion)
214 {
215 Qmss_MemRegInfo memInfo;
216 Int32 result;
217 Int n;
218 static int netapi_qm_region_index=0;
220 memset(&memInfo,0,sizeof(Qmss_MemRegInfo));
221 memInfo.descBase = pDescMemBase;
222 memInfo.descSize = descSize;
223 memInfo.descNum = numDesc;
224 memInfo.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
225 memInfo.memRegion = memRegion==NETAPI_GLOBAL_REGION ? Qmss_MemRegion_MEMORY_REGION0 : Qmss_MemRegion_MEMORY_REGION1;
227 if(memRegion == NETAPI_GLOBAL_REGION)
228 {
229 memInfo.startIndex = 0;
230 netapi_qm_region_index += numDesc;
231 }else if(memRegion ==NETAPI_LOCAL_REGION)
232 {
233 /* Global shared memory for all descriptors to all cores */
234 memInfo.startIndex = netapi_qm_region_index;
235 }
236 else
237 {
238 return -1 ;
239 }
241 result = Qmss_insertMemoryRegion (&memInfo);
242 if (result < QMSS_SOK)
243 {
244 printf ("function setup_qm_region: Qmss_insertMemoryRegion returned error code %d\n", result);
245 return (-1);
246 }
248 return 1;
250 }
252 //****************************************************
253 // Start QM (per thread)
254 //***************************************************
255 int netapi_start_qm(void)
256 {
257 int32_t result;
258 result = Qmss_start();
259 if (result != QMSS_SOK)
260 {
261 System_printf ("start_qm: Qmss_start failed with error code %d\n", result);
262 return (-1);
263 }
264 return 1;
265 }
267 //*************************************************
268 //initilaize CPPI (once per soc)
269 //*************************************************
270 int netapi_init_cppi(void)
271 {
272 int32_t result, i;
273 Cppi_GlobalConfigParams nwalTest_cppiGblCfgParams[CPPI_MAX_CPDMA];
275 for (i=0; i<CPPI_MAX_CPDMA; i++)
276 nwalTest_cppiGblCfgParams[i] = cppiGblCfgParams[i];
278 /* SRIO CPDMA regs */
279 nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs =
280 (void *)((uint32_t)netapi_VM_srioCfgVaddr +
281 (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
282 nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txChRegs =
283 (void *)((uint32_t)netapi_VM_srioCfgVaddr +
284 (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
286 nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxChRegs =
287 (void *)((uint32_t)netapi_VM_srioCfgVaddr +
288 (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
289 nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txSchedRegs =
290 (void *)((uint32_t)netapi_VM_srioCfgVaddr +
291 (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
292 nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs =
293 (void *)((uint32_t)netapi_VM_srioCfgVaddr +
294 (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
296 /* PASS CPDMA regs */
297 nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].gblCfgRegs =
298 (void *)((uint32_t)netapi_VM_passCfgVaddr +
299 (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
300 nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txChRegs =
301 (void *)((uint32_t)netapi_VM_passCfgVaddr +
302 (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
303 nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxChRegs =
304 (void *)((uint32_t)netapi_VM_passCfgVaddr +
305 (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
306 nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txSchedRegs =
307 (void *)((uint32_t)netapi_VM_passCfgVaddr +
308 (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
309 nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxFlowRegs =
310 (void *)((uint32_t)netapi_VM_passCfgVaddr +
311 (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
312 /* QMSS CPDMA regs */
313 nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs =
314 (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
315 (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
316 nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txChRegs =
317 (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
318 (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
319 nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxChRegs =
320 (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
321 (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
322 nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txSchedRegs =
323 (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
324 (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
325 nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs =
326 (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
327 (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
329 result = Cppi_init (nwalTest_cppiGblCfgParams);
330 if (result != CPPI_SOK)
331 {
332 printf ("function cppi_init: Cppi_init failed with error code %d\n", result);
333 return (-1);
334 }
335 return 1;
336 }
338 //*************************************************
339 //initialize NWAL (one per soc)
340 //*************************************************
341 /*** NWAL Memory Buffer Configuration ***/
342 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE 3400
343 uint8_t nwalInstMem[NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE]ALIGN(CACHE_LINESZ);
345 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_MAC 128
346 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_IPSEC_HANDLE_PER_CHAN 256
347 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_IP 128
348 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_PORT 128
349 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_L2L3_HDR 128
350 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_LOC_CONTEXT 384
351 #define NWAL_CHAN_HANDLE_SIZE ((NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_MAC * TUNE_NETAPI_MAX_NUM_MAC) + \
352 (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_IPSEC_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS) + \
353 (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_IP * TUNE_NETAPI_MAX_NUM_IP) + \
354 (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_PORT * TUNE_NETAPI_MAX_NUM_PORTS)+ \
355 (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_LOC_CONTEXT * TUNE_NETAPI_NUM_CORES) + \
356 (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_L2L3_HDR * TUNE_NETAPI_MAX_NUM_L2_L3_HDRS))
358 uint8_t nwalHandleMem[NWAL_CHAN_HANDLE_SIZE]ALIGN(CACHE_LINESZ);
360 /* todo: Check if below size information can be made available from pa interface file */
361 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0 128
362 /* PA instance */
363 /* Memory used for the PA Instance. Needs to be assigned global uncached memory for chip */
364 uint8_t paBuf0[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0]ALIGN(CACHE_LINESZ);
366 /* Memory used for PA handles */
367 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1 128
368 uint8_t paBuf1[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1]ALIGN(CACHE_LINESZ);
370 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2 256
371 uint8_t paBuf2[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2]ALIGN(CACHE_LINESZ);
373 /* Memory used for SA LLD global Handle */
374 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE 384
375 uint8_t salldHandle[NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE]ALIGN(CACHE_LINESZ);
377 /* Memory used for SA LLD global Handle */
378 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_CONTEXT_PER_CHAN 384
379 uint8_t saContext[NETAPI_NWAL_CONFIG_BUFSIZE_SA_CONTEXT_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS]ALIGN(CACHE_LINESZ);
381 /* Memory used by SA LLD per Channel */
382 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN 512
383 uint8_t salldChanHandle[NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS]ALIGN(CACHE_LINESZ);
386 /*******************************************
387 * Initialize the nwal subsystem for NETAPI use
388 ***********************************************/
389 int netapi_init_nwal(
390 int region2use,
391 Pktlib_HeapIfTable * p_table,
392 NETAPI_NWAL_GLOBAL_CONTEXT_T * p_nwal_context )
393 {
394 nwalSizeInfo_t nwalSizeInfo;
395 nwalMemBuf_t nwalMemBuf[nwal_N_BUFS];
396 nwal_RetValue nwalRetVal;
397 nwalGlobCfg_t nwalGlobCfg;
398 uint8_t count;
399 int sizes[nwal_N_BUFS];
400 int aligns[nwal_N_BUFS];
401 void* bases[nwal_N_BUFS];
403 memset(p_nwal_context,0,sizeof( NETAPI_NWAL_GLOBAL_CONTEXT_T) );
404 memset(&nwalGlobCfg,0,sizeof(nwalGlobCfg_t ) );
407 /* Initialize Buffer Pool for NetCP PA to SA packets */
408 nwalGlobCfg.pa2SaBufPool.numBufPools = 1;
409 nwalGlobCfg.pa2SaBufPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
410 nwalGlobCfg.pa2SaBufPool.bufPool[0].bufSize = TUNE_NETAPI_DEFAULT_BUFFER_SIZE;
411 nwalGlobCfg.pa2SaBufPool.bufPool[0].heapHandle =
412 Pktlib_createHeap("nwal PA2SA",
413 region2use,
414 0,
415 TUNE_NETAPI_DEFAULT_BUFFER_SIZE,
416 TUNE_NETAPI_CONFIG_MAX_PA_TO_SA_DESC,
417 0,
418 p_table);
419 if(nwalGlobCfg.pa2SaBufPool.bufPool[0].heapHandle == NULL)
420 {
421 printf ("Pktlib_createHeap:Heap Creation Failed for PA to SA Buffer Pool \n");
422 netapi_err_teardown();
423 return -1;
424 }
426 /* Initialize Buffer Pool for NetCP SA to PA packets */
427 nwalGlobCfg.sa2PaBufPool.numBufPools = 1;
428 nwalGlobCfg.sa2PaBufPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
429 nwalGlobCfg.sa2PaBufPool.bufPool[0].bufSize = TUNE_NETAPI_DEFAULT_BUFFER_SIZE;
431 nwalGlobCfg.sa2PaBufPool.bufPool[0].heapHandle =
432 Pktlib_createHeap("nwal SA2PA",
433 region2use,
434 0,
435 TUNE_NETAPI_DEFAULT_BUFFER_SIZE,
436 TUNE_NETAPI_CONFIG_MAX_SA_TO_PA_DESC,
437 0,
438 p_table);
439 if(nwalGlobCfg.sa2PaBufPool.bufPool[0].heapHandle == NULL)
440 {
441 printf ("Pktlib_createHeap:Heap Creation Failed for SA to PA Buffer Pool \n");
442 netapi_err_teardown();
443 return -1;
444 }
446 nwalGlobCfg.hopLimit = 5;/* Default TTL / Hop Limit */
447 nwalGlobCfg.lpbackPass = TUNE_NETAPI_NWAL_ENABLE_PASS_LOOPBACK;
448 nwalGlobCfg.paFwActive = nwal_TRUE;
449 nwalGlobCfg.saFwActive = nwal_TRUE;
451 /* Pick Default Physical Address */
452 nwalGlobCfg.paVirtBaseAddr = (uint32_t) netapi_VM_passCfgVaddr;
453 nwalGlobCfg.saVirtBaseAddr = (uint32_t) netapi_VM_passCfgVaddr +
454 ((uint32_t)CSL_PA_SS_CFG_CP_ACE_CFG_REGS - (uint32_t)CSL_PA_SS_CFG_REGS) ;
455 nwalGlobCfg.rxDefPktQ = QMSS_PARAM_NOT_SPECIFIED;
457 /* Get the Buffer Requirement from NWAL */
458 memset(&nwalMemBuf,0,sizeof(nwalMemBuf));
459 memset(&nwalSizeInfo,0,sizeof(nwalSizeInfo));
460 nwalSizeInfo.nMaxMacAddress = TUNE_NETAPI_MAX_NUM_MAC;
461 nwalSizeInfo.nMaxIpAddress = TUNE_NETAPI_MAX_NUM_IP;
462 nwalSizeInfo.nMaxL4Ports = TUNE_NETAPI_MAX_NUM_PORTS;
463 nwalSizeInfo.nMaxIpSecChannels = TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS;
464 nwalSizeInfo.nMaxL2L3Hdr = TUNE_NETAPI_MAX_NUM_L2_L3_HDRS;
465 nwalSizeInfo.nProc = TUNE_NETAPI_NUM_CORES;
466 for(count=0;count < nwal_N_BUFS;count++)
467 {
468 nwalMemBuf[count].cacheLineSize = CACHE_LINESZ;
469 }
470 nwalRetVal = nwal_getBufferReq(&nwalSizeInfo,
471 sizes,
472 aligns);
473 if(nwalRetVal != nwal_OK)
474 {
475 printf ("init_nwal: nwal_getBufferReq Failed %d\n", nwalRetVal);
476 return nwal_FALSE;
477 }
479 /* Check for memory size requirement and update the base */
480 count = 0;
481 bases[nwal_BUF_INDEX_INST] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)nwalInstMem);
482 if(NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE < sizes[nwal_BUF_INDEX_INST])
483 {
484 /* Resize Memory */
485 while(1);
486 }
487 count++;
489 bases[nwal_BUF_INDEX_INT_HANDLES] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)nwalHandleMem);
490 if(NWAL_CHAN_HANDLE_SIZE < sizes[nwal_BUF_INDEX_INT_HANDLES])
491 {
492 /* Resize Memory */
493 while(1);
494 }
495 count++;
496 bases[nwal_BUF_INDEX_PA_LLD_BUF0] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf0);
497 if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0) < sizes[nwal_BUF_INDEX_PA_LLD_BUF0])
498 {
499 /* Resize Memory */
500 while(1);
501 }
502 count++;
504 bases[nwal_BUF_INDEX_PA_LLD_BUF1] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf1);
505 if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1) < sizes[nwal_BUF_INDEX_PA_LLD_BUF1])
506 {
507 /* Resize Memory */
508 while(1);
509 }
510 count++;
512 bases[nwal_BUF_INDEX_PA_LLD_BUF2] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf2);
513 if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2) < sizes[nwal_BUF_INDEX_PA_LLD_BUF2])
514 {
515 /* Resize Memory */
516 while(1);
517 }
518 count++;
519 #ifdef NETAPI_ENABLE_SECURITY
520 bases[nwal_BUF_INDEX_SA_LLD_HANDLE] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)salldHandle);
521 if((NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE) < sizes[nwal_BUF_INDEX_SA_LLD_HANDLE])
522 {
523 /* Resize Memory */
524 while(1);
525 }
526 count++;
528 bases[nwal_BUF_INDEX_SA_CONTEXT] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)saContext);
529 if((NETAPI_NWAL_CONFIG_BUFSIZE_SA_CONTEXT_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS) <
530 sizes[nwal_BUF_INDEX_SA_CONTEXT])
531 {
532 /* Resize Memory */
533 while(1);
534 }
535 count++;
537 bases[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)salldChanHandle);
538 if((NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS) <
539 sizes[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE])
540 {
541 /* Resize Memory */
542 while(1);
543 }
544 count++;
545 #else
546 bases[nwal_BUF_INDEX_SA_LLD_HANDLE] = 0;
547 bases[nwal_BUF_INDEX_SA_CONTEXT] = 0;
548 bases[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE] = 0;
549 count = count+3;
550 #endif
551 if(count != nwal_N_BUFS)
552 {
553 while(1);
554 }
556 /* Initialize NWAL module */
557 nwalRetVal = nwal_create(&nwalGlobCfg,
558 &nwalSizeInfo,
559 sizes,
560 bases,
561 &p_nwal_context->nwalInstHandle);
562 if(nwalRetVal != nwal_OK)
563 {
564 printf ("init_nwal: nwal_create Failed %d\n",nwalRetVal);
565 while(1);
566 }
568 printf("init_nwal: Global and Local Network initialization Successful \n");
569 return 1;
570 }
572 //*************************************************
573 //* Local (per thread/core) nwal initialization0
574 //**************************************************
575 int netapi_start_nwal(Pktlib_HeapHandle pkt_heap,
576 Pktlib_HeapHandle cmd_heap,
577 NETAPI_NWAL_LOCAL_CONTEXT_T *p,
578 NETAPI_NWAL_GLOBAL_CONTEXT_T * p_nwal_glob_context )
579 {
580 nwalLocCfg_t nwalLocCfg;
581 int count;
582 nwal_RetValue nwalRetVal;
584 memset(&nwalLocCfg,0,sizeof(nwalLocCfg));
586 /* Common Initialization for all cores */
587 while(count < TUNE_NETAPI_MAX_NUM_TRANS)
588 {
589 p_nwal_glob_context->transInfos[count].transId = count;
590 count++;
591 }
593 /* Call back registration for the core */
594 nwalLocCfg.pRxPktCallBack = netapi_NWALRxPktCallback;
595 nwalLocCfg.pCmdCallBack = netapi_NWALCmdCallBack;
596 nwalLocCfg.pPaStatsCallBack = netapi_NWALCmdPaStatsReply;
598 /* Initialize Buffer Pool for Control packets from NetCP to Host */
599 nwalLocCfg.rxCtlPool.numBufPools = 1;
600 nwalLocCfg.rxCtlPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
601 nwalLocCfg.rxCtlPool.bufPool[0].bufSize = TUNE_NETAPI_CONFIG_MAX_CTL_RXTX_BUF_SIZE;
602 nwalLocCfg.rxCtlPool.bufPool[0].heapHandle = cmd_heap;
604 /* Initialize Buffer Pool for Control packets from Host to NetCP */
605 nwalLocCfg.txCtlPool.numBufPools = 1;
606 nwalLocCfg.txCtlPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
607 nwalLocCfg.txCtlPool.bufPool[0].bufSize = TUNE_NETAPI_CONFIG_MAX_CTL_RXTX_BUF_SIZE;
608 nwalLocCfg.txCtlPool.bufPool[0].heapHandle = cmd_heap;
610 /* Initialize Buffer Pool for Packets from NetCP to Host */
611 nwalLocCfg.rxPktPool.numBufPools = 1;
612 nwalLocCfg.rxPktPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
613 nwalLocCfg.rxPktPool.bufPool[0].bufSize = TUNE_NETAPI_DEFAULT_BUFFER_SIZE;
614 nwalLocCfg.rxPktPool.bufPool[0].heapHandle = pkt_heap;
616 /* Initialize Buffer Pool for Packets from Host to NetCP */
617 nwalLocCfg.txPktPool.numBufPools = 1;
618 nwalLocCfg.txPktPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
619 nwalLocCfg.txPktPool.bufPool[0].bufSize = TUNE_NETAPI_DEFAULT_BUFFER_SIZE;
620 nwalLocCfg.txPktPool.bufPool[0].heapHandle = pkt_heap;
622 memcpy(&p->nwalLocCfg,&nwalLocCfg,sizeof(nwalLocCfg_t));
623 while(1)
624 {
625 nwalRetVal = nwal_start(p_nwal_glob_context->nwalInstHandle,&nwalLocCfg);
626 if(nwalRetVal == nwal_ERR_INVALID_STATE)
627 {
628 continue;
629 }
630 break;
631 }
633 if(nwalRetVal != nwal_OK)
634 {
635 printf ("nwal_start:Failed ->err %d !!!\n", nwalRetVal);
636 return -1;
637 }
638 p->state = NETAPI_NW_CXT_LOC_ACTIVE;
639 return 1;
642 }
643 //***************************************************
644 // intialize timer
645 //***************************************************
646 int netapi_init_timer(void)
647 {
648 return t64_start();
649 }