1 /************************************************\r
2 * FILE: netapi_init.c\r
3 * Global, local initialization of NETAPI\r
4 *\r
5 * DESCRIPTION: Functions to initialize framework resources for running NETAPI\r
6 *\r
7 * REVISION HISTORY:\r
8 *\r
9 * Copyright (c) Texas Instruments Incorporated 2010-2011\r
10 * \r
11 * Redistribution and use in source and binary forms, with or without \r
12 * modification, are permitted provided that the following conditions \r
13 * are met:\r
14 *\r
15 * Redistributions of source code must retain the above copyright \r
16 * notice, this list of conditions and the following disclaimer.\r
17 *\r
18 * Redistributions in binary form must reproduce the above copyright\r
19 * notice, this list of conditions and the following disclaimer in the \r
20 * documentation and/or other materials provided with the \r
21 * distribution.\r
22 *\r
23 * Neither the name of Texas Instruments Incorporated nor the names of\r
24 * its contributors may be used to endorse or promote products derived\r
25 * from this software without specific prior written permission.\r
26 *\r
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
31 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
32 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
33 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
38 *\r
39 ***********************************************/\r
40 #include <stdint.h>\r
41 #include <stdio.h>\r
42 #include <string.h>\r
43 #include <sys/types.h>\r
44 #include <sys/stat.h>\r
45 #include <fcntl.h>\r
46 #include <sys/mman.h>\r
47 #include <errno.h>\r
48 #include <unistd.h>\r
49 \r
50 #include <ti/drv/nwal/nwal.h>\r
51 #include "netapi.h"\r
52 #include "netapi_vm.h"\r
53 #include "netapi_loc.h"\r
54 #include "ti/drv/nwal/nwal.h"\r
55 \r
56 /* CSL RL includes */\r
57 #include <ti/csl/cslr_device.h>\r
58 #include <ti/csl/cslr_qm_config.h>\r
59 #include <ti/csl/cslr_qm_descriptor_region_config.h>\r
60 #include <ti/csl/cslr_qm_queue_management.h>\r
61 #include <ti/csl/cslr_qm_queue_status_config.h>\r
62 #include <ti/csl/cslr_qm_intd.h>\r
63 #include <ti/csl/cslr_pdsp.h>\r
64 #include <ti/csl/csl_qm_queue.h>\r
65 #include <ti/csl/cslr_cppidma_global_config.h>\r
66 #include <ti/csl/cslr_cppidma_rx_channel_config.h>\r
67 #include <ti/csl/cslr_cppidma_rx_flow_config.h>\r
68 #include <ti/csl/cslr_cppidma_tx_channel_config.h>\r
69 #include <ti/csl/cslr_cppidma_tx_scheduler_config.h>\r
70 #include <ti/csl/csl_cppi.h>\r
71 #include <ti/csl/csl_pscAux.h>\r
72 #include <ti/csl/csl_semAux.h>\r
73 #include <ti/csl/csl_cacheAux.h>\r
74 #include <ti/csl/csl_xmcAux.h>\r
75 #include <ti/csl/csl_cpsw_3gfAux.h>\r
76 #include <ti/csl/csl_cpsw.h>\r
77 #include <ti/csl/csl_cpsgmiiAux.h>\r
78 #include <ti/drv/qmss/qmss_qm.h>\r
79 //pull in device config for qmss, cppi\r
80 #include <ti/drv/qmss/device/qmss_device.c>\r
81 #include <ti/drv/cppi/device/cppi_device.c>\r
82 \r
83 /* TODO verify: */\r
84 #define CACHE_LINESZ 64\r
85 \r
86 #define System_printf printf\r
87 #define ALIGN(x) __attribute__((aligned (x)))\r
88 \r
89 /*****************************************************************************\r
90 * Global Resources shared by all Cores\r
91 *****************************************************************************/\r
92 uint8_t *QMemGlobDescRam = 0;\r
93 uint8_t *cppiMemPaSaLinkBuf = 0;\r
94 uint8_t *cppiMemSaPaLinkBuf = 0;\r
95 \r
96 /*****************************************************************************\r
97 * Local Resource allocated at each Core\r
98 *****************************************************************************/\r
99 /* Descriptors in global shared */\r
100 uint8_t *QMemLocDescRam = NULL;\r
101 uint8_t *cppiMemRxPktLinkBuf = NULL;\r
102 uint8_t *cppiMemTxPktLinkBuf = NULL;\r
103 uint8_t *cppiMemRxCtlLinkBuf = NULL;\r
104 uint8_t *cppiMemTxCtlLinkBuf = NULL;\r
105 \r
106 \r
107 //****************************************************\r
108 // initialize CPSW (switch) [per SOC]\r
109 //***************************************************\r
110 int netapi_init_cpsw(void)\r
111 {\r
112 CSL_CPSW_3GF_ALE_PORTCONTROL alePortControlCfg;\r
113 \r
114 CSL_CPSW_3GF_clearAleTable();\r
115 \r
116 alePortControlCfg.dropUntaggedEnable = 0;\r
117 alePortControlCfg.vidIngressCheckEnable = 0;\r
118 \r
119 alePortControlCfg.mcastLimit = 0;\r
120 alePortControlCfg.bcastLimit = 0;\r
121 \r
122 /* Disable learning mode for Port 0 */\r
123 alePortControlCfg.noLearnModeEnable = 1;\r
124 alePortControlCfg.portState = ALE_PORTSTATE_FORWARD;\r
125 CSL_CPSW_3GF_setAlePortControlReg (0, &alePortControlCfg);\r
126 \r
127 /* Enable learning mode for Port 1 */\r
128 alePortControlCfg.noLearnModeEnable = 0;\r
129 alePortControlCfg.portState = ALE_PORTSTATE_FORWARD;\r
130 CSL_CPSW_3GF_setAlePortControlReg (1, &alePortControlCfg);\r
131 \r
132 /* Enable learning mode for Port 2 */\r
133 alePortControlCfg.noLearnModeEnable = 0;\r
134 alePortControlCfg.portState = ALE_PORTSTATE_FORWARD;\r
135 CSL_CPSW_3GF_setAlePortControlReg (2, &alePortControlCfg);\r
136 \r
137 return 1;\r
138 }\r
139 \r
140 //****************************************************\r
141 // initialize QM (per SOC)\r
142 //***************************************************\r
143 int netapi_init_qm(int max_descriptors)\r
144 {\r
145 Qmss_InitCfg qmssInitConfig;\r
146 int32_t result;\r
147 Qmss_GlobalConfigParams nwalTest_qmssGblCfgParams;\r
148 \r
149 memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));\r
150 \r
151 /* Use Internal Linking RAM for optimal performance */\r
152 qmssInitConfig.linkingRAM0Base = 0;\r
153 qmssInitConfig.linkingRAM0Size = 0;\r
154 qmssInitConfig.linkingRAM1Base = 0;\r
155 qmssInitConfig.maxDescNum = max_descriptors;\r
156 qmssInitConfig.qmssHwStatus =QMSS_HW_INIT_COMPLETE; //bypass some of the hw init\r
157 nwalTest_qmssGblCfgParams = qmssGblCfgParams[0];\r
158 \r
159 nwalTest_qmssGblCfgParams.qmConfigReg = (void *)((uint8_t *)netapi_VM_qmssCfgVaddr +\r
160 (CSL_QM_SS_CFG_CONFIG_STARVATION_COUNTER_REGS - CSL_QM_SS_CFG_QUE_PEEK_REGS));\r
161 nwalTest_qmssGblCfgParams.qmDescReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
162 ((uint32_t)CSL_QM_SS_CFG_DESCRIPTION_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
163 nwalTest_qmssGblCfgParams.qmQueMgmtReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
164 ((uint32_t)CSL_QM_SS_CFG_QM_QUEUE_DEQUEUE_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
165 nwalTest_qmssGblCfgParams.qmQueMgmtProxyReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
166 ((uint32_t)CSL_QM_SS_CFG_PROXY_QUEUE_DEQUEUE_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
167 nwalTest_qmssGblCfgParams.qmQueStatReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
168 ((uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
169 nwalTest_qmssGblCfgParams.qmQueIntdReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
170 ((uint32_t)CSL_QM_SS_CFG_INTD_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
171 nwalTest_qmssGblCfgParams.qmPdspCmdReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
172 ((uint32_t)CSL_QM_SS_CFG_SCRACH_RAM1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
173 nwalTest_qmssGblCfgParams.qmPdspCmdReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
174 ((uint32_t)CSL_QM_SS_CFG_SCRACH_RAM2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
175 nwalTest_qmssGblCfgParams.qmPdspCtrlReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
176 ((uint32_t)CSL_QM_SS_CFG_ADSP1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
177 nwalTest_qmssGblCfgParams.qmPdspCtrlReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
178 ((uint32_t)CSL_QM_SS_CFG_ADSP2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
179 nwalTest_qmssGblCfgParams.qmPdspIRamReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
180 ((uint32_t)CSL_QM_SS_CFG_APDSP1_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
181 nwalTest_qmssGblCfgParams.qmPdspIRamReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
182 ((uint32_t)CSL_QM_SS_CFG_APDSP2_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
183 nwalTest_qmssGblCfgParams.qmStatusRAM = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
184 ((uint32_t)CSL_QM_SS_CFG_QM_STATUS_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
185 nwalTest_qmssGblCfgParams.qmLinkingRAMReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
186 ((uint32_t)CSL_QM_SS_CFG_LINKING_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
187 nwalTest_qmssGblCfgParams.qmMcDMAReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
188 ((uint32_t)CSL_QM_SS_CFG_MCDMA_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
189 nwalTest_qmssGblCfgParams.qmTimer16Reg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
190 ((uint32_t)CSL_QM_SS_CFG_TIMER1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
191 nwalTest_qmssGblCfgParams.qmTimer16Reg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
192 ((uint32_t)CSL_QM_SS_CFG_TIMER2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);\r
193 nwalTest_qmssGblCfgParams.qmQueMgmtDataReg = (void *)((uint32_t)netapi_VM_qmssDataVaddr);\r
194 nwalTest_qmssGblCfgParams.qmQueMgmtProxyDataReg = \r
195 (void *)((uint32_t)netapi_VM_qmssDataVaddr + ((uint32_t)(0x44040000) - (uint32_t)(0x44020000)));\r
196 \r
197 result = Qmss_init (&qmssInitConfig, &nwalTest_qmssGblCfgParams);\r
198 if (result != QMSS_SOK) {\r
199 System_printf (">function init_qm: qmss_Init failed with error code %d\n", result);\r
200 return (nwal_FALSE);\r
201 }\r
202 \r
203 return 1;\r
204 }\r
205 \r
206 //****************************************************\r
207 // Set up QM memory region (per SOC)\r
208 //***************************************************\r
209 int netapi_qm_setup_mem_region(\r
210 uint32_t numDesc,\r
211 uint32_t descSize,\r
212 uint32_t* pDescMemBase,\r
213 Qmss_MemRegion memRegion)\r
214 {\r
215 Qmss_MemRegInfo memInfo;\r
216 Int32 result;\r
217 Int n;\r
218 static int netapi_qm_region_index=0;\r
219 \r
220 memset(&memInfo,0,sizeof(Qmss_MemRegInfo));\r
221 memInfo.descBase = pDescMemBase;\r
222 memInfo.descSize = descSize;\r
223 memInfo.descNum = numDesc;\r
224 memInfo.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;\r
225 memInfo.memRegion = memRegion;\r
226 \r
227 if(memRegion == NETAPI_GLOBAL_REGION)\r
228 {\r
229 memInfo.startIndex = TUNE_NETAPI_QM_START_INDEX; //was 0\r
230 netapi_qm_region_index += numDesc;\r
231 }else if(memRegion ==NETAPI_LOCAL_REGION)\r
232 {\r
233 /* 2nd region for descriptors (perhaps private?) */\r
234 memInfo.startIndex = netapi_qm_region_index;\r
235 }\r
236 else\r
237 {\r
238 return -1 ;\r
239 }\r
240 \r
241 memset (pDescMemBase, 0, (descSize * numDesc));\r
242 \r
243 result = Qmss_insertMemoryRegion (&memInfo);\r
244 if (result < QMSS_SOK) \r
245 {\r
246 printf (">function setup_qm_region: Qmss_insertMemoryRegion returned error code %d\n", result);\r
247 return (-1);\r
248 }\r
249 \r
250 return 1;\r
251 \r
252 }\r
253 \r
254 //****************************************************\r
255 // Start QM (per thread)\r
256 //***************************************************\r
257 int netapi_start_qm(void)\r
258 {\r
259 int32_t result;\r
260 result = Qmss_start();\r
261 if (result != QMSS_SOK)\r
262 {\r
263 System_printf (">start_qm: Qmss_start failed with error code %d\n", result);\r
264 return (-1);\r
265 }\r
266 return 1;\r
267 }\r
268 \r
269 //*************************************************\r
270 //initilaize CPPI (once per soc)\r
271 //*************************************************\r
272 int netapi_init_cppi(void)\r
273 {\r
274 int32_t result, i;\r
275 Cppi_GlobalConfigParams nwalTest_cppiGblCfgParams[CPPI_MAX_CPDMA];\r
276 \r
277 for (i=0; i<CPPI_MAX_CPDMA; i++)\r
278 nwalTest_cppiGblCfgParams[i] = cppiGblCfgParams[i];\r
279 \r
280 /* SRIO CPDMA regs */\r
281 nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs =\r
282 (void *)((uint32_t)netapi_VM_srioCfgVaddr +\r
283 (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));\r
284 nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txChRegs =\r
285 (void *)((uint32_t)netapi_VM_srioCfgVaddr +\r
286 (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));\r
287 \r
288 nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxChRegs =\r
289 (void *)((uint32_t)netapi_VM_srioCfgVaddr +\r
290 (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));\r
291 nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txSchedRegs =\r
292 (void *)((uint32_t)netapi_VM_srioCfgVaddr +\r
293 (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));\r
294 nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs =\r
295 (void *)((uint32_t)netapi_VM_srioCfgVaddr +\r
296 (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));\r
297 \r
298 /* PASS CPDMA regs */\r
299 nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].gblCfgRegs =\r
300 (void *)((uint32_t)netapi_VM_passCfgVaddr +\r
301 (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));\r
302 nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txChRegs =\r
303 (void *)((uint32_t)netapi_VM_passCfgVaddr +\r
304 (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));\r
305 nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxChRegs =\r
306 (void *)((uint32_t)netapi_VM_passCfgVaddr +\r
307 (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));\r
308 nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txSchedRegs =\r
309 (void *)((uint32_t)netapi_VM_passCfgVaddr +\r
310 (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));\r
311 nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxFlowRegs =\r
312 (void *)((uint32_t)netapi_VM_passCfgVaddr +\r
313 (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));\r
314 /* QMSS CPDMA regs */\r
315 nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs =\r
316 (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
317 (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));\r
318 nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txChRegs =\r
319 (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
320 (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));\r
321 nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxChRegs =\r
322 (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
323 (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));\r
324 nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txSchedRegs =\r
325 (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
326 (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));\r
327 nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs =\r
328 (void *)((uint32_t)netapi_VM_qmssCfgVaddr +\r
329 (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));\r
330 \r
331 result = Cppi_init (nwalTest_cppiGblCfgParams);\r
332 if (result != CPPI_SOK) \r
333 {\r
334 printf (">function cppi_init: Cppi_init failed with error code %d\n", result);\r
335 return (-1);\r
336 }\r
337 return 1;\r
338 }\r
339 \r
340 //*************************************************\r
341 //initialize NWAL (one per soc) \r
342 //*************************************************\r
343 /*** NWAL Memory Buffer Configuration ***/\r
344 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE 3400\r
345 uint8_t nwalInstMem[NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE]ALIGN(CACHE_LINESZ);\r
346 \r
347 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_MAC 128\r
348 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_IPSEC_HANDLE_PER_CHAN 256\r
349 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_IP 128\r
350 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_PORT 128\r
351 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_L2L3_HDR 128\r
352 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_LOC_CONTEXT 384\r
353 #define NWAL_CHAN_HANDLE_SIZE ((NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_MAC * TUNE_NETAPI_MAX_NUM_MAC) + \\r
354 (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_IPSEC_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS*2) + \\r
355 (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_IP * TUNE_NETAPI_MAX_NUM_IP) + \\r
356 (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_PORT * TUNE_NETAPI_MAX_NUM_PORTS)+ \\r
357 (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_LOC_CONTEXT * TUNE_NETAPI_NUM_CORES) + \\r
358 (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_L2L3_HDR * TUNE_NETAPI_MAX_NUM_L2_L3_HDRS))\r
359 \r
360 uint8_t nwalHandleMem[NWAL_CHAN_HANDLE_SIZE]ALIGN(CACHE_LINESZ);\r
361 \r
362 /* todo: Check if below size information can be made available from pa interface file */\r
363 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0 128\r
364 /* PA instance */\r
365 /* Memory used for the PA Instance. Needs to be assigned global uncached memory for chip */\r
366 uint8_t paBuf0[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0]ALIGN(CACHE_LINESZ);\r
367 \r
368 /* Memory used for PA handles */\r
369 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1 128\r
370 uint8_t paBuf1[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1]ALIGN(CACHE_LINESZ);\r
371 \r
372 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2 768 \r
373 uint8_t paBuf2[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2]ALIGN(CACHE_LINESZ);\r
374 \r
375 /* Memory used for SA LLD global Handle */\r
376 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE 384\r
377 uint8_t salldHandle[NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE]ALIGN(CACHE_LINESZ);\r
378 \r
379 #if 0 //need to alloc this since we need phy addr also \r
380 /* Memory used for SA contet Handle */\r
381 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_CONTEXT_PER_CHAN 384\r
382 uint8_t saContext[NETAPI_NWAL_CONFIG_BUFSIZE_SA_CONTEXT_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS]ALIGN(CACHE_LINESZ);\r
383 #endif\r
384 \r
385 /* Memory used by SA LLD per Channel */\r
386 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN 512\r
387 uint8_t salldChanHandle[NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS*2]ALIGN(CACHE_LINESZ);\r
388 \r
389 \r
390 /*******************************************\r
391 * Initialize the nwal subsystem for NETAPI use\r
392 ***********************************************/\r
393 int netapi_init_nwal(\r
394 int region2use, \r
395 Pktlib_HeapIfTable * p_table,\r
396 NETAPI_NWAL_GLOBAL_CONTEXT_T * p_nwal_context, \r
397 NETAPI_CFG_T*p_cfg )\r
398 {\r
399 nwalSizeInfo_t nwalSizeInfo;\r
400 nwalMemBuf_t nwalMemBuf[nwal_N_BUFS];\r
401 nwal_RetValue nwalRetVal;\r
402 nwalGlobCfg_t nwalGlobCfg;\r
403 uint8_t count;\r
404 int sizes[nwal_N_BUFS];\r
405 int aligns[nwal_N_BUFS];\r
406 void* bases[nwal_N_BUFS];\r
407 \r
408 memset(p_nwal_context,0,sizeof( NETAPI_NWAL_GLOBAL_CONTEXT_T) );\r
409 memset(&nwalGlobCfg,0,sizeof(nwalGlobCfg_t ) );\r
410 \r
411 \r
412 /* Initialize Buffer Pool for NetCP PA to SA packets */\r
413 nwalGlobCfg.pa2SaBufPool.numBufPools = 1;\r
414 nwalGlobCfg.pa2SaBufPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;\r
415 nwalGlobCfg.pa2SaBufPool.bufPool[0].bufSize = p_cfg->def_heap_buf_size;\r
416 nwalGlobCfg.pa2SaBufPool.bufPool[0].heapHandle = p_nwal_context->pa2sa_heap=\r
417 Pktlib_createHeap("nwal PA2SA",\r
418 region2use,\r
419 0,\r
420 p_cfg->def_heap_buf_size,\r
421 TUNE_NETAPI_CONFIG_MAX_PA_TO_SA_DESC,\r
422 0,\r
423 p_table);\r
424 if(nwalGlobCfg.pa2SaBufPool.bufPool[0].heapHandle == NULL)\r
425 {\r
426 printf (">Pktlib_createHeap:Heap Creation Failed for PA to SA Buffer Pool \n");\r
427 netapi_err_teardown(); \r
428 return -1;\r
429 }\r
430 \r
431 /* Initialize Buffer Pool for NetCP SA to PA packets */\r
432 nwalGlobCfg.sa2PaBufPool.numBufPools = 1;\r
433 nwalGlobCfg.sa2PaBufPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;\r
434 nwalGlobCfg.sa2PaBufPool.bufPool[0].bufSize = p_cfg->def_heap_buf_size;\r
435 \r
436 nwalGlobCfg.sa2PaBufPool.bufPool[0].heapHandle = p_nwal_context->sa2pa_heap=\r
437 Pktlib_createHeap("nwal SA2PA",\r
438 region2use,\r
439 0,\r
440 p_cfg->def_heap_buf_size,\r
441 TUNE_NETAPI_CONFIG_MAX_SA_TO_PA_DESC,\r
442 0,\r
443 p_table);\r
444 if(nwalGlobCfg.sa2PaBufPool.bufPool[0].heapHandle == NULL)\r
445 {\r
446 printf (">Pktlib_createHeap:Heap Creation Failed for SA to PA Buffer Pool \n");\r
447 netapi_err_teardown();\r
448 return -1;\r
449 }\r
450 \r
451 nwalGlobCfg.hopLimit = 5;/* Default TTL / Hop Limit */\r
452 nwalGlobCfg.lpbackPass = TUNE_NETAPI_NWAL_ENABLE_PASS_LOOPBACK;\r
453 nwalGlobCfg.paPowerOn = nwal_TRUE;\r
454 nwalGlobCfg.saPowerOn = nwal_TRUE;\r
455 nwalGlobCfg.paFwActive = nwal_TRUE;\r
456 nwalGlobCfg.saFwActive = nwal_FALSE;\r
457 \r
458 /* Pick Default Physical Address */\r
459 nwalGlobCfg.paVirtBaseAddr = (uint32_t) netapi_VM_passCfgVaddr;\r
460 nwalGlobCfg.saVirtBaseAddr = (uint32_t) netapi_VM_passCfgVaddr +\r
461 ((uint32_t)CSL_PA_SS_CFG_CP_ACE_CFG_REGS - (uint32_t)CSL_PA_SS_CFG_REGS) ;\r
462 nwalGlobCfg.rxDefPktQ = QMSS_PARAM_NOT_SPECIFIED;\r
463 \r
464 /* Get the Buffer Requirement from NWAL */\r
465 memset(&nwalMemBuf,0,sizeof(nwalMemBuf));\r
466 memset(&nwalSizeInfo,0,sizeof(nwalSizeInfo));\r
467 nwalSizeInfo.nMaxMacAddress = TUNE_NETAPI_MAX_NUM_MAC;\r
468 nwalSizeInfo.nMaxIpAddress = TUNE_NETAPI_MAX_NUM_IP;\r
469 nwalSizeInfo.nMaxL4Ports = TUNE_NETAPI_MAX_NUM_PORTS;\r
470 nwalSizeInfo.nMaxIpSecChannels = TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS;//we allocate 2 per channel\r
471 nwalSizeInfo.nMaxDmSecChannels = TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS;//we allocate 2 per channel\r
472 nwalSizeInfo.nMaxL2L3Hdr = TUNE_NETAPI_MAX_NUM_L2_L3_HDRS;\r
473 nwalSizeInfo.nProc = TUNE_NETAPI_NUM_CORES;\r
474 for(count=0;count < nwal_N_BUFS;count++)\r
475 {\r
476 nwalMemBuf[count].cacheLineSize = CACHE_LINESZ;\r
477 }\r
478 nwalRetVal = nwal_getBufferReq(&nwalSizeInfo,\r
479 sizes,\r
480 aligns);\r
481 if(nwalRetVal != nwal_OK)\r
482 {\r
483 printf (">netapi: init_nwal - nwal_getBufferReq Failed %d\n", nwalRetVal);\r
484 return nwal_FALSE;\r
485 }\r
486 \r
487 /* Check for memory size requirement and update the base */\r
488 count = 0;\r
489 bases[nwal_BUF_INDEX_INST] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)nwalInstMem);\r
490 if(NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE < sizes[nwal_BUF_INDEX_INST])\r
491 {\r
492 /* Resize Memory */\r
493 while(1);\r
494 }\r
495 count++;\r
496 \r
497 bases[nwal_BUF_INDEX_INT_HANDLES] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)nwalHandleMem);\r
498 if(NWAL_CHAN_HANDLE_SIZE < sizes[nwal_BUF_INDEX_INT_HANDLES])\r
499 {\r
500 /* Resize Memory */\r
501 while(1);\r
502 }\r
503 count++;\r
504 bases[nwal_BUF_INDEX_PA_LLD_BUF0] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf0);\r
505 if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0) < sizes[nwal_BUF_INDEX_PA_LLD_BUF0])\r
506 {\r
507 /* Resize Memory */\r
508 while(1);\r
509 }\r
510 count++;\r
511 \r
512 bases[nwal_BUF_INDEX_PA_LLD_BUF1] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf1);\r
513 if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1) < sizes[nwal_BUF_INDEX_PA_LLD_BUF1])\r
514 {\r
515 /* Resize Memory */\r
516 while(1);\r
517 }\r
518 count++;\r
519 \r
520 bases[nwal_BUF_INDEX_PA_LLD_BUF2] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf2);\r
521 if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2) < sizes[nwal_BUF_INDEX_PA_LLD_BUF2])\r
522 {\r
523 /* Resize Memory */\r
524 while(1);\r
525 }\r
526 count++;\r
527 #ifdef NETAPI_ENABLE_SECURITY\r
528 bases[nwal_BUF_INDEX_SA_LLD_HANDLE] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)salldHandle);\r
529 if((NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE) < sizes[nwal_BUF_INDEX_SA_LLD_HANDLE])\r
530 {\r
531 /* Resize Memory */\r
532 while(1);\r
533 }\r
534 count++;\r
535 \r
536 bases[nwal_BUF_INDEX_SA_CONTEXT] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)netapi_VM_SaContextVaddr);\r
537 count++;\r
538 \r
539 bases[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)salldChanHandle);\r
540 if((NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS*2) <\r
541 sizes[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE])\r
542 {\r
543 /* Resize Memory */\r
544 while(1);\r
545 }\r
546 count++;\r
547 #else\r
548 bases[nwal_BUF_INDEX_SA_LLD_HANDLE] = 0;\r
549 bases[nwal_BUF_INDEX_SA_CONTEXT] = 0;\r
550 bases[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE] = 0;\r
551 count = count+3;\r
552 #endif\r
553 if(count != nwal_N_BUFS)\r
554 {\r
555 while(1);\r
556 }\r
557 \r
558 /* Initialize NWAL module */\r
559 nwalRetVal = nwal_create(&nwalGlobCfg,\r
560 &nwalSizeInfo,\r
561 sizes,\r
562 bases,\r
563 &p_nwal_context->nwalInstHandle);\r
564 if(nwalRetVal != nwal_OK)\r
565 {\r
566 printf (">netapi: init_nwal- nwal_create Failed %d\n",nwalRetVal);\r
567 while(1);\r
568 }\r
569 \r
570 printf(">netapi: init_nwal - Global and Local Network initialization Successful \n");\r
571 return 1;\r
572 }\r
573 \r
574 //*************************************************\r
575 //* Local (per thread/core) nwal initialization0\r
576 //**************************************************\r
577 int netapi_start_nwal(Pktlib_HeapHandle pkt_heap,\r
578 Pktlib_HeapHandle cmd_heap,\r
579 NETAPI_NWAL_LOCAL_CONTEXT_T *p,\r
580 NETAPI_NWAL_GLOBAL_CONTEXT_T * p_nwal_glob_context )\r
581 {\r
582 nwalLocCfg_t nwalLocCfg;\r
583 int count;\r
584 nwal_RetValue nwalRetVal;\r
585 \r
586 memset(&nwalLocCfg,0,sizeof(nwalLocCfg));\r
587 \r
588 /* Common Initialization for all cores */\r
589 while(count < TUNE_NETAPI_MAX_NUM_TRANS)\r
590 {\r
591 p_nwal_glob_context->transInfos[count].transId = count;\r
592 count++;\r
593 }\r
594 \r
595 /* Call back registration for the core */\r
596 nwalLocCfg.pRxPktCallBack = netapi_NWALRxPktCallback;\r
597 nwalLocCfg.pCmdCallBack = netapi_NWALCmdCallBack;\r
598 nwalLocCfg.pPaStatsCallBack = netapi_NWALCmdPaStatsReply;\r
599 nwalLocCfg.pRxDmCallBack= netapi_NWALSBPktCallback; //sideband mode callback\r
600 \r
601 /* Initialize Buffer Pool for Control packets from NetCP to Host */\r
602 nwalLocCfg.rxCtlPool.numBufPools = 1;\r
603 nwalLocCfg.rxCtlPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;\r
604 nwalLocCfg.rxCtlPool.bufPool[0].bufSize = TUNE_NETAPI_CONFIG_MAX_CTL_RXTX_BUF_SIZE;\r
605 nwalLocCfg.rxCtlPool.bufPool[0].heapHandle = cmd_heap;\r
606 \r
607 /* Initialize Buffer Pool for Control packets from Host to NetCP */\r
608 nwalLocCfg.txCtlPool.numBufPools = 1;\r
609 nwalLocCfg.txCtlPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;\r
610 nwalLocCfg.txCtlPool.bufPool[0].bufSize = TUNE_NETAPI_CONFIG_MAX_CTL_RXTX_BUF_SIZE;\r
611 nwalLocCfg.txCtlPool.bufPool[0].heapHandle = cmd_heap;\r
612 \r
613 /* Initialize Buffer Pool for Packets from NetCP to Host */\r
614 nwalLocCfg.rxPktPool.numBufPools = 1;\r
615 nwalLocCfg.rxPktPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;\r
616 nwalLocCfg.rxPktPool.bufPool[0].bufSize = TUNE_NETAPI_DEFAULT_BUFFER_SIZE;\r
617 nwalLocCfg.rxPktPool.bufPool[0].heapHandle = pkt_heap;\r
618 \r
619 /* Initialize Buffer Pool for Packets from Host to NetCP */\r
620 nwalLocCfg.txPktPool.numBufPools = 1;\r
621 nwalLocCfg.txPktPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;\r
622 nwalLocCfg.txPktPool.bufPool[0].bufSize = TUNE_NETAPI_DEFAULT_BUFFER_SIZE;\r
623 nwalLocCfg.txPktPool.bufPool[0].heapHandle = pkt_heap;\r
624 \r
625 memcpy(&p->nwalLocCfg,&nwalLocCfg,sizeof(nwalLocCfg_t));\r
626 while(1)\r
627 {\r
628 nwalRetVal = nwal_start(p_nwal_glob_context->nwalInstHandle,&nwalLocCfg);\r
629 if(nwalRetVal == nwal_ERR_INVALID_STATE)\r
630 {\r
631 continue;\r
632 }\r
633 break;\r
634 }\r
635 \r
636 if(nwalRetVal != nwal_OK)\r
637 {\r
638 printf (">nwal_start:Failed ->err %d !!!\n", nwalRetVal);\r
639 return -1;\r
640 }\r
641 p->state = NETAPI_NW_CXT_LOC_ACTIVE;\r
642 return 1;\r
643 \r
644 \r
645 }\r
646 //***************************************************\r
647 // intialize timer\r
648 //***************************************************\r
649 int netapi_init_timer(void)\r
650 {\r
651 return t64_start();\r
652 }\r
653 \r
654 \r