This is the initial commit.
[keystone-rtos/netapi.git] / ti / runtime / netapi / src / netapi_init.c
1 /************************************************
2 *  FILE:  netapi_init.c
3 *  Global, local initialization of NETAPI
4  *
5  * DESCRIPTION: Functions to initialize framework resources for running NETAPI
6  *
7  * REVISION HISTORY:
8  *
9  *  Copyright (c) Texas Instruments Incorporated 2010-2011
10  * 
11  *  Redistribution and use in source and binary forms, with or without 
12  *  modification, are permitted provided that the following conditions 
13  *  are met:
14  *
15  *    Redistributions of source code must retain the above copyright 
16  *    notice, this list of conditions and the following disclaimer.
17  *
18  *    Redistributions in binary form must reproduce the above copyright
19  *    notice, this list of conditions and the following disclaimer in the 
20  *    documentation and/or other materials provided with the   
21  *    distribution.
22  *
23  *    Neither the name of Texas Instruments Incorporated nor the names of
24  *    its contributors may be used to endorse or promote products derived
25  *    from this software without specific prior written permission.
26  *
27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38  *
39  ***********************************************/
40 #include <stdint.h>
41 #include <stdio.h>
42 #include <string.h>
43 #include <sys/types.h>
44 #include <sys/stat.h>
45 #include <fcntl.h>
46 #include <sys/mman.h>
47 #include <errno.h>
48 #include <unistd.h>
50 #include <ti/drv/nwal/nwal.h>
51 #include "netapi.h"
52 #include "netapi_vm.h"
53 #include "netapi_loc.h"
54 #include "ti/drv/nwal/nwal.h"
56 /* CSL RL includes */
57 #include <ti/csl/cslr_device.h>
58 #include <ti/csl/cslr_qm_config.h>
59 #include <ti/csl/cslr_qm_descriptor_region_config.h>
60 #include <ti/csl/cslr_qm_queue_management.h>
61 #include <ti/csl/cslr_qm_queue_status_config.h>
62 #include <ti/csl/cslr_qm_intd.h>
63 #include <ti/csl/cslr_pdsp.h>
64 #include <ti/csl/csl_qm_queue.h>
65 #include <ti/csl/cslr_cppidma_global_config.h>
66 #include <ti/csl/cslr_cppidma_rx_channel_config.h>
67 #include <ti/csl/cslr_cppidma_rx_flow_config.h>
68 #include <ti/csl/cslr_cppidma_tx_channel_config.h>
69 #include <ti/csl/cslr_cppidma_tx_scheduler_config.h>
70 #include <ti/csl/csl_cppi.h>
71 #include <ti/csl/csl_pscAux.h>
72 #include <ti/csl/csl_semAux.h>
73 #include <ti/csl/csl_cacheAux.h>
74 #include <ti/csl/csl_xmcAux.h>
75 #include <ti/csl/csl_cpsw_3gfAux.h>
76 #include <ti/csl/csl_cpsw.h>
77 #include <ti/csl/csl_cpsgmiiAux.h>
78 #include <ti/drv/qmss/qmss_qm.h>
79 //pull in device config for qmss, cppi
80 #include <ti/drv/qmss/device/qmss_device.c>
81 #include <ti/drv/cppi/device/cppi_device.c>
83 /* TODO: */
84 #define DNUM    0
85 #define CACHE_LINESZ    64
87 #define System_printf   printf
88 #define ALIGN(x)    __attribute__((aligned (x)))
90 /*****************************************************************************
91  * Global Resources shared by all Cores
92  *****************************************************************************/
93 uint8_t *QMemGlobDescRam = 0;
94 uint8_t *cppiMemPaSaLinkBuf = 0;
95 uint8_t *cppiMemSaPaLinkBuf = 0;
97 /*****************************************************************************
98  * Local Resource allocated at each Core
99  *****************************************************************************/
100 /* Descriptors in global shared */
101 uint8_t *QMemLocDescRam = NULL;
102 uint8_t *cppiMemRxPktLinkBuf = NULL;
103 uint8_t *cppiMemTxPktLinkBuf = NULL;
104 uint8_t *cppiMemRxCtlLinkBuf = NULL;
105 uint8_t *cppiMemTxCtlLinkBuf = NULL;
108 //****************************************************
109 // initialize CPSW (switch) [per SOC]
110 //***************************************************
111 int netapi_init_cpsw(void)
113     CSL_CPSW_3GF_ALE_PORTCONTROL        alePortControlCfg;
115     CSL_CPSW_3GF_clearAleTable();
117     alePortControlCfg.dropUntaggedEnable    =   0;
118     alePortControlCfg.vidIngressCheckEnable =   0;
120     alePortControlCfg.mcastLimit            =   0;
121     alePortControlCfg.bcastLimit            =   0;
123     /* Disable learning mode for Port 0 */
124     alePortControlCfg.noLearnModeEnable     =   1;
125     alePortControlCfg.portState     =   ALE_PORTSTATE_FORWARD;
126     CSL_CPSW_3GF_setAlePortControlReg (0, &alePortControlCfg);
128     /* Enable learning mode for Port 1 */
129     alePortControlCfg.noLearnModeEnable     =   0;
130     alePortControlCfg.portState     =   ALE_PORTSTATE_FORWARD;
131     CSL_CPSW_3GF_setAlePortControlReg (1, &alePortControlCfg);
133     /* Enable learning mode for Port 2 */
134     alePortControlCfg.noLearnModeEnable     =   0;
135     alePortControlCfg.portState     =   ALE_PORTSTATE_FORWARD;
136     CSL_CPSW_3GF_setAlePortControlReg (2, &alePortControlCfg);
138     return 1;
141 //****************************************************
142 // initialize QM (per SOC)
143 //***************************************************
144 int netapi_init_qm(void)
146   Qmss_InitCfg     qmssInitConfig;
147   int32_t          result;
148   Qmss_GlobalConfigParams nwalTest_qmssGblCfgParams;
150   memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));
152   /* Use Internal Linking RAM for optimal performance */
153   qmssInitConfig.linkingRAM0Base = 0;
154   qmssInitConfig.linkingRAM0Size = 0;
155   qmssInitConfig.linkingRAM1Base = 0;
156   qmssInitConfig.maxDescNum      = TUNE_NETAPI_QM_CONFIG_MAX_DESC_NUM;
157   qmssInitConfig.qmssHwStatus =QMSS_HW_INIT_COMPLETE; //bypass some of the hw init
158   nwalTest_qmssGblCfgParams = qmssGblCfgParams[0];
160   nwalTest_qmssGblCfgParams.qmConfigReg = (void *)((uint8_t *)netapi_VM_qmssCfgVaddr +
161       (CSL_QM_SS_CFG_CONFIG_STARVATION_COUNTER_REGS - CSL_QM_SS_CFG_QUE_PEEK_REGS));
162   nwalTest_qmssGblCfgParams.qmDescReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
163       ((uint32_t)CSL_QM_SS_CFG_DESCRIPTION_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
164   nwalTest_qmssGblCfgParams.qmQueMgmtReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
165       ((uint32_t)CSL_QM_SS_CFG_QM_QUEUE_DEQUEUE_REGS)  - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
166   nwalTest_qmssGblCfgParams.qmQueMgmtProxyReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
167       ((uint32_t)CSL_QM_SS_CFG_PROXY_QUEUE_DEQUEUE_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
168   nwalTest_qmssGblCfgParams.qmQueStatReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
169       ((uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
170   nwalTest_qmssGblCfgParams.qmQueIntdReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
171       ((uint32_t)CSL_QM_SS_CFG_INTD_REGS)  - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
172   nwalTest_qmssGblCfgParams.qmPdspCmdReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
173       ((uint32_t)CSL_QM_SS_CFG_SCRACH_RAM1_REGS)  - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
174   nwalTest_qmssGblCfgParams.qmPdspCmdReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
175       ((uint32_t)CSL_QM_SS_CFG_SCRACH_RAM2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
176   nwalTest_qmssGblCfgParams.qmPdspCtrlReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
177       ((uint32_t)CSL_QM_SS_CFG_ADSP1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
178   nwalTest_qmssGblCfgParams.qmPdspCtrlReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
179       ((uint32_t)CSL_QM_SS_CFG_ADSP2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
180   nwalTest_qmssGblCfgParams.qmPdspIRamReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
181       ((uint32_t)CSL_QM_SS_CFG_APDSP1_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
182   nwalTest_qmssGblCfgParams.qmPdspIRamReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
183       ((uint32_t)CSL_QM_SS_CFG_APDSP2_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
184   nwalTest_qmssGblCfgParams.qmStatusRAM = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
185       ((uint32_t)CSL_QM_SS_CFG_QM_STATUS_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
186   nwalTest_qmssGblCfgParams.qmLinkingRAMReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
187       ((uint32_t)CSL_QM_SS_CFG_LINKING_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
188   nwalTest_qmssGblCfgParams.qmMcDMAReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
189       ((uint32_t)CSL_QM_SS_CFG_MCDMA_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
190   nwalTest_qmssGblCfgParams.qmTimer16Reg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
191       ((uint32_t)CSL_QM_SS_CFG_TIMER1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
192   nwalTest_qmssGblCfgParams.qmTimer16Reg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
193       ((uint32_t)CSL_QM_SS_CFG_TIMER2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
194   nwalTest_qmssGblCfgParams.qmQueMgmtDataReg = (void *)((uint32_t)netapi_VM_qmssDataVaddr);
195   nwalTest_qmssGblCfgParams.qmQueMgmtProxyDataReg = 
196       (void *)((uint32_t)netapi_VM_qmssDataVaddr + ((uint32_t)(0x44040000) - (uint32_t)(0x44020000)));
198   result = Qmss_init (&qmssInitConfig, &nwalTest_qmssGblCfgParams);
199   if (result != QMSS_SOK)  {
200     System_printf ("function init_qm: qmss_Init failed with error code %d\n", result);
201     return (nwal_FALSE);
202   }
204         return 1;
207 //****************************************************
208 // Set up  QM memory region (per SOC)
209 //***************************************************
210 int netapi_qm_setup_mem_region(
211                       uint32_t          numDesc,
212                       uint32_t          descSize,
213                       uint32_t*         pDescMemBase,
214                       Qmss_MemRegion    memRegion)
216   Qmss_MemRegInfo   memInfo;
217   Int32             result;
218   Int               n;
219   static int  netapi_qm_region_index=0;
221   memset(&memInfo,0,sizeof(Qmss_MemRegInfo));
222   memInfo.descBase       = pDescMemBase;
223   memInfo.descSize       = descSize;
224   memInfo.descNum        = numDesc;
225   memInfo.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
226   memInfo.memRegion      = memRegion==NETAPI_GLOBAL_REGION ? Qmss_MemRegion_MEMORY_REGION0 : Qmss_MemRegion_MEMORY_REGION1;
228   if(memRegion == NETAPI_GLOBAL_REGION)
229   {
230       memInfo.startIndex = 0;
231       netapi_qm_region_index += numDesc;
232   }else if(memRegion ==NETAPI_LOCAL_REGION)
233   {
234       /* Global shared memory for all descriptors to all cores */
235       memInfo.startIndex     = netapi_qm_region_index;
236   }
237   else
238   {
239       return -1 ;
240   }
242   result = Qmss_insertMemoryRegion (&memInfo);
243   if (result < QMSS_SOK)  
244   {
245     printf ("function setup_qm_region: Qmss_insertMemoryRegion returned error code %d\n", result);
246     return (-1);
247   }
249   return 1;
253 //****************************************************
254 // Start QM (per thread)
255 //***************************************************
256 int netapi_start_qm(void)
258      int32_t          result;
259      result = Qmss_start();
260      if (result != QMSS_SOK)
261      {
262          System_printf ("start_qm: Qmss_start failed with error code %d\n", result);
263          return (-1);
264      }
265      return 1;
268 //*************************************************
269 //initilaize CPPI (once per soc)
270 //*************************************************
271 int netapi_init_cppi(void)
273   int32_t result, i;
274   Cppi_GlobalConfigParams nwalTest_cppiGblCfgParams[CPPI_MAX_CPDMA];
276   for (i=0; i<CPPI_MAX_CPDMA; i++)
277     nwalTest_cppiGblCfgParams[i] = cppiGblCfgParams[i];
279   /* SRIO CPDMA regs */
280   nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs =
281       (void *)((uint32_t)netapi_VM_srioCfgVaddr +
282                (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
283   nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txChRegs =
284       (void *)((uint32_t)netapi_VM_srioCfgVaddr +
285                (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
287   nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxChRegs =
288       (void *)((uint32_t)netapi_VM_srioCfgVaddr +
289                (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
290   nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txSchedRegs =
291       (void *)((uint32_t)netapi_VM_srioCfgVaddr +
292                (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
293  nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs =
294       (void *)((uint32_t)netapi_VM_srioCfgVaddr +
295                (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
297   /* PASS CPDMA regs */
298   nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].gblCfgRegs =
299       (void *)((uint32_t)netapi_VM_passCfgVaddr +
300                (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
301   nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txChRegs =
302       (void *)((uint32_t)netapi_VM_passCfgVaddr +
303                (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
304   nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxChRegs =
305       (void *)((uint32_t)netapi_VM_passCfgVaddr +
306                (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
307   nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txSchedRegs =
308       (void *)((uint32_t)netapi_VM_passCfgVaddr +
309                (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
310   nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxFlowRegs =
311       (void *)((uint32_t)netapi_VM_passCfgVaddr +
312                (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
313  /* QMSS CPDMA regs */
314   nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs =
315       (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
316                (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
317   nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txChRegs =
318       (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
319                (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
320   nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxChRegs =
321       (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
322                (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
323   nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txSchedRegs =
324       (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
325                (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
326   nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs =
327       (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
328                (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
330   result = Cppi_init (nwalTest_cppiGblCfgParams);
331   if (result != CPPI_SOK)  
332   {
333     printf ("function cppi_init: Cppi_init failed with error code %d\n", result);
334     return (-1);
335   }
336    return 1;
339 //*************************************************
340 //initialize NWAL (one per soc) 
341 //*************************************************
342 /*** NWAL Memory Buffer Configuration ***/
343 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE     3400
344 uint8_t nwalInstMem[NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE]ALIGN(CACHE_LINESZ);
346 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_MAC                    128
347 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_IPSEC_HANDLE_PER_CHAN      256
348 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_IP                     128
349 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_PORT                   128
350 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_L2L3_HDR               128
351 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_LOC_CONTEXT            384
352 #define NWAL_CHAN_HANDLE_SIZE    ((NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_MAC * TUNE_NETAPI_MAX_NUM_MAC) + \
353                                   (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_IPSEC_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS) + \
354                                   (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_IP * TUNE_NETAPI_MAX_NUM_IP) + \
355                                   (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_PORT * TUNE_NETAPI_MAX_NUM_PORTS)+ \
356                                   (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_LOC_CONTEXT * TUNE_NETAPI_NUM_CORES) + \
357                                   (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_L2L3_HDR * TUNE_NETAPI_MAX_NUM_L2_L3_HDRS))
359 uint8_t nwalHandleMem[NWAL_CHAN_HANDLE_SIZE]ALIGN(CACHE_LINESZ);
361 /* todo: Check if below size information can be made available from pa interface file */
362 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0      128
363 /* PA instance */
364 /* Memory used for the PA Instance. Needs to be assigned global uncached memory for chip */
365 uint8_t paBuf0[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0]ALIGN(CACHE_LINESZ);
367 /* Memory used for PA handles */
368 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1    128
369 uint8_t paBuf1[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1]ALIGN(CACHE_LINESZ);
371 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2    256
372 uint8_t paBuf2[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2]ALIGN(CACHE_LINESZ);
374 /* Memory used for SA LLD global Handle */
375 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE    384
376 uint8_t salldHandle[NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE]ALIGN(CACHE_LINESZ);
378 /* Memory used for SA LLD global Handle */
379 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_CONTEXT_PER_CHAN             384
380 uint8_t saContext[NETAPI_NWAL_CONFIG_BUFSIZE_SA_CONTEXT_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS]ALIGN(CACHE_LINESZ);
382 /* Memory used by SA LLD per Channel */
383 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN          512
384 uint8_t salldChanHandle[NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS]ALIGN(CACHE_LINESZ);
387 /*******************************************
388  * Initialize the nwal subsystem for NETAPI use
389  ***********************************************/
390 int netapi_init_nwal(
391      int region2use,  
392      Pktlib_HeapIfTable * p_table,
393      NETAPI_NWAL_GLOBAL_CONTEXT_T * p_nwal_context )
395     nwalSizeInfo_t  nwalSizeInfo;
396     nwalMemBuf_t    nwalMemBuf[nwal_N_BUFS];
397     nwal_RetValue   nwalRetVal;
398     nwalGlobCfg_t   nwalGlobCfg;
399     uint8_t         count;
400     int             sizes[nwal_N_BUFS];
401     int             aligns[nwal_N_BUFS];
402     void*           bases[nwal_N_BUFS];
404     memset(p_nwal_context,0,sizeof( NETAPI_NWAL_GLOBAL_CONTEXT_T) );
405     memset(&nwalGlobCfg,0,sizeof(nwalGlobCfg_t ) );
408     /* Initialize Buffer Pool for NetCP PA to SA packets */
409     nwalGlobCfg.pa2SaBufPool.numBufPools = 1;
410     nwalGlobCfg.pa2SaBufPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
411     nwalGlobCfg.pa2SaBufPool.bufPool[0].bufSize =  TUNE_NETAPI_DEFAULT_BUFFER_SIZE;
412     nwalGlobCfg.pa2SaBufPool.bufPool[0].heapHandle =
413     Pktlib_createHeap("nwal PA2SA",
414                        region2use,
415                        0,
416                        TUNE_NETAPI_DEFAULT_BUFFER_SIZE,
417                        TUNE_NETAPI_CONFIG_MAX_PA_TO_SA_DESC,
418                        0,
419                        p_table);
420     if(nwalGlobCfg.pa2SaBufPool.bufPool[0].heapHandle == NULL)
421     {
422         printf ("Pktlib_createHeap:Heap Creation Failed for PA to SA Buffer Pool \n");
423         netapi_err_teardown(); 
424         return -1;
425     }
427  /* Initialize Buffer Pool for NetCP SA to PA packets */
428     nwalGlobCfg.sa2PaBufPool.numBufPools = 1;
429     nwalGlobCfg.sa2PaBufPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
430     nwalGlobCfg.sa2PaBufPool.bufPool[0].bufSize =  TUNE_NETAPI_DEFAULT_BUFFER_SIZE;
432     nwalGlobCfg.sa2PaBufPool.bufPool[0].heapHandle =
433         Pktlib_createHeap("nwal SA2PA",
434                           region2use,
435                           0,
436                           TUNE_NETAPI_DEFAULT_BUFFER_SIZE,
437                           TUNE_NETAPI_CONFIG_MAX_SA_TO_PA_DESC,
438                           0,
439                           p_table);
440     if(nwalGlobCfg.sa2PaBufPool.bufPool[0].heapHandle == NULL)
441     {
442         printf ("Pktlib_createHeap:Heap Creation Failed for SA to PA Buffer Pool \n");
443         netapi_err_teardown();
444         return -1;
445     }
447     nwalGlobCfg.hopLimit = 5;/* Default TTL / Hop Limit */
448     nwalGlobCfg.lpbackPass = TUNE_NETAPI_NWAL_ENABLE_PASS_LOOPBACK;
449     nwalGlobCfg.paFwActive = nwal_TRUE;
450     nwalGlobCfg.saFwActive = nwal_TRUE;
452     /* Pick Default Physical Address */
453     nwalGlobCfg.paVirtBaseAddr = (uint32_t) netapi_VM_passCfgVaddr;
454     nwalGlobCfg.saVirtBaseAddr = (uint32_t) netapi_VM_passCfgVaddr +
455                                  ((uint32_t)CSL_PA_SS_CFG_CP_ACE_CFG_REGS - (uint32_t)CSL_PA_SS_CFG_REGS) ;
456     nwalGlobCfg.rxDefPktQ = QMSS_PARAM_NOT_SPECIFIED;
458     /* Get the Buffer Requirement from NWAL */
459     memset(&nwalMemBuf,0,sizeof(nwalMemBuf));
460     memset(&nwalSizeInfo,0,sizeof(nwalSizeInfo));
461     nwalSizeInfo.nMaxMacAddress = TUNE_NETAPI_MAX_NUM_MAC;
462     nwalSizeInfo.nMaxIpAddress = TUNE_NETAPI_MAX_NUM_IP;
463     nwalSizeInfo.nMaxL4Ports = TUNE_NETAPI_MAX_NUM_PORTS;
464     nwalSizeInfo.nMaxIpSecChannels = TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS;
465     nwalSizeInfo.nMaxL2L3Hdr = TUNE_NETAPI_MAX_NUM_L2_L3_HDRS;
466     nwalSizeInfo.nProc = TUNE_NETAPI_NUM_CORES;
467     for(count=0;count < nwal_N_BUFS;count++)
468     {
469         nwalMemBuf[count].cacheLineSize = CACHE_LINESZ;
470     }
471     nwalRetVal = nwal_getBufferReq(&nwalSizeInfo,
472                                    sizes,
473                                    aligns);
474     if(nwalRetVal != nwal_OK)
475     {
476         printf ("init_nwal: nwal_getBufferReq Failed %d\n", nwalRetVal);
477         return nwal_FALSE;
478     }
480 /* Check for memory size requirement and update the base */
481     count = 0;
482     bases[nwal_BUF_INDEX_INST] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)nwalInstMem);
483     if(NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE < sizes[nwal_BUF_INDEX_INST])
484     {
485         /* Resize Memory */
486         while(1);
487     }
488     count++;
490     bases[nwal_BUF_INDEX_INT_HANDLES] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)nwalHandleMem);
491     if(NWAL_CHAN_HANDLE_SIZE  < sizes[nwal_BUF_INDEX_INT_HANDLES])
492     {
493         /* Resize Memory */
494         while(1);
495     }
496     count++;
497      bases[nwal_BUF_INDEX_PA_LLD_BUF0] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf0);
498     if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0) < sizes[nwal_BUF_INDEX_PA_LLD_BUF0])
499     {
500         /* Resize Memory */
501         while(1);
502     }
503     count++;
505     bases[nwal_BUF_INDEX_PA_LLD_BUF1] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf1);
506     if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1) < sizes[nwal_BUF_INDEX_PA_LLD_BUF1])
507     {
508         /* Resize Memory */
509         while(1);
510     }
511     count++;
513      bases[nwal_BUF_INDEX_PA_LLD_BUF2] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf2);
514     if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2) < sizes[nwal_BUF_INDEX_PA_LLD_BUF2])
515     {
516         /* Resize Memory */
517         while(1);
518     }
519     count++;
520 #ifdef NETAPI_ENABLE_SECURITY
521     bases[nwal_BUF_INDEX_SA_LLD_HANDLE] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)salldHandle);
522     if((NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE) < sizes[nwal_BUF_INDEX_SA_LLD_HANDLE])
523     {
524         /* Resize Memory */
525         while(1);
526     }
527     count++;
529     bases[nwal_BUF_INDEX_SA_CONTEXT] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)saContext);
530     if((NETAPI_NWAL_CONFIG_BUFSIZE_SA_CONTEXT_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS) <
531         sizes[nwal_BUF_INDEX_SA_CONTEXT])
532     {
533         /* Resize Memory */
534         while(1);
535     }
536     count++;
538     bases[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)salldChanHandle);
539     if((NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS) <
540         sizes[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE])
541     {
542         /* Resize Memory */
543         while(1);
544     }
545     count++;
546 #else
547     bases[nwal_BUF_INDEX_SA_LLD_HANDLE] = 0;
548     bases[nwal_BUF_INDEX_SA_CONTEXT] = 0;
549     bases[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE] = 0;
550     count = count+3;
551 #endif
552     if(count != nwal_N_BUFS)
553     {
554         while(1);
555     }
557     /* Initialize NWAL module */
558     nwalRetVal = nwal_create(&nwalGlobCfg,
559                              &nwalSizeInfo,
560                              sizes,
561                              bases,
562                              &p_nwal_context->nwalInstHandle);
563     if(nwalRetVal != nwal_OK)
564     {
565         printf ("init_nwal: nwal_create Failed %d\n",nwalRetVal);
566         while(1);
567     }
569     printf("init_nwal: Global and Local Network initialization Successful \n");
570     return 1;
573 //*************************************************
574 //* Local (per thread/core) nwal initialization0
575 //**************************************************
576 int netapi_start_nwal(Pktlib_HeapHandle pkt_heap,
577                     Pktlib_HeapHandle cmd_heap,
578                      NETAPI_NWAL_LOCAL_CONTEXT_T *p,
579                      NETAPI_NWAL_GLOBAL_CONTEXT_T * p_nwal_glob_context  )
581     nwalLocCfg_t    nwalLocCfg;
582     int count;
583     nwal_RetValue       nwalRetVal;
585     memset(&nwalLocCfg,0,sizeof(nwalLocCfg));
587     /* Common Initialization for all cores */
588     while(count < TUNE_NETAPI_MAX_NUM_TRANS)
589     {
590         p_nwal_glob_context->transInfos[count].transId = count;
591         count++;
592     }
594  /* Call back registration for the core */
595     nwalLocCfg.pRxPktCallBack = netapi_NWALRxPktCallback;
596     nwalLocCfg.pCmdCallBack = netapi_NWALCmdCallBack;
597     nwalLocCfg.pPaStatsCallBack = netapi_NWALCmdPaStatsReply;
599     /* Initialize Buffer Pool for Control packets from NetCP to Host */
600     nwalLocCfg.rxCtlPool.numBufPools = 1;
601     nwalLocCfg.rxCtlPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
602     nwalLocCfg.rxCtlPool.bufPool[0].bufSize = TUNE_NETAPI_CONFIG_MAX_CTL_RXTX_BUF_SIZE;
603     nwalLocCfg.rxCtlPool.bufPool[0].heapHandle = cmd_heap;
605     /* Initialize Buffer Pool for Control packets from Host to NetCP */
606     nwalLocCfg.txCtlPool.numBufPools = 1;
607     nwalLocCfg.txCtlPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
608     nwalLocCfg.txCtlPool.bufPool[0].bufSize = TUNE_NETAPI_CONFIG_MAX_CTL_RXTX_BUF_SIZE;
609     nwalLocCfg.txCtlPool.bufPool[0].heapHandle =  cmd_heap;
611 /* Initialize Buffer Pool for Packets from NetCP to Host */
612     nwalLocCfg.rxPktPool.numBufPools = 1;
613     nwalLocCfg.rxPktPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
614     nwalLocCfg.rxPktPool.bufPool[0].bufSize =  TUNE_NETAPI_DEFAULT_BUFFER_SIZE;
615     nwalLocCfg.rxPktPool.bufPool[0].heapHandle = pkt_heap;
617 /* Initialize Buffer Pool for Packets from Host to NetCP */
618     nwalLocCfg.txPktPool.numBufPools = 1;
619     nwalLocCfg.txPktPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
620     nwalLocCfg.txPktPool.bufPool[0].bufSize =  TUNE_NETAPI_DEFAULT_BUFFER_SIZE;
621     nwalLocCfg.txPktPool.bufPool[0].heapHandle = pkt_heap;
623     memcpy(&p->nwalLocCfg,&nwalLocCfg,sizeof(nwalLocCfg_t));
624     while(1)
625     {
626         nwalRetVal = nwal_start(p_nwal_glob_context->nwalInstHandle,&nwalLocCfg);
627         if(nwalRetVal == nwal_ERR_INVALID_STATE)
628         {
629             continue;
630         }
631         break;
632     }
634     if(nwalRetVal != nwal_OK)
635     {
636         printf ("nwal_start:Failed ->err %d !!!\n", nwalRetVal);
637         return -1;
638     }
639     p->state = NETAPI_NW_CXT_LOC_ACTIVE;
640     return 1;
644 //***************************************************
645 // intialize timer
646 //***************************************************
647 int netapi_init_timer(void)
649         return t64_start();