ti/runtime/netapi/src/netapi_init.c

   1 /************************************************
   2 *  FILE:  netapi_init.c
   3 *  Global, local initialization of NETAPI
   4  *
   5  * DESCRIPTION: Functions to initialize framework resources for running NETAPI
   6  *
   7  * REVISION HISTORY:
   8  *
   9  *  Copyright (c) Texas Instruments Incorporated 2010-2011
  10  *
  11  *  Redistribution and use in source and binary forms, with or without
  12  *  modification, are permitted provided that the following conditions
  13  *  are met:
  14  *
  15  *    Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  *
  18  *    Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the
  21  *    distribution.
  22  *
  23  *    Neither the name of Texas Instruments Incorporated nor the names of
  24  *    its contributors may be used to endorse or promote products derived
  25  *    from this software without specific prior written permission.
  26  *
  27  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  35  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  36  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  *
  39  ***********************************************/
  40 #include <stdint.h>
  41 #include <stdio.h>
  42 #include <string.h>
  43 #include <sys/types.h>
  44 #include <sys/stat.h>
  45 #include <fcntl.h>
  46 #include <sys/mman.h>
  47 #include <errno.h>
  48 #include <unistd.h>
  49
  50 #include <ti/drv/nwal/nwal.h>
  51 #include "netapi.h"
  52 #include "netapi_vm.h"
  53 #include "netapi_loc.h"
  54 #include "ti/drv/nwal/nwal.h"
  55
  56 /* CSL RL includes */
  57 #include <ti/csl/cslr_device.h>
  58 #include <ti/csl/cslr_qm_config.h>
  59 #include <ti/csl/cslr_qm_descriptor_region_config.h>
  60 #include <ti/csl/cslr_qm_queue_management.h>
  61 #include <ti/csl/cslr_qm_queue_status_config.h>
  62 #include <ti/csl/cslr_qm_intd.h>
  63 #include <ti/csl/cslr_pdsp.h>
  64 #include <ti/csl/csl_qm_queue.h>
  65 #include <ti/csl/cslr_cppidma_global_config.h>
  66 #include <ti/csl/cslr_cppidma_rx_channel_config.h>
  67 #include <ti/csl/cslr_cppidma_rx_flow_config.h>
  68 #include <ti/csl/cslr_cppidma_tx_channel_config.h>
  69 #include <ti/csl/cslr_cppidma_tx_scheduler_config.h>
  70 #include <ti/csl/csl_cppi.h>
  71 #include <ti/csl/csl_pscAux.h>
  72 #include <ti/csl/csl_semAux.h>
  73 #include <ti/csl/csl_cacheAux.h>
  74 #include <ti/csl/csl_xmcAux.h>
  75 #include <ti/csl/csl_cpsw_3gfAux.h>
  76 #include <ti/csl/csl_cpsw.h>
  77 #include <ti/csl/csl_cpsgmiiAux.h>
  78 #include <ti/drv/qmss/qmss_qm.h>
  79 //pull in device config for qmss, cppi
  80 #include <ti/drv/qmss/device/qmss_device.c>
  81 #include <ti/drv/cppi/device/cppi_device.c>
  82
  83 /* TODO verify: */
  84 #define CACHE_LINESZ    64
  85
  86 #define System_printf   printf
  87 #define ALIGN(x)    __attribute__((aligned (x)))
  88
  89 /*****************************************************************************
  90  * Global Resources shared by all Cores
  91  *****************************************************************************/
  92 uint8_t *QMemGlobDescRam = 0;
  93 uint8_t *cppiMemPaSaLinkBuf = 0;
  94 uint8_t *cppiMemSaPaLinkBuf = 0;
  95
  96 /*****************************************************************************
  97  * Local Resource allocated at each Core
  98  *****************************************************************************/
  99 /* Descriptors in global shared */
 100 uint8_t *QMemLocDescRam = NULL;
 101 uint8_t *cppiMemRxPktLinkBuf = NULL;
 102 uint8_t *cppiMemTxPktLinkBuf = NULL;
 103 uint8_t *cppiMemRxCtlLinkBuf = NULL;
 104 uint8_t *cppiMemTxCtlLinkBuf = NULL;
 105
 106
 107 //****************************************************
 108 // initialize CPSW (switch) [per SOC]
 109 //***************************************************
 110 int netapi_init_cpsw(void)
 111 {
 112     CSL_CPSW_3GF_ALE_PORTCONTROL        alePortControlCfg;
 113
 114     CSL_CPSW_3GF_clearAleTable();
 115
 116     alePortControlCfg.dropUntaggedEnable    =   0;
 117     alePortControlCfg.vidIngressCheckEnable =   0;
 118
 119     alePortControlCfg.mcastLimit            =   0;
 120     alePortControlCfg.bcastLimit            =   0;
 121
 122     /* Disable learning mode for Port 0 */
 123     alePortControlCfg.noLearnModeEnable     =   1;
 124     alePortControlCfg.portState     =   ALE_PORTSTATE_FORWARD;
 125     CSL_CPSW_3GF_setAlePortControlReg (0, &alePortControlCfg);
 126
 127     /* Enable learning mode for Port 1 */
 128     alePortControlCfg.noLearnModeEnable     =   0;
 129     alePortControlCfg.portState     =   ALE_PORTSTATE_FORWARD;
 130     CSL_CPSW_3GF_setAlePortControlReg (1, &alePortControlCfg);
 131
 132     /* Enable learning mode for Port 2 */
 133     alePortControlCfg.noLearnModeEnable     =   0;
 134     alePortControlCfg.portState     =   ALE_PORTSTATE_FORWARD;
 135     CSL_CPSW_3GF_setAlePortControlReg (2, &alePortControlCfg);
 136
 137     return 1;
 138 }
 139
 140 //****************************************************
 141 // initialize QM (per SOC)
 142 //***************************************************
 143 int netapi_init_qm(int max_descriptors)
 144 {
 145   Qmss_InitCfg     qmssInitConfig;
 146   int32_t          result;
 147   Qmss_GlobalConfigParams nwalTest_qmssGblCfgParams;
 148
 149   memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));
 150
 151   /* Use Internal Linking RAM for optimal performance */
 152   qmssInitConfig.linkingRAM0Base = 0;
 153   qmssInitConfig.linkingRAM0Size = 0;
 154   qmssInitConfig.linkingRAM1Base = 0;
 155   qmssInitConfig.maxDescNum      = max_descriptors;
 156   qmssInitConfig.qmssHwStatus =QMSS_HW_INIT_COMPLETE; //bypass some of the hw init
 157   nwalTest_qmssGblCfgParams = qmssGblCfgParams[0];
 158
 159   nwalTest_qmssGblCfgParams.qmConfigReg = (void *)((uint8_t *)netapi_VM_qmssCfgVaddr +
 160       (CSL_QM_SS_CFG_CONFIG_STARVATION_COUNTER_REGS - CSL_QM_SS_CFG_QUE_PEEK_REGS));
 161   nwalTest_qmssGblCfgParams.qmDescReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 162       ((uint32_t)CSL_QM_SS_CFG_DESCRIPTION_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 163   nwalTest_qmssGblCfgParams.qmQueMgmtReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 164       ((uint32_t)CSL_QM_SS_CFG_QM_QUEUE_DEQUEUE_REGS)  - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 165   nwalTest_qmssGblCfgParams.qmQueMgmtProxyReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 166       ((uint32_t)CSL_QM_SS_CFG_PROXY_QUEUE_DEQUEUE_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 167   nwalTest_qmssGblCfgParams.qmQueStatReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 168       ((uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 169   nwalTest_qmssGblCfgParams.qmQueIntdReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 170       ((uint32_t)CSL_QM_SS_CFG_INTD_REGS)  - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 171   nwalTest_qmssGblCfgParams.qmPdspCmdReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 172       ((uint32_t)CSL_QM_SS_CFG_SCRACH_RAM1_REGS)  - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 173   nwalTest_qmssGblCfgParams.qmPdspCmdReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 174       ((uint32_t)CSL_QM_SS_CFG_SCRACH_RAM2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 175   nwalTest_qmssGblCfgParams.qmPdspCtrlReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 176       ((uint32_t)CSL_QM_SS_CFG_ADSP1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 177   nwalTest_qmssGblCfgParams.qmPdspCtrlReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 178       ((uint32_t)CSL_QM_SS_CFG_ADSP2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 179   nwalTest_qmssGblCfgParams.qmPdspIRamReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 180       ((uint32_t)CSL_QM_SS_CFG_APDSP1_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 181   nwalTest_qmssGblCfgParams.qmPdspIRamReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 182       ((uint32_t)CSL_QM_SS_CFG_APDSP2_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 183   nwalTest_qmssGblCfgParams.qmStatusRAM = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 184       ((uint32_t)CSL_QM_SS_CFG_QM_STATUS_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 185   nwalTest_qmssGblCfgParams.qmLinkingRAMReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 186       ((uint32_t)CSL_QM_SS_CFG_LINKING_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 187   nwalTest_qmssGblCfgParams.qmMcDMAReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 188       ((uint32_t)CSL_QM_SS_CFG_MCDMA_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 189   nwalTest_qmssGblCfgParams.qmTimer16Reg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 190       ((uint32_t)CSL_QM_SS_CFG_TIMER1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 191   nwalTest_qmssGblCfgParams.qmTimer16Reg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 192       ((uint32_t)CSL_QM_SS_CFG_TIMER2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
 193   nwalTest_qmssGblCfgParams.qmQueMgmtDataReg = (void *)((uint32_t)netapi_VM_qmssDataVaddr);
 194   nwalTest_qmssGblCfgParams.qmQueMgmtProxyDataReg =
 195       (void *)((uint32_t)netapi_VM_qmssDataVaddr + ((uint32_t)(0x44040000) - (uint32_t)(0x44020000)));
 196
 197   result = Qmss_init (&qmssInitConfig, &nwalTest_qmssGblCfgParams);
 198   if (result != QMSS_SOK)  {
 199     System_printf (">function init_qm: qmss_Init failed with error code %d\n", result);
 200     return (nwal_FALSE);
 201   }
 202
 203         return 1;
 204 }
 205
 206 //****************************************************
 207 // Set up  QM memory region (per SOC)
 208 //***************************************************
 209 int netapi_qm_setup_mem_region(
 210                       uint32_t          numDesc,
 211                       uint32_t          descSize,
 212                       uint32_t*         pDescMemBase,
 213                       Qmss_MemRegion    memRegion)
 214 {
 215   Qmss_MemRegInfo   memInfo;
 216   Int32             result;
 217   Int               n;
 218   static int  netapi_qm_region_index=0;
 219
 220   memset(&memInfo,0,sizeof(Qmss_MemRegInfo));
 221   memInfo.descBase       = pDescMemBase;
 222   memInfo.descSize       = descSize;
 223   memInfo.descNum        = numDesc;
 224   memInfo.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
 225   memInfo.memRegion      = memRegion;
 226
 227   if(memRegion == NETAPI_GLOBAL_REGION)
 228   {
 229       memInfo.startIndex = TUNE_NETAPI_QM_START_INDEX;  //was 0
 230       netapi_qm_region_index += numDesc;
 231   }else if(memRegion ==NETAPI_LOCAL_REGION)
 232   {
 233       /* 2nd region for descriptors (perhaps private?) */
 234       memInfo.startIndex     = netapi_qm_region_index;
 235   }
 236   else
 237   {
 238       return -1 ;
 239   }
 240
 241   memset (pDescMemBase, 0, (descSize * numDesc));
 242
 243   result = Qmss_insertMemoryRegion (&memInfo);
 244   if (result < QMSS_SOK)
 245   {
 246     printf (">function setup_qm_region: Qmss_insertMemoryRegion returned error code %d\n", result);
 247     return (-1);
 248   }
 249
 250   return 1;
 251
 252 }
 253
 254 //****************************************************
 255 // Start QM (per thread)
 256 //***************************************************
 257 int netapi_start_qm(void)
 258 {
 259      int32_t          result;
 260      result = Qmss_start();
 261      if (result != QMSS_SOK)
 262      {
 263          System_printf (">start_qm: Qmss_start failed with error code %d\n", result);
 264          return (-1);
 265      }
 266      return 1;
 267 }
 268
 269 //*************************************************
 270 //initilaize CPPI (once per soc)
 271 //*************************************************
 272 int netapi_init_cppi(void)
 273 {
 274   int32_t result, i;
 275   Cppi_GlobalConfigParams nwalTest_cppiGblCfgParams[CPPI_MAX_CPDMA];
 276
 277   for (i=0; i<CPPI_MAX_CPDMA; i++)
 278     nwalTest_cppiGblCfgParams[i] = cppiGblCfgParams[i];
 279
 280   /* SRIO CPDMA regs */
 281   nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs =
 282       (void *)((uint32_t)netapi_VM_srioCfgVaddr +
 283                (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
 284   nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txChRegs =
 285       (void *)((uint32_t)netapi_VM_srioCfgVaddr +
 286                (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
 287
 288   nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxChRegs =
 289       (void *)((uint32_t)netapi_VM_srioCfgVaddr +
 290                (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
 291   nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txSchedRegs =
 292       (void *)((uint32_t)netapi_VM_srioCfgVaddr +
 293                (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
 294  nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs =
 295       (void *)((uint32_t)netapi_VM_srioCfgVaddr +
 296                (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
 297
 298   /* PASS CPDMA regs */
 299   nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].gblCfgRegs =
 300       (void *)((uint32_t)netapi_VM_passCfgVaddr +
 301                (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
 302   nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txChRegs =
 303       (void *)((uint32_t)netapi_VM_passCfgVaddr +
 304                (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
 305   nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxChRegs =
 306       (void *)((uint32_t)netapi_VM_passCfgVaddr +
 307                (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
 308   nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txSchedRegs =
 309       (void *)((uint32_t)netapi_VM_passCfgVaddr +
 310                (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
 311   nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxFlowRegs =
 312       (void *)((uint32_t)netapi_VM_passCfgVaddr +
 313                (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
 314  /* QMSS CPDMA regs */
 315   nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs =
 316       (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 317                (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
 318   nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txChRegs =
 319       (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 320                (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
 321   nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxChRegs =
 322       (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 323                (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
 324   nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txSchedRegs =
 325       (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 326                (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
 327   nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs =
 328       (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
 329                (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
 330
 331   result = Cppi_init (nwalTest_cppiGblCfgParams);
 332   if (result != CPPI_SOK)
 333   {
 334     printf (">function cppi_init: Cppi_init failed with error code %d\n", result);
 335     return (-1);
 336   }
 337    return 1;
 338 }
 339
 340 //*************************************************
 341 //initialize NWAL (one per soc)
 342 //*************************************************
 343 /*** NWAL Memory Buffer Configuration ***/
 344 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE     3400
 345 uint8_t nwalInstMem[NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE]ALIGN(CACHE_LINESZ);
 346
 347 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_MAC                    128
 348 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_IPSEC_HANDLE_PER_CHAN      256
 349 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_IP                     128
 350 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_PORT                   128
 351 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_L2L3_HDR               128
 352 #define NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_LOC_CONTEXT            384
 353 #define NWAL_CHAN_HANDLE_SIZE    ((NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_MAC * TUNE_NETAPI_MAX_NUM_MAC) + \
 354                                   (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_IPSEC_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS*2) + \
 355                                   (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_IP * TUNE_NETAPI_MAX_NUM_IP) + \
 356                                   (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_PORT * TUNE_NETAPI_MAX_NUM_PORTS)+ \
 357                                   (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_LOC_CONTEXT * TUNE_NETAPI_NUM_CORES) + \
 358                                   (NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_PER_L2L3_HDR * TUNE_NETAPI_MAX_NUM_L2_L3_HDRS))
 359
 360 uint8_t nwalHandleMem[NWAL_CHAN_HANDLE_SIZE]ALIGN(CACHE_LINESZ);
 361
 362 /* todo: Check if below size information can be made available from pa interface file */
 363 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0      128
 364 /* PA instance */
 365 /* Memory used for the PA Instance. Needs to be assigned global uncached memory for chip */
 366 uint8_t paBuf0[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0]ALIGN(CACHE_LINESZ);
 367
 368 /* Memory used for PA handles */
 369 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1    128
 370 uint8_t paBuf1[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1]ALIGN(CACHE_LINESZ);
 371
 372 //#define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2   768
 373 #define NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2   6144
 374 uint8_t paBuf2[NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2]ALIGN(CACHE_LINESZ);
 375
 376 /* Memory used for SA LLD global Handle */
 377 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE    384
 378 uint8_t salldHandle[NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE]ALIGN(CACHE_LINESZ);
 379
 380 #if 0  //need to alloc this since we need phy addr also
 381 /* Memory used for SA contet Handle */
 382 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_CONTEXT_PER_CHAN             384
 383 uint8_t saContext[NETAPI_NWAL_CONFIG_BUFSIZE_SA_CONTEXT_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS]ALIGN(CACHE_LINESZ);
 384 #endif
 385
 386 /* Memory used by SA LLD per Channel */
 387 #define NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN          512
 388 uint8_t salldChanHandle[NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS*2]ALIGN(CACHE_LINESZ);
 389
 390
 391 /*******************************************
 392  * Initialize the nwal subsystem for NETAPI use
 393  ***********************************************/
 394 int netapi_init_nwal(
 395      int region2use,
 396      Pktlib_HeapIfTable * p_table,
 397      NETAPI_NWAL_GLOBAL_CONTEXT_T * p_nwal_context,
 398      NETAPI_CFG_T*p_cfg )
 399 {
 400     nwalSizeInfo_t  nwalSizeInfo;
 401     nwalMemBuf_t    nwalMemBuf[nwal_N_BUFS];
 402     nwal_RetValue   nwalRetVal;
 403     nwalGlobCfg_t   nwalGlobCfg;
 404     uint8_t         count;
 405     int             sizes[nwal_N_BUFS];
 406     int             aligns[nwal_N_BUFS];
 407     void*           bases[nwal_N_BUFS];
 408     Pktlib_HeapCfg      heapCfg;
 409     int32_t             errCode;
 410
 411     memset(p_nwal_context,0,sizeof( NETAPI_NWAL_GLOBAL_CONTEXT_T) );
 412     memset(&nwalGlobCfg,0,sizeof(nwalGlobCfg_t ) );
 413
 414
 415     /* Initialize Buffer Pool for NetCP PA to SA packets */
 416     nwalGlobCfg.pa2SaBufPool.numBufPools = 1;
 417     nwalGlobCfg.pa2SaBufPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
 418     nwalGlobCfg.pa2SaBufPool.bufPool[0].bufSize =  p_cfg->def_heap_buf_size;
 419
 420     /* Initialize the heap configuration. */
 421     memset ((void *)&heapCfg, 0, sizeof(Pktlib_HeapCfg));
 422     /* Populate the heap configuration */
 423     heapCfg.name                = "nwal PA2SA";
 424     heapCfg.memRegion           = region2use;
 425     heapCfg.sharedHeap          = 0;
 426     heapCfg.useStarvationQueue  = 0;
 427     heapCfg.dataBufferSize      = p_cfg->def_heap_buf_size;
 428     heapCfg.numPkts             = TUNE_NETAPI_CONFIG_MAX_PA_TO_SA_DESC;
 429     heapCfg.numZeroBufferPackets= 0;
 430     heapCfg.heapInterfaceTable.data_malloc  = p_table->data_malloc;
 431     heapCfg.heapInterfaceTable.data_free    = p_table->data_free;
 432     heapCfg.dataBufferPktThreshold   = 0;
 433     heapCfg.zeroBufferPktThreshold   = 0;
 434
 435
 436     nwalGlobCfg.pa2SaBufPool.bufPool[0].heapHandle = p_nwal_context->pa2sa_heap=
 437                       Pktlib_createHeap(&heapCfg, &errCode);
 438     if(nwalGlobCfg.pa2SaBufPool.bufPool[0].heapHandle == NULL)
 439     {
 440         printf (">Pktlib_createHeap:Heap Creation Failed for PA to SA Buffer Pool , Error Code: %d\n",errCode);
 441         netapi_err_teardown();
 442         return -1;
 443     }
 444
 445  /* Initialize Buffer Pool for NetCP SA to PA packets */
 446     nwalGlobCfg.sa2PaBufPool.numBufPools = 1;
 447     nwalGlobCfg.sa2PaBufPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
 448     nwalGlobCfg.sa2PaBufPool.bufPool[0].bufSize =  p_cfg->def_heap_buf_size;
 449
 450      /* Populate the heap configuration */
 451     heapCfg.name                = "nwal SA2PA";
 452     heapCfg.numPkts             = TUNE_NETAPI_CONFIG_MAX_SA_TO_PA_DESC;
 453
 454     nwalGlobCfg.sa2PaBufPool.bufPool[0].heapHandle = p_nwal_context->sa2pa_heap=
 455         Pktlib_createHeap(&heapCfg, &errCode);
 456     if(nwalGlobCfg.sa2PaBufPool.bufPool[0].heapHandle == NULL)
 457     {
 458         printf (">Pktlib_createHeap:Heap Creation Failed for SA to PA Buffer Pool  , Error Code: %d\n",errCode);
 459         netapi_err_teardown();
 460         return -1;
 461     }
 462
 463     nwalGlobCfg.hopLimit = 5;/* Default TTL / Hop Limit */
 464     nwalGlobCfg.paPowerOn = nwal_TRUE;
 465     nwalGlobCfg.saPowerOn = nwal_TRUE;
 466     nwalGlobCfg.paFwActive = nwal_TRUE;
 467     nwalGlobCfg.saFwActive = nwal_FALSE;
 468
 469     /* Pick Default Physical Address */
 470     nwalGlobCfg.paVirtBaseAddr = (uint32_t) netapi_VM_passCfgVaddr;
 471     nwalGlobCfg.saVirtBaseAddr = (uint32_t) netapi_VM_passCfgVaddr +
 472                                  ((uint32_t)CSL_PA_SS_CFG_CP_ACE_CFG_REGS - (uint32_t)CSL_PA_SS_CFG_REGS) ;
 473     nwalGlobCfg.rxDefPktQ = QMSS_PARAM_NOT_SPECIFIED;
 474
 475     /* Get the Buffer Requirement from NWAL */
 476     memset(&nwalMemBuf,0,sizeof(nwalMemBuf));
 477     memset(&nwalSizeInfo,0,sizeof(nwalSizeInfo));
 478     nwalSizeInfo.nMaxMacAddress = TUNE_NETAPI_MAX_NUM_MAC;
 479     nwalSizeInfo.nMaxIpAddress = TUNE_NETAPI_MAX_NUM_IP;
 480     nwalSizeInfo.nMaxL4Ports = TUNE_NETAPI_MAX_NUM_PORTS;
 481     nwalSizeInfo.nMaxIpSecChannels = TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS;//we allocate 2 per channel
 482     nwalSizeInfo.nMaxDmSecChannels = TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS;//we allocate 2 per channel
 483     nwalSizeInfo.nMaxL2L3Hdr = TUNE_NETAPI_MAX_NUM_L2_L3_HDRS;
 484     nwalSizeInfo.nProc = TUNE_NETAPI_NUM_CORES;
 485     for(count=0;count < nwal_N_BUFS;count++)
 486     {
 487         nwalMemBuf[count].cacheLineSize = CACHE_LINESZ;
 488     }
 489     nwalRetVal = nwal_getBufferReq(&nwalSizeInfo,
 490                                    sizes,
 491                                    aligns);
 492     if(nwalRetVal != nwal_OK)
 493     {
 494         printf (">netapi: init_nwal - nwal_getBufferReq Failed %d\n", nwalRetVal);
 495         return nwal_FALSE;
 496     }
 497
 498 /* Check for memory size requirement and update the base */
 499     count = 0;
 500     bases[nwal_BUF_INDEX_INST] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)nwalInstMem);
 501     if(NETAPI_NWAL_CONFIG_BUFSIZE_NWAL_HANDLE < sizes[nwal_BUF_INDEX_INST])
 502     {
 503         /* Resize Memory */
 504         while(1);
 505     }
 506     count++;
 507
 508     bases[nwal_BUF_INDEX_INT_HANDLES] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)nwalHandleMem);
 509     if(NWAL_CHAN_HANDLE_SIZE  < sizes[nwal_BUF_INDEX_INT_HANDLES])
 510     {
 511         /* Resize Memory */
 512         while(1);
 513     }
 514     count++;
 515      bases[nwal_BUF_INDEX_PA_LLD_BUF0] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf0);
 516     if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF0) < sizes[nwal_BUF_INDEX_PA_LLD_BUF0])
 517     {
 518         /* Resize Memory */
 519         while(1);
 520     }
 521     count++;
 522
 523     bases[nwal_BUF_INDEX_PA_LLD_BUF1] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf1);
 524     if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF1) < sizes[nwal_BUF_INDEX_PA_LLD_BUF1])
 525     {
 526         /* Resize Memory */
 527         while(1);
 528     }
 529     count++;
 530
 531     bases[nwal_BUF_INDEX_PA_LLD_BUF2] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)paBuf2);
 532     if((NETAPI_NWAL_CONFIG_BUFSIZE_PA_BUF2) < sizes[nwal_BUF_INDEX_PA_LLD_BUF2])
 533     {
 534         /* Resize Memory */
 535         while(1);
 536     }
 537     count++;
 538 #ifdef NETAPI_ENABLE_SECURITY
 539     bases[nwal_BUF_INDEX_SA_LLD_HANDLE] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)salldHandle);
 540     if((NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE) < sizes[nwal_BUF_INDEX_SA_LLD_HANDLE])
 541     {
 542         /* Resize Memory */
 543         while(1);
 544     }
 545     count++;
 546
 547     bases[nwal_BUF_INDEX_SA_CONTEXT] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)netapi_VM_SaContextVaddr);
 548     count++;
 549
 550     bases[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE] = (uint32_t *)Osal_nwalLocToGlobAddr((uint32_t)salldChanHandle);
 551     if((NETAPI_NWAL_CONFIG_BUFSIZE_SA_LLD_HANDLE_PER_CHAN * TUNE_NETAPI_MAX_NUM_IPSEC_CHANNELS*2) <
 552         sizes[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE])
 553     {
 554         /* Resize Memory */
 555         while(1);
 556     }
 557     count++;
 558 #else
 559     bases[nwal_BUF_INDEX_SA_LLD_HANDLE] = 0;
 560     bases[nwal_BUF_INDEX_SA_CONTEXT] = 0;
 561     bases[nwal_BUF_INDEX_SA_LLD_CHAN_HANDLE] = 0;
 562     count = count+3;
 563 #endif
 564     if(count != nwal_N_BUFS)
 565     {
 566         while(1);
 567     }
 568
 569     /* Initialize NWAL module */
 570     nwalRetVal = nwal_create(&nwalGlobCfg,
 571                              &nwalSizeInfo,
 572                              sizes,
 573                              bases,
 574                              &p_nwal_context->nwalInstHandle);
 575     if(nwalRetVal != nwal_OK)
 576     {
 577         printf (">netapi: init_nwal- nwal_create Failed %d\n",nwalRetVal);
 578         while(1);
 579     }
 580
 581     printf(">netapi: init_nwal - Global and Local Network initialization Successful \n");
 582     return 1;
 583 }
 584
 585 //*************************************************
 586 //* Local (per thread/core) nwal initialization0
 587 //**************************************************
 588 int netapi_start_nwal(Pktlib_HeapHandle pkt_heap,
 589                       Pktlib_HeapHandle cmd_rx_heap,
 590                       Pktlib_HeapHandle cmd_tx_heap,
 591                       NETAPI_NWAL_LOCAL_CONTEXT_T *p,
 592                       NETAPI_CFG_T *p_cfg,
 593                       NETAPI_NWAL_GLOBAL_CONTEXT_T * p_nwal_glob_context  )
 594 {
 595     nwalLocCfg_t    nwalLocCfg;
 596     int count;
 597     nwal_RetValue       nwalRetVal;
 598
 599     memset(&nwalLocCfg,0,sizeof(nwalLocCfg));
 600
 601     /* Common Initialization for all cores */
 602     while(count < TUNE_NETAPI_MAX_NUM_TRANS)
 603     {
 604         p_nwal_glob_context->transInfos[count].transId = count;
 605         count++;
 606     }
 607
 608     /* Update the Start of Packet Offset for the default flows created
 609      * by NWAL
 610      */
 611     nwalLocCfg.rxSopPktOffset = p_cfg->def_flow_pkt_rx_offset;
 612     nwalLocCfg.rxPktTailRoomSz = p_cfg->def_heap_tailroom_size;
 613
 614  /* Call back registration for the core */
 615     nwalLocCfg.pRxPktCallBack = netapi_NWALRxPktCallback;
 616     nwalLocCfg.pCmdCallBack = netapi_NWALCmdCallBack;
 617     nwalLocCfg.pPaStatsCallBack = netapi_NWALCmdPaStatsReply;
 618     nwalLocCfg.pRxDmCallBack=  netapi_NWALSBPktCallback; //sideband mode callback
 619
 620     /* Initialize Buffer Pool for Control packets from NetCP to Host */
 621     nwalLocCfg.rxCtlPool.numBufPools = 1;
 622     nwalLocCfg.rxCtlPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
 623     nwalLocCfg.rxCtlPool.bufPool[0].bufSize = TUNE_NETAPI_CONFIG_MAX_CTL_RXTX_BUF_SIZE;
 624     nwalLocCfg.rxCtlPool.bufPool[0].heapHandle = cmd_rx_heap;
 625
 626     /* Initialize Buffer Pool for Control packets from Host to NetCP */
 627     nwalLocCfg.txCtlPool.numBufPools = 1;
 628     nwalLocCfg.txCtlPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
 629     nwalLocCfg.txCtlPool.bufPool[0].bufSize = TUNE_NETAPI_CONFIG_MAX_CTL_RXTX_BUF_SIZE;
 630     nwalLocCfg.txCtlPool.bufPool[0].heapHandle =  cmd_tx_heap;
 631
 632 /* Initialize Buffer Pool for Packets from NetCP to Host */
 633     nwalLocCfg.rxPktPool.numBufPools = 1;
 634     nwalLocCfg.rxPktPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
 635     nwalLocCfg.rxPktPool.bufPool[0].bufSize =  p_cfg->def_heap_buf_size;
 636     nwalLocCfg.rxPktPool.bufPool[0].heapHandle = pkt_heap;
 637
 638 /* Initialize Buffer Pool for Packets from Host to NetCP */
 639     nwalLocCfg.txPktPool.numBufPools = 1;
 640     nwalLocCfg.txPktPool.bufPool[0].descSize = TUNE_NETAPI_DESC_SIZE;
 641     nwalLocCfg.txPktPool.bufPool[0].bufSize =  p_cfg->def_heap_buf_size;
 642     nwalLocCfg.txPktPool.bufPool[0].heapHandle = pkt_heap;
 643
 644     memcpy(&p->nwalLocCfg,&nwalLocCfg,sizeof(nwalLocCfg_t));
 645     while(1)
 646     {
 647         nwalRetVal = nwal_start(p_nwal_glob_context->nwalInstHandle,&nwalLocCfg);
 648         if(nwalRetVal == nwal_ERR_INVALID_STATE)
 649         {
 650             continue;
 651         }
 652         break;
 653     }
 654
 655     if(nwalRetVal != nwal_OK)
 656     {
 657         printf (">nwal_start:Failed ->err %d !!!\n", nwalRetVal);
 658         return -1;
 659     }
 660     p->state = NETAPI_NW_CXT_LOC_ACTIVE;
 661     return 1;
 662
 663
 664 }
 665 //***************************************************
 666 // intialize timer
 667 //***************************************************
 668 int netapi_init_timer(void)
 669 {
 670         return t64_start();
 671 }
 672
 673