1 /******************************************************************************\r
2 * FILE PURPOSE: Functions to OSAL related routines for running NWAL, PA, QMSS,etc\r
3 ******************************************************************************\r
4 * FILE NAME: osal.c\r
5 *\r
6 * DESCRIPTION: Functions to initialize framework resources for running NWAL\r
7 *\r
8 * REVISION HISTORY:\r
9 *\r
10 * Copyright (c) Texas Instruments Incorporated 2010-2011\r
11 * \r
12 * Redistribution and use in source and binary forms, with or without \r
13 * modification, are permitted provided that the following conditions \r
14 * are met:\r
15 *\r
16 * Redistributions of source code must retain the above copyright \r
17 * notice, this list of conditions and the following disclaimer.\r
18 *\r
19 * Redistributions in binary form must reproduce the above copyright\r
20 * notice, this list of conditions and the following disclaimer in the \r
21 * documentation and/or other materials provided with the \r
22 * distribution.\r
23 *\r
24 * Neither the name of Texas Instruments Incorporated nor the names of\r
25 * its contributors may be used to endorse or promote products derived\r
26 * from this software without specific prior written permission.\r
27 *\r
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
39 *\r
40 */\r
41 \r
42 /* CSL RL includes */\r
43 #include <ti/csl/cslr_device.h>\r
44 #include <ti/csl/csl_pscAux.h>\r
45 #include <ti/csl/csl_semAux.h>\r
46 #include <ti/csl/csl_cacheAux.h>\r
47 #include <ti/csl/csl_xmcAux.h>\r
48 \r
49 #include <stdlib.h>\r
50 #include <stdio.h>\r
51 \r
52 #include "netapi_vm.h"\r
53 #include "netapi_timer.h"\r
54 #define System_printf printf\r
55 \r
56 uint32_t Osal_qmss_MallocCounter =0;\r
57 uint32_t Osal_qmss_FreeCounter =0;\r
58 uint32_t Osal_cppi_MallocCounter =0;\r
59 uint32_t Osal_cppi_FreeCounter =0;\r
60 \r
61 \r
62 \r
63 /* TODO: */\r
64 #define DNUM 0\r
65 \r
66 #if 0\r
67 uint32_t globalCritkey;\r
68 \r
69 /* Lock to be used for critical section */\r
70 pthread_mutex_t mutex_lock;\r
71 \r
72 void nwalTest_osalInit() \r
73 {\r
74 pthread_mutex_init(&mutex_lock, NULL);\r
75 return;\r
76 }\r
77 \r
78 void nwalTest_osalshutdown() \r
79 {\r
80 pthread_mutex_destroy(&mutex_lock);\r
81 return;\r
82 }\r
83 \r
84 static inline void nwalTest_osalEnterCS()\r
85 {\r
86 #if 0\r
87 pthread_mutex_lock(&mutex_lock);\r
88 #endif \r
89 return;\r
90 }\r
91 \r
92 static inline void nwalTest_osalLeaveCS()\r
93 {\r
94 \r
95 #if 0\r
96 pthread_mutex_unlock(&mutex_lock);\r
97 #endif\r
98 return;\r
99 }\r
100 \r
101 #endif\r
102 \r
103 /*****************************************************************************\r
104 * FUNCTION PURPOSE: Cache Invalidation Routine\r
105 ***************************************************************************** \r
106 * DESCRIPTION: Cache Invalidation Routine\r
107 *****************************************************************************/\r
108 void Osal_invalidateCache (void *blockPtr, uint32_t size) \r
109 {\r
110 /* Stub Function. TBD: Would need to handle when cache is enabled for ARM */\r
111 return;\r
112 }\r
113 \r
114 /*****************************************************************************\r
115 * FUNCTION PURPOSE: Cache Writeback Routine\r
116 ***************************************************************************** \r
117 * DESCRIPTION: Cache Invalidation Routine\r
118 *****************************************************************************/\r
119 void Osal_writeBackCache (void *blockPtr, uint32_t size) \r
120 {\r
121 /* Stub Function. TBD: Would need to handle when cache is enabled for ARM */\r
122 return;\r
123 }\r
124 \r
125 \r
126 void * Osal_qmssMtCsEnter()\r
127 {\r
128 /* Stub Function. TBD: Would need to handle when for multi proc access \r
129 * To be handled once infrastructure is available from Kernel\r
130 */\r
131 return NULL;\r
132 }\r
133 \r
134 \r
135 void Osal_qmssMtCsExit(void *key)\r
136 {\r
137 /* Stub Function. TBD: Would need to handle when for multi proc access \r
138 * To be handled once infrastructure is available from Kernel\r
139 */\r
140 return;\r
141 }\r
142 \r
143 void Osal_nwalCsEnter(uint32_t *key)\r
144 {\r
145 /* Stub Function. TBD: Would need to handle when for multi proc access \r
146 * To be handled once infrastructure is available from Kernel\r
147 */\r
148 return;\r
149 }\r
150 \r
151 void Osal_nwalCsExit(uint32_t key)\r
152 {\r
153 /* Stub Function. TBD: Would need to handle when for multi proc access \r
154 * To be handled once infrastructure is available from Kernel\r
155 */\r
156 return;\r
157 }\r
158 \r
159 \r
160 void Osal_qmssLog ( String fmt, ... )\r
161 {\r
162 }\r
163 \r
164 \r
165 void Osal_cppiCsEnter (uint32_t *key)\r
166 { \r
167 \r
168 /* Stub Function. TBD: Would need to handle when for multi proc access \r
169 * To be handled once infrastructure is available from Kernel\r
170 */\r
171 return;\r
172 }\r
173 \r
174 void Osal_cppiCsExit (uint32_t key)\r
175 {\r
176 \r
177 /* Stub Function. TBD: Would need to handle when for multi proc access \r
178 * To be handled once infrastructure is available from Kernel\r
179 */\r
180 return;\r
181 }\r
182 \r
183 void Osal_cppiLog ( String fmt, ... )\r
184 {\r
185 }\r
186 \r
187 void Osal_paBeginMemAccess (Ptr addr, uint32_t size)\r
188 {\r
189 /* Stub Function. TBD: Would need to handle when for multi proc access \r
190 * To be handled once infrastructure is available from Kernel\r
191 */\r
192 \r
193 }\r
194 \r
195 void Osal_paEndMemAccess (Ptr addr, uint32_t size)\r
196 { \r
197 /* Stub Function. TBD: Would need to handle when for multi proc access \r
198 * To be handled once infrastructure is available from Kernel\r
199 */\r
200 }\r
201 void Osal_paMtCsEnter (uint32_t *key)\r
202 {\r
203 /* Stub Function. TBD: Would need to handle when for multi proc access \r
204 * To be handled once infrastructure is available from Kernel\r
205 */\r
206 }\r
207 void Osal_paMtCsExit (uint32_t key)\r
208 {\r
209 /* Stub Function. TBD: Would need to handle when for multi proc access \r
210 * To be handled once infrastructure is available from Kernel\r
211 */\r
212 }\r
213 \r
214 \r
215 void* Osal_qmssCsEnter ()\r
216 {\r
217 \r
218 /* Stub Function. TBD: Would need to handle when for multi proc access \r
219 * To be handled once infrastructure is available from Kernel\r
220 */\r
221 return(NULL);\r
222 }\r
223 \r
224 void Osal_qmssCsExit (void * key)\r
225 {\r
226 /* Stub Function. TBD: Would need to handle when for multi proc access \r
227 * To be handled once infrastructure is available from Kernel\r
228 */\r
229 return;\r
230 }\r
231 \r
232 Ptr Osal_qmssMalloc (uint32_t num_bytes)\r
233 {\r
234 Ptr ret;\r
235 \r
236 Osal_qmss_MallocCounter++;\r
237 ret = malloc (num_bytes); \r
238 if(ret==NULL)\r
239 {\r
240 System_printf("\nERROR! QMSS Malloc failed!\n");\r
241 } \r
242 \r
243 return ret;\r
244 }\r
245 \r
246 void Osal_qmssFree (Ptr ptr, uint32_t size)\r
247 {\r
248 /* Increment the free counter. */\r
249 Osal_qmss_FreeCounter++; \r
250 free(ptr);\r
251 }\r
252 \r
253 Ptr Osal_cppiMalloc (uint32_t num_bytes)\r
254 {\r
255 Ptr ret;\r
256 \r
257 Osal_cppi_MallocCounter++;\r
258 num_bytes += (CACHE_L2_LINESIZE-1);\r
259 ret = malloc (num_bytes);\r
260 \r
261 if(ret==NULL)\r
262 {\r
263 System_printf("\nERROR! CPPI Malloc failed!\n");\r
264 } \r
265 \r
266 return ret;\r
267 }\r
268 \r
269 void Osal_cppiFree (Ptr ptr, uint32_t size)\r
270 {\r
271 /* Increment the free counter. */\r
272 Osal_cppi_FreeCounter++; \r
273 free(ptr); \r
274 }\r
275 \r
276 void Osal_qmssBeginMemAccess (void *blockPtr, uint32_t size)\r
277 {\r
278 Osal_invalidateCache(blockPtr,size);\r
279 return;\r
280 }\r
281 \r
282 void Osal_qmssEndMemAccess (void *blockPtr, uint32_t size)\r
283 {\r
284 Osal_writeBackCache(blockPtr,size);\r
285 return;\r
286 }\r
287 \r
288 void Osal_cppiBeginMemAccess (void *blockPtr, uint32_t size)\r
289 {\r
290 Osal_invalidateCache(blockPtr,size);\r
291 return;\r
292 }\r
293 \r
294 void Osal_cppiEndMemAccess (void *blockPtr, uint32_t size)\r
295 {\r
296 Osal_writeBackCache(blockPtr,size);\r
297 return;\r
298 }\r
299 \r
300 void Osal_nwalInvalidateCache (void *blockPtr, uint32_t size)\r
301 {\r
302 Osal_invalidateCache(blockPtr,size);\r
303 return;\r
304 }\r
305 \r
306 void Osal_nwalWriteBackCache (void *blockPtr, uint32_t size)\r
307 {\r
308 Osal_writeBackCache(blockPtr,size);\r
309 return;\r
310 }\r
311 \r
312 uint32_t Osal_nwalGetCacheLineSize (void )\r
313 {\r
314 /* By default assumes L2 cache line is enabled. If not return CACHE_L1D_LINESIZE */\r
315 return (CACHE_L2_LINESIZE);\r
316 }\r
317 \r
318 /********************************************************************\r
319 * FUNCTION PURPOSE: Convert local address to global\r
320 ********************************************************************\r
321 * DESCRIPTION: Returns global address\r
322 ********************************************************************/\r
323 \r
324 unsigned int Osal_nwalLocToGlobAddr(unsigned int x)\r
325 {\r
326 return x;\r
327 }\r
328 \r
329 uint16_t Osal_nwalGetProcId (void )\r
330 {\r
331 return DNUM;\r
332 }\r
333 uint64_t Osal_nwalGetTimeStamp(void)\r
334 {\r
335 /* Stub function to return timestamp\r
336 */\r
337 return netapi_getTimestamp();\r
338 }\r
339 \r
340 uint16_t Osal_saGetProcId (void )\r
341 {\r
342 return 0;\r
343 }\r
344 \r
345 void* Osal_saGetSCPhyAddr(void* vaddr)\r
346 {\r
347 if(vaddr == NULL)\r
348 {\r
349 return NULL;\r
350 }\r
351 return (void *)(netapi_VM_mem_start_phy + ((uint8_t*) vaddr - netapi_VM_mem_start));\r
352 \r
353 }\r
354 \r
355 void Osal_saBeginScAccess (void* addr, uint32_t size)\r
356 {\r
357 Osal_invalidateCache(addr,size);\r
358 \r
359 }\r
360 \r
361 void Osal_saEndScAccess (void* addr, uint32_t size)\r
362 {\r
363 Osal_writeBackCache(addr,size);\r
364 \r
365 }\r
366 \r
367 \r
368 void Osal_saCsEnter (uint32_t *key)\r
369 {\r
370 /* Stub Function. TBD: Would need to handle when for multi proc access \r
371 * To be handled once infrastructure is available from Kernel\r
372 */ \r
373 //((CSL_semAcquireDirect (SA_HW_SEM)) == 0); \r
374 return;\r
375 }\r
376 \r
377 void Osal_saCsExit (uint32_t key)\r
378 {\r
379 /* Stub Function. TBD: Would need to handle when for multi proc access \r
380 * To be handled once infrastructure is available from Kernel\r
381 */ \r
382 return;\r
383 }\r
384 \r
385 \r
386 void Osal_saMtCsEnter (uint32_t *key)\r
387 {\r
388 /* Stub Function. TBD: Would need to handle when for multi proc access \r
389 * To be handled once infrastructure is available from Kernel\r
390 */ \r
391 return;\r
392 }\r
393 \r
394 void Osal_saMtCsExit (uint32_t key)\r
395 {\r
396 /* Stub Function. TBD: Would need to handle when for multi proc access \r
397 * To be handled once infrastructure is available from Kernel\r
398 */ \r
399 return;\r
400 }\r
401 \r
402 void Osal_saBeginMemAccess (void *blockPtr, uint32_t size)\r
403 {\r
404 Osal_invalidateCache(blockPtr,size);\r
405 return;\r
406 }\r
407 \r
408 void Osal_saEndMemAccess (void *blockPtr, uint32_t size)\r
409 {\r
410 Osal_writeBackCache(blockPtr,size);\r
411 return;\r
412 }\r
413 \r
414 \r
415 \r
416 void Osal_pktLibBeginMemAccess(void* ptr, uint32_t size)\r
417 {\r
418 Osal_invalidateCache(ptr,size);\r
419 }\r
420 \r
421 \r
422 void Osal_pktLibEndMemAccess(void* ptr, uint32_t size)\r
423 {\r
424 Osal_writeBackCache(ptr,size);\r
425 }\r
426 \r
427 \r
428 void Osal_pktLibBeginPktAccess(Pktlib_HeapHandle heapHandle, Ti_Pkt* ptrPkt, uint32_t size)\r
429 {\r
430 /* TODO: We should use the 'heapHandle' and compare it with what we got from the\r
431 * 'create/find' HEAP API & depending upon the comparison take appropriate action. \r
432 * Just for testing we are always invalidating the cache here. */\r
433 \r
434 Osal_invalidateCache(ptrPkt,size);\r
435 }\r
436 \r
437 \r
438 void Osal_pktLibEndPktAccess(Pktlib_HeapHandle heapHandle, Ti_Pkt* ptrPkt, uint32_t size)\r
439 {\r
440 /* TODO: We should use the 'heapHandle' and compare it with what we got from the\r
441 * 'create/find' HEAP API & depending upon the comparison take appropriate action. \r
442 * Just for testing we are always writing back the cache here. */\r
443 \r
444 /* Writeback the contents of the cache. */\r
445 Osal_writeBackCache(ptrPkt,size);\r
446 }\r
447 \r
448 \r
449 void* Osal_pktLibEnterCriticalSection(Pktlib_HeapHandle heapHandle)\r
450 {\r
451 /* TODO: We should use the 'heapHandle' and compare it with what we got from the\r
452 * 'create/find' HEAP API & depending upon the comparison take appropriate action. \r
453 * Implementations here could range from a MULTI-THREAD protection if the packets in \r
454 * the heap are being accessed across multiple threads or MULTI-CORE if the packets\r
455 * are being accessed across multiple cores and features: split and clone are used.\r
456 * For NWAL layer no protection required.\r
457 *\r
458 * For testing we are not doing any of this so we are simply setting it to NOOP */\r
459 return NULL;\r
460 }\r
461 \r
462 \r
463 void Osal_pktLibExitCriticalSection(Pktlib_HeapHandle heapHandle, void* csHandle)\r
464 {\r
465 /* TODO: We should use the 'heapHandle' and compare it with what we got from the\r
466 * 'create/find' HEAP API & depending upon the comparison take appropriate action. \r
467 * Implementations here could range from a MULTI-THREAD protection if the packets in \r
468 * the heap are being accessed across multiple threads or MULTI-CORE if the packets\r
469 * are being accessed across multiple cores and features: split and clone are used.\r
470 * For NWAL layer no protection required.. \r
471 *\r
472 * For testing we are not doing any of this so we are simply setting it to NOOP */\r
473 return; \r
474 }\r
475 \r
476 void* Osal_qmssVirtToPhy (void *ptr)\r
477 {\r
478 return (void *)(netapi_VM_mem_start_phy + ((uint8_t*)ptr - netapi_VM_mem_start));\r
479 }\r
480 \r
481 void* Osal_qmssPhyToVirt (void *ptr)\r
482 {\r
483 if (!ptr) return (void *) 0;\r
484 //todo, see if out of range of mem_start_phy and size!! (like mmu would do)\r
485 return (void *)(netapi_VM_mem_start + ((uint8_t*)ptr - netapi_VM_mem_start_phy));\r
486 }\r
487 \r
488 /******************************************************************************\r
489 * Function to traverse a CPPI descriptor and convert all address references\r
490 * from virtual to physical.\r
491 ******************************************************************************/\r
492 void* Osal_qmssConvertDescVirtToPhy(void *descAddr)\r
493 {\r
494 if (!descAddr) return (void *)0;\r
495 \r
496 if (Cppi_getDescType((Cppi_Desc *)QMSS_DESC_PTR(descAddr)) == Cppi_DescType_HOST)\r
497 {\r
498 Cppi_HostDesc *nextBDPtr = (Cppi_HostDesc *)QMSS_DESC_PTR(descAddr);\r
499 Cppi_HostDesc *prevBDPtr = 0;\r
500 while (nextBDPtr)\r
501 {\r
502 void *buffPtr;\r
503 if (nextBDPtr->buffPtr)\r
504 {\r
505 buffPtr = (void *)nextBDPtr->buffPtr;\r
506 nextBDPtr->buffPtr = (uint32_t)Osal_qmssVirtToPhy((void *)(nextBDPtr->buffPtr));\r
507 if (!(nextBDPtr->buffPtr)) return (void *)0;\r
508 }\r
509 \r
510 if (nextBDPtr->origBuffPtr)\r
511 {\r
512 nextBDPtr->origBuffPtr = (uint32_t)Osal_qmssVirtToPhy((void *)(nextBDPtr->origBuffPtr));\r
513 if (!(nextBDPtr->origBuffPtr)) return (void *)0;\r
514 }\r
515 \r
516 prevBDPtr = nextBDPtr;\r
517 nextBDPtr = (Cppi_HostDesc *)QMSS_DESC_PTR((nextBDPtr->nextBDPtr));\r
518 if (prevBDPtr->nextBDPtr)\r
519 {\r
520 prevBDPtr->nextBDPtr = (uint32_t)Osal_qmssVirtToPhy((void *)(prevBDPtr->nextBDPtr));\r
521 if (!(prevBDPtr->nextBDPtr)) return (void *)0;\r
522 }\r
523 \r
524 Qmss_osalEndMemAccess(buffPtr, prevBDPtr->buffLen);\r
525 Qmss_osalEndMemAccess(prevBDPtr, sizeof(Cppi_HostDesc));\r
526 }\r
527 descAddr = Osal_qmssVirtToPhy(descAddr);\r
528 if (!descAddr) return (void *)0;\r
529 }\r
530 else if (Cppi_getDescType((Cppi_Desc *)QMSS_DESC_PTR(descAddr)) == Cppi_DescType_MONOLITHIC)\r
531 {\r
532 descAddr = Osal_qmssVirtToPhy(descAddr);\r
533 if (!descAddr) return (void *)0;\r
534 }\r
535 return descAddr;\r
536 \r
537 }\r
538 \r
539 \r
540 /******************************************************************************\r
541 * Function to traverse a CPPI descriptor and convert all address references\r
542 * from physical to virtual.\r
543 ******************************************************************************/\r
544 void* Osal_qmssConvertDescPhyToVirt(void *descAddr)\r
545 {\r
546 if (!descAddr) return (void *)0;\r
547 descAddr = Osal_qmssPhyToVirt(descAddr);\r
548 \r
549 if (Cppi_getDescType((Cppi_Desc *)QMSS_DESC_PTR(descAddr)) == Cppi_DescType_HOST)\r
550 {\r
551 Cppi_HostDesc *nextBDPtr = (Cppi_HostDesc *)QMSS_DESC_PTR(descAddr);\r
552 while (nextBDPtr)\r
553 {\r
554 Qmss_osalBeginMemAccess(nextBDPtr, sizeof(Cppi_HostDesc));\r
555 if (nextBDPtr->buffPtr)\r
556 {\r
557 nextBDPtr->buffPtr = (uint32_t)Osal_qmssPhyToVirt((void *)(nextBDPtr->buffPtr));\r
558 if (!(nextBDPtr->buffPtr)) return (void *)0;\r
559 }\r
560 \r
561 if (nextBDPtr->origBuffPtr)\r
562 {\r
563 nextBDPtr->origBuffPtr = (uint32_t)Osal_qmssPhyToVirt((void *)(nextBDPtr->origBuffPtr));\r
564 if (!(nextBDPtr->origBuffPtr)) return (void *)0;\r
565 }\r
566 \r
567 if (nextBDPtr->nextBDPtr)\r
568 {\r
569 nextBDPtr->nextBDPtr = (uint32_t)Osal_qmssPhyToVirt((void *)(nextBDPtr->nextBDPtr));\r
570 if (!(nextBDPtr->nextBDPtr)) return (void *)0;\r
571 }\r
572 \r
573 Qmss_osalBeginMemAccess((void *)(nextBDPtr->buffPtr), nextBDPtr->buffLen);\r
574 nextBDPtr = (void *)QMSS_DESC_PTR((nextBDPtr->nextBDPtr));\r
575 }\r
576 }\r
577 else if (Cppi_getDescType((Cppi_Desc *)QMSS_DESC_PTR(descAddr)) == Cppi_DescType_MONOLITHIC)\r
578 {\r
579 descAddr = Osal_qmssPhyToVirt(descAddr);\r
580 if (!descAddr) return (void *)0;\r
581 }\r
582 return descAddr;\r
583 }\r
584 \r
585 void* Osal_stubCsEnter (void)\r
586 {\r
587 \r
588 \r
589 }\r
590 void Osal_stubCsExit (void *CsHandle)\r
591 {\r
592 /* Release Semaphore using handle */\r
593 \r
594 \r
595 return;\r
596 }\r
597 \r