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raw | patch | inline | side by side (from parent 1: dc08af2)
author | Tinku Mannan <tmannan@ti.com> | |
Fri, 20 Feb 2015 21:55:02 +0000 (16:55 -0500) | ||
committer | Tinku Mannan <tmannan@ti.com> | |
Mon, 23 Feb 2015 15:29:01 +0000 (10:29 -0500) |
ti/runtime/netapi/src/netapi_init.c | patch | blob | history |
index 87bc8a9d68089b8cdb95b1d28b51e77e77604a1d..68168e0c0dfce577d449a18c4290c758c7cd97df 100755 (executable)
netapi_VM_MempoolAttr[0].phys_addr = 0;
netapi_VM_MempoolAttr[0].size = 0;
+#ifdef NETAPI_USE_DDR_AND_MSMC
/* Init attributes for un-cached MSMC */
netapi_VM_MempoolAttr[1].attr = HPLIB_ATTR_UN_CACHED;
netapi_VM_MempoolAttr[1].phys_addr = CSL_MSMC_SRAM_REGS;
netapi_VM_MempoolAttr[1].size = TUNE_NETAPI_PERM_MEM_SZ;
+#endif
#else
- netapi_VM_MempoolAttr[1].attr = HPLIB_ATTR_KM_CACHED0;
- netapi_VM_MempoolAttr[1].phys_addr = 0;
- netapi_VM_MempoolAttr[1].size = 0;
-
/* Init attributes for un-cached MSMC */
netapi_VM_MempoolAttr[0].attr = HPLIB_ATTR_UN_CACHED;
netapi_VM_MempoolAttr[0].phys_addr = CSL_MSMC_SRAM_REGS;
netapi_VM_MempoolAttr[0].size = TUNE_NETAPI_PERM_MEM_SZ;
+#ifdef NETAPI_USE_DDR_AND_MSMC
+ netapi_VM_MempoolAttr[1].attr = HPLIB_ATTR_KM_CACHED0;
+ netapi_VM_MempoolAttr[1].phys_addr = 0;
+ netapi_VM_MempoolAttr[1].size = 0;
+#endif
#endif
/* initialize all the memory we are going to use
- chunk for buffers, descriptors
- memory mapped peripherals we use, such as QMSS, PA, etc */
+#ifdef NETAPI_USE_DDR_AND_MSMC
result = hplib_vmInit(&netapi_VM_VirtAddr[0],
2,
&netapi_VM_MempoolAttr[0]);
+#else
+ result = hplib_vmInit(&netapi_VM_VirtAddr[0],
+ 1,
+ &netapi_VM_MempoolAttr[0]);
+#endif
if (result != hplib_OK)
{
if (global_master_process == NETAPI_TRUE)
{
hplib_initMallocArea(0);
+#ifdef NETAPI_USE_DDR_AND_MSMC
hplib_initMallocArea(1);
+#endif
#ifdef NETAPI_ENABLE_SECURITY
#define SEC_CONTEXT_SZ 384 //not tunable
/* allocate 2x number of tunnels since we need one for inflow and one for data mode */