Update for Keystone-2 changes
authorRaghu Nambiath <rnambiath@ti.com>
Fri, 19 Oct 2012 18:52:27 +0000 (14:52 -0400)
committerRaghu Nambiath <rnambiath@ti.com>
Fri, 19 Oct 2012 18:52:27 +0000 (14:52 -0400)
ti/runtime/netapi/build/Makefile
ti/runtime/netapi/src/netapi_init.c
ti/runtime/netapi/src/netapi_loc.h
ti/runtime/netapi/src/netapi_vm.c
ti/runtime/netapi/src/netapi_vm.h
ti/runtime/netapi/src/pdk/v2/netapi_navig.c [new file with mode: 0644]
ti/runtime/netapi/src/pdk/v3/netapi_navig.c [new file with mode: 0644]

index 4c10b679f09ffe6bedc91858cb91d4557adf391f..8c80c064ad9cfb6f43b611dd1db5d3fa09a7c064 100755 (executable)
@@ -4,6 +4,19 @@ CPPI_INC_DIR = $(PDK_INSTALL_PATH)/ti/drv/cppi
 
 INCDIR := $(PDK_INSTALL_PATH);  $(QMSS_INC_DIR); $(CPPI_INC_DIR)
 
+export PDK_VER ?= v2
+NETAPI_NAVIG_INIT_SRC=$(NETAPI_INC_DIR)/src/pdk/$(PDK_VER)
+
+export SOC ?= tci6634
+ifeq ($(PDK_VER),v3)
+QMSS_DEV_DIR = $(PDK_INSTALL_PATH)/ti/drv/qmss/device/$(SOC)/src
+CPPI_DEV_DIR = $(PDK_INSTALL_PATH)/ti/drv/cppi/device/$(SOC)/src
+endif
+ifeq ($(PDK_VER),v2)
+QMSS_DEV_DIR = $(PDK_INSTALL_PATH)/ti/drv/qmss/device
+CPPI_DEV_DIR = $(PDK_INSTALL_PATH)/ti/drv/cppi/device
+endif
+
 # Output for prebuilt generated libraries
 export ARMV7LIBDIR ?= ../lib
 export ARMV7OBJDIR ?= ../obj
@@ -19,7 +32,7 @@ INTERNALLINKDEFS =
 NETAPI_INC_DIR = $(NETAPI_INSTALL_PATH)/ti/runtime/netapi
 SRCDIR = $(NETAPI_INC_DIR)/src
 
-VPATH=$(SRCDIR)
+VPATH=$(SRCDIR):$(NETAPI_NAVIG_INIT_SRC)
 
 
 #Cross tools
@@ -39,6 +52,7 @@ COMMONSRCC = \
     osal.c \
     pktio.c \
     tim64.c\
+    netapi_navig.c\
     timlist.c
 
 CFLAGS= $(DEBUG_FLAG) -I$(NETAPI_INC_DIR) -I.  -I $(SRCDIR) -I$(PDK_INSTALL_PATH) -I$(NWAL_INSTALL_PATH) -I$(PKTLIB_INSTALL_PATH) -I$(TRANS_SDK_INSTALL_PATH) -I$(QMSS_INC_DIR) -I$(CPPI_INC_DIR) -I$(SA_INSTALL_PATH) -D__ARMv7 -D_VIRTUAL_ADDR_SUPPORT -D__LINUX_USER_SPACE -D_LITTLE_ENDIAN=1 -DMAKEFILE_BUILD -pthread -D _GNU_SOURCE
index 90aed7d0b4223f01c860d17dce3bceeef922054b..6b860a7bdd185331013a3d697fc1cc588f372fe2 100755 (executable)
 #include <ti/csl/csl_semAux.h>
 #include <ti/csl/csl_cacheAux.h>
 #include <ti/csl/csl_xmcAux.h>
-#include <ti/csl/csl_cpsw_3gfAux.h>
-#include <ti/csl/csl_cpsw.h>
-#include <ti/csl/csl_cpsgmiiAux.h>
 #include <ti/drv/qmss/qmss_qm.h>
-//pull in device config for qmss, cppi
-#include <ti/drv/qmss/device/qmss_device.c>
-#include <ti/drv/cppi/device/cppi_device.c>
 
 /* TODO verify: */
 #define CACHE_LINESZ    64
@@ -104,105 +98,6 @@ uint8_t *cppiMemRxCtlLinkBuf = NULL;
 uint8_t *cppiMemTxCtlLinkBuf = NULL;
 
 
-//****************************************************
-// initialize CPSW (switch) [per SOC]
-//***************************************************
-int netapi_init_cpsw(void)
-{
-    CSL_CPSW_3GF_ALE_PORTCONTROL        alePortControlCfg;
-
-    CSL_CPSW_3GF_clearAleTable();
-
-    alePortControlCfg.dropUntaggedEnable    =   0;
-    alePortControlCfg.vidIngressCheckEnable =   0;
-
-    alePortControlCfg.mcastLimit            =   0;
-    alePortControlCfg.bcastLimit            =   0;
-
-    /* Disable learning mode for Port 0 */
-    alePortControlCfg.noLearnModeEnable     =   1;
-    alePortControlCfg.portState     =   ALE_PORTSTATE_FORWARD;
-    CSL_CPSW_3GF_setAlePortControlReg (0, &alePortControlCfg);
-
-    /* Enable learning mode for Port 1 */
-    alePortControlCfg.noLearnModeEnable     =   0;
-    alePortControlCfg.portState     =   ALE_PORTSTATE_FORWARD;
-    CSL_CPSW_3GF_setAlePortControlReg (1, &alePortControlCfg);
-
-    /* Enable learning mode for Port 2 */
-    alePortControlCfg.noLearnModeEnable     =   0;
-    alePortControlCfg.portState     =   ALE_PORTSTATE_FORWARD;
-    CSL_CPSW_3GF_setAlePortControlReg (2, &alePortControlCfg);
-
-    return 1;
-}
-
-//****************************************************
-// initialize QM (per SOC)
-//***************************************************
-int netapi_init_qm(int max_descriptors)
-{
-  Qmss_InitCfg     qmssInitConfig;
-  int32_t          result;
-  Qmss_GlobalConfigParams nwalTest_qmssGblCfgParams;
-
-  memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));
-
-  /* Use Internal Linking RAM for optimal performance */
-  qmssInitConfig.linkingRAM0Base = 0;
-  qmssInitConfig.linkingRAM0Size = 0;
-  qmssInitConfig.linkingRAM1Base = 0;
-  qmssInitConfig.maxDescNum      = max_descriptors;
-  qmssInitConfig.qmssHwStatus =QMSS_HW_INIT_COMPLETE; //bypass some of the hw init
-  nwalTest_qmssGblCfgParams = qmssGblCfgParams[0];
-
-  nwalTest_qmssGblCfgParams.qmConfigReg = (void *)((uint8_t *)netapi_VM_qmssCfgVaddr +
-      (CSL_QM_SS_CFG_CONFIG_STARVATION_COUNTER_REGS - CSL_QM_SS_CFG_QUE_PEEK_REGS));
-  nwalTest_qmssGblCfgParams.qmDescReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_DESCRIPTION_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmQueMgmtReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_QM_QUEUE_DEQUEUE_REGS)  - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmQueMgmtProxyReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_PROXY_QUEUE_DEQUEUE_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmQueStatReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmQueIntdReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_INTD_REGS)  - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmPdspCmdReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_SCRACH_RAM1_REGS)  - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmPdspCmdReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_SCRACH_RAM2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmPdspCtrlReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_ADSP1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmPdspCtrlReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_ADSP2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmPdspIRamReg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_APDSP1_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmPdspIRamReg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_APDSP2_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmStatusRAM = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_QM_STATUS_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmLinkingRAMReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_LINKING_RAM_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmMcDMAReg = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_MCDMA_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmTimer16Reg[0] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_TIMER1_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmTimer16Reg[1] = (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-      ((uint32_t)CSL_QM_SS_CFG_TIMER2_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS);
-  nwalTest_qmssGblCfgParams.qmQueMgmtDataReg = (void *)((uint32_t)netapi_VM_qmssDataVaddr);
-  nwalTest_qmssGblCfgParams.qmQueMgmtProxyDataReg = 
-      (void *)((uint32_t)netapi_VM_qmssDataVaddr + ((uint32_t)(0x44040000) - (uint32_t)(0x44020000)));
-
-  result = Qmss_init (&qmssInitConfig, &nwalTest_qmssGblCfgParams);
-  if (result != QMSS_SOK)  {
-    System_printf (">function init_qm: qmss_Init failed with error code %d\n", result);
-    return (nwal_FALSE);
-  }
-
-       return 1;
-}
-
 //****************************************************
 // Set up  QM memory region (per SOC)
 //***************************************************
@@ -266,77 +161,6 @@ int netapi_start_qm(void)
      return 1;
 }
 
-//*************************************************
-//initilaize CPPI (once per soc)
-//*************************************************
-int netapi_init_cppi(void)
-{
-  int32_t result, i;
-  Cppi_GlobalConfigParams nwalTest_cppiGblCfgParams[CPPI_MAX_CPDMA];
-
-  for (i=0; i<CPPI_MAX_CPDMA; i++)
-    nwalTest_cppiGblCfgParams[i] = cppiGblCfgParams[i];
-
-  /* SRIO CPDMA regs */
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs =
-      (void *)((uint32_t)netapi_VM_srioCfgVaddr +
-               (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txChRegs =
-      (void *)((uint32_t)netapi_VM_srioCfgVaddr +
-               (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
-
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxChRegs =
-      (void *)((uint32_t)netapi_VM_srioCfgVaddr +
-               (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txSchedRegs =
-      (void *)((uint32_t)netapi_VM_srioCfgVaddr +
-               (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
- nwalTest_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs =
-      (void *)((uint32_t)netapi_VM_srioCfgVaddr +
-               (((uint32_t)CSL_SRIO_CONFIG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_SRIO_CONFIG_REGS));
-
-  /* PASS CPDMA regs */
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].gblCfgRegs =
-      (void *)((uint32_t)netapi_VM_passCfgVaddr +
-               (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txChRegs =
-      (void *)((uint32_t)netapi_VM_passCfgVaddr +
-               (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxChRegs =
-      (void *)((uint32_t)netapi_VM_passCfgVaddr +
-               (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txSchedRegs =
-      (void *)((uint32_t)netapi_VM_passCfgVaddr +
-               (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxFlowRegs =
-      (void *)((uint32_t)netapi_VM_passCfgVaddr +
-               (((uint32_t)CSL_PA_SS_CFG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_PA_SS_CFG_REGS));
- /* QMSS CPDMA regs */
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs =
-      (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-               (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_GLOBAL_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txChRegs =
-      (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-               (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_TX_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxChRegs =
-      (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-               (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_RX_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txSchedRegs =
-      (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-               (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_TX_SCHEDULER_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
-  nwalTest_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs =
-      (void *)((uint32_t)netapi_VM_qmssCfgVaddr +
-               (((uint32_t)CSL_QM_SS_CFG_CPPI_DMA_RX_FLOW_CFG_REGS) - (uint32_t)CSL_QM_SS_CFG_QUE_PEEK_REGS));
-
-  result = Cppi_init (nwalTest_cppiGblCfgParams);
-  if (result != CPPI_SOK)  
-  {
-    printf (">function cppi_init: Cppi_init failed with error code %d\n", result);
-    return (-1);
-  }
-   return 1;
-}
-
 //*************************************************
 //initialize NWAL (one per soc) 
 //*************************************************
index 97e90711f9550833fd26aa2477447b6f6648fce2..c66e1c6da0f59fc5beb40408882c20d37242b182 100755 (executable)
@@ -216,7 +216,6 @@ void * cookie;  /*set by calling thread */
 //internal initialization routines */
 int netapi_init_qm(int max_descriptors);
 int netapi_init_cppi(void);
-int netapi_init_cpsw(void);
 int netapi_start_qm(void);
 int netapi_init_nwal(
      int region2use,
index cba24bedce4f271f9b0b50edf4317fcd007f2bb0..b732255d23e6b31193fae33d0bd9487b983609ab 100755 (executable)
 
 #define NETAPI_PERM_MEM_SZ  (TUNE_NETAPI_PERM_MEM_SZ) 
 
-/* Physical address map & size for various subsystems */
-#define QMSS_CFG_BASE_ADDR  CSL_QM_SS_CFG_QUE_PEEK_REGS
-#define QMSS_CFG_BLK_SZ (1*1024*1024)
-#define QMSS_DATA_BASE_ADDR 0x44020000 
-#define QMSS_DATA_BLK_SZ (0x60000)
-#define SRIO_CFG_BASE_ADDR  CSL_SRIO_CONFIG_REGS
-#define SRIO_CFG_BLK_SZ (132*1024)
-#define PASS_CFG_BASE_ADDR  CSL_PA_SS_CFG_REGS 
-#define PASS_CFG_BLK_SZ (1*1024*1024)
+
 
 #define MSMC_SRAM_BASE_ADDR CSL_MSMC_SRAM_REGS
 uint8_t *netapi_VM_mem_start_phy = (uint8_t*)0;
index db55152f50d85fdfe15fa7e517111268d38f7ca6..b9fbcdf736dba9feb8b4a1e9ead7d800a0758479 100755 (executable)
@@ -8,6 +8,36 @@
 #include "ti/drv/nwal/nwal.h"
 #include "netapi_util.h"
 
+#ifndef CSL_PA_SS_CFG_REGS
+#define CSL_PA_SS_CFG_REGS  CSL_NETCP_CFG_REGS
+#endif
+#ifndef CSL_PA_SS_CFG_CP_ACE_CFG_REGS
+#define CSL_PA_SS_CFG_CP_ACE_CFG_REGS (CSL_NETCP_CFG_REGS + 0xC0000)
+#endif
+
+/* Physical address map & size for various subsystems */
+#ifdef CSL_QM_SS_CFG_QUE_PEEK_REGS
+/* PDK Version 2 */
+#define QMSS_CFG_BASE_ADDR  CSL_QM_SS_CFG_QUE_PEEK_REGS
+#define QMSS_CFG_BLK_SZ (1*1024*1024)
+#define QMSS_DATA_BASE_ADDR 0x44020000
+#define QMSS_DATA_ARM_PROXY_QUEUE_DEQUEUE_REGS (0x44040000)
+#define QMSS_DATA_BLK_SZ (0x60000)
+#define SRIO_CFG_BASE_ADDR  CSL_SRIO_CONFIG_REGS
+#define PASS_CFG_BASE_ADDR  CSL_PA_SS_CFG_REGS
+#else
+#define QMSS_CFG_BASE_ADDR  CSL_QMSS_CFG_BASE
+#define QMSS_CFG_BLK_SZ ((CSL_QMSS_LINKING_RAM - CSL_QMSS_CFG_BASE) + 0x100000)
+#define QMSS_DATA_BASE_ADDR CSL_QMSS_DATA_QM1_QUEUE_MANAGEMENT_REGS
+#define QMSS_DATA_BASE_QUEUE_PROXY_ADDR CSL_QMSS_DATA_BASE
+#define QMSS_DATA_BLK_SZ ((CSL_QMSS_DATA_QM2_QUEUE_PROXY_REGS - QMSS_DATA_BASE_QUEUE_PROXY_ADDR) + 0x50000)
+#define SRIO_CFG_BASE_ADDR  CSL_SRIO_CFG_REGS
+#define PASS_CFG_BASE_ADDR  CSL_NETCP_CFG_REGS
+
+#endif
+#define PASS_CFG_BLK_SZ (1*1024*1024)
+#define SRIO_CFG_BLK_SZ (132*1024)
+
 /* Function to initialize memory allocator */
 nwal_Bool_t netapi_VM_memAllocInit
 (
diff --git a/ti/runtime/netapi/src/pdk/v2/netapi_navig.c b/ti/runtime/netapi/src/pdk/v2/netapi_navig.c
new file mode 100644 (file)
index 0000000..352ecd7
--- /dev/null
@@ -0,0 +1,291 @@
+/************************************************
+*  FILE:  netapi_device.c
+ *  Device specific initialization for NETAPI
+ *
+ * DESCRIPTION: Functions to initialize multicore navigator related global
+ *              resources
+ *
+ * REVISION HISTORY:
+ *
+ *  Copyright (c) Texas Instruments Incorporated 2010-2012
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***********************************************/
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <errno.h>
+#include <unistd.h>
+
+#include <ti/csl/cslr_device.h>
+#include <ti/drv/qmss/qmss_qm.h>
+#include "netapi_vm.h"
+
+//pull in device config for qmss, cppi
+#include "qmss_device.c"
+#include "cppi_device.c"
+
+/******************************************************************************
+* Macro to convert to IP Register Virtual Address from a mapped base Virtual
+* Address
+* Input: virtBaseAddr: Virtual base address mapped using mmap for IP
+*        phyBaseAddr: Physical base address for the IP
+*        phyRegAddr:  Physical register address
+******************************************************************************/
+static inline void* NETAPI_GET_REG_VADDR (void *    virtBaseAddr,
+                                          uint32_t  phyBaseAddr,
+                                          uint32_t  phyRegAddr)
+{
+    return((void *)((uint8_t *)virtBaseAddr + (phyRegAddr - phyBaseAddr)));
+}
+
+
+//*************************************************
+//initilaize CPPI (once per soc)
+//*************************************************
+int netapi_init_cppi(void)
+{
+  int32_t result, i;
+  Cppi_GlobalConfigParams     netapi_cppiGblCfgParams[CPPI_MAX_CPDMA];
+
+  for (i=0; i<CPPI_MAX_CPDMA; i++)
+    netapi_cppiGblCfgParams[i] = cppiGblCfgParams[i];
+
+  /* SRIO CPDMA regs */
+  netapi_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs =
+   NETAPI_GET_REG_VADDR(netapi_VM_srioCfgVaddr,
+                        CSL_SRIO_CONFIG_REGS,
+                        (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txChRegs =
+   NETAPI_GET_REG_VADDR(netapi_VM_srioCfgVaddr,
+                        CSL_SRIO_CONFIG_REGS,
+                        (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txChRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxChRegs =
+   NETAPI_GET_REG_VADDR(netapi_VM_srioCfgVaddr,
+                        CSL_SRIO_CONFIG_REGS,
+                        (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxChRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txSchedRegs =
+   NETAPI_GET_REG_VADDR(netapi_VM_srioCfgVaddr,
+                        CSL_SRIO_CONFIG_REGS,
+                        (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].txSchedRegs);
+
+ netapi_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs =
+   NETAPI_GET_REG_VADDR(netapi_VM_srioCfgVaddr,
+                        CSL_SRIO_CONFIG_REGS,
+                        (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs);
+
+  /* PASS CPDMA regs */
+  netapi_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].gblCfgRegs =
+    NETAPI_GET_REG_VADDR(netapi_VM_passCfgVaddr,
+                         CSL_PA_SS_CFG_REGS,
+                         (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].gblCfgRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txChRegs =
+    NETAPI_GET_REG_VADDR(netapi_VM_passCfgVaddr,
+                         CSL_PA_SS_CFG_REGS,
+                         (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txChRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxChRegs =
+    NETAPI_GET_REG_VADDR(netapi_VM_passCfgVaddr,
+                         CSL_PA_SS_CFG_REGS,
+                         (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxChRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txSchedRegs =
+    NETAPI_GET_REG_VADDR(netapi_VM_passCfgVaddr,
+                         CSL_PA_SS_CFG_REGS,
+                         (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].txSchedRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxFlowRegs =
+    NETAPI_GET_REG_VADDR(netapi_VM_passCfgVaddr,
+                         CSL_PA_SS_CFG_REGS,
+                         (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_PASS_CPDMA].rxFlowRegs);
+
+ /* QMSS CPDMA regs */
+  netapi_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txChRegs =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txChRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxChRegs =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxChRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txSchedRegs =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].txSchedRegs);
+
+  netapi_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_cppiGblCfgParams[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs);
+
+  result = Cppi_init (netapi_cppiGblCfgParams);
+  if (result != CPPI_SOK)
+  {
+    printf (">function cppi_init: Cppi_init failed with error code %d\n", result);
+    return (-1);
+  }
+   return 1;
+}
+
+//****************************************************
+// initialize QM (per SOC)
+//***************************************************
+int netapi_init_qm(int max_descriptors)
+{
+  Qmss_InitCfg     qmssInitConfig;
+  int32_t          result;
+  Qmss_GlobalConfigParams netapi_qmssGblCfgParams;
+
+  memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));
+
+  /* Use Internal Linking RAM for optimal performance */
+  qmssInitConfig.linkingRAM0Base = 0;
+  qmssInitConfig.linkingRAM0Size = 0;
+  qmssInitConfig.linkingRAM1Base = 0;
+  qmssInitConfig.maxDescNum      = max_descriptors;
+  qmssInitConfig.qmssHwStatus =QMSS_HW_INIT_COMPLETE; //bypass some of the hw init
+  netapi_qmssGblCfgParams = qmssGblCfgParams[0];
+
+  netapi_qmssGblCfgParams.qmConfigReg =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmConfigReg);
+
+  netapi_qmssGblCfgParams.qmDescReg =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmDescReg);
+
+  netapi_qmssGblCfgParams.qmQueMgmtReg =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmQueMgmtReg);
+
+  netapi_qmssGblCfgParams.qmQueMgmtProxyReg =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmQueMgmtProxyReg);
+
+  netapi_qmssGblCfgParams.qmQueStatReg =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmQueStatReg);
+
+  netapi_qmssGblCfgParams.qmQueIntdReg =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmQueIntdReg);
+
+  netapi_qmssGblCfgParams.qmPdspCmdReg[0] =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmPdspCmdReg[0]);
+
+  netapi_qmssGblCfgParams.qmPdspCmdReg[1] =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmPdspCmdReg[1]);
+
+  netapi_qmssGblCfgParams.qmPdspCtrlReg[0] =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmPdspCtrlReg[0]);
+
+  netapi_qmssGblCfgParams.qmPdspCtrlReg[1] =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmPdspCtrlReg[1]);
+
+  netapi_qmssGblCfgParams.qmPdspIRamReg[0] =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmPdspIRamReg[0]);
+
+  netapi_qmssGblCfgParams.qmPdspIRamReg[1] =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmPdspIRamReg[1]);
+
+  netapi_qmssGblCfgParams.qmStatusRAM =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmStatusRAM);
+  netapi_qmssGblCfgParams.qmLinkingRAMReg =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmLinkingRAMReg);
+  netapi_qmssGblCfgParams.qmMcDMAReg =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmMcDMAReg);
+
+  netapi_qmssGblCfgParams.qmTimer16Reg[0] =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmTimer16Reg[0]);
+
+  netapi_qmssGblCfgParams.qmTimer16Reg[1] =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                         QMSS_CFG_BASE_ADDR,
+                         (uint32_t)netapi_qmssGblCfgParams.qmTimer16Reg[1]);
+
+  netapi_qmssGblCfgParams.qmQueMgmtDataReg =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssDataVaddr,
+                         QMSS_DATA_BASE_ADDR,
+                         netapi_qmssGblCfgParams.qmQueMgmtDataReg);
+
+  netapi_qmssGblCfgParams.qmQueMgmtProxyDataReg =
+    NETAPI_GET_REG_VADDR(netapi_VM_qmssDataVaddr,
+                         QMSS_DATA_BASE_ADDR,
+                         QMSS_DATA_ARM_PROXY_QUEUE_DEQUEUE_REGS);
+
+  result = Qmss_init (&qmssInitConfig, &netapi_qmssGblCfgParams);
+  if (result != QMSS_SOK)  {
+    printf (">function init_qm: qmss_Init failed with error code %d\n", result);
+    return (nwal_FALSE);
+  }
+
+    return 1;
+}
diff --git a/ti/runtime/netapi/src/pdk/v3/netapi_navig.c b/ti/runtime/netapi/src/pdk/v3/netapi_navig.c
new file mode 100644 (file)
index 0000000..c325ed1
--- /dev/null
@@ -0,0 +1,282 @@
+/************************************************
+*  FILE:  netapi_device.c
+ *  Device specific initialization for NETAPI
+ *
+ * DESCRIPTION: Functions to initialize multicore navigator related global
+ *              resources
+ *
+ * REVISION HISTORY:
+ *
+ *  Copyright (c) Texas Instruments Incorporated 2010-2012
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***********************************************/
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <errno.h>
+#include <unistd.h>
+
+#include <ti/csl/cslr_device.h>
+#include <ti/drv/qmss/qmss_qm.h>
+#include "netapi_vm.h"
+
+//pull in device config for qmss, cppi
+#include "qmss_device.c"
+#include "cppi_device.c"
+
+/******************************************************************************
+* Macro to convert to IP Register Virtual Address from a mapped base Virtual
+* Address
+* Input: virtBaseAddr: Virtual base address mapped using mmap for IP
+*        phyBaseAddr: Physical base address for the IP
+*        phyRegAddr:  Physical register address
+******************************************************************************/
+static inline void* NETAPI_GET_REG_VADDR (void *    virtBaseAddr,
+                                          uint32_t  phyBaseAddr,
+                                          uint32_t  phyRegAddr)
+{
+    return((void *)((uint8_t *)virtBaseAddr + (phyRegAddr - phyBaseAddr)));
+}
+
+
+/*****************************************************************************
+ * FUNCTION PURPOSE: Global Initialization of CPPI. Once Per System
+ *****************************************************************************
+ * DESCRIPTION: The function will initialize the CPPI
+ *****************************************************************************/
+int netapi_init_cppi(void)
+{
+
+    int32_t                         result;
+    Cppi_GlobalConfigParams         netapi_cppiGblCfgParams;
+
+    netapi_cppiGblCfgParams = cppiGblCfgParams;
+    /* Convert Physical address to Virtual address for LLD access */
+    /* SRIO CPDMA regs */
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_srioCfgVaddr,
+                             CSL_SRIO_CFG_REGS,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].gblCfgRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].txChRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_srioCfgVaddr,
+                             CSL_SRIO_CFG_REGS,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].txChRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].rxChRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_srioCfgVaddr,
+                             CSL_SRIO_CFG_REGS,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].rxChRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].txSchedRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_srioCfgVaddr,
+                             CSL_SRIO_CFG_REGS,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].txSchedRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_srioCfgVaddr,
+                             CSL_SRIO_CFG_REGS,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_SRIO_CPDMA].rxFlowRegs);
+
+    /* PASS CPDMA regs */
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].gblCfgRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_passCfgVaddr,
+                             CSL_NETCP_CFG_REGS,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].gblCfgRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].txChRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_passCfgVaddr,
+                             CSL_NETCP_CFG_REGS,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].txChRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].rxChRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_passCfgVaddr,
+                             CSL_NETCP_CFG_REGS,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].rxChRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].txSchedRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_passCfgVaddr,
+                             CSL_NETCP_CFG_REGS,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].txSchedRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].rxFlowRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_passCfgVaddr,
+                             CSL_NETCP_CFG_REGS,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_PASS_CPDMA].rxFlowRegs);
+
+    /* QMSS CPDMA regs */
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                             QMSS_CFG_BASE_ADDR,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].gblCfgRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].txChRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                             QMSS_CFG_BASE_ADDR,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].txChRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].rxChRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                             QMSS_CFG_BASE_ADDR,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].rxChRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].txSchedRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                             QMSS_CFG_BASE_ADDR,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].txSchedRegs);
+
+    netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs =
+        NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                             QMSS_CFG_BASE_ADDR,
+                             (uint32_t)netapi_cppiGblCfgParams.cpDmaCfgs[Cppi_CpDma_QMSS_CPDMA].rxFlowRegs);
+    result = Cppi_init (&netapi_cppiGblCfgParams);
+    if (result != CPPI_SOK)  {
+        printf ("function testNwGlobCppiInit: Cppi_init failed with error code %d\n", result);
+        return (-1);
+    }
+    return (1);
+}
+
+/*****************************************************************************
+ * FUNCTION PURPOSE: Global Initialization of Queue Manager. Once Per System
+ *****************************************************************************
+ * DESCRIPTION: The function will initialize the Queue Manager
+ *****************************************************************************/
+int netapi_init_qm(int max_descriptors)
+{
+    Qmss_InitCfg              qmssInitConfig;
+    int32_t                   result;
+    Qmss_GlobalConfigParams   netapi_qmssGblCfgParams;
+    uint32_t                  count;
+
+    memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));
+
+    /* Use Internal Linking RAM for optimal performance */
+    qmssInitConfig.linkingRAM0Base = 0;
+    qmssInitConfig.linkingRAM0Size = 0;
+    qmssInitConfig.linkingRAM1Base = 0;
+    qmssInitConfig.maxDescNum      = max_descriptors;
+    qmssInitConfig.qmssHwStatus = QMSS_HW_INIT_COMPLETE;
+
+    netapi_qmssGblCfgParams = qmssGblCfgParams;
+
+    /* Convert address to Virtual address */
+    for(count=0;count < netapi_qmssGblCfgParams.maxQueMgrGroups;count++)
+    {
+        netapi_qmssGblCfgParams.groupRegs[count].qmConfigReg =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                                 QMSS_CFG_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.groupRegs[count].qmConfigReg);
+
+        netapi_qmssGblCfgParams.groupRegs[count].qmDescReg =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                                 QMSS_CFG_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.groupRegs[count].qmDescReg);
+
+        netapi_qmssGblCfgParams.groupRegs[count].qmQueMgmtReg =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                                 QMSS_CFG_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.groupRegs[count].qmQueMgmtReg);
+
+        netapi_qmssGblCfgParams.groupRegs[count].qmQueMgmtProxyReg =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                                 QMSS_CFG_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.groupRegs[count].qmQueMgmtProxyReg);
+
+        netapi_qmssGblCfgParams.groupRegs[count].qmQueStatReg =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                                 QMSS_CFG_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.groupRegs[count].qmQueStatReg);
+
+        netapi_qmssGblCfgParams.groupRegs[count].qmStatusRAM =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                                 QMSS_CFG_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.groupRegs[count].qmStatusRAM);
+
+        netapi_qmssGblCfgParams.groupRegs[count].qmQueMgmtDataReg =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssDataVaddr,
+                                 QMSS_DATA_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.groupRegs[count].qmQueMgmtDataReg);
+
+        netapi_qmssGblCfgParams.groupRegs[count].qmQueMgmtProxyDataReg =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssDataVaddr,
+                                 QMSS_DATA_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.groupRegs[count].qmQueMgmtProxyDataReg);
+    }
+
+    for(count=0;count < QMSS_MAX_INTD;count++)
+    {
+        netapi_qmssGblCfgParams.regs.qmQueIntdReg[count] =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                                 QMSS_CFG_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.regs.qmQueIntdReg[count]);
+    }
+
+    for(count=0;count < QMSS_MAX_PDSP;count++)
+    {
+        netapi_qmssGblCfgParams.regs.qmPdspCmdReg[count] =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                                 QMSS_CFG_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.regs.qmPdspCmdReg[count]);
+
+        netapi_qmssGblCfgParams.regs.qmPdspCtrlReg[count] =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                                 QMSS_CFG_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.regs.qmPdspCtrlReg[count]);
+
+        netapi_qmssGblCfgParams.regs.qmPdspIRamReg[count] =
+            NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                                 QMSS_CFG_BASE_ADDR,
+                                 (uint32_t)netapi_qmssGblCfgParams.regs.qmPdspIRamReg[count]);
+    }
+
+    netapi_qmssGblCfgParams.regs.qmLinkingRAMReg =
+        NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                             QMSS_CFG_BASE_ADDR,
+                             (uint32_t)netapi_qmssGblCfgParams.regs.qmLinkingRAMReg);
+
+    netapi_qmssGblCfgParams.regs.qmBaseAddr =
+        NETAPI_GET_REG_VADDR(netapi_VM_qmssCfgVaddr,
+                             QMSS_CFG_BASE_ADDR,
+                             (uint32_t)netapi_qmssGblCfgParams.regs.qmBaseAddr);
+
+    result = Qmss_init (&qmssInitConfig, &netapi_qmssGblCfgParams);
+    if (result != QMSS_SOK)
+    {
+        printf ("function testNwGlobQmInit: qmss_Init failed with error code %d\n", result);
+        return (nwal_FALSE);
+    }
+    return 1;
+}